xref: /linux/drivers/phy/qualcomm/phy-qcom-qmp.h (revision 0623fdf30b1105c22f58baeeca954c803bdf5f8b) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef QCOM_PHY_QMP_H_
7 #define QCOM_PHY_QMP_H_
8 
9 #include "phy-qcom-qmp-qserdes-com.h"
10 #include "phy-qcom-qmp-qserdes-txrx.h"
11 
12 #include "phy-qcom-qmp-qserdes-com-v3.h"
13 #include "phy-qcom-qmp-qserdes-txrx-v3.h"
14 
15 #include "phy-qcom-qmp-qserdes-com-v4.h"
16 #include "phy-qcom-qmp-qserdes-txrx-v4.h"
17 #include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
18 
19 #include "phy-qcom-qmp-qserdes-com-v5.h"
20 #include "phy-qcom-qmp-qserdes-txrx-v5.h"
21 #include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
22 #include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h"
23 
24 #include "phy-qcom-qmp-qserdes-com-v6.h"
25 #include "phy-qcom-qmp-qserdes-txrx-v6.h"
26 #include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
27 #include "phy-qcom-qmp-qserdes-txrx-v6_n4.h"
28 #include "phy-qcom-qmp-qserdes-ln-shrd-v5.h"
29 #include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
30 
31 #include "phy-qcom-qmp-qserdes-com-v7.h"
32 #include "phy-qcom-qmp-qserdes-txrx-v7.h"
33 
34 #include "phy-qcom-qmp-qserdes-com-v8.h"
35 #include "phy-qcom-qmp-qserdes-txrx-v8.h"
36 
37 #include "phy-qcom-qmp-qserdes-pll.h"
38 
39 #include "phy-qcom-qmp-pcs-v2.h"
40 
41 #include "phy-qcom-qmp-pcs-v3.h"
42 
43 #include "phy-qcom-qmp-pcs-v4.h"
44 
45 #include "phy-qcom-qmp-pcs-v4_20.h"
46 
47 #include "phy-qcom-qmp-pcs-v5.h"
48 
49 #include "phy-qcom-qmp-pcs-v5_20.h"
50 
51 #include "phy-qcom-qmp-pcs-v6.h"
52 
53 #include "phy-qcom-qmp-pcs-v6-n4.h"
54 
55 #include "phy-qcom-qmp-pcs-v6_20.h"
56 
57 #include "phy-qcom-qmp-pcs-v7.h"
58 
59 #include "phy-qcom-qmp-pcs-v8.h"
60 
61 #include "phy-qcom-qmp-pcs-v8_50.h"
62 
63 /* QPHY_SW_RESET bit */
64 #define SW_RESET				BIT(0)
65 /* QPHY_POWER_DOWN_CONTROL */
66 #define SW_PWRDN				BIT(0)
67 #define REFCLK_DRV_DSBL				BIT(1) /* PCIe */
68 
69 /* QPHY_START_CONTROL bits */
70 #define SERDES_START				BIT(0)
71 #define PCS_START				BIT(1)
72 
73 /* QPHY_PCS_STATUS bit */
74 #define PHYSTATUS				BIT(6)
75 #define PHYSTATUS_4_20				BIT(7)
76 
77 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
78 #define ARCVR_DTCT_EN				BIT(0)
79 #define ALFPS_DTCT_EN				BIT(1)
80 #define ARCVR_DTCT_EVENT_SEL			BIT(4)
81 
82 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
83 #define IRQ_CLEAR				BIT(0)
84 
85 /* QPHY_PCS_MISC_CLAMP_ENABLE register bits */
86 #define CLAMP_EN				BIT(0) /* enables i/o clamp_n */
87 
88 #endif
89