xref: /titanic_41/usr/src/uts/common/io/pcn/pcn.h (revision 438b5f69eb4f998015cc0835f19f2f80663f2f53)
1 /*
2  * Copyright 2011 Jason King.
3  * Copyright (c) 2000 Berkeley Software Design, Inc.
4  * Copyright (c) 1997, 1998, 1999, 2000
5  *	Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *	This product includes software developed by Bill Paul.
18  * 4. Neither the name of the author nor the names of any co-contributors
19  *    may be used to endorse or promote products derived from this software
20  *    without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32  * THE POSSIBILITY OF SUCH DAMAGE.
33  *
34  */
35 
36 #ifndef	_PCN_H
37 #define	_PCN_H
38 
39 #ifdef	__cplusplus
40 extern "C" {
41 #endif
42 
43 /*
44  * 16-bit I/O map
45  * To switch to 32-bit mode, write to RDP.
46  */
47 #define	PCN_IO16_APROM00	0x00
48 #define	PCN_IO16_APROM01	0x02
49 #define	PCN_IO16_APROM02	0x04
50 #define	PCN_IO16_APROM03	0x06
51 #define	PCN_IO16_APROM04	0x08
52 #define	PCN_IO16_APROM05	0x0A
53 #define	PCN_IO16_APROM06	0x0C
54 #define	PCN_IO16_APROM07	0x0E
55 #define	PCN_IO16_RDP		0x10
56 #define	PCN_IO16_RAP		0x12
57 #define	PCN_IO16_RESET		0x14
58 #define	PCN_IO16_BDP		0x16
59 
60 /*
61  * 32-bit I/O map
62  */
63 #define	PCN_IO32_APROM00	0x00
64 #define	PCN_IO32_APROM01	0x04
65 #define	PCN_IO32_APROM02	0x08
66 #define	PCN_IO32_APROM03	0x0C
67 #define	PCN_IO32_RDP		0x10
68 #define	PCN_IO32_RAP		0x14
69 #define	PCN_IO32_RESET		0x18
70 #define	PCN_IO32_BDP		0x1C
71 
72 /*
73  * CSR registers
74  */
75 #define	PCN_CSR_CSR		0x00
76 #define	PCN_CSR_IAB0		0x01
77 #define	PCN_CSR_IAB1		0x02
78 #define	PCN_CSR_IMR		0x03
79 #define	PCN_CSR_TFEAT		0x04
80 #define	PCN_CSR_EXTCTL1		0x05
81 #define	PCN_CSR_DTBLLEN		0x06
82 #define	PCN_CSR_EXTCTL2		0x07
83 #define	PCN_CSR_MAR0		0x08
84 #define	PCN_CSR_MAR1		0x09
85 #define	PCN_CSR_MAR2		0x0A
86 #define	PCN_CSR_MAR3		0x0B
87 #define	PCN_CSR_PAR0		0x0C
88 #define	PCN_CSR_PAR1		0x0D
89 #define	PCN_CSR_PAR2		0x0E
90 #define	PCN_CSR_MODE		0x0F
91 #define	PCN_CSR_RXADDR0		0x18
92 #define	PCN_CSR_RXADDR1		0x19
93 #define	PCN_CSR_TXADDR0		0x1E
94 #define	PCN_CSR_TXADDR1		0x1F
95 #define	PCN_CSR_TXPOLL		0x2F
96 #define	PCN_CSR_RXPOLL		0x31
97 #define	PCN_CSR_RXRINGLEN	0x4C
98 #define	PCN_CSR_TXRINGLEN	0x4E
99 #define	PCN_CSR_DMACTL		0x50
100 #define	PCN_CSR_BUSTIMER	0x52
101 #define	PCN_CSR_MEMERRTIMEO	0x64
102 #define	PCN_CSR_ONNOWMISC	0x74
103 #define	PCN_CSR_ADVFEAT		0x7A
104 #define	PCN_CSR_MACCFG		0x7D
105 #define	PCN_CSR_CHIPID0		0x58
106 #define	PCN_CSR_CHIPID1		0x59
107 
108 
109 #define	PCN_CSR_INIT		0x0001
110 #define	PCN_CSR_START		0x0002
111 #define	PCN_CSR_STOP		0x0004
112 #define	PCN_CSR_TX		0x0008
113 #define	PCN_CSR_TXON		0x0010
114 #define	PCN_CSR_RXON		0x0020
115 #define	PCN_CSR_INTEN		0x0040
116 #define	PCN_CSR_INTR		0x0080
117 #define	PCN_CSR_IDONE		0x0100
118 #define	PCN_CSR_TINT		0x0200
119 #define	PCN_CSR_RINT		0x0400
120 #define	PCN_CSR_MERR		0x0800
121 #define	PCN_CSR_MISS		0x1000
122 #define	PCN_CSR_CERR		0x2000
123 #define	PCN_CSR_ERR		0x8000
124 #define	PCN_CSR_STR \
125 	"\020" \
126 	"\001INIT" \
127 	"\002START" \
128 	"\003STOP" \
129 	"\004TX" \
130 	"\005TXON" \
131 	"\006RXON" \
132 	"\007INTEN" \
133 	"\010INTR" \
134 	"\011IDONE" \
135 	"\012TINT" \
136 	"\013RINT" \
137 	"\014MERR" \
138 	"\015MISS" \
139 	"\016CERR" \
140 	"\017ERR"
141 
142 /*
143  * Interrupt masks and deferral control (CSR3)
144  */
145 #define	PCN_IMR_BSWAP		0x0004
146 #define	PCN_IMR_ENMBA		0x0008	/* enable modified backoff alg */
147 #define	PCN_IMR_DXMT2PD		0x0010
148 #define	PCN_IMR_LAPPEN		0x0020	/* lookahead packet processing enb */
149 #define	PCN_IMR_DXSUFLO		0x0040	/* disable TX stop on underflow */
150 #define	PCN_IMR_IDONE		0x0100
151 #define	PCN_IMR_TINT		0x0200
152 #define	PCN_IMR_RINT		0x0400
153 #define	PCN_IMR_MERR		0x0800
154 #define	PCN_IMR_MISS		0x1000
155 #define	PCN_IMR_STR \
156 	"\020" \
157 	"\003BSWAP" \
158 	"\004ENMBA" \
159 	"\005DXMT2PD" \
160 	"\006LAPPEN" \
161 	"\007DXSUFLO" \
162 	"\010IDONE" \
163 	"\011TINT" \
164 	"\012RINT" \
165 	"\013MERR" \
166 	"\014MISS"
167 
168 /*
169  * Test and features control (CSR4)
170  */
171 #define	PCN_TFEAT_TXSTRTMASK	0x0004
172 #define	PCN_TFEAT_TXSTRT	0x0008
173 #define	PCN_TFEAT_RXCCOFLOWM	0x0010	/* Rx collision counter oflow */
174 #define	PCN_TFEAT_RXCCOFLOW	0x0020
175 #define	PCN_TFEAT_UINT		0x0040
176 #define	PCN_TFEAT_UINTREQ	0x0080
177 #define	PCN_TFEAT_MISSOFLOWM	0x0100
178 #define	PCN_TFEAT_MISSOFLOW	0x0200
179 #define	PCN_TFEAT_STRIP_FCS	0x0400
180 #define	PCN_TFEAT_PAD_TX	0x0800
181 #define	PCN_TFEAT_TXDPOLL	0x1000
182 #define	PCN_TFEAT_DMAPLUS	0x4000
183 
184 /*
185  * Extended control and interrupt 1 (CSR5)
186  */
187 #define	PCN_EXTCTL1_SPND	0x0001	/* suspend */
188 #define	PCN_EXTCTL1_MPMODE	0x0002	/* magic packet mode */
189 #define	PCN_EXTCTL1_MPENB	0x0004	/* magic packet enable */
190 #define	PCN_EXTCTL1_MPINTEN	0x0008	/* magic packet interrupt enable */
191 #define	PCN_EXTCTL1_MPINT	0x0010	/* magic packet interrupt */
192 #define	PCN_EXTCTL1_MPPLBA	0x0020	/* magic packet phys. logical bcast */
193 #define	PCN_EXTCTL1_EXDEFEN	0x0040	/* excessive deferral interrupt enb. */
194 #define	PCN_EXTCTL1_EXDEF	0x0080	/* excessive deferral interrupt */
195 #define	PCN_EXTCTL1_SINTEN	0x0400	/* system interrupt enable */
196 #define	PCN_EXTCTL1_SINT	0x0800	/* system interrupt */
197 #define	PCN_EXTCTL1_LTINTEN	0x4000	/* last TX interrupt enb */
198 #define	PCN_EXTCTL1_TXOKINTD	0x8000	/* TX OK interrupt disable */
199 #define	PCN_EXTCTL1_STR \
200 	"\020" \
201 	"\001SPND" \
202 	"\002MPMODE" \
203 	"\003MPENB" \
204 	"\004MPINTEN" \
205 	"\005MPINT" \
206 	"\006MPPLB" \
207 	"\007EXDEFEN" \
208 	"\010EXDEF" \
209 	"\013SINTEN" \
210 	"\014SINT" \
211 	"\017LTINTEN" \
212 	"\020TXOKINTD"
213 
214 /*
215  * RX/TX descriptor len (CSR6)
216  */
217 #define	PCN_DTBLLEN_RLEN	0x0F00
218 #define	PCN_DTBLLEN_TLEN	0xF000
219 
220 /*
221  * Extended control and interrupt 2 (CSR7)
222  */
223 #define	PCN_EXTCTL2_MIIPDTINTE	0x0001
224 #define	PCN_EXTCTL2_MIIPDTINT	0x0002
225 #define	PCN_EXTCTL2_MCCIINTE	0x0004
226 #define	PCN_EXTCTL2_MCCIINT	0x0008
227 #define	PCN_EXTCTL2_MCCINTE	0x0010
228 #define	PCN_EXTCTL2_MCCINT	0x0020
229 #define	PCN_EXTCTL2_MAPINTE	0x0040
230 #define	PCN_EXTCTL2_MAPINT	0x0080
231 #define	PCN_EXTCTL2_MREINTE	0x0100
232 #define	PCN_EXTCTL2_MREINT	0x0200
233 #define	PCN_EXTCTL2_STINTE	0x0400
234 #define	PCN_EXTCTL2_STINT	0x0800
235 #define	PCN_EXTCTL2_RXDPOLL	0x1000
236 #define	PCN_EXTCTL2_RDMD	0x2000
237 #define	PCN_EXTCTL2_RXFRTG	0x4000
238 #define	PCN_EXTCTL2_FASTSPNDE	0x8000
239 #define	PCN_EXTCTL2_STR \
240 	"\020" \
241 	"\001MIIPDTINTE" \
242 	"\002MIIPDTINT" \
243 	"\003MCCIINTTE" \
244 	"\004MCCIINT" \
245 	"\005MCCINTE" \
246 	"\006MCCINT" \
247 	"\007MAPINTE" \
248 	"\010MAPINT" \
249 	"\011MRTINTE" \
250 	"\012MREINT" \
251 	"\013STINTE" \
252 	"\014STINT" \
253 	"\015RXDPOLL" \
254 	"\016RDMD" \
255 	"\017RXFRTG" \
256 	"\020FASTSPNDE"
257 
258 /*
259  * Mode (CSR15)
260  */
261 #define	PCN_MODE_RXD		0x0001	/* RX disable */
262 #define	PCN_MODE_TXD		0x0002	/* TX disable */
263 #define	PCN_MODE_LOOP		0x0004	/* loopback enable */
264 #define	PCN_MODE_TXCRCD		0x0008
265 #define	PCN_MODE_FORCECOLL	0x0010
266 #define	PCN_MODE_RETRYD		0x0020
267 #define	PCN_MODE_INTLOOP	0x0040
268 #define	PCN_MODE_PORTSEL	0x0180
269 #define	PCN_MODE_RXVPAD		0x2000
270 #define	PCN_MODE_RXNOBROAD	0x4000
271 #define	PCN_MODE_PROMISC	0x8000
272 #define	PCN_MODE_STR \
273 	"\020" \
274 	"\001RXD" \
275 	"\002TXD" \
276 	"\003LOOP" \
277 	"\004TXCRCD" \
278 	"\005FORCECOLL" \
279 	"\006RETRYD" \
280 	"\007INTLOOP" \
281 	"\016RXVPAD" \
282 	"\017RXNOBROAD" \
283 	"\020PROMISC"
284 
285 /* Settings for PCN_MODE_PORTSEL when ASEL (BCR2[1]) is 0 */
286 #define	PCN_PORT_AUI		0x0000
287 #define	PCN_PORT_10BASET	0x0080
288 #define	PCN_PORT_GPSI		0x0100
289 #define	PCN_PORT_MII		0x0180
290 
291 /*
292  * Chip ID values.
293  */
294 
295 #define	CHIPID_MANFID(x)	(((x) >> 1) & 0x3ff)
296 #define	CHIPID_PARTID(x)	(((x) >> 12) & 0xffff)
297 #define	CHIPID_VER(x)		(((x) >> 28) & 0x7)
298 
299 /* CSR88-89: Chip ID masks */
300 #define	Am79C970  0x0003
301 #define	Am79C970A 0x2621
302 #define	Am79C971  0x2623
303 #define	Am79C972  0x2624
304 #define	Am79C973  0x2625
305 #define	Am79C978  0x2626
306 #define	Am79C975  0x2627
307 #define	Am79C976  0x2628
308 
309 /*
310  * Advanced feature control (CSR122)
311  */
312 #define	PCN_AFC_RXALIGN		0x0001
313 
314 /*
315  * BCR (bus control) registers
316  */
317 #define	PCN_BCR_MMRA		0x00	/* Master Mode Read Active */
318 #define	PCN_BCR_MMW		0x01	/* Master Mode Write Active */
319 #define	PCN_BCR_MISCCFG		0x02
320 #define	PCN_BCR_LED0		0x04
321 #define	PCN_BCR_LED1		0x05
322 #define	PCN_BCR_LED2		0x06
323 #define	PCN_BCR_LED3		0x07
324 #define	PCN_BCR_DUPLEX		0x09
325 #define	PCN_BCR_BUSCTL		0x12
326 #define	PCN_BCR_EECTL		0x13
327 #define	PCN_BCR_SSTYLE		0x14
328 #define	PCN_BCR_PCILAT		0x16
329 #define	PCN_BCR_PCISUBVENID	0x17
330 #define	PCN_BCR_PCISUBSYSID	0x18
331 #define	PCN_BCR_SRAMSIZE	0x19
332 #define	PCN_BCR_SRAMBOUND	0x1A
333 #define	PCN_BCR_SRAMCTL		0x1B
334 #define	PCN_BCR_TIMER		0x1F
335 #define	PCN_BCR_MIICTL		0x20
336 #define	PCN_BCR_MIIADDR		0x21
337 #define	PCN_BCR_MIIDATA		0x22
338 #define	PCN_BCR_PCIVENID	0x23
339 #define	PCN_BCR_PCIPCAP		0x24
340 #define	PCN_BCR_DATA0		0x25
341 #define	PCN_BCR_DATA1		0x26
342 #define	PCN_BCR_DATA2		0x27
343 #define	PCN_BCR_DATA3		0x28
344 #define	PCN_BCR_DATA4		0x29
345 #define	PCN_BCR_DATA5		0x2A
346 #define	PCN_BCR_DATA6		0x2B
347 #define	PCN_BCR_DATA7		0x2C
348 #define	PCN_BCR_ONNOWPAT0	0x2D
349 #define	PCN_BCR_ONNOWPAT1	0x2E
350 #define	PCN_BCR_ONNOWPAT2	0x2F
351 #define	PCN_BCR_PHYSEL		0x31
352 
353 /*
354  * Miscellaneous Configuration (BCR2)
355  */
356 #define	PCN_MISC_TMAULOOP	1<<14	/* T-MAU Loopback packet enable. */
357 #define	PCN_MISC_LEDPE		1<<12	/* LED Program Enable */
358 #define	PCN_MISC_APROMWE	1<<8	/* Address PROM Write Enable */
359 #define	PCN_MISC_INTLEVEL	1<<7	/* Interrupt level */
360 #define	PCN_MISC_EADISEL	1<<3	/* EADI Select */
361 #define	PCN_MISC_AWAKE		1<<2	/* Power saving mode select */
362 #define	PCN_MISC_ASEL		1<<1	/* Auto Select */
363 #define	PCN_MISC_XMAUSEL	1<<0	/* Reserved. */
364 
365 /*
366  * Full duplex control (BCR9)
367  */
368 #define	PCN_DUPLEX_FDEN		0x0001	/* Full-duplex enable */
369 #define	PCN_DUPLEX_AUI		0x0002	/* AUI full-duplex */
370 #define	PCN_DUPLEX_FDRPAD	0x0004	/* Full-duplex runt pkt accept dis. */
371 
372 /*
373  * Burst and bus control register (BCR18)
374  */
375 #define	PCN_BUSCTL_BWRITE	0x0020
376 #define	PCN_BUSCTL_BREAD	0x0040
377 #define	PCN_BUSCTL_DWIO		0x0080
378 #define	PCN_BUSCTL_EXTREQ	0x0100
379 #define	PCN_BUSCTL_MEMCMD	0x0200
380 #define	PCN_BUSCTL_NOUFLOW	0x0800
381 #define	PCN_BUSCTL_ROMTMG	0xF000
382 
383 /*
384  * EEPROM control (BCR19)
385  */
386 #define	PCN_EECTL_EDATA		0x0001
387 #define	PCN_EECTL_ECLK		0x0002
388 #define	PCN_EECTL_EECS		0x0004
389 #define	PCN_EECTL_EEN		0x0100
390 #define	PCN_EECTL_EEDET		0x2000
391 #define	PCN_EECTL_PREAD		0x4000
392 #define	PCN_EECTL_PVALID	0x8000
393 
394 /*
395  * Software style (BCR20)
396  */
397 #define	PCN_SSTYLE_APERREN	0x0400	/* advanced parity error checking */
398 #define	PCN_SSTYLE_SSIZE32	0x0100
399 #define	PCN_SSTYLE_SWSTYLE	0x00FF
400 
401 #define	PCN_SWSTYLE_LANCE		0x0000
402 #define	PCN_SWSTYLE_PCNETPCI		0x0102
403 #define	PCN_SWSTYLE_PCNETPCI_BURST	0x0103
404 
405 /*
406  * MII control and status (BCR32)
407  */
408 #define	PCN_MIICTL_MIILP	0x0002	/* MII internal loopback */
409 #define	PCN_MIICTL_XPHYSP	0x0008	/* external PHY speed */
410 #define	PCN_MIICTL_XPHYFD	0x0010	/* external PHY full duplex */
411 #define	PCN_MIICTL_XPHYANE	0x0020	/* external phy auto-neg enable */
412 #define	PCN_MIICTL_XPHYRST	0x0040	/* external PHY reset */
413 #define	PCN_MIICTL_DANAS	0x0080	/* disable auto-neg auto-setup */
414 #define	PCN_MIICTL_APDW		0x0700	/* auto-poll dwell time */
415 #define	PCN_MIICTL_APEP		0x0100	/* auto-poll external PHY */
416 #define	PCN_MIICTL_FMDC		0x3000	/* data clock speed */
417 #define	PCN_MIICTL_MIIPD	0x4000	/* PHY detect */
418 #define	PCN_MIICTL_ANTST	0x8000	/* Manufacturing test */
419 
420 /*
421  * MII address register (BCR33)
422  */
423 #define	PCN_MIIADDR_REGAD	0x001F
424 #define	PCN_MIIADDR_PHYAD	0x03E0
425 
426 /* addresses of internal PHYs */
427 #define	PCN_PHYAD_100BTX	30
428 #define	PCN_PHYAD_10BT		31
429 
430 /*
431  * MII data register (BCR34)
432  */
433 #define	PCN_MIIDATA_MIIMD	0xFFFF
434 
435 /*
436  * PHY selection (BCR49) (HomePNA NIC only)
437  */
438 #define	PCN_PHYSEL_PHYSEL	0x0003
439 #define	PCN_PHYSEL_DEFAULT	0x0300
440 #define	PCN_PHYSEL_PCNET	0x8000
441 
442 #define	PCN_PHY_10BT		0x0000
443 #define	PCN_PHY_HOMEPNA		0x0001
444 #define	PCN_PHY_EXTERNAL	0x0002
445 
446 #ifdef	__cplusplus
447 }
448 #endif
449 
450 #endif /* _PCN_H */
451