1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef SMU_13_0_6_PMFW_H 24 #define SMU_13_0_6_PMFW_H 25 26 #define NUM_VCLK_DPM_LEVELS 4 27 #define NUM_DCLK_DPM_LEVELS 4 28 #define NUM_SOCCLK_DPM_LEVELS 4 29 #define NUM_LCLK_DPM_LEVELS 4 30 #define NUM_UCLK_DPM_LEVELS 4 31 #define NUM_FCLK_DPM_LEVELS 4 32 #define NUM_XGMI_DPM_LEVELS 2 33 #define NUM_CXL_BITRATES 4 34 #define NUM_PCIE_BITRATES 4 35 #define NUM_XGMI_BITRATES 4 36 #define NUM_XGMI_WIDTHS 3 37 #define NUM_SOC_P2S_TABLES 3 38 #define NUM_TDP_GROUPS 4 39 40 typedef enum { 41 /*0*/ FEATURE_DATA_CALCULATION = 0, 42 /*1*/ FEATURE_DPM_CCLK = 1, 43 /*2*/ FEATURE_DPM_FCLK = 2, 44 /*3*/ FEATURE_DPM_GFXCLK = 3, 45 /*4*/ FEATURE_DPM_LCLK = 4, 46 /*5*/ FEATURE_DPM_SOCCLK = 5, 47 /*6*/ FEATURE_DPM_UCLK = 6, 48 /*7*/ FEATURE_DPM_VCN = 7, 49 /*8*/ FEATURE_DPM_XGMI = 8, 50 /*9*/ FEATURE_DS_FCLK = 9, 51 /*10*/ FEATURE_DS_GFXCLK = 10, 52 /*11*/ FEATURE_DS_LCLK = 11, 53 /*12*/ FEATURE_DS_MP0CLK = 12, 54 /*13*/ FEATURE_DS_MP1CLK = 13, 55 /*14*/ FEATURE_DS_MPIOCLK = 14, 56 /*15*/ FEATURE_DS_SOCCLK = 15, 57 /*16*/ FEATURE_DS_VCN = 16, 58 /*17*/ FEATURE_APCC_DFLL = 17, 59 /*18*/ FEATURE_APCC_PLUS = 18, 60 /*19*/ FEATURE_DF_CSTATE = 19, 61 /*20*/ FEATURE_CC6 = 20, 62 /*21*/ FEATURE_PC6 = 21, 63 /*22*/ FEATURE_CPPC = 22, 64 /*23*/ FEATURE_PPT = 23, 65 /*24*/ FEATURE_TDC = 24, 66 /*25*/ FEATURE_THERMAL = 25, 67 /*26*/ FEATURE_SOC_PCC = 26, 68 /*27*/ FEATURE_CCD_PCC = 27, 69 /*28*/ FEATURE_CCD_EDC = 28, 70 /*29*/ FEATURE_PROCHOT = 29, 71 /*30*/ FEATURE_DVO_CCLK = 30, 72 /*31*/ FEATURE_FDD_AID_HBM = 31, 73 /*32*/ FEATURE_FDD_AID_SOC = 32, 74 /*33*/ FEATURE_FDD_XCD_EDC = 33, 75 /*34*/ FEATURE_FDD_XCD_XVMIN = 34, 76 /*35*/ FEATURE_FW_CTF = 35, 77 /*36*/ FEATURE_GFXOFF = 36, 78 /*37*/ FEATURE_SMU_CG = 37, 79 /*38*/ FEATURE_PSI7 = 38, 80 /*39*/ FEATURE_CSTATE_BOOST = 39, 81 /*40*/ FEATURE_XGMI_PER_LINK_PWR_DOWN = 40, 82 /*41*/ FEATURE_CXL_QOS = 41, 83 /*42*/ FEATURE_SOC_DC_RTC = 42, 84 /*43*/ FEATURE_GFX_DC_RTC = 43, 85 /*44*/ FEATURE_DVM_MIN_PSM = 44, 86 /*45*/ FEATURE_PRC = 45, 87 88 /*46*/ NUM_FEATURES = 46 89 } FEATURE_LIST_e; 90 91 //enum for MPIO PCIe gen speed msgs 92 typedef enum { 93 PCIE_LINK_SPEED_INDEX_TABLE_GEN1, 94 PCIE_LINK_SPEED_INDEX_TABLE_GEN2, 95 PCIE_LINK_SPEED_INDEX_TABLE_GEN3, 96 PCIE_LINK_SPEED_INDEX_TABLE_GEN4, 97 PCIE_LINK_SPEED_INDEX_TABLE_GEN4_ESM, 98 PCIE_LINK_SPEED_INDEX_TABLE_GEN5, 99 PCIE_LINK_SPEED_INDEX_TABLE_COUNT 100 } PCIE_LINK_SPEED_INDEX_TABLE_e; 101 102 typedef enum { 103 VOLTAGE_COLD_0, 104 VOLTAGE_COLD_1, 105 VOLTAGE_COLD_2, 106 VOLTAGE_COLD_3, 107 VOLTAGE_COLD_4, 108 VOLTAGE_COLD_5, 109 VOLTAGE_COLD_6, 110 VOLTAGE_COLD_7, 111 VOLTAGE_MID_0, 112 VOLTAGE_MID_1, 113 VOLTAGE_MID_2, 114 VOLTAGE_MID_3, 115 VOLTAGE_MID_4, 116 VOLTAGE_MID_5, 117 VOLTAGE_MID_6, 118 VOLTAGE_MID_7, 119 VOLTAGE_HOT_0, 120 VOLTAGE_HOT_1, 121 VOLTAGE_HOT_2, 122 VOLTAGE_HOT_3, 123 VOLTAGE_HOT_4, 124 VOLTAGE_HOT_5, 125 VOLTAGE_HOT_6, 126 VOLTAGE_HOT_7, 127 VOLTAGE_GUARDBAND_COUNT 128 } GFX_GUARDBAND_e; 129 130 #define SMU_METRICS_TABLE_VERSION 0xF 131 132 typedef struct __attribute__((packed, aligned(4))) { 133 uint32_t AccumulationCounter; 134 135 //TEMPERATURE 136 uint32_t MaxSocketTemperature; 137 uint32_t MaxVrTemperature; 138 uint32_t MaxHbmTemperature; 139 uint64_t MaxSocketTemperatureAcc; 140 uint64_t MaxVrTemperatureAcc; 141 uint64_t MaxHbmTemperatureAcc; 142 143 //POWER 144 uint32_t SocketPowerLimit; 145 uint32_t MaxSocketPowerLimit; 146 uint32_t SocketPower; 147 148 //ENERGY 149 uint64_t Timestamp; 150 uint64_t SocketEnergyAcc; 151 uint64_t CcdEnergyAcc; 152 uint64_t XcdEnergyAcc; 153 uint64_t AidEnergyAcc; 154 uint64_t HbmEnergyAcc; 155 156 //FREQUENCY 157 uint32_t CclkFrequencyLimit; 158 uint32_t GfxclkFrequencyLimit; 159 uint32_t FclkFrequency; 160 uint32_t UclkFrequency; 161 uint32_t SocclkFrequency[4]; 162 uint32_t VclkFrequency[4]; 163 uint32_t DclkFrequency[4]; 164 uint32_t LclkFrequency[4]; 165 uint64_t GfxclkFrequencyAcc[8]; 166 uint64_t CclkFrequencyAcc[96]; 167 168 //FREQUENCY RANGE 169 uint32_t MaxCclkFrequency; 170 uint32_t MinCclkFrequency; 171 uint32_t MaxGfxclkFrequency; 172 uint32_t MinGfxclkFrequency; 173 uint32_t FclkFrequencyTable[4]; 174 uint32_t UclkFrequencyTable[4]; 175 uint32_t SocclkFrequencyTable[4]; 176 uint32_t VclkFrequencyTable[4]; 177 uint32_t DclkFrequencyTable[4]; 178 uint32_t LclkFrequencyTable[4]; 179 uint32_t MaxLclkDpmRange; 180 uint32_t MinLclkDpmRange; 181 182 //XGMI 183 uint32_t XgmiWidth; 184 uint32_t XgmiBitrate; 185 uint64_t XgmiReadBandwidthAcc[8]; 186 uint64_t XgmiWriteBandwidthAcc[8]; 187 188 //ACTIVITY 189 uint32_t SocketC0Residency; 190 uint32_t SocketGfxBusy; 191 uint32_t DramBandwidthUtilization; 192 uint64_t SocketC0ResidencyAcc; 193 uint64_t SocketGfxBusyAcc; 194 uint64_t DramBandwidthAcc; 195 uint32_t MaxDramBandwidth; 196 uint64_t DramBandwidthUtilizationAcc; 197 uint64_t PcieBandwidthAcc[4]; 198 199 //THROTTLERS 200 uint32_t ProchotResidencyAcc; 201 uint32_t PptResidencyAcc; 202 uint32_t SocketThmResidencyAcc; 203 uint32_t VrThmResidencyAcc; 204 uint32_t HbmThmResidencyAcc; 205 uint32_t GfxLockXCDMak; 206 207 // New Items at end to maintain driver compatibility 208 uint32_t GfxclkFrequency[8]; 209 210 //PSNs 211 uint64_t PublicSerialNumber_AID[4]; 212 uint64_t PublicSerialNumber_XCD[8]; 213 uint64_t PublicSerialNumber_CCD[12]; 214 215 //XGMI Data tranfser size 216 uint64_t XgmiReadDataSizeAcc[8];//in KByte 217 uint64_t XgmiWriteDataSizeAcc[8];//in KByte 218 219 //PCIE BW Data and error count 220 uint32_t PcieBandwidth[4]; 221 uint32_t PCIeL0ToRecoveryCountAcc; // The Pcie counter itself is accumulated 222 uint32_t PCIenReplayAAcc; // The Pcie counter itself is accumulated 223 uint32_t PCIenReplayARolloverCountAcc; // The Pcie counter itself is accumulated 224 uint32_t PCIeNAKSentCountAcc; // The Pcie counter itself is accumulated 225 uint32_t PCIeNAKReceivedCountAcc; // The Pcie counter itself is accumulated 226 227 // VCN/JPEG ACTIVITY 228 uint32_t VcnBusy[4]; 229 uint32_t JpegBusy[32]; 230 231 // PCIE LINK Speed and width 232 uint32_t PCIeLinkSpeed; 233 uint32_t PCIeLinkWidth; 234 235 // PER XCD ACTIVITY 236 uint32_t GfxBusy[8]; 237 uint64_t GfxBusyAcc[8]; 238 239 //PCIE BW Data and error count 240 uint32_t PCIeOtherEndRecoveryAcc; // The Pcie counter itself is accumulated 241 242 //Total App Clock Counter 243 uint64_t GfxclkBelowHostLimitAcc[8]; 244 } MetricsTableX_t; 245 246 typedef struct __attribute__((packed, aligned(4))) { 247 uint32_t AccumulationCounter; 248 249 //TEMPERATURE 250 uint32_t MaxSocketTemperature; 251 uint32_t MaxVrTemperature; 252 uint32_t MaxHbmTemperature; 253 uint64_t MaxSocketTemperatureAcc; 254 uint64_t MaxVrTemperatureAcc; 255 uint64_t MaxHbmTemperatureAcc; 256 257 //POWER 258 uint32_t SocketPowerLimit; 259 uint32_t MaxSocketPowerLimit; 260 uint32_t SocketPower; 261 262 //ENERGY 263 uint64_t Timestamp; 264 uint64_t SocketEnergyAcc; 265 uint64_t CcdEnergyAcc; 266 uint64_t XcdEnergyAcc; 267 uint64_t AidEnergyAcc; 268 uint64_t HbmEnergyAcc; 269 270 //FREQUENCY 271 uint32_t CclkFrequencyLimit; 272 uint32_t GfxclkFrequencyLimit; 273 uint32_t FclkFrequency; 274 uint32_t UclkFrequency; 275 uint32_t SocclkFrequency[4]; 276 uint32_t VclkFrequency[4]; 277 uint32_t DclkFrequency[4]; 278 uint32_t LclkFrequency[4]; 279 uint64_t GfxclkFrequencyAcc[8]; 280 uint64_t CclkFrequencyAcc[96]; 281 282 //FREQUENCY RANGE 283 uint32_t MaxCclkFrequency; 284 uint32_t MinCclkFrequency; 285 uint32_t MaxGfxclkFrequency; 286 uint32_t MinGfxclkFrequency; 287 uint32_t FclkFrequencyTable[4]; 288 uint32_t UclkFrequencyTable[4]; 289 uint32_t SocclkFrequencyTable[4]; 290 uint32_t VclkFrequencyTable[4]; 291 uint32_t DclkFrequencyTable[4]; 292 uint32_t LclkFrequencyTable[4]; 293 uint32_t MaxLclkDpmRange; 294 uint32_t MinLclkDpmRange; 295 296 //XGMI 297 uint32_t XgmiWidth; 298 uint32_t XgmiBitrate; 299 uint64_t XgmiReadBandwidthAcc[8]; 300 uint64_t XgmiWriteBandwidthAcc[8]; 301 302 //ACTIVITY 303 uint32_t SocketC0Residency; 304 uint32_t SocketGfxBusy; 305 uint32_t DramBandwidthUtilization; 306 uint64_t SocketC0ResidencyAcc; 307 uint64_t SocketGfxBusyAcc; 308 uint64_t DramBandwidthAcc; 309 uint32_t MaxDramBandwidth; 310 uint64_t DramBandwidthUtilizationAcc; 311 uint64_t PcieBandwidthAcc[4]; 312 313 //THROTTLERS 314 uint32_t ProchotResidencyAcc; 315 uint32_t PptResidencyAcc; 316 uint32_t SocketThmResidencyAcc; 317 uint32_t VrThmResidencyAcc; 318 uint32_t HbmThmResidencyAcc; 319 uint32_t GfxLockXCDMak; 320 321 // New Items at end to maintain driver compatibility 322 uint32_t GfxclkFrequency[8]; 323 324 //PSNs 325 uint64_t PublicSerialNumber_AID[4]; 326 uint64_t PublicSerialNumber_XCD[8]; 327 uint64_t PublicSerialNumber_CCD[12]; 328 329 //XGMI Data tranfser size 330 uint64_t XgmiReadDataSizeAcc[8];//in KByte 331 uint64_t XgmiWriteDataSizeAcc[8];//in KByte 332 333 // VCN/JPEG ACTIVITY 334 uint32_t VcnBusy[4]; 335 uint32_t JpegBusy[32]; 336 } MetricsTableA_t; 337 338 #define SMU_VF_METRICS_TABLE_VERSION 0x5 339 340 typedef struct __attribute__((packed, aligned(4))) { 341 uint32_t AccumulationCounter; 342 uint32_t InstGfxclk_TargFreq; 343 uint64_t AccGfxclk_TargFreq; 344 uint64_t AccGfxRsmuDpm_Busy; 345 uint64_t AccGfxclkBelowHostLimit; 346 } VfMetricsTable_t; 347 348 #endif 349