1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright 1997, Stefan Esser <se@freebsd.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 */
28
29 #ifndef _PCIVAR_H_
30 #define _PCIVAR_H_
31
32 #include <sys/queue.h>
33 #include <sys/_eventhandler.h>
34
35 /* some PCI bus constants */
36 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
37 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
38 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
39
40 typedef uint64_t pci_addr_t;
41
42 /* Config registers for PCI-PCI and PCI-Cardbus bridges. */
43 struct pcicfg_bridge {
44 uint8_t br_seclat;
45 uint8_t br_subbus;
46 uint8_t br_secbus;
47 uint8_t br_pribus;
48 uint16_t br_control;
49 };
50
51 /* Interesting values for PCI power management */
52 struct pcicfg_pp {
53 uint16_t pp_cap; /* PCI power management capabilities */
54 uint8_t pp_location; /* Offset of power management registers */
55 };
56
57 struct pci_map {
58 pci_addr_t pm_value; /* Raw BAR value */
59 pci_addr_t pm_size;
60 uint16_t pm_reg;
61 STAILQ_ENTRY(pci_map) pm_link;
62 };
63
64 struct vpd_readonly {
65 char keyword[2];
66 char *value;
67 int len;
68 };
69
70 struct vpd_write {
71 char keyword[2];
72 char *value;
73 int start;
74 int len;
75 };
76
77 struct pcicfg_vpd {
78 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
79 char vpd_cached;
80 char *vpd_ident; /* string identifier */
81 int vpd_rocnt;
82 struct vpd_readonly *vpd_ros;
83 int vpd_wcnt;
84 struct vpd_write *vpd_w;
85 };
86
87 /* Interesting values for PCI MSI */
88 struct pcicfg_msi {
89 uint16_t msi_ctrl; /* Message Control */
90 uint8_t msi_location; /* Offset of MSI capability registers. */
91 int msi_alloc; /* Number of allocated messages. */
92 uint64_t msi_addr; /* Contents of address register. */
93 uint16_t msi_data; /* Contents of data register. */
94 u_int msi_handlers;
95 };
96
97 /* Interesting values for PCI MSI-X */
98 struct msix_vector {
99 uint64_t mv_address; /* Contents of address register. */
100 uint32_t mv_data; /* Contents of data register. */
101 int mv_irq;
102 };
103
104 struct msix_table_entry {
105 u_int mte_vector; /* 1-based index into msix_vectors array. */
106 u_int mte_handlers;
107 };
108
109 struct pcicfg_msix {
110 uint16_t msix_ctrl; /* Message Control */
111 uint8_t msix_location; /* Offset of MSI-X capability registers. */
112 uint8_t msix_table_bar; /* BAR containing vector table. */
113 uint8_t msix_pba_bar; /* BAR containing PBA. */
114 uint32_t msix_table_offset;
115 uint32_t msix_pba_offset;
116 u_int msix_alloc; /* Number of allocated vectors. */
117 u_int msix_table_len; /* Length of virtual table. */
118 struct msix_table_entry *msix_table; /* Virtual table. */
119 struct msix_vector *msix_vectors; /* Array of allocated vectors. */
120 struct resource *msix_table_res; /* Resource containing vector table. */
121 struct resource *msix_pba_res; /* Resource containing PBA. */
122 };
123
124 struct pci_id_ofw_iommu {
125 uintptr_t xref;
126 uint32_t id;
127 };
128
129 /* Interesting values for HyperTransport */
130 struct pcicfg_ht {
131 uint8_t ht_slave; /* Non-zero if device is an HT slave. */
132 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
133 uint16_t ht_msictrl; /* MSI mapping control */
134 uint64_t ht_msiaddr; /* MSI mapping base address */
135 };
136
137 /* Interesting values for PCI-express */
138 struct pcicfg_pcie {
139 uint8_t pcie_location; /* Offset of PCI-e capability registers. */
140 uint8_t pcie_type; /* Device type. */
141 uint16_t pcie_flags; /* Device capabilities register. */
142 uint16_t pcie_device_ctl; /* Device control register. */
143 uint16_t pcie_link_ctl; /* Link control register. */
144 uint16_t pcie_slot_ctl; /* Slot control register. */
145 uint16_t pcie_root_ctl; /* Root control register. */
146 uint16_t pcie_device_ctl2; /* Second device control register. */
147 uint16_t pcie_link_ctl2; /* Second link control register. */
148 uint16_t pcie_slot_ctl2; /* Second slot control register. */
149 };
150
151 struct pcicfg_pcix {
152 uint16_t pcix_command;
153 uint8_t pcix_location; /* Offset of PCI-X capability registers. */
154 };
155
156 struct pcicfg_vf {
157 int index;
158 };
159
160 struct pci_ea_entry {
161 int eae_bei;
162 uint32_t eae_flags;
163 uint64_t eae_base;
164 uint64_t eae_max_offset;
165 uint32_t eae_cfg_offset;
166 STAILQ_ENTRY(pci_ea_entry) eae_link;
167 };
168
169 struct pcicfg_ea {
170 int ea_location; /* Structure offset in Configuration Header */
171 STAILQ_HEAD(, pci_ea_entry) ea_entries; /* EA entries */
172 };
173
174 #define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */
175
176 /* config header information common to all header types */
177 typedef struct pcicfg {
178 device_t dev; /* device which owns this */
179
180 STAILQ_HEAD(, pci_map) maps; /* BARs */
181
182 uint16_t subvendor; /* card vendor ID */
183 uint16_t subdevice; /* card device ID, assigned by card vendor */
184 uint16_t vendor; /* chip vendor ID */
185 uint16_t device; /* chip device ID, assigned by chip vendor */
186
187 uint16_t cmdreg; /* disable/enable chip and PCI options */
188 uint16_t statreg; /* supported PCI features and error state */
189
190 uint8_t baseclass; /* chip PCI class */
191 uint8_t subclass; /* chip PCI subclass */
192 uint8_t progif; /* chip PCI programming interface */
193 uint8_t revid; /* chip revision ID */
194
195 uint8_t hdrtype; /* chip config header type */
196 uint8_t cachelnsz; /* cache line size in 4byte units */
197 uint8_t intpin; /* PCI interrupt pin */
198 uint8_t intline; /* interrupt line (IRQ for PC arch) */
199
200 uint8_t mingnt; /* min. useful bus grant time in 250ns units */
201 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
202 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
203
204 uint8_t mfdev; /* multi-function device (from hdrtype reg) */
205 uint8_t nummaps; /* actual number of PCI maps used */
206
207 uint32_t domain; /* PCI domain */
208 uint8_t bus; /* config space bus address */
209 uint8_t slot; /* config space slot address */
210 uint8_t func; /* config space function number */
211
212 uint32_t flags; /* flags defined above */
213
214 struct pcicfg_bridge bridge; /* Bridges */
215 struct pcicfg_pp pp; /* Power management */
216 struct pcicfg_vpd vpd; /* Vital product data */
217 struct pcicfg_msi msi; /* PCI MSI */
218 struct pcicfg_msix msix; /* PCI MSI-X */
219 struct pcicfg_ht ht; /* HyperTransport */
220 struct pcicfg_pcie pcie; /* PCI Express */
221 struct pcicfg_pcix pcix; /* PCI-X */
222 struct pcicfg_iov *iov; /* SR-IOV */
223 struct pcicfg_vf vf; /* SR-IOV Virtual Function */
224 struct pcicfg_ea ea; /* Enhanced Allocation */
225 } pcicfgregs;
226
227 /* additional type 1 device config header information (PCI to PCI bridge) */
228
229 typedef struct {
230 pci_addr_t pmembase; /* base address of prefetchable memory */
231 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
232 uint32_t membase; /* base address of memory window */
233 uint32_t memlimit; /* topmost address of memory window */
234 uint32_t iobase; /* base address of port window */
235 uint32_t iolimit; /* topmost address of port window */
236 uint16_t secstat; /* secondary bus status register */
237 uint16_t bridgectl; /* bridge control register */
238 uint8_t seclat; /* CardBus latency timer */
239 } pcih1cfgregs;
240
241 /* additional type 2 device config header information (CardBus bridge) */
242
243 typedef struct {
244 uint32_t membase0; /* base address of memory window */
245 uint32_t memlimit0; /* topmost address of memory window */
246 uint32_t membase1; /* base address of memory window */
247 uint32_t memlimit1; /* topmost address of memory window */
248 uint32_t iobase0; /* base address of port window */
249 uint32_t iolimit0; /* topmost address of port window */
250 uint32_t iobase1; /* base address of port window */
251 uint32_t iolimit1; /* topmost address of port window */
252 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
253 uint16_t secstat; /* secondary bus status register */
254 uint16_t bridgectl; /* bridge control register */
255 uint8_t seclat; /* CardBus latency timer */
256 } pcih2cfgregs;
257
258 extern uint32_t pci_numdevs;
259 extern int pci_enable_aspm;
260
261 /*
262 * The bitfield has to be stable and match the fields below (so that
263 * match_flag_vendor must be bit 0) so we have to do the endian dance. We can't
264 * use enums or #define constants because then the macros for subsetting matches
265 * wouldn't work. These tables are parsed by devmatch and others to connect
266 * modules with devices on the PCI bus.
267 */
268 struct pci_device_table {
269 #if BYTE_ORDER == LITTLE_ENDIAN
270 uint16_t
271 match_flag_vendor:1,
272 match_flag_device:1,
273 match_flag_subvendor:1,
274 match_flag_subdevice:1,
275 match_flag_class:1,
276 match_flag_subclass:1,
277 match_flag_revid:1,
278 match_flag_unused:9;
279 #else
280 uint16_t
281 match_flag_unused:9,
282 match_flag_revid:1,
283 match_flag_subclass:1,
284 match_flag_class:1,
285 match_flag_subdevice:1,
286 match_flag_subvendor:1,
287 match_flag_device:1,
288 match_flag_vendor:1;
289 #endif
290 uint16_t vendor;
291 uint16_t device;
292 uint16_t subvendor;
293 uint16_t subdevice;
294 uint16_t class_id;
295 uint16_t subclass;
296 uint16_t revid;
297 uint16_t unused;
298 uintptr_t driver_data;
299 char *descr;
300 };
301
302 #define PCI_DEV(v, d) \
303 .match_flag_vendor = 1, .vendor = (v), \
304 .match_flag_device = 1, .device = (d)
305 #define PCI_SUBDEV(sv, sd) \
306 .match_flag_subvendor = 1, .subvendor = (sv), \
307 .match_flag_subdevice = 1, .subdevice = (sd)
308 #define PCI_CLASS(x) \
309 .match_flag_class = 1, .class_id = (x)
310 #define PCI_SUBCLASS(x) \
311 .match_flag_subclass = 1, .subclass = (x)
312 #define PCI_REVID(x) \
313 .match_flag_revid = 1, .revid = (x)
314 #define PCI_DESCR(x) \
315 .descr = (x)
316 #define PCI_PNP_STR \
317 "M16:mask;U16:vendor;U16:device;U16:subvendor;U16:subdevice;" \
318 "U16:class;U16:subclass;U16:revid;"
319 #define PCI_PNP_INFO(table) \
320 MODULE_PNP_INFO(PCI_PNP_STR, pci, table, table, \
321 sizeof(table) / sizeof(table[0]))
322
323 const struct pci_device_table *pci_match_device(device_t child,
324 const struct pci_device_table *id, size_t nelt);
325 #define PCI_MATCH(child, table) \
326 pci_match_device(child, (table), nitems(table));
327
328 /* Only if the prerequisites are present */
329 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
330 struct pci_devinfo {
331 STAILQ_ENTRY(pci_devinfo) pci_links;
332 struct resource_list resources;
333 pcicfgregs cfg;
334 struct pci_conf conf;
335 };
336 #endif
337
338 #ifdef _SYS_BUS_H_
339
340 #include "pci_if.h"
341
342 enum pci_device_ivars {
343 PCI_IVAR_SUBVENDOR,
344 PCI_IVAR_SUBDEVICE,
345 PCI_IVAR_VENDOR,
346 PCI_IVAR_DEVICE,
347 PCI_IVAR_DEVID,
348 PCI_IVAR_CLASS,
349 PCI_IVAR_SUBCLASS,
350 PCI_IVAR_PROGIF,
351 PCI_IVAR_REVID,
352 PCI_IVAR_INTPIN,
353 PCI_IVAR_IRQ,
354 PCI_IVAR_DOMAIN,
355 PCI_IVAR_BUS,
356 PCI_IVAR_SLOT,
357 PCI_IVAR_FUNCTION,
358 PCI_IVAR_ETHADDR,
359 PCI_IVAR_CMDREG,
360 PCI_IVAR_CACHELNSZ,
361 PCI_IVAR_MINGNT,
362 PCI_IVAR_MAXLAT,
363 PCI_IVAR_LATTIMER
364 };
365
366 /*
367 * Simplified accessors for pci devices
368 */
369 #define PCI_ACCESSOR(var, ivar, type) \
370 __BUS_ACCESSOR(pci, var, PCI, ivar, type)
371
PCI_ACCESSOR(subvendor,SUBVENDOR,uint16_t)372 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
373 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
374 PCI_ACCESSOR(vendor, VENDOR, uint16_t)
375 PCI_ACCESSOR(device, DEVICE, uint16_t)
376 PCI_ACCESSOR(devid, DEVID, uint32_t)
377 PCI_ACCESSOR(class, CLASS, uint8_t)
378 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
379 PCI_ACCESSOR(progif, PROGIF, uint8_t)
380 PCI_ACCESSOR(revid, REVID, uint8_t)
381 PCI_ACCESSOR(intpin, INTPIN, uint8_t)
382 PCI_ACCESSOR(irq, IRQ, uint8_t)
383 PCI_ACCESSOR(domain, DOMAIN, uint32_t)
384 PCI_ACCESSOR(bus, BUS, uint8_t)
385 PCI_ACCESSOR(slot, SLOT, uint8_t)
386 PCI_ACCESSOR(function, FUNCTION, uint8_t)
387 PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
388 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
389 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
390 PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
391 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
392 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
393
394 #undef PCI_ACCESSOR
395
396 /*
397 * Operations on configuration space.
398 */
399 static __inline uint32_t
400 pci_read_config(device_t dev, int reg, int width)
401 {
402 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
403 }
404
405 static __inline void
pci_write_config(device_t dev,int reg,uint32_t val,int width)406 pci_write_config(device_t dev, int reg, uint32_t val, int width)
407 {
408 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
409 }
410
411 /*
412 * Ivars for pci bridges.
413 */
414
415 /*typedef enum pci_device_ivars pcib_device_ivars;*/
416 enum pcib_device_ivars {
417 PCIB_IVAR_DOMAIN,
418 PCIB_IVAR_BUS
419 };
420
421 #define PCIB_ACCESSOR(var, ivar, type) \
422 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
423
PCIB_ACCESSOR(domain,DOMAIN,uint32_t)424 PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
425 PCIB_ACCESSOR(bus, BUS, uint32_t)
426
427 #undef PCIB_ACCESSOR
428
429 /*
430 * PCI interrupt validation. Invalid interrupt values such as 0 or 128
431 * on i386 or other platforms should be mapped out in the MD pcireadconf
432 * code and not here, since the only MI invalid IRQ is 255.
433 */
434 #define PCI_INVALID_IRQ 255
435 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
436
437 /*
438 * Convenience functions.
439 *
440 * These should be used in preference to manually manipulating
441 * configuration space.
442 */
443 static __inline int
444 pci_enable_busmaster(device_t dev)
445 {
446 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
447 }
448
449 static __inline int
pci_disable_busmaster(device_t dev)450 pci_disable_busmaster(device_t dev)
451 {
452 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
453 }
454
455 static __inline int
pci_enable_io(device_t dev,int space)456 pci_enable_io(device_t dev, int space)
457 {
458 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
459 }
460
461 static __inline int
pci_disable_io(device_t dev,int space)462 pci_disable_io(device_t dev, int space)
463 {
464 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
465 }
466
467 static __inline int
pci_get_vpd_ident(device_t dev,const char ** identptr)468 pci_get_vpd_ident(device_t dev, const char **identptr)
469 {
470 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
471 }
472
473 static __inline int
pci_get_vpd_readonly(device_t dev,const char * kw,const char ** vptr)474 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr)
475 {
476 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr));
477 }
478
479 /*
480 * Check if the address range falls within the VGA defined address range(s)
481 */
482 static __inline int
pci_is_vga_ioport_range(rman_res_t start,rman_res_t end)483 pci_is_vga_ioport_range(rman_res_t start, rman_res_t end)
484 {
485
486 return (((start >= 0x3b0 && end <= 0x3bb) ||
487 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
488 }
489
490 static __inline int
pci_is_vga_memory_range(rman_res_t start,rman_res_t end)491 pci_is_vga_memory_range(rman_res_t start, rman_res_t end)
492 {
493
494 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
495 }
496
497 /*
498 * PCI power states are as defined by ACPI:
499 *
500 * D0 State in which device is on and running. It is receiving full
501 * power from the system and delivering full functionality to the user.
502 * D1 Class-specific low-power state in which device context may or may not
503 * be lost. Buses in D1 cannot do anything to the bus that would force
504 * devices on that bus to lose context.
505 * D2 Class-specific low-power state in which device context may or may
506 * not be lost. Attains greater power savings than D1. Buses in D2
507 * can cause devices on that bus to lose some context. Devices in D2
508 * must be prepared for the bus to be in D2 or higher.
509 * D3hot State in which the device is off and not running. Device context is
510 * lost. Power can be removed from the device.
511 * D3cold Same as D3hot, but power has been removed from the device.
512 */
513 #define PCI_POWERSTATE_D0 0
514 #define PCI_POWERSTATE_D1 1
515 #define PCI_POWERSTATE_D2 2
516 #define PCI_POWERSTATE_D3_HOT 3
517 #define PCI_POWERSTATE_D3_COLD 4
518 #define PCI_POWERSTATE_D3 PCI_POWERSTATE_D3_COLD
519 #define PCI_POWERSTATE_MAX PCI_POWERSTATE_D3_COLD
520 #define PCI_POWERSTATE_COUNT 5
521 #define PCI_POWERSTATE_UNKNOWN -1
522
523 static __inline const char *
pci_powerstate_to_str(int state)524 pci_powerstate_to_str(int state)
525 {
526 const char *strs[PCI_POWERSTATE_COUNT] = {"D0", "D1", "D2", "D3hot",
527 "D3cold"};
528
529 MPASS(state >= PCI_POWERSTATE_D0 && state <= PCI_POWERSTATE_MAX);
530 return (strs[state]);
531 }
532
533 static __inline int
pci_set_powerstate(device_t dev,int state)534 pci_set_powerstate(device_t dev, int state)
535 {
536 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
537 }
538
539 static __inline int
pci_get_powerstate(device_t dev)540 pci_get_powerstate(device_t dev)
541 {
542 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
543 }
544
545 static __inline int
pci_find_cap(device_t dev,int capability,int * capreg)546 pci_find_cap(device_t dev, int capability, int *capreg)
547 {
548 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg));
549 }
550
551 static __inline int
pci_find_next_cap(device_t dev,int capability,int start,int * capreg)552 pci_find_next_cap(device_t dev, int capability, int start, int *capreg)
553 {
554 return (PCI_FIND_NEXT_CAP(device_get_parent(dev), dev, capability, start,
555 capreg));
556 }
557
558 static __inline int
pci_find_extcap(device_t dev,int capability,int * capreg)559 pci_find_extcap(device_t dev, int capability, int *capreg)
560 {
561 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg));
562 }
563
564 static __inline int
pci_find_next_extcap(device_t dev,int capability,int start,int * capreg)565 pci_find_next_extcap(device_t dev, int capability, int start, int *capreg)
566 {
567 return (PCI_FIND_NEXT_EXTCAP(device_get_parent(dev), dev, capability,
568 start, capreg));
569 }
570
571 static __inline int
pci_find_htcap(device_t dev,int capability,int * capreg)572 pci_find_htcap(device_t dev, int capability, int *capreg)
573 {
574 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg));
575 }
576
577 static __inline int
pci_find_next_htcap(device_t dev,int capability,int start,int * capreg)578 pci_find_next_htcap(device_t dev, int capability, int start, int *capreg)
579 {
580 return (PCI_FIND_NEXT_HTCAP(device_get_parent(dev), dev, capability,
581 start, capreg));
582 }
583
584 static __inline int
pci_alloc_msi(device_t dev,int * count)585 pci_alloc_msi(device_t dev, int *count)
586 {
587 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
588 }
589
590 static __inline int
pci_alloc_msix(device_t dev,int * count)591 pci_alloc_msix(device_t dev, int *count)
592 {
593 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
594 }
595
596 static __inline void
pci_enable_msi(device_t dev,uint64_t address,uint16_t data)597 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
598 {
599 PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data);
600 }
601
602 static __inline void
pci_enable_msix(device_t dev,u_int index,uint64_t address,uint32_t data)603 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
604 {
605 PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data);
606 }
607
608 static __inline void
pci_disable_msi(device_t dev)609 pci_disable_msi(device_t dev)
610 {
611 PCI_DISABLE_MSI(device_get_parent(dev), dev);
612 }
613
614 static __inline int
pci_remap_msix(device_t dev,int count,const u_int * vectors)615 pci_remap_msix(device_t dev, int count, const u_int *vectors)
616 {
617 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
618 }
619
620 static __inline int
pci_release_msi(device_t dev)621 pci_release_msi(device_t dev)
622 {
623 return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
624 }
625
626 static __inline int
pci_msi_count(device_t dev)627 pci_msi_count(device_t dev)
628 {
629 return (PCI_MSI_COUNT(device_get_parent(dev), dev));
630 }
631
632 static __inline int
pci_msix_count(device_t dev)633 pci_msix_count(device_t dev)
634 {
635 return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
636 }
637
638 static __inline int
pci_msix_pba_bar(device_t dev)639 pci_msix_pba_bar(device_t dev)
640 {
641 return (PCI_MSIX_PBA_BAR(device_get_parent(dev), dev));
642 }
643
644 static __inline int
pci_msix_table_bar(device_t dev)645 pci_msix_table_bar(device_t dev)
646 {
647 return (PCI_MSIX_TABLE_BAR(device_get_parent(dev), dev));
648 }
649
650 static __inline int
pci_get_id(device_t dev,enum pci_id_type type,uintptr_t * id)651 pci_get_id(device_t dev, enum pci_id_type type, uintptr_t *id)
652 {
653 return (PCI_GET_ID(device_get_parent(dev), dev, type, id));
654 }
655
656 /*
657 * This is the deprecated interface, there is no way to tell the difference
658 * between a failure and a valid value that happens to be the same as the
659 * failure value.
660 */
661 static __inline uint16_t
pci_get_rid(device_t dev)662 pci_get_rid(device_t dev)
663 {
664 uintptr_t rid;
665
666 if (pci_get_id(dev, PCI_ID_RID, &rid) != 0)
667 return (0);
668
669 return (rid);
670 }
671
672 static __inline void
pci_child_added(device_t dev)673 pci_child_added(device_t dev)
674 {
675
676 return (PCI_CHILD_ADDED(device_get_parent(dev), dev));
677 }
678
679 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
680 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
681 device_t pci_find_device(uint16_t, uint16_t);
682 device_t pci_find_class(uint8_t class, uint8_t subclass);
683 device_t pci_find_class_from(uint8_t class, uint8_t subclass, device_t devfrom);
684 device_t pci_find_base_class_from(uint8_t class, device_t devfrom);
685
686 /* Can be used by drivers to manage the MSI-X table. */
687 int pci_pending_msix(device_t dev, u_int index);
688
689 int pci_msi_device_blacklisted(device_t dev);
690 int pci_msix_device_blacklisted(device_t dev);
691
692 void pci_ht_map_msi(device_t dev, uint64_t addr);
693
694 device_t pci_find_pcie_root_port(device_t dev);
695 int pci_get_relaxed_ordering_enabled(device_t dev);
696 int pci_get_max_payload(device_t dev);
697 int pci_get_max_read_req(device_t dev);
698 void pci_restore_state(device_t dev);
699 void pci_save_state(device_t dev);
700 int pci_set_max_read_req(device_t dev, int size);
701 int pci_power_reset(device_t dev);
702 void pci_clear_pme(device_t dev);
703 void pci_enable_pme(device_t dev);
704 bool pci_has_pm(device_t dev);
705 uint32_t pcie_read_config(device_t dev, int reg, int width);
706 void pcie_write_config(device_t dev, int reg, uint32_t value, int width);
707 uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask,
708 uint32_t value, int width);
709 void pcie_apei_error(device_t dev, int sev, uint8_t *aer);
710 bool pcie_flr(device_t dev, u_int max_delay, bool force);
711 int pcie_get_max_completion_timeout(device_t dev);
712 bool pcie_wait_for_pending_transactions(device_t dev, u_int max_delay);
713 int pcie_link_reset(device_t port, int pcie_location);
714
715 void pci_print_faulted_dev(void);
716
717 #endif /* _SYS_BUS_H_ */
718
719 /*
720 * cdev switch for control device, initialised in generic PCI code
721 */
722 extern struct cdevsw pcicdev;
723
724 /*
725 * List of all PCI devices, generation count for the list.
726 */
727 STAILQ_HEAD(devlist, pci_devinfo);
728
729 extern struct devlist pci_devq;
730 extern uint32_t pci_generation;
731
732 struct pci_map *pci_find_bar(device_t dev, int reg);
733 struct pci_map *pci_first_bar(device_t dev);
734 struct pci_map *pci_next_bar(struct pci_map *pm);
735 int pci_bar_enabled(device_t dev, struct pci_map *pm);
736 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev);
737
738 #define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000
739 #define VGA_PCI_BIOS_SHADOW_SIZE 131072
740
741 int vga_pci_is_boot_display(device_t dev);
742 void * vga_pci_map_bios(device_t dev, size_t *size);
743 void vga_pci_unmap_bios(device_t dev, void *bios);
744 int vga_pci_repost(device_t dev);
745
746 /**
747 * Global eventhandlers invoked when PCI devices are added or removed
748 * from the system.
749 */
750 typedef void (*pci_event_fn)(void *arg, device_t dev);
751 EVENTHANDLER_DECLARE(pci_add_device, pci_event_fn);
752 EVENTHANDLER_DECLARE(pci_delete_device, pci_event_fn);
753
754 #endif /* _PCIVAR_H_ */
755