xref: /titanic_41/usr/src/uts/common/sys/pci.h (revision 265a3f1d64f26bd7637bd62d476fc0fb08785666)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  * Copyright 2016 Joyent, Inc.
25  */
26 
27 #ifndef	_SYS_PCI_H
28 #define	_SYS_PCI_H
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 /*
35  * PCI Configuration Header offsets
36  */
37 #define	PCI_CONF_VENID		0x0	/* vendor id, 2 bytes */
38 #define	PCI_CONF_DEVID		0x2	/* device id, 2 bytes */
39 #define	PCI_CONF_COMM		0x4	/* command register, 2 bytes */
40 #define	PCI_CONF_STAT		0x6	/* status register, 2 bytes */
41 #define	PCI_CONF_REVID		0x8	/* revision id, 1 byte */
42 #define	PCI_CONF_PROGCLASS	0x9	/* programming class code, 1 byte */
43 #define	PCI_CONF_SUBCLASS	0xA	/* sub-class code, 1 byte */
44 #define	PCI_CONF_BASCLASS	0xB	/* basic class code, 1 byte */
45 #define	PCI_CONF_CACHE_LINESZ	0xC	/* cache line size, 1 byte */
46 #define	PCI_CONF_LATENCY_TIMER	0xD	/* latency timer, 1 byte */
47 #define	PCI_CONF_HEADER		0xE	/* header type, 1 byte */
48 #define	PCI_CONF_BIST		0xF	/* builtin self test, 1 byte */
49 
50 /*
51  * Header type 0 offsets
52  */
53 #define	PCI_CONF_BASE0		0x10	/* base register 0, 4 bytes */
54 #define	PCI_CONF_BASE1		0x14	/* base register 1, 4 bytes */
55 #define	PCI_CONF_BASE2		0x18	/* base register 2, 4 bytes */
56 #define	PCI_CONF_BASE3		0x1c	/* base register 3, 4 bytes */
57 #define	PCI_CONF_BASE4		0x20	/* base register 4, 4 bytes */
58 #define	PCI_CONF_BASE5		0x24	/* base register 5, 4 bytes */
59 #define	PCI_CONF_CIS		0x28	/* Cardbus CIS Pointer */
60 #define	PCI_CONF_SUBVENID	0x2c	/* Subsystem Vendor ID */
61 #define	PCI_CONF_SUBSYSID	0x2e	/* Subsystem ID */
62 #define	PCI_CONF_ROM		0x30	/* ROM base register, 4 bytes */
63 #define	PCI_CONF_CAP_PTR	0x34	/* capabilities pointer, 1 byte */
64 #define	PCI_CONF_ILINE		0x3c	/* interrupt line, 1 byte */
65 #define	PCI_CONF_IPIN		0x3d	/* interrupt pin, 1 byte */
66 #define	PCI_CONF_MIN_G		0x3e	/* minimum grant, 1 byte */
67 #define	PCI_CONF_MAX_L		0x3f	/* maximum grant, 1 byte */
68 
69 /*
70  * PCI to PCI bridge configuration space header format
71  */
72 #define	PCI_BCNF_PRIBUS		0x18	/* primary bus number */
73 #define	PCI_BCNF_SECBUS		0x19	/* secondary bus number */
74 #define	PCI_BCNF_SUBBUS		0x1a	/* subordinate bus number */
75 #define	PCI_BCNF_LATENCY_TIMER	0x1b
76 #define	PCI_BCNF_IO_BASE_LOW	0x1c
77 #define	PCI_BCNF_IO_LIMIT_LOW	0x1d
78 #define	PCI_BCNF_SEC_STATUS	0x1e
79 #define	PCI_BCNF_MEM_BASE	0x20
80 #define	PCI_BCNF_MEM_LIMIT	0x22
81 #define	PCI_BCNF_PF_BASE_LOW	0x24
82 #define	PCI_BCNF_PF_LIMIT_LOW	0x26
83 #define	PCI_BCNF_PF_BASE_HIGH	0x28
84 #define	PCI_BCNF_PF_LIMIT_HIGH	0x2c
85 #define	PCI_BCNF_IO_BASE_HI	0x30
86 #define	PCI_BCNF_IO_LIMIT_HI	0x32
87 #define	PCI_BCNF_CAP_PTR	0x34
88 #define	PCI_BCNF_ROM		0x38
89 #define	PCI_BCNF_ILINE		0x3c
90 #define	PCI_BCNF_IPIN		0x3d
91 #define	PCI_BCNF_BCNTRL		0x3e
92 
93 #define	PCI_BCNF_BASE_NUM	0x2
94 
95 /*
96  * PCI to PCI bridge control register (0x3e) format
97  */
98 #define	PCI_BCNF_BCNTRL_PARITY_ENABLE	0x1
99 #define	PCI_BCNF_BCNTRL_SERR_ENABLE	0x2
100 #define	PCI_BCNF_BCNTRL_ISA_ENABLE	0x4
101 #define	PCI_BCNF_BCNTRL_VGA_ENABLE	0x8
102 #define	PCI_BCNF_BCNTRL_MAST_AB_MODE	0x20
103 #define	PCI_BCNF_BCNTRL_DTO_STAT	0x400
104 
105 #define	PCI_BCNF_BCNTRL_RESET		0x0040
106 #define	PCI_BCNF_BCNTRL_B2B_ENAB	0x0080
107 
108 #define	PCI_BCNF_IO_MASK	0xf0
109 #define	PCI_BCNF_IO_SHIFT	8
110 #define	PCI_BCNF_MEM_MASK	0xfff0
111 #define	PCI_BCNF_MEM_SHIFT	16
112 #define	PCI_BCNF_ADDR_MASK	0x000f
113 
114 #define	PCI_BCNF_IO_32BIT	0x01
115 #define	PCI_BCNF_PF_MEM_64BIT	0x01
116 
117 /*
118  * Header type 2 (Cardbus) offsets
119  */
120 #define	PCI_CBUS_SOCK_REG	0x10	/* Cardbus socket regs, 4 bytes */
121 #define	PCI_CBUS_CAP_PTR	0x14	/* Capability ptr, 1 byte */
122 #define	PCI_CBUS_RESERVED1	0x15	/* Reserved, 1 byte */
123 #define	PCI_CBUS_SEC_STATUS	0x16	/* Secondary status, 2 bytes */
124 #define	PCI_CBUS_PCI_BUS_NO	0x18	/* PCI bus number, 1 byte */
125 #define	PCI_CBUS_CBUS_NO	0x19	/* Cardbus bus number, 1 byte */
126 #define	PCI_CBUS_SUB_BUS_NO	0x1a	/* Subordinate bus number, 1 byte */
127 #define	PCI_CBUS_LATENCY_TIMER	0x1b	/* Cardbus latency timer, 1 byte */
128 #define	PCI_CBUS_MEM_BASE0	0x1c	/* Memory base reg 0, 4 bytes */
129 #define	PCI_CBUS_MEM_LIMIT0	0x20	/* Memory limit reg 0, 4 bytes */
130 #define	PCI_CBUS_MEM_BASE1	0x24	/* Memory base reg 1, 4 bytes */
131 #define	PCI_CBUS_MEM_LIMIT1	0x28	/* Memory limit reg 1, 4 bytes */
132 #define	PCI_CBUS_IO_BASE0	0x2c	/* IO base reg 0, 4 bytes */
133 #define	PCI_CBUS_IO_LIMIT0	0x30	/* IO limit reg 0, 4 bytes */
134 #define	PCI_CBUS_IO_BASE1	0x34	/* IO base reg 1, 4 bytes */
135 #define	PCI_CBUS_IO_LIMIT1	0x38	/* IO limit reg 1, 4 bytes */
136 #define	PCI_CBUS_ILINE		0x3c	/* interrupt line, 1 byte */
137 #define	PCI_CBUS_IPIN		0x3d	/* interrupt pin, 1 byte */
138 #define	PCI_CBUS_BRIDGE_CTRL	0x3e	/* Bridge control, 2 bytes */
139 #define	PCI_CBUS_SUBVENID	0x40	/* Subsystem Vendor ID, 2 bytes */
140 #define	PCI_CBUS_SUBSYSID	0x42	/* Subsystem ID, 2 bytes */
141 #define	PCI_CBUS_LEG_MODE_ADDR	0x44	/* PCCard 16bit IF legacy mode addr */
142 
143 #define	PCI_CBUS_BASE_NUM	0x1	/* number of base registers */
144 
145 /*
146  * PCI command register bits
147  */
148 #define	PCI_COMM_IO		0x1	/* I/O access enable */
149 #define	PCI_COMM_MAE		0x2	/* memory access enable */
150 #define	PCI_COMM_ME		0x4	/* master enable */
151 #define	PCI_COMM_SPEC_CYC	0x8
152 #define	PCI_COMM_MEMWR_INVAL	0x10
153 #define	PCI_COMM_PALETTE_SNOOP	0x20
154 #define	PCI_COMM_PARITY_DETECT	0x40
155 #define	PCI_COMM_WAIT_CYC_ENAB	0x80
156 #define	PCI_COMM_SERR_ENABLE	0x100
157 #define	PCI_COMM_BACK2BACK_ENAB	0x200
158 #define	PCI_COMM_INTX_DISABLE	0x400	/* INTx emulation disable */
159 
160 /*
161  * PCI Interrupt pin value
162  */
163 #define	PCI_INTA	1
164 #define	PCI_INTB	2
165 #define	PCI_INTC	3
166 #define	PCI_INTD	4
167 
168 /*
169  * PCI status register bits
170  */
171 #define	PCI_STAT_INTR		0x8	/* Interrupt state */
172 #define	PCI_STAT_CAP		0x10	/* Implements Capabilities */
173 #define	PCI_STAT_66MHZ		0x20	/* 66 MHz capable */
174 #define	PCI_STAT_UDF		0x40	/* UDF supported */
175 #define	PCI_STAT_FBBC		0x80	/* Fast Back-to-Back Capable */
176 #define	PCI_STAT_S_PERROR	0x100	/* Data Parity Reported */
177 #define	PCI_STAT_DEVSELT	0x600	/* Device select timing */
178 #define	PCI_STAT_S_TARG_AB	0x800	/* Signaled Target Abort */
179 #define	PCI_STAT_R_TARG_AB	0x1000	/* Received Target Abort */
180 #define	PCI_STAT_R_MAST_AB	0x2000	/* Received Master Abort */
181 #define	PCI_STAT_S_SYSERR	0x4000	/* Signaled System Error */
182 #define	PCI_STAT_PERROR		0x8000	/* Detected Parity Error */
183 
184 /*
185  * DEVSEL timing values
186  */
187 #define	PCI_STAT_DEVSELT_FAST	0x0000
188 #define	PCI_STAT_DEVSELT_MEDIUM	0x0200
189 #define	PCI_STAT_DEVSELT_SLOW	0x0400
190 
191 /*
192  * BIST values
193  */
194 #define	PCI_BIST_SUPPORTED	0x80
195 #define	PCI_BIST_GO		0x40
196 #define	PCI_BIST_RESULT_M	0x0f
197 #define	PCI_BIST_RESULT_OK	0x00
198 
199 /*
200  * PCI class codes
201  */
202 #define	PCI_CLASS_NONE		0x0	/* class code for pre-2.0 devices */
203 #define	PCI_CLASS_MASS		0x1	/* Mass storage Controller class */
204 #define	PCI_CLASS_NET		0x2	/* Network Controller class */
205 #define	PCI_CLASS_DISPLAY	0x3	/* Display Controller class */
206 #define	PCI_CLASS_MM		0x4	/* Multimedia Controller class */
207 #define	PCI_CLASS_MEM		0x5	/* Memory Controller class */
208 #define	PCI_CLASS_BRIDGE	0x6	/* Bridge Controller class */
209 #define	PCI_CLASS_COMM		0x7	/* Communications Controller class */
210 #define	PCI_CLASS_PERIPH	0x8	/* Peripheral Controller class */
211 #define	PCI_CLASS_INPUT		0x9	/* Input Device class */
212 #define	PCI_CLASS_DOCK		0xa	/* Docking Station class */
213 #define	PCI_CLASS_PROCESSOR	0xb	/* Processor class */
214 #define	PCI_CLASS_SERIALBUS	0xc	/* Serial Bus class */
215 #define	PCI_CLASS_WIRELESS	0xd	/* Wireless Controller class */
216 #define	PCI_CLASS_INTIO		0xe	/* Intelligent IO Controller class */
217 #define	PCI_CLASS_SATELLITE	0xf	/* Satellite Communication class */
218 #define	PCI_CLASS_CRYPT		0x10	/* Encrytion/Decryption class */
219 #define	PCI_CLASS_SIGNAL	0x11	/* Signal Processing class */
220 
221 /*
222  * PCI Sub-class codes - base class 0x0 (no new devices should use this code).
223  */
224 #define	PCI_NONE_NOTVGA		0x0	/* All devices except VGA compatible */
225 #define	PCI_NONE_VGA		0x1	/* VGA compatible */
226 
227 /*
228  * PCI Sub-class codes - base class 0x1 (mass storage controllers)
229  */
230 #define	PCI_MASS_SCSI		0x0	/* SCSI bus Controller */
231 #define	PCI_MASS_IDE		0x1	/* IDE Controller */
232 #define	PCI_MASS_FD		0x2	/* Floppy disk Controller */
233 #define	PCI_MASS_IPI		0x3	/* IPI bus Controller */
234 #define	PCI_MASS_RAID		0x4	/* RAID Controller */
235 #define	PCI_MASS_ATA		0x5	/* ATA Controller */
236 #define	PCI_MASS_SATA		0x6	/* Serial ATA */
237 #define	PCI_MASS_SAS		0x7	/* Serial Attached SCSI (SAS) Cntrlr */
238 #define	PCI_MASS_OTHER		0x80	/* Other Mass Storage Controller */
239 
240 /*
241  * programming interface for IDE (subclass 1)
242  */
243 #define	PCI_IDE_IF_NATIVE_PRI	0x1	/* primary channel is native */
244 #define	PCI_IDE_IF_PROG_PRI	0x2	/* primary can operate in either mode */
245 #define	PCI_IDE_IF_NATIVE_SEC	0x4	/* secondary channel is native */
246 #define	PCI_IDE_IF_PROG_SEC	0x8	/* sec. can operate in either mode */
247 #define	PCI_IDE_IF_MASK		0xf	/* programming interface mask */
248 
249 
250 /*
251  * programming interface for ATA (subclass 5)
252  */
253 #define	PCI_ATA_IF_SINGLE_DMA	0x20	/* ATA controller with single DMA */
254 #define	PCI_ATA_IF_CHAINED_DMA	0x30	/* ATA controller with chained DMA */
255 
256 /*
257  * programming interface for ATA (subclass 6) for SATA
258  */
259 #define	PCI_SATA_VS_INTERFACE	0x0	/* SATA Ctlr Vendor Specific Intfc */
260 #define	PCI_SATA_AHCI_INTERFACE	0x1	/* SATA Ctlr AHCI 1.0 Interface */
261 #define	PCI_SATA_SSB_INTERFACE	0x2	/* Serial Storage Bus Interface */
262 
263 /*
264  * programming interface for ATA (subclass 7) for SAS
265  */
266 #define	PCI_SAS_CONTROLLER	0x0	/* SAS Controller */
267 #define	PCI_SAS_BUS_INTERFACE	0x1	/* Serial Storage Bus Interface */
268 
269 /*
270  * PCI Sub-class codes - base class 0x2 (Network controllers)
271  */
272 #define	PCI_NET_ENET		0x0	/* Ethernet Controller */
273 #define	PCI_NET_TOKEN		0x1	/* Token Ring Controller */
274 #define	PCI_NET_FDDI		0x2	/* FDDI Controller */
275 #define	PCI_NET_ATM		0x3	/* ATM Controller */
276 #define	PCI_NET_ISDN		0x4	/* ISDN Controller */
277 #define	PCI_NET_WFIP		0x5	/* WorldFip Controller */
278 #define	PCI_NET_PICMG		0x6	/* PICMG 2.14 Multi Computing */
279 #define	PCI_NET_OTHER		0x80	/* Other Network Controller */
280 
281 /*
282  * PCI Sub-class codes - base class 03 (display controllers)
283  */
284 #define	PCI_DISPLAY_VGA		0x0	/* VGA device */
285 #define	PCI_DISPLAY_XGA		0x1	/* XGA device */
286 #define	PCI_DISPLAY_3D		0x2	/* 3D controller */
287 #define	PCI_DISPLAY_OTHER	0x80	/* Other Display Device */
288 
289 /*
290  * programming interface for display for display class (subclass 0) VGA ctrlrs
291  */
292 #define	PCI_DISPLAY_IF_VGA	0x0	/* VGA compatible */
293 #define	PCI_DISPLAY_IF_8514	0x1	/* 8514 compatible */
294 
295 /*
296  * PCI Sub-class codes - base class 0x4 (multi-media devices)
297  */
298 #define	PCI_MM_VIDEO		0x0	/* Video device */
299 #define	PCI_MM_AUDIO		0x1	/* Audio device */
300 #define	PCI_MM_TELEPHONY	0x2	/* Computer Telephony device */
301 #define	PCI_MM_MIXED_MODE	0x3	/* Mixed Mode device */
302 #define	PCI_MM_OTHER		0x80	/* Other Multimedia Device */
303 
304 /*
305  * PCI Sub-class codes - base class 0x5 (memory controllers)
306  */
307 #define	PCI_MEM_RAM		0x0	/* RAM device */
308 #define	PCI_MEM_FLASH		0x1	/* FLASH device */
309 #define	PCI_MEM_OTHER		0x80	/* Other Memory Controller */
310 
311 /*
312  * PCI Sub-class codes - base class 0x6 (Bridge devices)
313  */
314 #define	PCI_BRIDGE_HOST		0x0	/* Host/PCI Bridge */
315 #define	PCI_BRIDGE_ISA		0x1	/* PCI/ISA Bridge */
316 #define	PCI_BRIDGE_EISA		0x2	/* PCI/EISA Bridge */
317 #define	PCI_BRIDGE_MC		0x3	/* PCI/MC Bridge */
318 #define	PCI_BRIDGE_PCI		0x4	/* PCI/PCI Bridge */
319 #define	PCI_BRIDGE_PCMCIA	0x5	/* PCI/PCMCIA Bridge */
320 #define	PCI_BRIDGE_NUBUS	0x6	/* PCI/NUBUS Bridge */
321 #define	PCI_BRIDGE_CARDBUS	0x7	/* PCI/CARDBUS Bridge */
322 #define	PCI_BRIDGE_RACE		0x8	/* RACE-way Bridge */
323 #define	PCI_BRIDGE_STPCI	0x9	/* Semi-transparent PCI/PCI Bridge */
324 #define	PCI_BRIDGE_IB		0xA	/* InfiniBand/PCI host Bridge */
325 #define	PCI_BRIDGE_AS		0xB	/* AS/PCI host Bridge */
326 #define	PCI_BRIDGE_OTHER	0x80	/* PCI/Other Bridge Device */
327 
328 /*
329  * programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge
330  */
331 #define	PCI_BRIDGE_PCI_IF_PCI2PCI	0x0	/* PCI-PCI bridge */
332 #define	PCI_BRIDGE_PCI_IF_SUBDECODE	0x1	/* Subtractive Decode */
333 						/* PCI/PCI bridge */
334 
335 /*
336  * programming interface for Bridges class 0x6 (subclass 08) RACEway bridge
337  */
338 #define	PCI_BRIDGE_RACE_IF_TRANSPARENT	0x0	/* Transport mode */
339 #define	PCI_BRIDGE_RACE_IF_ENDPOINT	0x1	/* Endpoint mode */
340 
341 /*
342  * programming interface for Bridges class 0x6 (subclass 09)
343  * Semi-transparent PCI-to-PCI bridge
344  */
345 #define	PCI_BRIDGE_STPCI_IF_PRIMARY	0x40	/* primary PCI side bus */
346 						/* facing system processor */
347 #define	PCI_BRIDGE_STPCI_IF_SECONDARY	0x80	/* secondary PCI side bus */
348 						/* facing system processor */
349 
350 /*
351  * programming interface for Bridges class 0x6 (subclass 0B) AS bridge
352  */
353 #define	PCI_BRIDGE_AS_CUSTOM_INTFC	0x0	/* Custom interface */
354 #define	PCI_BRIDGE_AS_PORTAL_INTFC	0x1	/* ASI-SIG Portal Interface */
355 
356 /*
357  * PCI Sub-class codes - base class 0x7 (communication devices)
358  */
359 #define	PCI_COMM_GENERIC_XT	0x0	/* XT Compatible Serial Controller */
360 #define	PCI_COMM_PARALLEL	0x1	/* Parallel Port Controller */
361 #define	PCI_COMM_MSC		0x2	/* Multiport Serial Controller */
362 #define	PCI_COMM_MODEM		0x3	/* Modem Controller */
363 #define	PCI_COMM_GPIB		0x4	/* GPIB Controller */
364 #define	PCI_COMM_SMARTCARD	0x5	/* Smart Card Controller */
365 #define	PCI_COMM_OTHER		0x80	/* Other Communications Controller */
366 
367 /*
368  * Programming interfaces for class 0x7 / subclass 0x0 (Serial)
369  */
370 #define	PCI_COMM_SERIAL_IF_GENERIC	0x0	/* Generic XT-compat serial */
371 #define	PCI_COMM_SERIAL_IF_16450	0x1	/* 16450-compat serial ctrlr */
372 #define	PCI_COMM_SERIAL_IF_16550	0x2	/* 16550-compat serial ctrlr */
373 #define	PCI_COMM_SERIAL_IF_16650	0x3	/* 16650-compat serial ctrlr */
374 #define	PCI_COMM_SERIAL_IF_16750	0x4	/* 16750-compat serial ctrlr */
375 #define	PCI_COMM_SERIAL_IF_16850	0x5	/* 16850-compat serial ctrlr */
376 #define	PCI_COMM_SERIAL_IF_16950	0x6	/* 16950-compat serial ctrlr */
377 
378 /*
379  * Programming interfaces for class 0x7 / subclass 0x1 (Parallel)
380  */
381 #define	PCI_COMM_PARALLEL_IF_GENERIC	0x0	/* Generic Parallel port */
382 #define	PCI_COMM_PARALLEL_IF_BIDIRECT	0x1	/* Bi-directional Parallel */
383 #define	PCI_COMM_PARALLEL_IF_ECP	0x2	/* ECP 1.X Parallel port */
384 #define	PCI_COMM_PARALLEL_IF_1284	0x3	/* IEEE 1284 Parallel port */
385 #define	PCI_COMM_PARALLEL_IF_1284_TARG	0xFE	/* IEEE 1284 target device */
386 
387 /*
388  * Programming interfaces for class 0x7 / subclass 0x3 (Modem)
389  */
390 #define	PCI_COMM_MODEM_IF_GENERIC	0x0	/* Generic Modem */
391 #define	PCI_COMM_MODEM_IF_HAYES_16450	0x1	/* Hayes 16450-compat Modem */
392 #define	PCI_COMM_MODEM_IF_HAYES_16550	0x2	/* Hayes 16550-compat Modem */
393 #define	PCI_COMM_MODEM_IF_HAYES_16650	0x3	/* Hayes 16650-compat Modem */
394 #define	PCI_COMM_MODEM_IF_HAYES_16750	0x4	/* Hayes 16750-compat Modem */
395 
396 /*
397  * PCI Sub-class codes - base class 0x8
398  */
399 #define	PCI_PERIPH_PIC		0x0	/* Generic PIC */
400 #define	PCI_PERIPH_DMA		0x1	/* Generic DMA Controller */
401 #define	PCI_PERIPH_TIMER	0x2	/* Generic System Timer Controller */
402 #define	PCI_PERIPH_RTC		0x3	/* Generic RTC Controller */
403 #define	PCI_PERIPH_HPC		0x4	/* Generic PCI Hot-Plug Controller */
404 #define	PCI_PERIPH_SD_HC	0x5	/* SD Host Controller */
405 #define	PCI_PERIPH_IOMMU	0x6	/* IOMMU */
406 #define	PCI_PERIPH_OTHER	0x80	/* Other System Peripheral */
407 
408 /*
409  * Programming interfaces for class 0x8 / subclass 0x0 (interrupt controller)
410  */
411 #define	PCI_PERIPH_PIC_IF_GENERIC	0x0	/* Generic 8259 APIC */
412 #define	PCI_PERIPH_PIC_IF_ISA		0x1	/* ISA PIC */
413 #define	PCI_PERIPH_PIC_IF_EISA		0x2	/* EISA PIC */
414 #define	PCI_PERIPH_PIC_IF_IO_APIC	0x10	/* I/O APIC interrupt ctrlr */
415 #define	PCI_PERIPH_PIC_IF_IOX_APIC	0x20	/* I/O(x) APIC intr ctrlr */
416 
417 /*
418  * Programming interfaces for class 0x8 / subclass 0x1 (DMA controller)
419  */
420 #define	PCI_PERIPH_DMA_IF_GENERIC	0x0	/* Generic 8237 DMA ctrlr */
421 #define	PCI_PERIPH_DMA_IF_ISA		0x1	/* ISA DMA ctrlr */
422 #define	PCI_PERIPH_DMA_IF_EISA		0x2	/* EISA DMA ctrlr */
423 
424 /*
425  * Programming interfaces for class 0x8 / subclass 0x2 (timer)
426  */
427 #define	PCI_PERIPH_TIMER_IF_GENERIC	0x0	/* Generic 8254 system timer */
428 #define	PCI_PERIPH_TIMER_IF_ISA		0x1	/* ISA system timers */
429 #define	PCI_PERIPH_TIMER_IF_EISA	0x2	/* EISA system timers (two) */
430 #define	PCI_PERIPH_TIMER_IF_HPET	0x3	/* High Perf Event timer */
431 
432 /*
433  * Programming interfaces for class 0x8 / subclass 0x3 (realtime clock)
434  */
435 #define	PCI_PERIPH_RTC_IF_GENERIC	0x0	/* Generic RTC controller */
436 #define	PCI_PERIPH_RTC_IF_ISA		0x1	/* ISA RTC controller */
437 
438 /*
439  * PCI Sub-class codes - base class 0x9
440  */
441 #define	PCI_INPUT_KEYBOARD	0x0	/* Keyboard Controller */
442 #define	PCI_INPUT_DIGITIZ	0x1	/* Digitizer (Pen) */
443 #define	PCI_INPUT_MOUSE		0x2	/* Mouse Controller */
444 #define	PCI_INPUT_SCANNER	0x3	/* Scanner Controller */
445 #define	PCI_INPUT_GAMEPORT	0x4	/* Gameport Controller */
446 #define	PCI_INPUT_OTHER		0x80	/* Other Input Controller */
447 
448 /*
449  * Programming interfaces for class 0x9 / subclass 0x4 (Gameport controller)
450  */
451 #define	PCI_INPUT_GAMEPORT_IF_GENERIC	0x00	/* Generic controller */
452 #define	PCI_INPUT_GAMEPORT_IF_LEGACY	0x10	/* Legacy controller */
453 
454 /*
455  * PCI Sub-class codes - base class 0xA
456  */
457 #define	PCI_DOCK_GENERIC	0x00	/* Generic Docking Station */
458 #define	PCI_DOCK_OTHER		0x80	/* Other Type of Docking Station */
459 
460 /*
461  * PCI Sub-class codes - base class 0xB
462  */
463 #define	PCI_PROCESSOR_386	0x0	/* 386 */
464 #define	PCI_PROCESSOR_486	0x1	/* 486 */
465 #define	PCI_PROCESSOR_PENT	0x2	/* Pentium */
466 #define	PCI_PROCESSOR_ALPHA	0x10	/* Alpha */
467 #define	PCI_PROCESSOR_POWERPC	0x20	/* PowerPC */
468 #define	PCI_PROCESSOR_MIPS	0x30	/* MIPS */
469 #define	PCI_PROCESSOR_COPROC	0x40	/* Co-processor */
470 #define	PCI_PROCESSOR_OTHER	0x80	/* Other processors */
471 
472 /*
473  * PCI Sub-class codes - base class 0xC (Serial Controllers)
474  */
475 #define	PCI_SERIAL_FIRE		0x0	/* FireWire (IEEE 1394) */
476 #define	PCI_SERIAL_ACCESS	0x1	/* ACCESS.bus */
477 #define	PCI_SERIAL_SSA		0x2	/* SSA */
478 #define	PCI_SERIAL_USB		0x3	/* Universal Serial Bus */
479 #define	PCI_SERIAL_FIBRE	0x4	/* Fibre Channel */
480 #define	PCI_SERIAL_SMBUS	0x5	/* System Management Bus */
481 #define	PCI_SERIAL_IB		0x6	/* InfiniBand */
482 #define	PCI_SERIAL_IPMI		0x7	/* IPMI */
483 #define	PCI_SERIAL_SERCOS	0x8	/* SERCOS Interface Std (IEC 61491) */
484 #define	PCI_SERIAL_CANBUS	0x9	/* CANbus */
485 #define	PCI_SERIAL_OTHER	0x80	/* Other Serial Bus Controllers */
486 
487 /*
488  * Programming interfaces for class 0xC / subclass 0x0 (Firewire)
489  */
490 #define	PCI_SERIAL_FIRE_WIRE  		0x00	/* IEEE 1394 (Firewire) */
491 #define	PCI_SERIAL_FIRE_1394_HCI 	0x10	/* 1394 OpenHCI Host Cntrlr */
492 
493 /*
494  * Programming interfaces for class 0xC / subclass 0x3 (USB controller)
495  */
496 #define	PCI_SERIAL_USB_IF_UHCI 		0x00	/* UHCI Compliant */
497 #define	PCI_SERIAL_USB_IF_OHCI 		0x10	/* OHCI Compliant */
498 #define	PCI_SERIAL_USB_IF_EHCI 		0x20	/* EHCI Compliant */
499 #define	PCI_SERIAL_USB_IF_GENERIC 	0x80	/* no specific HCD */
500 #define	PCI_SERIAL_USB_IF_DEVICE 	0xFE	/* not a HCD */
501 
502 /*
503  * Programming interfaces for class 0xC / subclass 0x7 (IPMI controller)
504  */
505 #define	PCI_SERIAL_IPMI_IF_SMIC 	0x0	/* SMIC Interface */
506 #define	PCI_SERIAL_IPMI_IF_KBD 		0x1	/* Keyboard Ctrl Style Intfc */
507 #define	PCI_SERIAL_IPMI_IF_BTI		0x2	/* Block Transfer Interface */
508 
509 /*
510  * PCI Sub-class codes - base class 0xD (Wireless controllers)
511  */
512 #define	PCI_WIRELESS_IRDA		0x0	/* iRDA Compatible Controller */
513 #define	PCI_WIRELESS_IR			0x1	/* Consumer IR Controller */
514 #define	PCI_WIRELESS_RF			0x10	/* RF Controller */
515 #define	PCI_WIRELESS_BLUETOOTH		0x11	/* Bluetooth Controller */
516 #define	PCI_WIRELESS_BROADBAND		0x12	/* Broadband Controller */
517 #define	PCI_WIRELESS_80211A		0x20	/* Ethernet 802.11a 5 GHz */
518 #define	PCI_WIRELESS_80211B		0x21	/* Ethernet 802.11b 2.4 GHz */
519 #define	PCI_WIRELESS_OTHER		0x80	/* Other Wireless Controllers */
520 
521 /*
522  * Programming interfaces for class 0xD / subclass 0x1 (Consumer IR controller)
523  */
524 #define	PCI_WIRELESS_IR_CONSUMER 	0x00	/* Consumer IR Controller */
525 #define	PCI_WIRELESS_IR_UWB_RC 		0x10	/* UWB Radio Controller */
526 
527 /*
528  * PCI Sub-class codes - base class 0xE (Intelligent I/O controllers)
529  */
530 #define	PCI_INTIO_MSG_FIFO		0x0	/* Message FIFO at off 40h */
531 #define	PCI_INTIO_I20			0x1	/* I20 Arch Spec 1.0 */
532 
533 /*
534  * PCI Sub-class codes - base class 0xF (Satellite Communication controllers)
535  */
536 #define	PCI_SATELLITE_COMM_TV		0x01	/* TV */
537 #define	PCI_SATELLITE_COMM_AUDIO	0x02	/* Audio */
538 #define	PCI_SATELLITE_COMM_VOICE	0x03	/* Voice */
539 #define	PCI_SATELLITE_COMM_DATA		0x04	/* DATA */
540 #define	PCI_SATELLITE_COMM_OTHER	0x80	/* Other Satelite Comm Cntrlr */
541 
542 /*
543  * PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers)
544  */
545 #define	PCI_CRYPT_NETWORK		0x00	/* Network and Computing */
546 #define	PCI_CRYPT_ENTERTAINMENT		0x10	/* Entertainment en/decrypt */
547 #define	PCI_CRYPT_OTHER			0x80	/* Other en/decryption ctrlrs */
548 
549 /*
550  * PCI Sub-class codes - base class 0x11 (Signal Processing controllers)
551  */
552 #define	PCI_SIGNAL_DPIO			0x00	/* DPIO modules */
553 #define	PCI_SIGNAL_PERF_COUNTERS	0x01	/* Performance counters */
554 #define	PCI_SIGNAL_COMM_SYNC		0x10	/* Comm. synchronization plus */
555 						/* time and freq test ctrlr */
556 #define	PCI_SIGNAL_MANAGEMENT		0x20	/* Management card */
557 #define	PCI_SIGNAL_OTHER		0x80	/* DSP/DAP controller */
558 
559 /* PCI header decode */
560 #define	PCI_HEADER_MULTI	0x80	/* multi-function device */
561 #define	PCI_HEADER_ZERO		0x00	/* type zero PCI header */
562 #define	PCI_HEADER_ONE		0x01	/* type one PCI header */
563 #define	PCI_HEADER_TWO		0x02	/* type two PCI header */
564 #define	PCI_HEADER_PPB		PCI_HEADER_ONE  /* type one PCI to PCI Bridge */
565 #define	PCI_HEADER_CARDBUS	PCI_HEADER_TWO	/* type one PCI header */
566 
567 #define	PCI_HEADER_TYPE_M	0x7f  /* type mask for header */
568 
569 /*
570  * Base register bit definitions.
571  */
572 #define	PCI_BASE_SPACE_M    0x1  /* memory space indicator */
573 #define	PCI_BASE_SPACE_IO   0x1   /* IO space */
574 #define	PCI_BASE_SPACE_MEM  0x0   /* memory space */
575 
576 #define	PCI_BASE_TYPE_MEM   0x0   /* 32-bit memory address */
577 #define	PCI_BASE_TYPE_LOW   0x2   /* less than 1Mb address */
578 #define	PCI_BASE_TYPE_ALL   0x4   /* 64-bit memory address */
579 #define	PCI_BASE_TYPE_RES   0x6   /* reserved */
580 
581 #define	PCI_BASE_TYPE_M		0x00000006  /* type indicator mask */
582 #define	PCI_BASE_PREF_M		0x00000008  /* prefetch mask */
583 #define	PCI_BASE_M_ADDR_M	0xfffffff0  /* memory address mask */
584 #define	PCI_BASE_IO_ADDR_M	0xfffffffe  /* I/O address mask */
585 
586 #define	PCI_BASE_ROM_ADDR_M	0xfffff800  /* ROM address mask */
587 #define	PCI_BASE_ROM_ENABLE	0x00000001  /* ROM decoder enable */
588 
589 /*
590  * Capabilities linked list entry offsets
591  */
592 #define	PCI_CAP_ID		0x0	/* capability identifier, 1 byte */
593 #define	PCI_CAP_NEXT_PTR	0x1	/* next entry pointer, 1 byte */
594 #define	PCI_CAP_ID_REGS_OFF	0x2	/* cap id register offset */
595 #define	PCI_CAP_MAX_PTR		0x30	/* maximum number of cap pointers */
596 #define	PCI_CAP_PTR_OFF		0x40	/* minimum cap pointer offset */
597 #define	PCI_CAP_PTR_MASK	0xFC	/* mask for capability pointer */
598 
599 /*
600  * Capability identifier values
601  */
602 #define	PCI_CAP_ID_PM		0x1	/* power management entry */
603 #define	PCI_CAP_ID_AGP		0x2	/* AGP supported */
604 #define	PCI_CAP_ID_VPD		0x3	/* VPD supported */
605 #define	PCI_CAP_ID_SLOT_ID	0x4	/* Slot Identification supported */
606 #define	PCI_CAP_ID_MSI		0x5	/* MSI supported */
607 #define	PCI_CAP_ID_cPCI_HS	0x6	/* CompactPCI Host Swap supported */
608 #define	PCI_CAP_ID_PCIX		0x7	/* PCI-X supported */
609 #define	PCI_CAP_ID_HT		0x8	/* HyperTransport supported */
610 #define	PCI_CAP_ID_VS		0x9	/* Vendor Specific */
611 #define	PCI_CAP_ID_DEBUG_PORT	0xA	/* Debug Port supported */
612 #define	PCI_CAP_ID_cPCI_CRC	0xB	/* CompactPCI central resource ctrl */
613 #define	PCI_CAP_ID_PCI_HOTPLUG	0xC	/* PCI Hot Plug (SHPC) supported */
614 #define	PCI_CAP_ID_P2P_SUBSYS	0xD	/* PCI bridge Sub-system ID */
615 #define	PCI_CAP_ID_AGP_8X	0xE	/* AGP 8X supported */
616 #define	PCI_CAP_ID_SECURE_DEV	0xF	/* Secure Device supported */
617 #define	PCI_CAP_ID_PCI_E	0x10	/* PCI Express supported */
618 #define	PCI_CAP_ID_MSI_X	0x11	/* MSI-X supported */
619 #define	PCI_CAP_ID_SATA		0x12	/* SATA Data/Index Config supported */
620 #define	PCI_CAP_ID_FLR		0x13	/* Function Level Reset supported */
621 
622 /*
623  * Capability next entry pointer values
624  */
625 #define	PCI_CAP_NEXT_PTR_NULL	0x0	/* no more entries in the list */
626 
627 /*
628  * PCI power management (PM) capability entry offsets
629  */
630 #define	PCI_PMCAP		0x2	/* PM capabilities, 2 bytes */
631 #define	PCI_PMCSR		0x4	/* PM control/status reg, 2 bytes */
632 #define	PCI_PMCSR_BSE		0x6	/* PCI-PCI bridge extensions, 1 byte */
633 #define	PCI_PMDATA		0x7	/* PM data, 1 byte */
634 
635 /*
636  * PM capabilities values - 2 bytes
637  */
638 #define	PCI_PMCAP_VER_1_0	0x1	/* PCI PM spec 1.0 */
639 #define	PCI_PMCAP_VER_1_1	0x2	/* PCI PM spec 1.1 */
640 #define	PCI_PMCAP_VER_MASK	0x7	/* version mask */
641 #define	PCI_PMCAP_PME_CLOCK	0x8	/* needs PCI clock for PME */
642 #define	PCI_PMCAP_DSI		0x20	/* needs device specific init */
643 #define	PCI_PMCAP_AUX_CUR_SELF	0x0	/* 0 aux current - self powered */
644 #define	PCI_PMCAP_AUX_CUR_55mA	0x40	/* 55 mA aux current */
645 #define	PCI_PMCAP_AUX_CUR_100mA	0x80	/* 100 mA aux current */
646 #define	PCI_PMCAP_AUX_CUR_160mA	0xc0	/* 160 mA aux current */
647 #define	PCI_PMCAP_AUX_CUR_220mA	0x100	/* 220 mA aux current */
648 #define	PCI_PMCAP_AUX_CUR_270mA	0x140	/* 270 mA aux current */
649 #define	PCI_PMCAP_AUX_CUR_320mA	0x180	/* 320 mA aux current */
650 #define	PCI_PMCAP_AUX_CUR_375mA	0x1c0	/* 375 mA aux current */
651 #define	PCI_PMCAP_AUX_CUR_MASK	0x1c0	/* 3.3Vaux aux current needs */
652 #define	PCI_PMCAP_D1		0x200	/* D1 state supported */
653 #define	PCI_PMCAP_D2		0x400	/* D2 state supported */
654 #define	PCI_PMCAP_D0_PME	0x800	/* PME from D0 */
655 #define	PCI_PMCAP_D1_PME	0x1000	/* PME from D1 */
656 #define	PCI_PMCAP_D2_PME	0x2000	/* PME from D2 */
657 #define	PCI_PMCAP_D3HOT_PME	0x4000	/* PME from D3hot */
658 #define	PCI_PMCAP_D3COLD_PME	0x8000	/* PME from D3cold */
659 #define	PCI_PMCAP_PME_MASK	0xf800	/* PME support mask */
660 
661 /*
662  * PM control/status values - 2 bytes
663  */
664 #define	PCI_PMCSR_D0			0x0	/* power state D0 */
665 #define	PCI_PMCSR_D1			0x1	/* power state D1 */
666 #define	PCI_PMCSR_D2			0x2	/* power state D2 */
667 #define	PCI_PMCSR_D3HOT			0x3	/* power state D3hot */
668 #define	PCI_PMCSR_STATE_MASK		0x3	/* power state mask */
669 #define	PCI_PMCSR_PME_EN		0x100	/* enable PME assertion */
670 #define	PCI_PMCSR_DSEL_D0_PWR_C		0x0	/* D0 power consumed */
671 #define	PCI_PMCSR_DSEL_D1_PWR_C		0x200	/* D1 power consumed */
672 #define	PCI_PMCSR_DSEL_D2_PWR_C		0x400	/* D2 power consumed */
673 #define	PCI_PMCSR_DSEL_D3_PWR_C		0x600	/* D3 power consumed */
674 #define	PCI_PMCSR_DSEL_D0_PWR_D		0x800	/* D0 power dissipated */
675 #define	PCI_PMCSR_DSEL_D1_PWR_D		0xa00	/* D1 power dissipated */
676 #define	PCI_PMCSR_DSEL_D2_PWR_D		0xc00	/* D2 power dissipated */
677 #define	PCI_PMCSR_DSEL_D3_PWR_D		0xe00	/* D3 power dissipated */
678 #define	PCI_PMCSR_DSEL_COM_C		0x1000	/* common power consumption */
679 #define	PCI_PMCSR_DSEL_MASK		0x1e00	/* data select mask */
680 #define	PCI_PMCSR_DSCL_UNKNOWN		0x0	/* data scale unknown */
681 #define	PCI_PMCSR_DSCL_1_BY_10		0x2000	/* data scale 0.1x */
682 #define	PCI_PMCSR_DSCL_1_BY_100		0x4000	/* data scale 0.01x */
683 #define	PCI_PMCSR_DSCL_1_BY_1000	0x6000	/* data scale 0.001x */
684 #define	PCI_PMCSR_DSCL_MASK		0x6000	/* data scale mask */
685 #define	PCI_PMCSR_PME_STAT		0x8000	/* PME status */
686 
687 /*
688  * PM PMCSR PCI to PCI bridge support extension values - 1 byte
689  */
690 #define	PCI_PMCSR_BSE_B2_B3	0x40	/* bridge D3hot -> secondary B2 */
691 #define	PCI_PMCSR_BSE_BPCC_EN	0x80	/* bus power/clock control enabled */
692 
693 /*
694  * PCI-X capability related definitions
695  */
696 #define	PCI_PCIX_COMMAND	0x2	/* Command register offset */
697 #define	PCI_PCIX_STATUS		0x4	/* Status register offset */
698 #define	PCI_PCIX_ECC_STATUS	0x8	/* ECC Status register offset */
699 #define	PCI_PCIX_ECC_FST_AD	0xC	/* ECC First address register offset */
700 #define	PCI_PCIX_ECC_SEC_AD	0x10	/* ECC Second address register offset */
701 #define	PCI_PCIX_ECC_ATTR	0x14	/* ECC Attribute register offset */
702 
703 /*
704  * PCI-X bridge capability related definitions
705  */
706 #define	PCI_PCIX_SEC_STATUS		0x2	/* Secondary Status offset */
707 #define	PCI_PCIX_SEC_STATUS_SCD		0x4	/* Split Completion Discarded */
708 #define	PCI_PCIX_SEC_STATUS_USC		0x8	/* Unexpected Split Complete */
709 #define	PCI_PCIX_SEC_STATUS_SCO		0x10	/* Split Completion Overrun */
710 #define	PCI_PCIX_SEC_STATUS_SRD		0x20	/* Split Completion Delayed */
711 #define	PCI_PCIX_SEC_STATUS_ERR_MASK	0x3C
712 
713 #define	PCI_PCIX_BDG_STATUS		0x4	/* Bridge Status offset */
714 #define	PCI_PCIX_BDG_STATUS_USC		0x80000
715 #define	PCI_PCIX_BDG_STATUS_SCO		0x100000
716 #define	PCI_PCIX_BDG_STATUS_SRD		0x200000
717 #define	PCI_PCIX_BDG_STATUS_ERR_MASK	0x380000
718 
719 #define	PCI_PCIX_UP_SPL_CTL	0x8	/* Upstream split ctrl reg offset */
720 #define	PCI_PCIX_DOWN_SPL_CTL	0xC	/* Downstream split ctrl reg offset */
721 #define	PCI_PCIX_BDG_ECC_STATUS	0x10	/* ECC Status register offset */
722 #define	PCI_PCIX_BDG_ECC_FST_AD	0x14	/* ECC First address register offset */
723 #define	PCI_PCIX_BDG_ECC_SEC_AD	0x18	/* ECC Second address register offset */
724 #define	PCI_PCIX_BDG_ECC_ATTR	0x1C	/* ECC Attribute register offset */
725 
726 /*
727  * PCIX capabilities values
728  */
729 #define	PCI_PCIX_VER_MASK	0x3000	/* Bits 12 and 13 */
730 #define	PCI_PCIX_VER_0		0x0000	/* PCIX cap list item version 0 */
731 #define	PCI_PCIX_VER_1		0x1000	/* PCIX cap list item version 1 */
732 #define	PCI_PCIX_VER_2		0x2000	/* PCIX cap list item version 2 */
733 
734 #define	PCI_PCIX_SPL_DSCD	0x40000 /* Split Completion Discarded */
735 #define	PCI_PCIX_UNEX_SPL	0x80000	/* Unexpected Split Completion */
736 #define	PCI_PCIX_RX_SPL_MSG	0x20000000 /* Recieved Spl Comp Error Message */
737 
738 #define	PCI_PCIX_ECC_SEL	0x1	/* Secondary ECC register select */
739 #define	PCI_PCIX_ECC_EP		0x2	/* Error Present on other side */
740 #define	PCI_PCIX_ECC_S_CE	0x4	/* Addl Correctable ECC Error */
741 #define	PCI_PCIX_ECC_S_UE	0x8	/* Addl Uncorrectable ECC Error */
742 #define	PCI_PCIX_ECC_PHASE	0x70	/* ECC Error Phase */
743 #define	PCI_PCIX_ECC_CORR	0x80	/* ECC Error Corrected */
744 #define	PCI_PCIX_ECC_SYN	0xff00	/* ECC Error Syndrome */
745 #define	PCI_PCIX_ECC_FST_CMD	0xf0000	 /* ECC Error First Command */
746 #define	PCI_PCIX_ECC_SEC_CMD	0xf00000 /* ECC Error Second Command */
747 #define	PCI_PCIX_ECC_UP_ATTR	0xf000000 /* ECC Error Upper Attributes */
748 
749 /*
750  * PCIX ECC Phase Values
751  */
752 #define	PCI_PCIX_ECC_PHASE_NOERR	0x0
753 #define	PCI_PCIX_ECC_PHASE_FADDR	0x1
754 #define	PCI_PCIX_ECC_PHASE_SADDR	0x2
755 #define	PCI_PCIX_ECC_PHASE_ATTR		0x3
756 #define	PCI_PCIX_ECC_PHASE_DATA32	0x4
757 #define	PCI_PCIX_ECC_PHASE_DATA64	0x5
758 
759 /*
760  * PCI-X Command Encoding
761  */
762 #define	PCI_PCIX_CMD_INTR		0x0
763 #define	PCI_PCIX_CMD_SPEC		0x1
764 #define	PCI_PCIX_CMD_IORD		0x2
765 #define	PCI_PCIX_CMD_IOWR		0x3
766 #define	PCI_PCIX_CMD_DEVID		0x5
767 #define	PCI_PCIX_CMD_MEMRD_DW		0x6
768 #define	PCI_PCIX_CMD_MEMWR		0x7
769 #define	PCI_PCIX_CMD_MEMRD_BL		0x8
770 #define	PCI_PCIX_CMD_MEMWR_BL		0x9
771 #define	PCI_PCIX_CMD_CFRD		0xA
772 #define	PCI_PCIX_CMD_CFWR		0xB
773 #define	PCI_PCIX_CMD_SPL		0xC
774 #define	PCI_PCIX_CMD_DADR		0xD
775 #define	PCI_PCIX_CMD_MEMRDBL		0xE
776 #define	PCI_PCIX_CMD_MEMWRBL		0xF
777 
778 #if defined(_BIT_FIELDS_LTOH)
779 typedef struct pcix_attr {
780 	uint32_t	lbc	:8,
781 			rid	:16,
782 			tag	:5,
783 			ro	:1,
784 			ns	:1,
785 			r	:1;
786 } pcix_attr_t;
787 #elif defined(_BIT_FIELDS_HTOL)
788 typedef struct pcix_attr {
789 	uint32_t	r	:1,
790 			ns	:1,
791 			ro	:1,
792 			tag	:5,
793 			rid	:16,
794 			lbc	:8;
795 } pcix_attr_t;
796 #else
797 #error "bit field not defined"
798 #endif
799 
800 #define	PCI_PCIX_BSS_SPL_DSCD	0x4	/* Secondary split comp discarded */
801 #define	PCI_PCIX_BSS_UNEX_SPL	0x8	/* Secondary unexpected split comp */
802 #define	PCI_PCIX_BSS_SPL_OR	0x10	/* Secondary split comp overrun */
803 #define	PCI_PCIX_BSS_SPL_DLY	0x20	/* Secondary split comp delayed */
804 
805 /*
806  * PCI Hotplug capability entry offsets
807  *
808  * SHPC based PCI hotplug controller registers accessed via the DWORD
809  * select and DATA registers in PCI configuration space relative to the
810  * PCI HP capibility pointer.
811  */
812 #define	PCI_HP_DWORD_SELECT_OFF		0x2
813 #define	PCI_HP_DWORD_DATA_OFF		0x4
814 
815 #define	PCI_HP_BASE_OFFSET_REG		0x00
816 #define	PCI_HP_SLOTS_AVAIL_I_REG	0x01
817 #define	PCI_HP_SLOTS_AVAIL_II_REG	0x02
818 #define	PCI_HP_SLOT_CONFIGURATION_REG	0x03
819 #define	PCI_HP_PROF_IF_SBCR_REG		0x04
820 #define	PCI_HP_COMMAND_STATUS_REG	0x05
821 #define	PCI_HP_IRQ_LOCATOR_REG		0x06
822 #define	PCI_HP_SERR_LOCATOR_REG		0x07
823 #define	PCI_HP_CTRL_SERR_INT_REG	0x08
824 #define	PCI_HP_LOGICAL_SLOT_REGS	0x09
825 #define	PCI_HP_VENDOR_SPECIFIC		0x28
826 
827 /* Definitions used with the PCI_HP_SLOTS_AVAIL_I_REG register */
828 #define	PCI_HP_AVAIL_33MHZ_CONV_SPEED_SHIFT	0
829 #define	PCI_HP_AVAIL_66MHZ_PCIX_SPEED_SHIFT	8
830 #define	PCI_HP_AVAIL_100MHZ_PCIX_SPEED_SHIFT	16
831 #define	PCI_HP_AVAIL_133MHZ_PCIX_SPEED_SHIFT	24
832 #define	PCI_HP_AVAIL_SPEED_MASK			0x1F
833 
834 /* Definitions used with the PCI_HP_SLOTS_AVAIL_II_REG register */
835 #define	PCI_HP_AVAIL_66MHZ_CONV_SPEED_SHIFT	0
836 
837 /* Register bits used with the PCI_HP_PROF_IF_SBCR_REG register */
838 #define	PCI_HP_SBCR_33MHZ_CONV_SPEED		0x0
839 #define	PCI_HP_SBCR_66MHZ_CONV_SPEED		0x1
840 #define	PCI_HP_SBCR_66MHZ_PCIX_SPEED		0x2
841 #define	PCI_HP_SBCR_100MHZ_PCIX_SPEED		0x3
842 #define	PCI_HP_SBCR_133MHZ_PCIX_SPEED		0x4
843 #define	PCI_HP_SBCR_SPEED_MASK			0x7
844 
845 /* Register bits used with the PCI_HP_COMMAND_STATUS_REG register */
846 #define	PCI_HP_COMM_STS_ERR_INVALID_SPEED	0x80000
847 #define	PCI_HP_COMM_STS_ERR_INVALID_COMMAND	0x40000
848 #define	PCI_HP_COMM_STS_ERR_MRL_OPEN		0x20000
849 #define	PCI_HP_COMM_STS_ERR_MASK		0xe0000
850 #define	PCI_HP_COMM_STS_CTRL_BUSY		0x10000
851 #define	PCI_HP_COMM_STS_SET_SPEED		0x40
852 
853 /* Register bits used with the PCI_HP_CTRL_SERR_INT_REG register */
854 #define	PCI_HP_SERR_INT_GLOBAL_IRQ_MASK		0x1
855 #define	PCI_HP_SERR_INT_GLOBAL_SERR_MASK	0x2
856 #define	PCI_HP_SERR_INT_CMD_COMPLETE_MASK	0x4
857 #define	PCI_HP_SERR_INT_ARBITER_SERR_MASK	0x8
858 #define	PCI_HP_SERR_INT_CMD_COMPLETE_IRQ	0x10000
859 #define	PCI_HP_SERR_INT_ARBITER_IRQ		0x20000
860 #define	PCI_HP_SERR_INT_MASK_ALL		0xf
861 
862 /* Register bits used with the PCI_HP_LOGICAL_SLOT_REGS register */
863 #define	PCI_HP_SLOT_POWER_ONLY			0x1
864 #define	PCI_HP_SLOT_ENABLED			0x2
865 #define	PCI_HP_SLOT_DISABLED			0x3
866 #define	PCI_HP_SLOT_STATE_MASK			0x3
867 #define	PCI_HP_SLOT_MRL_STATE_MASK		0x100
868 #define	PCI_HP_SLOT_66MHZ_CONV_CAPABLE		0x200
869 #define	PCI_HP_SLOT_CARD_EMPTY_MASK		0xc00
870 #define	PCI_HP_SLOT_66MHZ_PCIX_CAPABLE		0x1000
871 #define	PCI_HP_SLOT_100MHZ_PCIX_CAPABLE		0x2000
872 #define	PCI_HP_SLOT_133MHZ_PCIX_CAPABLE		0x3000
873 #define	PCI_HP_SLOT_PCIX_CAPABLE_MASK		0x3000
874 #define	PCI_HP_SLOT_PCIX_CAPABLE_SHIFT		12
875 #define	PCI_HP_SLOT_PRESENCE_DETECTED		0x10000
876 #define	PCI_HP_SLOT_ISO_PWR_DETECTED		0x20000
877 #define	PCI_HP_SLOT_ATTN_DETECTED		0x40000
878 #define	PCI_HP_SLOT_MRL_DETECTED		0x80000
879 #define	PCI_HP_SLOT_POWER_DETECTED		0x100000
880 #define	PCI_HP_SLOT_PRESENCE_MASK		0x1000000
881 #define	PCI_HP_SLOT_ISO_PWR_MASK		0x2000000
882 #define	PCI_HP_SLOT_ATTN_MASK			0x4000000
883 #define	PCI_HP_SLOT_MRL_MASK			0x8000000
884 #define	PCI_HP_SLOT_POWER_MASK			0x10000000
885 #define	PCI_HP_SLOT_MRL_SERR_MASK		0x20000000
886 #define	PCI_HP_SLOT_POWER_SERR_MASK		0x40000000
887 #define	PCI_HP_SLOT_MASK_ALL			0x5f000000
888 
889 /* Register bits used with the PCI_HP_IRQ_LOCATOR_REG register */
890 #define	PCI_HP_IRQ_CMD_COMPLETE			0x1
891 #define	PCI_HP_IRQ_SLOT_N_PENDING		0x2
892 
893 /* Register bits used with the PCI_HP_SERR_LOCATOR_REG register */
894 #define	PCI_HP_IRQ_SERR_ARBITER_PENDING		0x1
895 #define	PCI_HP_IRQ_SERR_SLOT_N_PENDING		0x2
896 
897 /* Register bits used with the PCI_HP_SLOT_CONFIGURATION_REG register */
898 #define	PCI_HP_SLOT_CONFIG_MRL_SENSOR		0x40000000
899 #define	PCI_HP_SLOT_CONFIG_ATTN_BUTTON		0x80000000
900 #define	PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_SHIFT	16
901 #define	PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_MASK	0x3FF
902 
903 /*
904  * PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit
905  */
906 #define	PCI_MSI_CTRL		0x02	/* MSI control register, 2 bytes */
907 #define	PCI_MSI_ADDR_OFFSET	0x04	/* MSI 32-bit msg address, 4 bytes */
908 #define	PCI_MSI_32BIT_DATA	0x08	/* MSI 32-bit msg data, 2 bytes */
909 #define	PCI_MSI_32BIT_MASK	0x0C	/* MSI 32-bit mask bits, 4 bytes */
910 #define	PCI_MSI_32BIT_PENDING	0x10	/* MSI 32-bit pending bits, 4 bytes */
911 
912 /*
913  * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit
914  */
915 #define	PCI_MSI_64BIT_DATA	0x0C	/* MSI 64-bit msg data, 2 bytes */
916 #define	PCI_MSI_64BIT_MASKBITS	0x10	/* MSI 64-bit mask bits, 4 bytes */
917 #define	PCI_MSI_64BIT_PENDING	0x14	/* MSI 64-bit pending bits, 4 bytes */
918 
919 /*
920  * PCI Message Signalled Interrupts (MSI) capability masks and shifts
921  */
922 #define	PCI_MSI_ENABLE_BIT	0x0001	/* MSI enable mask in MSI ctrl reg */
923 #define	PCI_MSI_MMC_MASK	0x000E	/* MMC mask in MSI ctrl reg */
924 #define	PCI_MSI_MMC_SHIFT	0x1	/* Shift for MMC bits */
925 #define	PCI_MSI_MME_MASK	0x0070	/* MME mask in MSI ctrl reg */
926 #define	PCI_MSI_MME_SHIFT	0x4	/* Shift for MME bits */
927 #define	PCI_MSI_64BIT_MASK	0x0080	/* 64bit support mask in MSI ctrl reg */
928 #define	PCI_MSI_PVM_MASK	0x0100	/* PVM support mask in MSI ctrl reg */
929 
930 /*
931  * PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets
932  */
933 #define	PCI_MSIX_CTRL		0x02	/* MSI-X control register, 2 bytes */
934 #define	PCI_MSIX_TBL_OFFSET	0x04	/* MSI-X table offset, 4 bytes */
935 #define	PCI_MSIX_TBL_BIR_MASK	0x0007	/* MSI-X table BIR mask */
936 #define	PCI_MSIX_PBA_OFFSET	0x08	/* MSI-X pending bit array, 4 bytes */
937 #define	PCI_MSIX_PBA_BIR_MASK	0x0007	/* MSI-X PBA BIR mask */
938 
939 #define	PCI_MSIX_TBL_SIZE_MASK	0x07FF	/* table size mask in MSI-X ctrl reg */
940 #define	PCI_MSIX_FUNCTION_MASK	0x4000	/* function mask in MSI-X ctrl reg */
941 #define	PCI_MSIX_ENABLE_BIT	0x8000	/* MSI-X enable mask in MSI-X ctl reg */
942 
943 #define	PCI_MSIX_LOWER_ADDR_OFFSET	0	/* MSI-X lower addr offset */
944 #define	PCI_MSIX_UPPER_ADDR_OFFSET	4	/* MSI-X upper addr offset */
945 #define	PCI_MSIX_DATA_OFFSET		8	/* MSI-X data offset */
946 #define	PCI_MSIX_VECTOR_CTRL_OFFSET	12	/* MSI-X vector ctrl offset */
947 #define	PCI_MSIX_VECTOR_SIZE		16	/* MSI-X size of each vector */
948 
949 /*
950  * PCI Message Signalled Interrupts: other interesting constants
951  */
952 #define	PCI_MSI_MAX_INTRS	32	/* maximum MSI interrupts supported */
953 #define	PCI_MSIX_MAX_INTRS	2048	/* maximum MSI-X interrupts supported */
954 
955 /*
956  * PCI Slot Id Capabilities, 2 bytes
957  */
958 /* Byte 1: Expansion Slot Register (ESR), Byte 2: Chassis Number Register */
959 #define	PCI_CAPSLOT_ESR_NSLOTS_MASK	0x1F	/* Number of slots mask */
960 #define	PCI_CAPSLOT_ESR_FIC		0x20	/* First In Chassis bit */
961 #define	PCI_CAPSLOT_ESR_FIC_MASK	0x01	/* First In Chassis mask */
962 #define	PCI_CAPSLOT_ESR_FIC_SHIFT	5	/* First In Chassis shift */
963 #define	PCI_CAPSLOT_FIC(esr_reg)	((esr_reg) & PCI_CAPSLOT_ESR_FIC)
964 #define	PCI_CAPSLOT_NSLOTS(esr_reg)	((esr_reg) & \
965 						PCI_CAPSLOT_ESR_NSLOTS_MASK)
966 
967 /*
968  * HyperTransport Capabilities; each HT cap uses the same PCI cap id of
969  * PCI_CAP_ID_HT.  The header's upper 16-bits (command reg) contains an HT
970  * cap type reg at bits [15:11].  For Slave/Pri Interface and Host/Sec
971  * Interface types, only bits [15:13] are used.
972  */
973 #define	PCI_HTCAP_TYPE_MASK		0xF800
974 #define	PCI_HTCAP_TYPE_SLHOST_MASK	0xE000	/* SLPRI and HOSTSEC types */
975 #define	PCI_HTCAP_TYPE_SHIFT		11
976 
977 #define	PCI_HTCAP_SLPRI_ID		0x00
978 #define	PCI_HTCAP_HOSTSEC_ID		0x04
979 #define	PCI_HTCAP_SWITCH_ID		0x08
980 #define	PCI_HTCAP_INTCONF_ID		0x10
981 #define	PCI_HTCAP_REVID_ID		0x11
982 #define	PCI_HTCAP_UNITID_CLUMP_ID	0x12
983 #define	PCI_HTCAP_ECFG_ID		0x13
984 #define	PCI_HTCAP_ADDRMAP_ID		0x14
985 #define	PCI_HTCAP_MSIMAP_ID		0x15
986 #define	PCI_HTCAP_DIRROUTE_ID		0x16
987 #define	PCI_HTCAP_VCSET_ID		0x17
988 #define	PCI_HTCAP_RETRYMODE_ID		0x18
989 #define	PCI_HTCAP_X86ENC_ID		0x19
990 #define	PCI_HTCAP_GEN3_ID		0x1A
991 #define	PCI_HTCAP_FUNCEXT_ID		0x1B
992 #define	PCI_HTCAP_PM_ID			0x1C
993 
994 #define	PCI_HTCAP_SLPRI_TYPE		/* 0x0000 */	\
995 	(PCI_HTCAP_SLPRI_ID	<< PCI_HTCAP_TYPE_SHIFT)
996 
997 #define	PCI_HTCAP_HOSTSEC_TYPE		/* 0x2000 */	\
998 	(PCI_HTCAP_HOSTSEC_ID	<< PCI_HTCAP_TYPE_SHIFT)
999 
1000 #define	PCI_HTCAP_SWITCH_TYPE		/* 0x4000 */	\
1001 	(PCI_HTCAP_SWITCH_ID	<< PCI_HTCAP_TYPE_SHIFT)
1002 
1003 #define	PCI_HTCAP_INTCONF_TYPE		/* 0x8000 */	\
1004 	(PCI_HTCAP_INTCONF_ID	<< PCI_HTCAP_TYPE_SHIFT)
1005 
1006 #define	PCI_HTCAP_REVID_TYPE		/* 0x8800 */	\
1007 	(PCI_HTCAP_REVID_ID	<< PCI_HTCAP_TYPE_SHIFT)
1008 
1009 #define	PCI_HTCAP_UNITID_CLUMP_TYPE	/* 0x9000 */	\
1010 	(PCI_HTCAP_UNITID_CLUMP_ID	<< PCI_HTCAP_TYPE_SHIFT)
1011 
1012 #define	PCI_HTCAP_ECFG_TYPE		/* 0x9800 */	\
1013 	(PCI_HTCAP_ECFG_ID	<< PCI_HTCAP_TYPE_SHIFT)
1014 
1015 #define	PCI_HTCAP_ADDRMAP_TYPE		/* 0xA000 */	\
1016 	(PCI_HTCAP_ADDRMAP_ID	<< PCI_HTCAP_TYPE_SHIFT)
1017 
1018 #define	PCI_HTCAP_MSIMAP_TYPE		/* 0xA800 */	\
1019 	(PCI_HTCAP_MSIMAP_ID	<< PCI_HTCAP_TYPE_SHIFT)
1020 
1021 #define	PCI_HTCAP_DIRROUTE_TYPE		/* 0xB000 */	\
1022 	(PCI_HTCAP_DIRROUTE_ID	<< PCI_HTCAP_TYPE_SHIFT)
1023 
1024 #define	PCI_HTCAP_VCSET_TYPE		/* 0xB800 */	\
1025 	(PCI_HTCAP_VCSET_ID	<< PCI_HTCAP_TYPE_SHIFT)
1026 
1027 #define	PCI_HTCAP_RETRYMODE_TYPE	/* 0xC000 */	\
1028 	(PCI_HTCAP_RETRYMODE_ID	<< PCI_HTCAP_TYPE_SHIFT)
1029 
1030 #define	PCI_HTCAP_X86ENC_TYPE		/* 0xC800 */	\
1031 	(PCI_HTCAP_X86ENC_ID	<< PCI_HTCAP_TYPE_SHIFT)
1032 
1033 #define	PCI_HTCAP_GEN3_TYPE		/* 0xD000 */	\
1034 	(PCI_HTCAP_GEN3_ID	<< PCI_HTCAP_TYPE_SHIFT)
1035 
1036 #define	PCI_HTCAP_FUNCEXT_TYPE		/* 0xD800 */	\
1037 	(PCI_HTCAP_FUNCEXT_ID	<< PCI_HTCAP_TYPE_SHIFT)
1038 
1039 #define	PCI_HTCAP_PM_TYPE		/* 0xE000 */	\
1040 	(PCI_HTCAP_PM_ID	<< PCI_HTCAP_TYPE_SHIFT)
1041 
1042 #define	PCI_HTCAP_MSIMAP_ENABLE			0x0001
1043 #define	PCI_HTCAP_MSIMAP_ENABLE_MASK		0x0001
1044 
1045 #define	PCI_HTCAP_ADDRMAP_MAPTYPE_MASK		0x600
1046 #define	PCI_HTCAP_ADDRMAP_MAPTYPE_SHIFT		9
1047 #define	PCI_HTCAP_ADDRMAP_NUMMAP_MASK		0xF
1048 #define	PCI_HTCAP_ADDRMAP_40BIT_ID		0x0
1049 #define	PCI_HTCAP_ADDRMAP_64BIT_ID		0x1
1050 
1051 #define	PCI_HTCAP_FUNCEXT_LEN_MASK		0xFF
1052 
1053 
1054 /*
1055  * other interesting PCI constants
1056  */
1057 #define	PCI_BASE_NUM	6	/* num of base regs in configuration header */
1058 #define	PCI_BAR_SZ_32	4	/* size of 32 bit base addr reg in bytes */
1059 #define	PCI_BAR_SZ_64	8	/* size of 64 bit base addr reg in bytes */
1060 #define	PCI_BASE_SIZE	4	/* size of base reg in bytes */
1061 #define	PCI_CONF_HDR_SIZE	256	/* configuration header size */
1062 #define	PCI_MAX_BUS_NUM		256		/* Maximum PCI buses allowed */
1063 #define	PCI_MAX_DEVICES		32		/* Max PCI devices allowed */
1064 #define	PCI_MAX_FUNCTIONS	8		/* Max PCI functions allowed */
1065 #define	PCI_MAX_CHILDREN	PCI_MAX_DEVICES * PCI_MAX_FUNCTIONS
1066 #define	PCI_CLK_33MHZ	(33 * 1000 * 1000)	/* 33MHz clock speed */
1067 #define	PCI_CLK_66MHZ	(66 * 1000 * 1000)	/* 66MHz clock speed */
1068 #define	PCI_CLK_133MHZ	(133 * 1000 * 1000)	/* 133MHz clock speed */
1069 
1070 /*
1071  * pci bus range definition
1072  */
1073 typedef struct pci_bus_range {
1074 	uint32_t lo;
1075 	uint32_t hi;
1076 } pci_bus_range_t;
1077 
1078 /*
1079  * The following typedef is used to represent an entry in the "ranges"
1080  * property of a pci hostbridge device node.
1081  */
1082 typedef struct pci_ranges {
1083 	uint32_t child_high;
1084 	uint32_t child_mid;
1085 	uint32_t child_low;
1086 	uint32_t parent_high;
1087 	uint32_t parent_low;
1088 	uint32_t size_high;
1089 	uint32_t size_low;
1090 } pci_ranges_t;
1091 
1092 /*
1093  * The following typedef is used to represent an entry in the "ranges"
1094  * property of a pci-pci bridge device node.
1095  */
1096 typedef struct {
1097 	uint32_t child_high;
1098 	uint32_t child_mid;
1099 	uint32_t child_low;
1100 	uint32_t parent_high;
1101 	uint32_t parent_mid;
1102 	uint32_t parent_low;
1103 	uint32_t size_high;
1104 	uint32_t size_low;
1105 } ppb_ranges_t;
1106 
1107 /*
1108  * This structure represents one entry of the 1275 "reg" property and
1109  * "assigned-addresses" property for a PCI node.  For the "reg" property, it
1110  * may be one of an arbitrary length array for devices with multiple address
1111  * windows.  For the "assigned-addresses" property, it denotes an assigned
1112  * physical address on the PCI bus.  It may be one entry of the six entries
1113  * for devices with multiple base registers.
1114  *
1115  * The physical address format is:
1116  *
1117  *             Bit#:  33222222 22221111 11111100 00000000
1118  *                    10987654 32109876 54321098 76543210
1119  *
1120  * pci_phys_hi cell:  npt000ss bbbbbbbb dddddfff rrrrrrrr
1121  * pci_phys_mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
1122  * pci_phys_low cell: llllllll llllllll llllllll llllllll
1123  *
1124  * n          is 0 if the address is relocatable, 1 otherwise
1125  * p          is 1 if the addressable region is "prefetchable", 0 otherwise
1126  * t          is 1 if the address is aliased (for non-relocatable I/O), below
1127  *	      1MB (for mem), or below 64 KB (for relocatable I/O).
1128  * ss         is the type code, denoting which address space
1129  * bbbbbbbb   is the 8-bit bus number
1130  * ddddd      is the 5-bit device number
1131  * fff        is the 3-bit function number
1132  * rrrrrrrr   is the 8-bit register number
1133  *	      should be zero for non-relocatable, when ss is 01, or 10
1134  * hh...hhh   is the 32-bit unsigned number
1135  * ll...lll   is the 32-bit unsigned number
1136  *
1137  * The physical size format is:
1138  *
1139  * pci_size_hi cell:  hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
1140  * pci_size_low cell: llllllll llllllll llllllll llllllll
1141  *
1142  * hh...hhh   is the 32-bit unsigned number
1143  * ll...lll   is the 32-bit unsigned number
1144  */
1145 struct pci_phys_spec {
1146 	uint_t pci_phys_hi;		/* child's address, hi word */
1147 	uint_t pci_phys_mid;		/* child's address, middle word */
1148 	uint_t pci_phys_low;		/* child's address, low word */
1149 	uint_t pci_size_hi;		/* high word of size field */
1150 	uint_t pci_size_low;		/* low word of size field */
1151 };
1152 
1153 typedef struct pci_phys_spec pci_regspec_t;
1154 
1155 /*
1156  * PCI masks for pci_phy_hi of PCI 1275 address cell.
1157  */
1158 #define	PCI_REG_REG_M		0xff		/* register mask */
1159 #define	PCI_REG_FUNC_M		0x700		/* function mask */
1160 #define	PCI_REG_DEV_M		0xf800		/* device mask */
1161 #define	PCI_REG_BUS_M		0xff0000	/* bus number mask */
1162 #define	PCI_REG_ADDR_M		0x3000000	/* address space mask */
1163 #define	PCI_REG_ALIAS_M		0x20000000	/* aliased bit mask */
1164 #define	PCI_REG_PF_M		0x40000000	/* prefetch bit mask */
1165 #define	PCI_REG_REL_M		0x80000000	/* relocation bit mask */
1166 #define	PCI_REG_BDFR_M		0xffffff	/* bus, dev, func, reg mask */
1167 #define	PCI_REG_EXTREG_M	0xF0000000	/* extended config bits mask */
1168 
1169 #define	PCI_REG_FUNC_SHIFT	8		/* Offset of function bits */
1170 #define	PCI_REG_DEV_SHIFT	11		/* Offset of device bits */
1171 #define	PCI_REG_BUS_SHIFT	16		/* Offset of bus bits */
1172 #define	PCI_REG_ADDR_SHIFT	24		/* Offset of address bits */
1173 #define	PCI_REG_EXTREG_SHIFT	28		/* Offset of ext. config bits */
1174 
1175 #define	PCI_REG_REG_G(x)	((x) & PCI_REG_REG_M)
1176 #define	PCI_REG_FUNC_G(x)	(((x) & PCI_REG_FUNC_M) >> PCI_REG_FUNC_SHIFT)
1177 #define	PCI_REG_DEV_G(x)	(((x) & PCI_REG_DEV_M) >> PCI_REG_DEV_SHIFT)
1178 #define	PCI_REG_BUS_G(x)	(((x) & PCI_REG_BUS_M) >> PCI_REG_BUS_SHIFT)
1179 #define	PCI_REG_ADDR_G(x)	(((x) & PCI_REG_ADDR_M) >> PCI_REG_ADDR_SHIFT)
1180 #define	PCI_REG_BDFR_G(x)	((x) & PCI_REG_BDFR_M)
1181 
1182 /*
1183  * PCI bit encodings of pci_phys_hi of PCI 1275 address cell.
1184  */
1185 #define	PCI_ADDR_MASK		PCI_REG_ADDR_M
1186 #define	PCI_ADDR_CONFIG		0x00000000	/* configuration address */
1187 #define	PCI_ADDR_IO		0x01000000	/* I/O address */
1188 #define	PCI_ADDR_MEM32		0x02000000	/* 32-bit memory address */
1189 #define	PCI_ADDR_MEM64		0x03000000	/* 64-bit memory address */
1190 #define	PCI_ALIAS_B		PCI_REG_ALIAS_M	/* aliased bit */
1191 #define	PCI_PREFETCH_B		PCI_REG_PF_M	/* prefetch bit */
1192 #define	PCI_RELOCAT_B		PCI_REG_REL_M	/* non-relocatable bit */
1193 #define	PCI_CONF_ADDR_MASK	0x00ffffff	/* mask for config address */
1194 
1195 #define	PCI_HARDDEC_8514 2	/* number of reg entries for 8514 hard-decode */
1196 #define	PCI_HARDDEC_VGA	3	/* number of reg entries for VGA hard-decode */
1197 #define	PCI_HARDDEC_IDE	4	/* number of reg entries for IDE hard-decode */
1198 #define	PCI_HARDDEC_IDE_PRI 2	/* number of reg entries for IDE primary */
1199 #define	PCI_HARDDEC_IDE_SEC 2	/* number of reg entries for IDE secondary */
1200 
1201 /*
1202  * PCI Expansion ROM Header Format
1203  */
1204 #define	PCI_ROM_SIGNATURE		0x0	/* ROM Signature 0xaa55 */
1205 #define	PCI_ROM_ARCH_UNIQUE_START	0x2	/* Start of processor unique */
1206 #define	PCI_ROM_PCI_DATA_STRUCT_PTR	0x18	/* Ptr to PCI Data Structure */
1207 
1208 /*
1209  * PCI Data Structure
1210  *
1211  * The PCI Data Structure is located within the first 64KB
1212  * of the ROM image and must be DWORD aligned.
1213  */
1214 #define	PCI_PDS_SIGNATURE	0x0	/* Signature, the string 'PCIR' */
1215 #define	PCI_PDS_VENDOR_ID	0x4	/* Vendor Identification */
1216 #define	PCI_PDS_DEVICE_ID	0x6	/* Device Identification */
1217 #define	PCI_PDS_VPD_PTR		0x8	/* Pointer to Vital Product Data */
1218 #define	PCI_PDS_PDS_LENGTH	0xa	/* PCI Data Structure Length */
1219 #define	PCI_PDS_PDS_REVISION	0xc	/* PCI Data Structure Revision */
1220 #define	PCI_PDS_CLASS_CODE	0xd	/* Class Code */
1221 #define	PCI_PDS_IMAGE_LENGTH	0x10	/* Image Length in 512 byte units */
1222 #define	PCI_PDS_CODE_REVISON	0x12	/* Revision Level of Code/Data */
1223 #define	PCI_PDS_CODE_TYPE	0x14	/* Code Type */
1224 #define	PCI_PDS_INDICATOR	0x15	/* Indicates if image is last in ROM */
1225 
1226 #define	PCI_PDS_CODE_TYPE_PCAT		0x0	/* Intel x86/PC-AT Type */
1227 #define	PCI_PDS_CODE_TYPE_OPEN_FW	0x1	/* Open Firmware */
1228 
1229 /*
1230  * we recognize the non transparent bridge child nodes with the
1231  * following property. This is specific to an implementation only.
1232  * This property is specific to AP nodes only.
1233  */
1234 #define	PCI_DEV_CONF_MAP_PROP	"pci-parent-indirect"
1235 
1236 /*
1237  * If a bridge device provides its own config space access services,
1238  * and supports a hotplug/hotswap bus below at any level, then
1239  * the following property must be defined for the node either by
1240  * the driver or the OBP.
1241  */
1242 #define	PCI_BUS_CONF_MAP_PROP	"pci-conf-indirect"
1243 
1244 #ifdef	__cplusplus
1245 }
1246 #endif
1247 
1248 #endif	/* _SYS_PCI_H */
1249