1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2025 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 #include <linux/device/driver.h> 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_private.h> 49 50 #include <machine/resource.h> 51 52 #include <linux/list.h> 53 #include <linux/dmapool.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/compiler.h> 56 #include <linux/errno.h> 57 #include <asm/atomic.h> 58 #include <asm/memtype.h> 59 #include <linux/device.h> 60 #include <linux/pci_ids.h> 61 #include <linux/pm.h> 62 #include <linux/interrupt.h> 63 64 /* 65 * <linux/ioport.h> should be included here, like Linux, but we can't have that 66 * because Linux `struct resource` definition would conflict with FreeBSD 67 * native definition. 68 * 69 * At least the amdgpu DRM driver (amdgpu_isp.c at the time of this writing) 70 * relies on this indirect include to get the definition of Linux `struct 71 * resource`. As a workaround, we include <linux/ioport.h> from 72 * <linux/mfd/core.h>. 73 */ 74 75 #include <linux/kernel.h> /* pr_debug */ 76 77 struct pci_device_id { 78 uint32_t vendor; 79 uint32_t device; 80 uint32_t subvendor; 81 uint32_t subdevice; 82 uint32_t class; 83 uint32_t class_mask; 84 uintptr_t driver_data; 85 }; 86 87 #define MODULE_DEVICE_TABLE_BUS_pci(_bus, _table) \ 88 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 89 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 90 91 #define PCI_ANY_ID -1U 92 93 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 94 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 95 #define PCI_FUNC(devfn) ((devfn) & 0x07) 96 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 97 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn)) 98 99 #define PCI_VDEVICE(_vendor, _device) \ 100 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 101 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 102 .class = 0, .class_mask = 0 103 #define PCI_DEVICE(_vendor, _device) \ 104 .vendor = (_vendor), .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 107 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 108 109 #define PCI_STD_NUM_BARS 6 110 #define PCI_BASE_ADDRESS_0 PCIR_BARS 111 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64 112 #define PCI_VENDOR_ID PCIR_VENDOR 113 #define PCI_DEVICE_ID PCIR_DEVICE 114 #define PCI_COMMAND PCIR_COMMAND 115 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 116 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 117 #define PCI_PRIMARY_BUS PCIR_PRIBUS_1 118 #define PCI_SECONDARY_BUS PCIR_SECBUS_1 119 #define PCI_SUBORDINATE_BUS PCIR_SUBBUS_1 120 #define PCI_SEC_LATENCY_TIMER PCIR_SECLAT_1 121 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 122 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 123 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 124 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 125 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 126 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 127 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 128 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 129 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 130 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 131 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 132 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 133 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 134 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 135 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 136 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 137 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 138 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 139 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 140 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 141 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 142 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 143 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 144 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 145 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 146 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 147 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 148 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 149 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 150 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 151 #define PCI_EXP_TYPE_UPSTREAM PCIEM_TYPE_UPSTREAM_PORT /* Upstream Port */ 152 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 153 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 154 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 155 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 156 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 157 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 158 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 159 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 160 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 161 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 162 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 163 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 164 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 165 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 166 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 167 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 168 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 169 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 170 #define PCI_EXP_LNKCTL2_TLS 0x000f 171 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 172 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 173 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 174 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 175 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 176 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 177 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 178 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 179 180 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 181 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 182 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 183 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 184 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 185 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 186 187 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 188 #define PCI_EXP_DEVSTA_TRPND 0x0020 189 190 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 191 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 192 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 193 194 enum pci_bus_speed { 195 PCI_SPEED_UNKNOWN = -1, 196 PCIE_SPEED_2_5GT, 197 PCIE_SPEED_5_0GT, 198 PCIE_SPEED_8_0GT, 199 PCIE_SPEED_16_0GT, 200 PCIE_SPEED_32_0GT, 201 PCIE_SPEED_64_0GT, 202 }; 203 204 enum pcie_link_width { 205 PCIE_LNK_WIDTH_RESRV = 0x00, 206 PCIE_LNK_X1 = 0x01, 207 PCIE_LNK_X2 = 0x02, 208 PCIE_LNK_X4 = 0x04, 209 PCIE_LNK_X8 = 0x08, 210 PCIE_LNK_X12 = 0x0c, 211 PCIE_LNK_X16 = 0x10, 212 PCIE_LNK_X32 = 0x20, 213 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 214 }; 215 216 #define PCIE_LINK_STATE_L0S 0x00000001 217 #define PCIE_LINK_STATE_L1 0x00000002 218 #define PCIE_LINK_STATE_CLKPM 0x00000004 219 220 typedef int pci_power_t; 221 222 #define PCI_D0 PCI_POWERSTATE_D0 223 #define PCI_D1 PCI_POWERSTATE_D1 224 #define PCI_D2 PCI_POWERSTATE_D2 225 #define PCI_D3hot PCI_POWERSTATE_D3_HOT 226 #define PCI_D3cold PCI_POWERSTATE_D3_COLD 227 228 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 229 230 extern const char *pci_power_names[6]; 231 232 #define PCI_ERR_UNCOR_STATUS PCIR_AER_UC_STATUS 233 #define PCI_ERR_COR_STATUS PCIR_AER_COR_STATUS 234 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 235 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 236 237 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 238 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 239 240 #define PCI_L1SS_CTL1 0x8 241 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 242 243 #define PCI_IRQ_INTX 0x01 244 #define PCI_IRQ_MSI 0x02 245 #define PCI_IRQ_MSIX 0x04 246 #define PCI_IRQ_AFFINITY 0x08 247 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_INTX) 248 249 #if defined(LINUXKPI_VERSION) && (LINUXKPI_VERSION <= 61000) 250 #define PCI_IRQ_LEGACY PCI_IRQ_INTX 251 #endif 252 253 /* 254 * Linux PCI code uses `PCI_SET_ERROR_RESPONSE()` to indicate to the caller of 255 * a `pci_read_*()` function that the read failed. An example of failure is 256 * whether the device was disconnected. It is a bit weird because Linux 257 * `pci_read_*()` can return an error value, as the read value is stored in a 258 * integer passed by pointer. 259 * 260 * We don't set PCI_ERROR_RESPONSE anywhere as of this commit, but the DRM 261 * drivers started to use `PCI_POSSIBLE_ERROR()`. 262 */ 263 #define PCI_ERROR_RESPONSE (~0ULL) 264 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 265 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 266 267 struct pci_dev; 268 269 struct pci_driver { 270 struct list_head node; 271 char *name; 272 const struct pci_device_id *id_table; 273 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 274 void (*remove)(struct pci_dev *dev); 275 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 276 int (*resume) (struct pci_dev *dev); /* Device woken up */ 277 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 278 driver_t bsddriver; 279 devclass_t bsdclass; 280 struct device_driver driver; 281 const struct pci_error_handlers *err_handler; 282 bool isdrm; 283 int bsd_probe_return; 284 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 285 const nvlist_t *pf_config); 286 void (*bsd_iov_uninit)(device_t dev); 287 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 288 const nvlist_t *vf_config); 289 }; 290 291 struct pci_bus { 292 struct pci_dev *self; 293 /* struct pci_bus *parent */ 294 int domain; 295 int number; 296 }; 297 298 #define __devexit_p(x) x 299 300 #define module_pci_driver(_drv) \ 301 module_driver(_drv, linux_pci_register_driver, linux_pci_unregister_driver) 302 303 struct msi_msg { 304 uint32_t data; 305 }; 306 307 struct pci_msi_desc { 308 struct { 309 bool is_64; 310 } msi_attrib; 311 }; 312 313 struct msi_desc { 314 struct msi_msg msg; 315 struct pci_msi_desc pci; 316 }; 317 318 struct msix_entry { 319 int entry; 320 int vector; 321 }; 322 323 /* 324 * If we find drivers accessing this from multiple KPIs we may have to 325 * refcount objects of this structure. 326 */ 327 struct resource; 328 struct pci_mmio_region { 329 TAILQ_ENTRY(pci_mmio_region) next; 330 struct resource *res; 331 int rid; 332 int type; 333 }; 334 335 struct pci_dev { 336 struct device dev; 337 struct list_head links; 338 struct pci_driver *pdrv; 339 struct pci_bus *bus; 340 struct pci_dev *root; 341 pci_power_t current_state; 342 uint16_t device; 343 uint16_t vendor; 344 uint16_t subsystem_vendor; 345 uint16_t subsystem_device; 346 unsigned int irq; 347 unsigned int devfn; 348 uint32_t class; 349 uint8_t revision; 350 uint8_t msi_cap; 351 uint8_t msix_cap; 352 bool managed; /* devres "pcim_*(). */ 353 bool want_iomap_res; 354 bool msi_enabled; 355 bool msix_enabled; 356 phys_addr_t rom; 357 size_t romlen; 358 struct msi_desc **msi_desc; 359 char *path_name; 360 spinlock_t pcie_cap_lock; 361 362 TAILQ_HEAD(, pci_mmio_region) mmio; 363 }; 364 365 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 366 unsigned int flags); 367 bool pci_device_is_present(struct pci_dev *pdev); 368 369 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 370 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 371 void *linuxkpi_pci_iomap_range(struct pci_dev *, int, 372 unsigned long, unsigned long); 373 void *linuxkpi_pci_iomap(struct pci_dev *, int, unsigned long); 374 void *linuxkpi_pcim_iomap(struct pci_dev *, int, unsigned long); 375 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 376 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 377 const char *name); 378 int linuxkpi_pci_request_region(struct pci_dev *, int, const char *); 379 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 380 int linuxkpi_pcim_request_all_regions(struct pci_dev *, const char *); 381 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 382 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 383 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 384 int nreq); 385 386 /* Internal helper function(s). */ 387 struct pci_dev *lkpinew_pci_dev(device_t); 388 void lkpi_pci_devres_release(struct device *, void *); 389 struct pci_dev *lkpi_pci_get_device(uint32_t, uint32_t, struct pci_dev *); 390 struct msi_desc *lkpi_pci_msi_desc_alloc(unsigned int); 391 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 392 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 393 394 #define pci_err(pdev, fmt, ...) \ 395 dev_err(&(pdev)->dev, fmt, ##__VA_ARGS__) 396 #define pci_info(pdev, fmt, ...) \ 397 dev_info(&(pdev)->dev, fmt, ##__VA_ARGS__) 398 399 static inline bool 400 dev_is_pci(struct device *dev) 401 { 402 return (is_pci_device(dev->bsddev)); 403 } 404 405 static inline uint16_t 406 pci_dev_id(struct pci_dev *pdev) 407 { 408 return (PCI_DEVID(pdev->bus->number, pdev->devfn)); 409 } 410 411 static inline int 412 pci_resource_type(struct pci_dev *pdev, int bar) 413 { 414 struct pci_map *pm; 415 416 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 417 if (!pm) 418 return (-1); 419 420 if (PCI_BAR_IO(pm->pm_value)) 421 return (SYS_RES_IOPORT); 422 else 423 return (SYS_RES_MEMORY); 424 } 425 426 /* 427 * All drivers just seem to want to inspect the type not flags. 428 */ 429 static inline int 430 pci_resource_flags(struct pci_dev *pdev, int bar) 431 { 432 int type; 433 434 type = pci_resource_type(pdev, bar); 435 if (type < 0) 436 return (0); 437 return (1 << type); 438 } 439 440 static inline int 441 pci_select_bars(struct pci_dev *pdev, unsigned long flags) 442 { 443 int bars, bar; 444 445 bars = 0; 446 /* We only support BARs here; Linux may support more types. */ 447 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 448 int bar_flags; 449 450 bar_flags = pci_resource_flags(pdev, bar); 451 if ((bar_flags & flags) != 0) 452 bars |= (1 << bar); 453 } 454 455 return (bars); 456 } 457 458 static inline const char * 459 pci_name(struct pci_dev *d) 460 { 461 return d->path_name; 462 } 463 464 static inline void * 465 pci_get_drvdata(struct pci_dev *pdev) 466 { 467 468 return dev_get_drvdata(&pdev->dev); 469 } 470 471 static inline void 472 pci_set_drvdata(struct pci_dev *pdev, void *data) 473 { 474 475 dev_set_drvdata(&pdev->dev, data); 476 } 477 478 static inline struct pci_dev * 479 pci_dev_get(struct pci_dev *pdev) 480 { 481 482 if (pdev != NULL) 483 get_device(&pdev->dev); 484 return (pdev); 485 } 486 487 static __inline void 488 pci_dev_put(struct pci_dev *pdev) 489 { 490 491 if (pdev != NULL) 492 put_device(&pdev->dev); 493 } 494 495 static inline int 496 pci_enable_device(struct pci_dev *pdev) 497 { 498 499 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 500 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 501 return (0); 502 } 503 504 static inline void 505 pci_disable_device(struct pci_dev *pdev) 506 { 507 508 pci_disable_busmaster(pdev->dev.bsddev); 509 } 510 511 static inline int 512 pci_set_master(struct pci_dev *pdev) 513 { 514 515 pci_enable_busmaster(pdev->dev.bsddev); 516 return (0); 517 } 518 519 static inline int 520 pci_set_power_state(struct pci_dev *pdev, int state) 521 { 522 523 pci_set_powerstate(pdev->dev.bsddev, state); 524 return (0); 525 } 526 527 static inline int 528 pci_clear_master(struct pci_dev *pdev) 529 { 530 531 pci_disable_busmaster(pdev->dev.bsddev); 532 return (0); 533 } 534 535 static inline bool 536 pci_is_root_bus(struct pci_bus *pbus) 537 { 538 539 return (pbus->self == NULL); 540 } 541 542 static inline struct pci_dev * 543 pci_upstream_bridge(struct pci_dev *pdev) 544 { 545 546 if (pci_is_root_bus(pdev->bus)) 547 return (NULL); 548 549 /* 550 * If we do not have a (proper) "upstream bridge" set, e.g., we point 551 * to ourselves, try to handle this case on the fly like we do 552 * for pcie_find_root_port(). 553 */ 554 if (pdev == pdev->bus->self) { 555 device_t bridge; 556 557 /* 558 * In the case of DRM drivers, the passed device is a child of 559 * `vgapci`. We want to start the lookup from `vgapci`, so the 560 * parent of the passed `drmn`. 561 * 562 * We can use the `isdrm` flag to determine this. 563 */ 564 bridge = pdev->dev.bsddev; 565 if (pdev->pdrv != NULL && pdev->pdrv->isdrm) 566 bridge = device_get_parent(bridge); 567 if (bridge == NULL) 568 goto done; 569 570 bridge = device_get_parent(bridge); 571 if (bridge == NULL) 572 goto done; 573 bridge = device_get_parent(bridge); 574 if (bridge == NULL) 575 goto done; 576 if (!is_pci_device(bridge)) 577 goto done; 578 579 /* 580 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 581 * for it so it can be returned. 582 */ 583 pdev->bus->self = lkpinew_pci_dev(bridge); 584 } 585 done: 586 return (pdev->bus->self); 587 } 588 589 #define pci_request_region(pdev, bar, res_name) \ 590 linuxkpi_pci_request_region(pdev, bar, res_name) 591 #define pci_release_region(pdev, bar) \ 592 linuxkpi_pci_release_region(pdev, bar) 593 #define pci_request_regions(pdev, res_name) \ 594 linuxkpi_pci_request_regions(pdev, res_name) 595 #define pci_release_regions(pdev) \ 596 linuxkpi_pci_release_regions(pdev) 597 #define pcim_request_all_regions(pdev, name) \ 598 linuxkpi_pcim_request_all_regions(pdev, name) 599 600 static inline void 601 lkpi_pci_disable_msix(struct pci_dev *pdev) 602 { 603 604 pci_release_msi(pdev->dev.bsddev); 605 606 /* 607 * The MSIX IRQ numbers associated with this PCI device are no 608 * longer valid and might be re-assigned. Make sure 609 * lkpi_pci_find_irq_dev() does no longer see them by 610 * resetting their references to zero: 611 */ 612 pdev->dev.irq_start = 0; 613 pdev->dev.irq_end = 0; 614 pdev->msix_enabled = false; 615 } 616 /* Only for consistency. No conflict on that one. */ 617 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 618 619 static inline void 620 lkpi_pci_disable_msi(struct pci_dev *pdev) 621 { 622 623 pci_release_msi(pdev->dev.bsddev); 624 625 pdev->dev.irq_start = 0; 626 pdev->dev.irq_end = 0; 627 pdev->irq = pdev->dev.irq; 628 pdev->msi_enabled = false; 629 } 630 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 631 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 632 633 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 634 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 635 636 static inline bus_addr_t 637 pci_bus_address(struct pci_dev *pdev, int bar) 638 { 639 640 return (pci_resource_start(pdev, bar)); 641 } 642 643 #define PCI_CAP_ID_EXP PCIY_EXPRESS 644 #define PCI_CAP_ID_PCIX PCIY_PCIX 645 #define PCI_CAP_ID_AGP PCIY_AGP 646 #define PCI_CAP_ID_PM PCIY_PMG 647 648 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 649 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 650 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 651 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 652 #define PCI_EXP_LNKSTA PCIER_LINK_STA 653 654 static inline int 655 pci_find_capability(struct pci_dev *pdev, int capid) 656 { 657 int reg; 658 659 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 660 return (0); 661 return (reg); 662 } 663 664 static inline int pci_pcie_cap(struct pci_dev *dev) 665 { 666 return pci_find_capability(dev, PCI_CAP_ID_EXP); 667 } 668 669 static inline int 670 pci_find_ext_capability(struct pci_dev *pdev, int capid) 671 { 672 int reg; 673 674 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 675 return (0); 676 return (reg); 677 } 678 679 static __inline bool 680 pci_pme_capable(struct pci_dev *pdev, pci_power_t state) 681 { 682 return (pci_has_pme(pdev->dev.bsddev, state)); 683 } 684 685 static inline int 686 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 687 { 688 689 if (!pci_enable_aspm) 690 return (-EPERM); 691 692 return (-ENXIO); 693 } 694 695 static inline int 696 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 697 { 698 699 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 700 return (0); 701 } 702 703 static inline int 704 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 705 { 706 707 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 708 return (0); 709 } 710 711 static inline int 712 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 713 { 714 715 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 716 return (0); 717 } 718 719 static inline int 720 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 721 { 722 723 pci_write_config(pdev->dev.bsddev, where, val, 1); 724 return (0); 725 } 726 727 static inline int 728 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 729 { 730 731 pci_write_config(pdev->dev.bsddev, where, val, 2); 732 return (0); 733 } 734 735 static inline int 736 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 737 { 738 739 pci_write_config(pdev->dev.bsddev, where, val, 4); 740 return (0); 741 } 742 743 int linux_pci_register_driver(struct pci_driver *pdrv); 744 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 745 void linux_pci_unregister_driver(struct pci_driver *pdrv); 746 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 747 748 #define pci_register_driver(pdrv) \ 749 linux_pci_register_driver(pdrv) 750 #define pci_unregister_driver(pdrv) \ 751 linux_pci_unregister_driver(pdrv) 752 753 /* 754 * Enable msix, positive errors indicate actual number of available 755 * vectors. Negative errors are failures. 756 * 757 * NB: define added to prevent this definition of pci_enable_msix from 758 * clashing with the native FreeBSD version. 759 */ 760 #define pci_enable_msix(...) \ 761 linuxkpi_pci_enable_msix(__VA_ARGS__) 762 763 #define pci_enable_msix_range(...) \ 764 linux_pci_enable_msix_range(__VA_ARGS__) 765 766 static inline int 767 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 768 int minvec, int maxvec) 769 { 770 int nvec = maxvec; 771 int rc; 772 773 if (maxvec < minvec) 774 return (-ERANGE); 775 776 do { 777 rc = pci_enable_msix(dev, entries, nvec); 778 if (rc < 0) { 779 return (rc); 780 } else if (rc > 0) { 781 if (rc < minvec) 782 return (-ENOSPC); 783 nvec = rc; 784 } 785 } while (rc); 786 return (nvec); 787 } 788 789 #define pci_enable_msi(pdev) \ 790 linux_pci_enable_msi(pdev) 791 792 static inline int 793 pci_enable_msi(struct pci_dev *pdev) 794 { 795 796 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 797 } 798 799 static inline int 800 pci_channel_offline(struct pci_dev *pdev) 801 { 802 803 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 804 } 805 806 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 807 { 808 return -ENODEV; 809 } 810 811 static inline void pci_disable_sriov(struct pci_dev *dev) 812 { 813 } 814 815 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \ 816 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) 817 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 818 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 819 #define pcim_iomap(pdev, bar, maxlen) \ 820 linuxkpi_pcim_iomap(pdev, bar, maxlen) 821 #define pci_iounmap(pdev, res) \ 822 linuxkpi_pci_iounmap(pdev, res) 823 824 static inline void 825 lkpi_pci_save_state(struct pci_dev *pdev) 826 { 827 828 pci_save_state(pdev->dev.bsddev); 829 } 830 831 static inline void 832 lkpi_pci_restore_state(struct pci_dev *pdev) 833 { 834 835 pci_restore_state(pdev->dev.bsddev); 836 } 837 838 #define pci_save_state(dev) lkpi_pci_save_state(dev) 839 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 840 841 static inline int 842 linuxkpi_pci_enable_wake(struct pci_dev *pdev, pci_power_t state, bool ena) 843 { 844 /* 845 * We do not currently support this in device.h either to 846 * check if the device is allowed to wake up in first place. 847 */ 848 pr_debug("%s: TODO\n", __func__); 849 return (0); 850 } 851 #define pci_enable_wake(dev, state, ena) \ 852 linuxkpi_pci_enable_wake(dev, state, ena) 853 854 static inline int 855 pci_reset_function(struct pci_dev *pdev) 856 { 857 858 return (-ENOSYS); 859 } 860 861 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 862 const struct pci_device_id _table[] __devinitdata 863 864 /* XXX This should not be necessary. */ 865 #define pcix_set_mmrbc(d, v) 0 866 #define pcix_get_max_mmrbc(d) 0 867 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 868 869 #define PCI_DMA_BIDIRECTIONAL 0 870 #define PCI_DMA_TODEVICE 1 871 #define PCI_DMA_FROMDEVICE 2 872 #define PCI_DMA_NONE 3 873 874 #define pci_pool dma_pool 875 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 876 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 877 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 878 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 879 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 880 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 881 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 882 _size, _vaddr, _dma_handle) 883 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 884 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 885 _sg, _nents, (enum dma_data_direction)_dir) 886 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 887 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 888 (_ptr), (_size), (enum dma_data_direction)_dir) 889 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 890 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 891 _addr, _size, (enum dma_data_direction)_dir) 892 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 893 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 894 _sg, _nents, (enum dma_data_direction)_dir) 895 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 896 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 897 _offset, _size, (enum dma_data_direction)_dir) 898 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 899 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 900 _dma_address, _size, (enum dma_data_direction)_dir) 901 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 902 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 903 dma_mapping_error(&(_pdev)->dev, _dma_addr) 904 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 905 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 906 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 907 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 908 #define pci_unmap_addr dma_unmap_addr 909 #define pci_unmap_addr_set dma_unmap_addr_set 910 #define pci_unmap_len dma_unmap_len 911 #define pci_unmap_len_set dma_unmap_len_set 912 913 void *linuxkpi_pci_map_rom(struct pci_dev *pdev, size_t *size); 914 void linuxkpi_pci_unmap_rom(struct pci_dev *pdev, void *rom); 915 #define pci_map_rom(pdev, size) linuxkpi_pci_map_rom(pdev, size) 916 #define pci_unmap_rom(pdev, rom) linuxkpi_pci_unmap_rom(pdev, rom) 917 918 typedef unsigned int __bitwise pci_channel_state_t; 919 typedef unsigned int __bitwise pci_ers_result_t; 920 921 enum pci_channel_state { 922 pci_channel_io_normal = 1, 923 pci_channel_io_frozen = 2, 924 pci_channel_io_perm_failure = 3, 925 }; 926 927 enum pci_ers_result { 928 PCI_ERS_RESULT_NONE = 1, 929 PCI_ERS_RESULT_CAN_RECOVER = 2, 930 PCI_ERS_RESULT_NEED_RESET = 3, 931 PCI_ERS_RESULT_DISCONNECT = 4, 932 PCI_ERS_RESULT_RECOVERED = 5, 933 }; 934 935 /* PCI bus error event callbacks */ 936 struct pci_error_handlers { 937 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 938 enum pci_channel_state error); 939 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 940 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 941 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 942 void (*resume)(struct pci_dev *dev); 943 void (*reset_prepare)(struct pci_dev *); 944 void (*reset_done)(struct pci_dev *); 945 }; 946 947 /* FreeBSD does not support SRIOV - yet */ 948 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 949 { 950 return dev; 951 } 952 953 static inline bool pci_is_pcie(struct pci_dev *dev) 954 { 955 return !!pci_pcie_cap(dev); 956 } 957 958 static inline u16 pcie_flags_reg(struct pci_dev *dev) 959 { 960 int pos; 961 u16 reg16; 962 963 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 964 if (!pos) 965 return 0; 966 967 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 968 969 return reg16; 970 } 971 972 static inline int pci_pcie_type(struct pci_dev *dev) 973 { 974 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 975 } 976 977 static inline int pcie_cap_version(struct pci_dev *dev) 978 { 979 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 980 } 981 982 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 983 { 984 int type = pci_pcie_type(dev); 985 986 return pcie_cap_version(dev) > 1 || 987 type == PCI_EXP_TYPE_ROOT_PORT || 988 type == PCI_EXP_TYPE_ENDPOINT || 989 type == PCI_EXP_TYPE_LEG_END; 990 } 991 992 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 993 { 994 return true; 995 } 996 997 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 998 { 999 int type = pci_pcie_type(dev); 1000 1001 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1002 (type == PCI_EXP_TYPE_DOWNSTREAM && 1003 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1004 } 1005 1006 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1007 { 1008 int type = pci_pcie_type(dev); 1009 1010 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1011 type == PCI_EXP_TYPE_RC_EC; 1012 } 1013 1014 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1015 { 1016 if (!pci_is_pcie(dev)) 1017 return false; 1018 1019 switch (pos) { 1020 case PCI_EXP_FLAGS_TYPE: 1021 return true; 1022 case PCI_EXP_DEVCAP: 1023 case PCI_EXP_DEVCTL: 1024 case PCI_EXP_DEVSTA: 1025 return pcie_cap_has_devctl(dev); 1026 case PCI_EXP_LNKCAP: 1027 case PCI_EXP_LNKCTL: 1028 case PCI_EXP_LNKSTA: 1029 return pcie_cap_has_lnkctl(dev); 1030 case PCI_EXP_SLTCAP: 1031 case PCI_EXP_SLTCTL: 1032 case PCI_EXP_SLTSTA: 1033 return pcie_cap_has_sltctl(dev); 1034 case PCI_EXP_RTCTL: 1035 case PCI_EXP_RTCAP: 1036 case PCI_EXP_RTSTA: 1037 return pcie_cap_has_rtctl(dev); 1038 case PCI_EXP_DEVCAP2: 1039 case PCI_EXP_DEVCTL2: 1040 case PCI_EXP_LNKCAP2: 1041 case PCI_EXP_LNKCTL2: 1042 case PCI_EXP_LNKSTA2: 1043 return pcie_cap_version(dev) > 1; 1044 default: 1045 return false; 1046 } 1047 } 1048 1049 static inline int 1050 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1051 { 1052 *dst = 0; 1053 if (pos & 3) 1054 return -EINVAL; 1055 1056 if (!pcie_capability_reg_implemented(dev, pos)) 1057 return -EINVAL; 1058 1059 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1060 } 1061 1062 static inline int 1063 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1064 { 1065 *dst = 0; 1066 if (pos & 3) 1067 return -EINVAL; 1068 1069 if (!pcie_capability_reg_implemented(dev, pos)) 1070 return -EINVAL; 1071 1072 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1073 } 1074 1075 static inline int 1076 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1077 { 1078 if (pos & 1) 1079 return -EINVAL; 1080 1081 if (!pcie_capability_reg_implemented(dev, pos)) 1082 return 0; 1083 1084 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1085 } 1086 1087 static inline int 1088 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1089 uint16_t clear, uint16_t set) 1090 { 1091 int error; 1092 uint16_t v; 1093 1094 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1095 spin_lock(&dev->pcie_cap_lock); 1096 1097 error = pcie_capability_read_word(dev, pos, &v); 1098 if (error == 0) { 1099 v &= ~clear; 1100 v |= set; 1101 error = pcie_capability_write_word(dev, pos, v); 1102 } 1103 1104 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1105 spin_unlock(&dev->pcie_cap_lock); 1106 1107 return (error); 1108 } 1109 1110 static inline int 1111 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1112 { 1113 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1114 } 1115 1116 static inline int 1117 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1118 { 1119 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1120 } 1121 1122 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1123 enum pci_bus_speed *speed, enum pcie_link_width *width) 1124 { 1125 *speed = PCI_SPEED_UNKNOWN; 1126 *width = PCIE_LNK_WIDTH_UNKNOWN; 1127 return (0); 1128 } 1129 1130 static inline int 1131 pci_num_vf(struct pci_dev *dev) 1132 { 1133 return (0); 1134 } 1135 1136 static inline enum pci_bus_speed 1137 pcie_get_speed_cap(struct pci_dev *dev) 1138 { 1139 struct pci_dev *pbus; 1140 device_t root; 1141 uint32_t lnkcap, lnkcap2; 1142 int error, pos; 1143 1144 /* 1145 * We should always be called on a PCI device. 1146 * The only current consumer I could find was amdgpu which either 1147 * calls us directly on a pdev(drmn?) or with the result of 1148 * pci_upstream_bridge(). 1149 * 1150 * Treat "drmn" as special again as it is not a PCI device. 1151 */ 1152 if (dev->pdrv != NULL && dev->pdrv->isdrm) { 1153 pbus = pci_upstream_bridge(dev); 1154 if (pbus == NULL) 1155 return (PCI_SPEED_UNKNOWN); 1156 } else 1157 pbus = dev; 1158 1159 /* "root" may be misleading as it may not be that. */ 1160 root = pbus->dev.bsddev; 1161 1162 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1163 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1164 return (PCI_SPEED_UNKNOWN); 1165 1166 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1167 return (PCI_SPEED_UNKNOWN); 1168 1169 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1170 1171 if (lnkcap2) { /* PCIe r3.0-compliant */ 1172 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1173 return (PCIE_SPEED_2_5GT); 1174 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1175 return (PCIE_SPEED_5_0GT); 1176 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1177 return (PCIE_SPEED_8_0GT); 1178 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1179 return (PCIE_SPEED_16_0GT); 1180 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1181 return (PCIE_SPEED_32_0GT); 1182 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1183 return (PCIE_SPEED_64_0GT); 1184 } else { /* pre-r3.0 */ 1185 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1186 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1187 return (PCIE_SPEED_2_5GT); 1188 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1189 return (PCIE_SPEED_5_0GT); 1190 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1191 return (PCIE_SPEED_8_0GT); 1192 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1193 return (PCIE_SPEED_16_0GT); 1194 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1195 return (PCIE_SPEED_32_0GT); 1196 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1197 return (PCIE_SPEED_64_0GT); 1198 } 1199 return (PCI_SPEED_UNKNOWN); 1200 } 1201 1202 static inline enum pcie_link_width 1203 pcie_get_width_cap(struct pci_dev *dev) 1204 { 1205 uint32_t lnkcap; 1206 1207 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1208 if (lnkcap) 1209 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1210 1211 return (PCIE_LNK_WIDTH_UNKNOWN); 1212 } 1213 1214 static inline int 1215 pcie_get_mps(struct pci_dev *dev) 1216 { 1217 return (pci_get_max_payload(dev->dev.bsddev)); 1218 } 1219 1220 static inline uint32_t 1221 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1222 { 1223 1224 switch(spd) { 1225 case PCIE_SPEED_64_0GT: 1226 return (64000 * 128 / 130); 1227 case PCIE_SPEED_32_0GT: 1228 return (32000 * 128 / 130); 1229 case PCIE_SPEED_16_0GT: 1230 return (16000 * 128 / 130); 1231 case PCIE_SPEED_8_0GT: 1232 return (8000 * 128 / 130); 1233 case PCIE_SPEED_5_0GT: 1234 return (5000 * 8 / 10); 1235 case PCIE_SPEED_2_5GT: 1236 return (2500 * 8 / 10); 1237 default: 1238 return (0); 1239 } 1240 } 1241 1242 static inline uint32_t 1243 pcie_bandwidth_available(struct pci_dev *pdev, 1244 struct pci_dev **limiting, 1245 enum pci_bus_speed *speed, 1246 enum pcie_link_width *width) 1247 { 1248 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1249 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1250 1251 if (speed) 1252 *speed = nspeed; 1253 if (width) 1254 *width = nwidth; 1255 1256 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1257 } 1258 1259 static inline bool 1260 pcie_aspm_enabled(struct pci_dev *pdev) 1261 { 1262 return (false); 1263 } 1264 1265 static inline struct pci_dev * 1266 pcie_find_root_port(struct pci_dev *pdev) 1267 { 1268 device_t root; 1269 1270 if (pdev->root != NULL) 1271 return (pdev->root); 1272 1273 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1274 if (root == NULL) 1275 return (NULL); 1276 1277 pdev->root = lkpinew_pci_dev(root); 1278 return (pdev->root); 1279 } 1280 1281 /* This is needed when people rip out the device "HotPlug". */ 1282 static inline void 1283 pci_lock_rescan_remove(void) 1284 { 1285 } 1286 1287 static inline void 1288 pci_unlock_rescan_remove(void) 1289 { 1290 } 1291 1292 static __inline void 1293 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1294 { 1295 } 1296 1297 static inline int 1298 pci_rescan_bus(struct pci_bus *pbus) 1299 { 1300 device_t *devlist, parent; 1301 int devcount, error; 1302 1303 if (!device_is_attached(pbus->self->dev.bsddev)) 1304 return (0); 1305 /* pci_rescan_method() will work on the pcib (parent). */ 1306 error = BUS_RESCAN(pbus->self->dev.bsddev); 1307 if (error != 0) 1308 return (0); 1309 1310 parent = device_get_parent(pbus->self->dev.bsddev); 1311 error = device_get_children(parent, &devlist, &devcount); 1312 if (error != 0) 1313 return (0); 1314 if (devcount != 0) 1315 free(devlist, M_TEMP); 1316 1317 return (devcount); 1318 } 1319 1320 /* 1321 * The following functions can be used to attach/detach the LinuxKPI's 1322 * PCI device runtime. The pci_driver and pci_device_id pointer is 1323 * allowed to be NULL. Other pointers must be all valid. 1324 * The pci_dev structure should be zero-initialized before passed 1325 * to the linux_pci_attach_device function. 1326 */ 1327 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1328 const struct pci_device_id *, struct pci_dev *); 1329 extern int linux_pci_detach_device(struct pci_dev *); 1330 1331 static inline int 1332 pci_dev_present(const struct pci_device_id *cur) 1333 { 1334 while (cur != NULL && (cur->vendor || cur->device)) { 1335 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1336 return (1); 1337 } 1338 cur++; 1339 } 1340 return (0); 1341 } 1342 1343 static inline bool 1344 pci_dev_is_disconnected(const struct pci_dev *pdev) 1345 { 1346 pr_debug("TODO: %s\n", __func__); 1347 return (false); 1348 } 1349 1350 static inline const struct pci_device_id * 1351 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev) 1352 { 1353 if (ids == NULL) 1354 return (NULL); 1355 1356 for (; 1357 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0; 1358 ids++) 1359 if ((ids->vendor == PCI_ANY_ID || 1360 ids->vendor == pdev->vendor) && 1361 (ids->device == PCI_ANY_ID || 1362 ids->device == pdev->device) && 1363 (ids->subvendor == PCI_ANY_ID || 1364 ids->subvendor == pdev->subsystem_vendor) && 1365 (ids->subdevice == PCI_ANY_ID || 1366 ids->subdevice == pdev->subsystem_device) && 1367 ((ids->class ^ pdev->class) & ids->class_mask) == 0) 1368 return (ids); 1369 1370 return (NULL); 1371 } 1372 1373 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1374 unsigned int bus, unsigned int devfn); 1375 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1376 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1377 1378 struct pci_dev *lkpi_pci_get_slot(struct pci_bus *, unsigned int); 1379 #ifndef WANT_NATIVE_PCI_GET_SLOT 1380 #define pci_get_slot(_pbus, _devfn) \ 1381 lkpi_pci_get_slot(_pbus, _devfn) 1382 #endif 1383 1384 static inline int 1385 pci_domain_nr(struct pci_bus *pbus) 1386 { 1387 1388 return (pbus->domain); 1389 } 1390 1391 static inline int 1392 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1393 int pos, uint32_t *val, int len) 1394 { 1395 1396 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1397 return (0); 1398 } 1399 1400 static inline int 1401 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1402 { 1403 uint32_t tmp; 1404 int ret; 1405 1406 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1407 *val = (u16)tmp; 1408 return (ret); 1409 } 1410 1411 static inline int 1412 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1413 { 1414 uint32_t tmp; 1415 int ret; 1416 1417 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1418 *val = (u8)tmp; 1419 return (ret); 1420 } 1421 1422 static inline int 1423 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1424 uint32_t val, int size) 1425 { 1426 1427 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1428 return (0); 1429 } 1430 1431 static inline int 1432 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1433 uint8_t val) 1434 { 1435 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1436 } 1437 1438 static inline int 1439 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1440 uint16_t val) 1441 { 1442 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1443 } 1444 1445 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1446 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1447 struct pci_dev *lkpi_pci_get_base_class(unsigned int class, 1448 struct pci_dev *from); 1449 #define pci_get_base_class(class, from) lkpi_pci_get_base_class(class, from) 1450 1451 /* -------------------------------------------------------------------------- */ 1452 1453 #define pcim_enable_device(pdev) \ 1454 linuxkpi_pcim_enable_device(pdev) 1455 #define pcim_iomap_table(pdev) \ 1456 linuxkpi_pcim_iomap_table(pdev) 1457 #define pcim_iomap_regions(pdev, mask, name) \ 1458 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1459 1460 static inline int 1461 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1462 { 1463 uint32_t requests, req_mask; 1464 int bar, error; 1465 1466 /* Request all the BARs ("regions") we do not iomap. */ 1467 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1468 for (bar = requests = 0; requests != req_mask; bar++) { 1469 if ((req_mask & (1 << bar)) == 0) 1470 continue; 1471 error = pci_request_region(pdev, bar, name); 1472 if (error != 0 && error != -ENODEV) 1473 goto err; 1474 requests |= (1 << bar); 1475 } 1476 1477 error = pcim_iomap_regions(pdev, mask, name); 1478 if (error != 0) 1479 goto err; 1480 1481 return (0); 1482 1483 err: 1484 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1485 if ((requests & (1 << bar)) != 0) 1486 pci_release_region(pdev, bar); 1487 } 1488 1489 return (-EINVAL); 1490 } 1491 1492 /* 1493 * We cannot simply re-define pci_get_device() as we would normally do 1494 * and then hide it in linux_pci.c as too many semi-native drivers still 1495 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1496 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1497 */ 1498 static inline struct pci_dev * 1499 linuxkpi_pci_get_device(uint32_t vendor, uint32_t device, struct pci_dev *odev) 1500 { 1501 1502 return (lkpi_pci_get_device(vendor, device, odev)); 1503 } 1504 1505 #define for_each_pci_dev(_pdev) \ 1506 while ((_pdev = linuxkpi_pci_get_device(PCI_ANY_ID, PCI_ANY_ID, _pdev)) != NULL) 1507 1508 /* This is a FreeBSD extension so we can use bus_*(). */ 1509 static inline void 1510 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1511 { 1512 pdev->want_iomap_res = true; 1513 } 1514 1515 static inline bool 1516 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1517 { 1518 1519 return (false); 1520 } 1521 1522 static inline void * 1523 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1524 { 1525 1526 return (NULL); 1527 } 1528 1529 static inline void 1530 pci_ignore_hotplug(struct pci_dev *pdev) 1531 { 1532 } 1533 1534 static inline const char * 1535 pci_power_name(pci_power_t state) 1536 { 1537 int pstate = state + 1; 1538 1539 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1540 return (pci_power_names[pstate]); 1541 else 1542 return (pci_power_names[0]); 1543 } 1544 1545 static inline int 1546 pcie_get_readrq(struct pci_dev *dev) 1547 { 1548 u16 ctl; 1549 1550 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1551 return (-EINVAL); 1552 1553 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1554 } 1555 1556 static inline bool 1557 pci_is_enabled(struct pci_dev *pdev) 1558 { 1559 1560 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1561 PCIM_CMD_BUSMASTEREN) != 0); 1562 } 1563 1564 static inline int 1565 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1566 { 1567 1568 return (0); 1569 } 1570 1571 static inline int 1572 pci_assign_resource(struct pci_dev *pdev, int bar) 1573 { 1574 1575 return (0); 1576 } 1577 1578 static inline int 1579 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1580 { 1581 1582 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1583 if (vector != 0) 1584 return (-EINVAL); 1585 return (pdev->irq); 1586 } 1587 1588 if (pdev->msix_enabled || pdev->msi_enabled) { 1589 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1590 return (-EINVAL); 1591 return (pdev->dev.irq_start + vector); 1592 } 1593 1594 return (-ENXIO); 1595 } 1596 1597 static inline int 1598 pci_msix_vec_count(struct pci_dev *pdev) 1599 { 1600 int avail; 1601 1602 avail = pci_msix_count(pdev->dev.bsddev); 1603 if (avail == 0) 1604 return (-EINVAL); 1605 return (avail); 1606 } 1607 1608 static inline int 1609 pci_wake_from_d3(struct pci_dev *pdev, bool enable) 1610 { 1611 1612 pr_debug("%s: TODO\n", __func__); 1613 return (0); 1614 } 1615 1616 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1617