1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2025 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 #include <linux/device/driver.h> 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_private.h> 49 50 #include <machine/resource.h> 51 52 #include <linux/list.h> 53 #include <linux/dmapool.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/compiler.h> 56 #include <linux/errno.h> 57 #include <asm/atomic.h> 58 #include <asm/memtype.h> 59 #include <linux/device.h> 60 #include <linux/pci_ids.h> 61 #include <linux/pm.h> 62 #include <linux/interrupt.h> 63 64 /* 65 * <linux/ioport.h> should be included here, like Linux, but we can't have that 66 * because Linux `struct resource` definition would conflict with FreeBSD 67 * native definition. 68 * 69 * At least the amdgpu DRM driver (amdgpu_isp.c at the time of this writing) 70 * relies on this indirect include to get the definition of Linux `struct 71 * resource`. As a workaround, we include <linux/ioport.h> from 72 * <linux/mfd/core.h>. 73 */ 74 75 #include <linux/kernel.h> /* pr_debug */ 76 77 struct pci_device_id { 78 uint32_t vendor; 79 uint32_t device; 80 uint32_t subvendor; 81 uint32_t subdevice; 82 uint32_t class; 83 uint32_t class_mask; 84 uintptr_t driver_data; 85 }; 86 87 #define MODULE_DEVICE_TABLE_BUS_pci(_bus, _table) \ 88 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 89 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 90 91 #define PCI_ANY_ID -1U 92 93 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 94 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 95 #define PCI_FUNC(devfn) ((devfn) & 0x07) 96 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 97 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn)) 98 99 #define PCI_VDEVICE(_vendor, _device) \ 100 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 101 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 102 .class = 0, .class_mask = 0 103 #define PCI_DEVICE(_vendor, _device) \ 104 .vendor = (_vendor), .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 107 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 108 109 #define PCI_STD_NUM_BARS 6 110 #define PCI_BASE_ADDRESS_0 PCIR_BARS 111 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64 112 #define PCI_VENDOR_ID PCIR_VENDOR 113 #define PCI_DEVICE_ID PCIR_DEVICE 114 #define PCI_COMMAND PCIR_COMMAND 115 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 116 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 117 #define PCI_PRIMARY_BUS PCIR_PRIBUS_1 118 #define PCI_SECONDARY_BUS PCIR_SECBUS_1 119 #define PCI_SUBORDINATE_BUS PCIR_SUBBUS_1 120 #define PCI_SEC_LATENCY_TIMER PCIR_SECLAT_1 121 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 122 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 123 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 124 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 125 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 126 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 127 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 128 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 129 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 130 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 131 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 132 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 133 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 134 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 135 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 136 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 137 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 138 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 139 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 140 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 141 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 142 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 143 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 144 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 145 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 146 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 147 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 148 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 149 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 150 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 151 #define PCI_EXP_TYPE_UPSTREAM PCIEM_TYPE_UPSTREAM_PORT /* Upstream Port */ 152 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 153 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 154 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 155 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 156 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 157 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 158 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 159 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 160 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 161 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 162 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 163 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 164 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 165 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 166 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 167 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 168 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 169 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 170 #define PCI_EXP_LNKCTL2_TLS 0x000f 171 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 172 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 173 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 174 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 175 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 176 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 177 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 178 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 179 180 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 181 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 182 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 183 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 184 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 185 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 186 187 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 188 #define PCI_EXP_DEVSTA_TRPND 0x0020 189 190 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 191 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 192 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 193 194 enum pci_bus_speed { 195 PCI_SPEED_UNKNOWN = -1, 196 PCIE_SPEED_2_5GT, 197 PCIE_SPEED_5_0GT, 198 PCIE_SPEED_8_0GT, 199 PCIE_SPEED_16_0GT, 200 PCIE_SPEED_32_0GT, 201 PCIE_SPEED_64_0GT, 202 }; 203 204 enum pcie_link_width { 205 PCIE_LNK_WIDTH_RESRV = 0x00, 206 PCIE_LNK_X1 = 0x01, 207 PCIE_LNK_X2 = 0x02, 208 PCIE_LNK_X4 = 0x04, 209 PCIE_LNK_X8 = 0x08, 210 PCIE_LNK_X12 = 0x0c, 211 PCIE_LNK_X16 = 0x10, 212 PCIE_LNK_X32 = 0x20, 213 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 214 }; 215 216 #define PCIE_LINK_STATE_L0S 0x00000001 217 #define PCIE_LINK_STATE_L1 0x00000002 218 #define PCIE_LINK_STATE_CLKPM 0x00000004 219 220 typedef int pci_power_t; 221 222 #define PCI_D0 PCI_POWERSTATE_D0 223 #define PCI_D1 PCI_POWERSTATE_D1 224 #define PCI_D2 PCI_POWERSTATE_D2 225 #define PCI_D3hot PCI_POWERSTATE_D3_HOT 226 #define PCI_D3cold PCI_POWERSTATE_D3_COLD 227 228 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 229 230 extern const char *pci_power_names[6]; 231 232 #define PCI_ERR_UNCOR_STATUS PCIR_AER_UC_STATUS 233 #define PCI_ERR_COR_STATUS PCIR_AER_COR_STATUS 234 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 235 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 236 237 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 238 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 239 240 #define PCI_L1SS_CTL1 0x8 241 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 242 243 #define PCI_IRQ_INTX 0x01 244 #define PCI_IRQ_MSI 0x02 245 #define PCI_IRQ_MSIX 0x04 246 #define PCI_IRQ_AFFINITY 0x08 247 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_INTX) 248 249 #if defined(LINUXKPI_VERSION) && (LINUXKPI_VERSION <= 61000) 250 #define PCI_IRQ_LEGACY PCI_IRQ_INTX 251 #endif 252 253 /* 254 * Linux PCI code uses `PCI_SET_ERROR_RESPONSE()` to indicate to the caller of 255 * a `pci_read_*()` function that the read failed. An example of failure is 256 * whether the device was disconnected. It is a bit weird because Linux 257 * `pci_read_*()` can return an error value, as the read value is stored in a 258 * integer passed by pointer. 259 * 260 * We don't set PCI_ERROR_RESPONSE anywhere as of this commit, but the DRM 261 * drivers started to use `PCI_POSSIBLE_ERROR()`. 262 */ 263 #define PCI_ERROR_RESPONSE (~0ULL) 264 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 265 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 266 267 struct pci_dev; 268 269 struct pci_driver { 270 struct list_head node; 271 char *name; 272 const struct pci_device_id *id_table; 273 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 274 void (*remove)(struct pci_dev *dev); 275 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 276 int (*resume) (struct pci_dev *dev); /* Device woken up */ 277 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 278 driver_t bsddriver; 279 devclass_t bsdclass; 280 struct device_driver driver; 281 const struct pci_error_handlers *err_handler; 282 bool isdrm; 283 int bsd_probe_return; 284 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 285 const nvlist_t *pf_config); 286 void (*bsd_iov_uninit)(device_t dev); 287 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 288 const nvlist_t *vf_config); 289 }; 290 291 struct pci_bus { 292 struct pci_dev *self; 293 /* struct pci_bus *parent */ 294 int domain; 295 int number; 296 }; 297 298 #define __devexit_p(x) x 299 300 #define module_pci_driver(_drv) \ 301 module_driver(_drv, linux_pci_register_driver, linux_pci_unregister_driver) 302 303 struct msi_msg { 304 uint32_t data; 305 }; 306 307 struct pci_msi_desc { 308 struct { 309 bool is_64; 310 } msi_attrib; 311 }; 312 313 struct msi_desc { 314 struct msi_msg msg; 315 struct pci_msi_desc pci; 316 }; 317 318 struct msix_entry { 319 int entry; 320 int vector; 321 }; 322 323 /* 324 * If we find drivers accessing this from multiple KPIs we may have to 325 * refcount objects of this structure. 326 */ 327 struct resource; 328 struct pci_mmio_region { 329 TAILQ_ENTRY(pci_mmio_region) next; 330 struct resource *res; 331 int rid; 332 int type; 333 }; 334 335 struct pci_dev { 336 struct device dev; 337 struct list_head links; 338 struct pci_driver *pdrv; 339 struct pci_bus *bus; 340 struct pci_dev *root; 341 pci_power_t current_state; 342 uint16_t device; 343 uint16_t vendor; 344 uint16_t subsystem_vendor; 345 uint16_t subsystem_device; 346 unsigned int irq; 347 unsigned int devfn; 348 uint32_t class; 349 uint8_t revision; 350 uint8_t msi_cap; 351 uint8_t msix_cap; 352 bool managed; /* devres "pcim_*(). */ 353 bool want_iomap_res; 354 bool msi_enabled; 355 bool msix_enabled; 356 phys_addr_t rom; 357 size_t romlen; 358 struct msi_desc **msi_desc; 359 char *path_name; 360 spinlock_t pcie_cap_lock; 361 362 TAILQ_HEAD(, pci_mmio_region) mmio; 363 }; 364 365 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 366 unsigned int flags); 367 bool pci_device_is_present(struct pci_dev *pdev); 368 369 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 370 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 371 void *linuxkpi_pci_iomap_range(struct pci_dev *, int, 372 unsigned long, unsigned long); 373 void *linuxkpi_pci_iomap(struct pci_dev *, int, unsigned long); 374 void *linuxkpi_pcim_iomap(struct pci_dev *, int, unsigned long); 375 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 376 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 377 const char *name); 378 int linuxkpi_pci_request_region(struct pci_dev *, int, const char *); 379 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 380 int linuxkpi_pcim_request_all_regions(struct pci_dev *, const char *); 381 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 382 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 383 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 384 int nreq); 385 386 /* Internal helper function(s). */ 387 struct pci_dev *lkpinew_pci_dev(device_t); 388 void lkpi_pci_devres_release(struct device *, void *); 389 struct pci_dev *lkpi_pci_get_device(uint32_t, uint32_t, struct pci_dev *); 390 struct msi_desc *lkpi_pci_msi_desc_alloc(unsigned int); 391 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 392 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 393 394 #define pci_err(pdev, fmt, ...) \ 395 dev_err(&(pdev)->dev, fmt, ##__VA_ARGS__) 396 #define pci_info(pdev, fmt, ...) \ 397 dev_info(&(pdev)->dev, fmt, ##__VA_ARGS__) 398 399 static inline bool 400 dev_is_pci(struct device *dev) 401 { 402 return (is_pci_device(dev->bsddev)); 403 } 404 405 static inline uint16_t 406 pci_dev_id(struct pci_dev *pdev) 407 { 408 return (PCI_DEVID(pdev->bus->number, pdev->devfn)); 409 } 410 411 static inline bool 412 pci_is_vga(struct pci_dev *pdev) 413 { 414 /* pdev->class holds only the base class. */ 415 uint8_t class = pci_get_class(pdev->dev.bsddev); 416 uint8_t subclass = pci_get_subclass(pdev->dev.bsddev); 417 418 return ((class == PCIC_DISPLAY && subclass == PCIS_DISPLAY_VGA) || 419 (class == PCIC_OLD && subclass == PCIS_OLD_VGA)); 420 } 421 422 static inline int 423 pci_resource_type(struct pci_dev *pdev, int bar) 424 { 425 struct pci_map *pm; 426 427 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 428 if (!pm) 429 return (-1); 430 431 if (PCI_BAR_IO(pm->pm_value)) 432 return (SYS_RES_IOPORT); 433 else 434 return (SYS_RES_MEMORY); 435 } 436 437 /* 438 * All drivers just seem to want to inspect the type not flags. 439 */ 440 static inline int 441 pci_resource_flags(struct pci_dev *pdev, int bar) 442 { 443 int type; 444 445 type = pci_resource_type(pdev, bar); 446 if (type < 0) 447 return (0); 448 return (1 << type); 449 } 450 451 static inline int 452 pci_select_bars(struct pci_dev *pdev, unsigned long flags) 453 { 454 int bars, bar; 455 456 bars = 0; 457 /* We only support BARs here; Linux may support more types. */ 458 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 459 int bar_flags; 460 461 bar_flags = pci_resource_flags(pdev, bar); 462 if ((bar_flags & flags) != 0) 463 bars |= (1 << bar); 464 } 465 466 return (bars); 467 } 468 469 static inline const char * 470 pci_name(struct pci_dev *d) 471 { 472 return d->path_name; 473 } 474 475 static inline void * 476 pci_get_drvdata(struct pci_dev *pdev) 477 { 478 479 return dev_get_drvdata(&pdev->dev); 480 } 481 482 static inline void 483 pci_set_drvdata(struct pci_dev *pdev, void *data) 484 { 485 486 dev_set_drvdata(&pdev->dev, data); 487 } 488 489 static inline struct pci_dev * 490 pci_dev_get(struct pci_dev *pdev) 491 { 492 493 if (pdev != NULL) 494 get_device(&pdev->dev); 495 return (pdev); 496 } 497 498 static __inline void 499 pci_dev_put(struct pci_dev *pdev) 500 { 501 502 if (pdev != NULL) 503 put_device(&pdev->dev); 504 } 505 506 static inline int 507 pci_enable_device(struct pci_dev *pdev) 508 { 509 510 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 511 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 512 return (0); 513 } 514 515 static inline void 516 pci_disable_device(struct pci_dev *pdev) 517 { 518 519 pci_disable_busmaster(pdev->dev.bsddev); 520 } 521 522 static inline int 523 pci_set_master(struct pci_dev *pdev) 524 { 525 526 pci_enable_busmaster(pdev->dev.bsddev); 527 return (0); 528 } 529 530 static inline int 531 pci_set_power_state(struct pci_dev *pdev, int state) 532 { 533 534 pci_set_powerstate(pdev->dev.bsddev, state); 535 return (0); 536 } 537 538 static inline int 539 pci_clear_master(struct pci_dev *pdev) 540 { 541 542 pci_disable_busmaster(pdev->dev.bsddev); 543 return (0); 544 } 545 546 static inline bool 547 pci_is_root_bus(struct pci_bus *pbus) 548 { 549 550 return (pbus->self == NULL); 551 } 552 553 static inline struct pci_dev * 554 pci_upstream_bridge(struct pci_dev *pdev) 555 { 556 557 if (pci_is_root_bus(pdev->bus)) 558 return (NULL); 559 560 /* 561 * If we do not have a (proper) "upstream bridge" set, e.g., we point 562 * to ourselves, try to handle this case on the fly like we do 563 * for pcie_find_root_port(). 564 */ 565 if (pdev == pdev->bus->self) { 566 device_t bridge; 567 568 /* 569 * In the case of DRM drivers, the passed device is a child of 570 * `vgapci`. We want to start the lookup from `vgapci`, so the 571 * parent of the passed `drmn`. 572 * 573 * We can use the `isdrm` flag to determine this. 574 */ 575 bridge = pdev->dev.bsddev; 576 if (pdev->pdrv != NULL && pdev->pdrv->isdrm) 577 bridge = device_get_parent(bridge); 578 if (bridge == NULL) 579 goto done; 580 581 bridge = device_get_parent(bridge); 582 if (bridge == NULL) 583 goto done; 584 bridge = device_get_parent(bridge); 585 if (bridge == NULL) 586 goto done; 587 if (!is_pci_device(bridge)) 588 goto done; 589 590 /* 591 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 592 * for it so it can be returned. 593 */ 594 pdev->bus->self = lkpinew_pci_dev(bridge); 595 } 596 done: 597 return (pdev->bus->self); 598 } 599 600 #define pci_request_region(pdev, bar, res_name) \ 601 linuxkpi_pci_request_region(pdev, bar, res_name) 602 #define pci_release_region(pdev, bar) \ 603 linuxkpi_pci_release_region(pdev, bar) 604 #define pci_request_regions(pdev, res_name) \ 605 linuxkpi_pci_request_regions(pdev, res_name) 606 #define pci_release_regions(pdev) \ 607 linuxkpi_pci_release_regions(pdev) 608 #define pcim_request_all_regions(pdev, name) \ 609 linuxkpi_pcim_request_all_regions(pdev, name) 610 611 static inline void 612 lkpi_pci_disable_msix(struct pci_dev *pdev) 613 { 614 615 pci_release_msi(pdev->dev.bsddev); 616 617 /* 618 * The MSIX IRQ numbers associated with this PCI device are no 619 * longer valid and might be re-assigned. Make sure 620 * lkpi_pci_find_irq_dev() does no longer see them by 621 * resetting their references to zero: 622 */ 623 pdev->dev.irq_start = 0; 624 pdev->dev.irq_end = 0; 625 pdev->msix_enabled = false; 626 } 627 /* Only for consistency. No conflict on that one. */ 628 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 629 630 static inline void 631 lkpi_pci_disable_msi(struct pci_dev *pdev) 632 { 633 634 pci_release_msi(pdev->dev.bsddev); 635 636 pdev->dev.irq_start = 0; 637 pdev->dev.irq_end = 0; 638 pdev->irq = pdev->dev.irq; 639 pdev->msi_enabled = false; 640 } 641 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 642 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 643 644 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 645 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 646 647 static inline bus_addr_t 648 pci_bus_address(struct pci_dev *pdev, int bar) 649 { 650 651 return (pci_resource_start(pdev, bar)); 652 } 653 654 #define PCI_CAP_ID_EXP PCIY_EXPRESS 655 #define PCI_CAP_ID_PCIX PCIY_PCIX 656 #define PCI_CAP_ID_AGP PCIY_AGP 657 #define PCI_CAP_ID_PM PCIY_PMG 658 659 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 660 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 661 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 662 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 663 #define PCI_EXP_LNKSTA PCIER_LINK_STA 664 665 static inline int 666 pci_find_capability(struct pci_dev *pdev, int capid) 667 { 668 int reg; 669 670 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 671 return (0); 672 return (reg); 673 } 674 675 static inline int pci_pcie_cap(struct pci_dev *dev) 676 { 677 return pci_find_capability(dev, PCI_CAP_ID_EXP); 678 } 679 680 static inline int 681 pci_find_ext_capability(struct pci_dev *pdev, int capid) 682 { 683 int reg; 684 685 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 686 return (0); 687 return (reg); 688 } 689 690 static __inline bool 691 pci_pme_capable(struct pci_dev *pdev, pci_power_t state) 692 { 693 return (pci_has_pme(pdev->dev.bsddev, state)); 694 } 695 696 static inline int 697 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 698 { 699 700 if (!pci_enable_aspm) 701 return (-EPERM); 702 703 return (-ENXIO); 704 } 705 706 static inline int 707 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 708 { 709 710 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 711 return (0); 712 } 713 714 static inline int 715 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 716 { 717 718 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 719 return (0); 720 } 721 722 static inline int 723 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 724 { 725 726 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 727 return (0); 728 } 729 730 static inline int 731 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 732 { 733 734 pci_write_config(pdev->dev.bsddev, where, val, 1); 735 return (0); 736 } 737 738 static inline int 739 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 740 { 741 742 pci_write_config(pdev->dev.bsddev, where, val, 2); 743 return (0); 744 } 745 746 static inline int 747 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 748 { 749 750 pci_write_config(pdev->dev.bsddev, where, val, 4); 751 return (0); 752 } 753 754 int linux_pci_register_driver(struct pci_driver *pdrv); 755 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 756 void linux_pci_unregister_driver(struct pci_driver *pdrv); 757 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 758 759 #define pci_register_driver(pdrv) \ 760 linux_pci_register_driver(pdrv) 761 #define pci_unregister_driver(pdrv) \ 762 linux_pci_unregister_driver(pdrv) 763 764 /* 765 * Enable msix, positive errors indicate actual number of available 766 * vectors. Negative errors are failures. 767 * 768 * NB: define added to prevent this definition of pci_enable_msix from 769 * clashing with the native FreeBSD version. 770 */ 771 #define pci_enable_msix(...) \ 772 linuxkpi_pci_enable_msix(__VA_ARGS__) 773 774 #define pci_enable_msix_range(...) \ 775 linux_pci_enable_msix_range(__VA_ARGS__) 776 777 static inline int 778 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 779 int minvec, int maxvec) 780 { 781 int nvec = maxvec; 782 int rc; 783 784 if (maxvec < minvec) 785 return (-ERANGE); 786 787 do { 788 rc = pci_enable_msix(dev, entries, nvec); 789 if (rc < 0) { 790 return (rc); 791 } else if (rc > 0) { 792 if (rc < minvec) 793 return (-ENOSPC); 794 nvec = rc; 795 } 796 } while (rc); 797 return (nvec); 798 } 799 800 #define pci_enable_msi(pdev) \ 801 linux_pci_enable_msi(pdev) 802 803 static inline int 804 pci_enable_msi(struct pci_dev *pdev) 805 { 806 807 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 808 } 809 810 static inline int 811 pci_channel_offline(struct pci_dev *pdev) 812 { 813 814 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 815 } 816 817 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 818 { 819 return -ENODEV; 820 } 821 822 static inline void pci_disable_sriov(struct pci_dev *dev) 823 { 824 } 825 826 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \ 827 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) 828 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 829 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 830 #define pcim_iomap(pdev, bar, maxlen) \ 831 linuxkpi_pcim_iomap(pdev, bar, maxlen) 832 #define pci_iounmap(pdev, res) \ 833 linuxkpi_pci_iounmap(pdev, res) 834 835 static inline void 836 lkpi_pci_save_state(struct pci_dev *pdev) 837 { 838 839 pci_save_state(pdev->dev.bsddev); 840 } 841 842 static inline void 843 lkpi_pci_restore_state(struct pci_dev *pdev) 844 { 845 846 pci_restore_state(pdev->dev.bsddev); 847 } 848 849 #define pci_save_state(dev) lkpi_pci_save_state(dev) 850 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 851 852 static inline int 853 linuxkpi_pci_enable_wake(struct pci_dev *pdev, pci_power_t state, bool ena) 854 { 855 /* 856 * We do not currently support this in device.h either to 857 * check if the device is allowed to wake up in first place. 858 */ 859 pr_debug("%s: TODO\n", __func__); 860 return (0); 861 } 862 #define pci_enable_wake(dev, state, ena) \ 863 linuxkpi_pci_enable_wake(dev, state, ena) 864 865 static inline int 866 pci_reset_function(struct pci_dev *pdev) 867 { 868 869 return (-ENOSYS); 870 } 871 872 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 873 const struct pci_device_id _table[] __devinitdata 874 875 /* XXX This should not be necessary. */ 876 #define pcix_set_mmrbc(d, v) 0 877 #define pcix_get_max_mmrbc(d) 0 878 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 879 880 #define PCI_DMA_BIDIRECTIONAL 0 881 #define PCI_DMA_TODEVICE 1 882 #define PCI_DMA_FROMDEVICE 2 883 #define PCI_DMA_NONE 3 884 885 #define pci_pool dma_pool 886 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 887 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 888 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 889 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 890 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 891 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 892 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 893 _size, _vaddr, _dma_handle) 894 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 895 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 896 _sg, _nents, (enum dma_data_direction)_dir) 897 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 898 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 899 (_ptr), (_size), (enum dma_data_direction)_dir) 900 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 901 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 902 _addr, _size, (enum dma_data_direction)_dir) 903 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 904 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 905 _sg, _nents, (enum dma_data_direction)_dir) 906 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 907 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 908 _offset, _size, (enum dma_data_direction)_dir) 909 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 910 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 911 _dma_address, _size, (enum dma_data_direction)_dir) 912 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 913 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 914 dma_mapping_error(&(_pdev)->dev, _dma_addr) 915 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 916 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 917 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 918 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 919 #define pci_unmap_addr dma_unmap_addr 920 #define pci_unmap_addr_set dma_unmap_addr_set 921 #define pci_unmap_len dma_unmap_len 922 #define pci_unmap_len_set dma_unmap_len_set 923 924 void *linuxkpi_pci_map_rom(struct pci_dev *pdev, size_t *size); 925 void linuxkpi_pci_unmap_rom(struct pci_dev *pdev, void *rom); 926 #define pci_map_rom(pdev, size) linuxkpi_pci_map_rom(pdev, size) 927 #define pci_unmap_rom(pdev, rom) linuxkpi_pci_unmap_rom(pdev, rom) 928 929 typedef unsigned int __bitwise pci_channel_state_t; 930 typedef unsigned int __bitwise pci_ers_result_t; 931 932 enum pci_channel_state { 933 pci_channel_io_normal = 1, 934 pci_channel_io_frozen = 2, 935 pci_channel_io_perm_failure = 3, 936 }; 937 938 enum pci_ers_result { 939 PCI_ERS_RESULT_NONE = 1, 940 PCI_ERS_RESULT_CAN_RECOVER = 2, 941 PCI_ERS_RESULT_NEED_RESET = 3, 942 PCI_ERS_RESULT_DISCONNECT = 4, 943 PCI_ERS_RESULT_RECOVERED = 5, 944 }; 945 946 /* PCI bus error event callbacks */ 947 struct pci_error_handlers { 948 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 949 enum pci_channel_state error); 950 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 951 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 952 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 953 void (*resume)(struct pci_dev *dev); 954 void (*reset_prepare)(struct pci_dev *); 955 void (*reset_done)(struct pci_dev *); 956 }; 957 958 /* FreeBSD does not support SRIOV - yet */ 959 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 960 { 961 return dev; 962 } 963 964 static inline bool pci_is_pcie(struct pci_dev *dev) 965 { 966 return !!pci_pcie_cap(dev); 967 } 968 969 static inline u16 pcie_flags_reg(struct pci_dev *dev) 970 { 971 int pos; 972 u16 reg16; 973 974 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 975 if (!pos) 976 return 0; 977 978 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 979 980 return reg16; 981 } 982 983 static inline int pci_pcie_type(struct pci_dev *dev) 984 { 985 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 986 } 987 988 static inline int pcie_cap_version(struct pci_dev *dev) 989 { 990 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 991 } 992 993 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 994 { 995 int type = pci_pcie_type(dev); 996 997 return pcie_cap_version(dev) > 1 || 998 type == PCI_EXP_TYPE_ROOT_PORT || 999 type == PCI_EXP_TYPE_ENDPOINT || 1000 type == PCI_EXP_TYPE_LEG_END; 1001 } 1002 1003 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1004 { 1005 return true; 1006 } 1007 1008 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1009 { 1010 int type = pci_pcie_type(dev); 1011 1012 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1013 (type == PCI_EXP_TYPE_DOWNSTREAM && 1014 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1015 } 1016 1017 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1018 { 1019 int type = pci_pcie_type(dev); 1020 1021 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1022 type == PCI_EXP_TYPE_RC_EC; 1023 } 1024 1025 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1026 { 1027 if (!pci_is_pcie(dev)) 1028 return false; 1029 1030 switch (pos) { 1031 case PCI_EXP_FLAGS_TYPE: 1032 return true; 1033 case PCI_EXP_DEVCAP: 1034 case PCI_EXP_DEVCTL: 1035 case PCI_EXP_DEVSTA: 1036 return pcie_cap_has_devctl(dev); 1037 case PCI_EXP_LNKCAP: 1038 case PCI_EXP_LNKCTL: 1039 case PCI_EXP_LNKSTA: 1040 return pcie_cap_has_lnkctl(dev); 1041 case PCI_EXP_SLTCAP: 1042 case PCI_EXP_SLTCTL: 1043 case PCI_EXP_SLTSTA: 1044 return pcie_cap_has_sltctl(dev); 1045 case PCI_EXP_RTCTL: 1046 case PCI_EXP_RTCAP: 1047 case PCI_EXP_RTSTA: 1048 return pcie_cap_has_rtctl(dev); 1049 case PCI_EXP_DEVCAP2: 1050 case PCI_EXP_DEVCTL2: 1051 case PCI_EXP_LNKCAP2: 1052 case PCI_EXP_LNKCTL2: 1053 case PCI_EXP_LNKSTA2: 1054 return pcie_cap_version(dev) > 1; 1055 default: 1056 return false; 1057 } 1058 } 1059 1060 static inline int 1061 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1062 { 1063 *dst = 0; 1064 if (pos & 3) 1065 return -EINVAL; 1066 1067 if (!pcie_capability_reg_implemented(dev, pos)) 1068 return -EINVAL; 1069 1070 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1071 } 1072 1073 static inline int 1074 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1075 { 1076 *dst = 0; 1077 if (pos & 3) 1078 return -EINVAL; 1079 1080 if (!pcie_capability_reg_implemented(dev, pos)) 1081 return -EINVAL; 1082 1083 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1084 } 1085 1086 static inline int 1087 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1088 { 1089 if (pos & 1) 1090 return -EINVAL; 1091 1092 if (!pcie_capability_reg_implemented(dev, pos)) 1093 return 0; 1094 1095 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1096 } 1097 1098 static inline int 1099 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1100 uint16_t clear, uint16_t set) 1101 { 1102 int error; 1103 uint16_t v; 1104 1105 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1106 spin_lock(&dev->pcie_cap_lock); 1107 1108 error = pcie_capability_read_word(dev, pos, &v); 1109 if (error == 0) { 1110 v &= ~clear; 1111 v |= set; 1112 error = pcie_capability_write_word(dev, pos, v); 1113 } 1114 1115 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1116 spin_unlock(&dev->pcie_cap_lock); 1117 1118 return (error); 1119 } 1120 1121 static inline int 1122 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1123 { 1124 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1125 } 1126 1127 static inline int 1128 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1129 { 1130 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1131 } 1132 1133 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1134 enum pci_bus_speed *speed, enum pcie_link_width *width) 1135 { 1136 *speed = PCI_SPEED_UNKNOWN; 1137 *width = PCIE_LNK_WIDTH_UNKNOWN; 1138 return (0); 1139 } 1140 1141 static inline int 1142 pci_num_vf(struct pci_dev *dev) 1143 { 1144 return (0); 1145 } 1146 1147 static inline enum pci_bus_speed 1148 pcie_get_speed_cap(struct pci_dev *dev) 1149 { 1150 struct pci_dev *pbus; 1151 device_t root; 1152 uint32_t lnkcap, lnkcap2; 1153 int error, pos; 1154 1155 /* 1156 * We should always be called on a PCI device. 1157 * The only current consumer I could find was amdgpu which either 1158 * calls us directly on a pdev(drmn?) or with the result of 1159 * pci_upstream_bridge(). 1160 * 1161 * Treat "drmn" as special again as it is not a PCI device. 1162 */ 1163 if (dev->pdrv != NULL && dev->pdrv->isdrm) { 1164 pbus = pci_upstream_bridge(dev); 1165 if (pbus == NULL) 1166 return (PCI_SPEED_UNKNOWN); 1167 } else 1168 pbus = dev; 1169 1170 /* "root" may be misleading as it may not be that. */ 1171 root = pbus->dev.bsddev; 1172 1173 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1174 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1175 return (PCI_SPEED_UNKNOWN); 1176 1177 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1178 return (PCI_SPEED_UNKNOWN); 1179 1180 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1181 1182 if (lnkcap2) { /* PCIe r3.0-compliant */ 1183 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1184 return (PCIE_SPEED_2_5GT); 1185 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1186 return (PCIE_SPEED_5_0GT); 1187 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1188 return (PCIE_SPEED_8_0GT); 1189 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1190 return (PCIE_SPEED_16_0GT); 1191 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1192 return (PCIE_SPEED_32_0GT); 1193 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1194 return (PCIE_SPEED_64_0GT); 1195 } else { /* pre-r3.0 */ 1196 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1197 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1198 return (PCIE_SPEED_2_5GT); 1199 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1200 return (PCIE_SPEED_5_0GT); 1201 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1202 return (PCIE_SPEED_8_0GT); 1203 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1204 return (PCIE_SPEED_16_0GT); 1205 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1206 return (PCIE_SPEED_32_0GT); 1207 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1208 return (PCIE_SPEED_64_0GT); 1209 } 1210 return (PCI_SPEED_UNKNOWN); 1211 } 1212 1213 static inline enum pcie_link_width 1214 pcie_get_width_cap(struct pci_dev *dev) 1215 { 1216 uint32_t lnkcap; 1217 1218 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1219 if (lnkcap) 1220 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1221 1222 return (PCIE_LNK_WIDTH_UNKNOWN); 1223 } 1224 1225 static inline int 1226 pcie_get_mps(struct pci_dev *dev) 1227 { 1228 return (pci_get_max_payload(dev->dev.bsddev)); 1229 } 1230 1231 static inline uint32_t 1232 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1233 { 1234 1235 switch(spd) { 1236 case PCIE_SPEED_64_0GT: 1237 return (64000 * 128 / 130); 1238 case PCIE_SPEED_32_0GT: 1239 return (32000 * 128 / 130); 1240 case PCIE_SPEED_16_0GT: 1241 return (16000 * 128 / 130); 1242 case PCIE_SPEED_8_0GT: 1243 return (8000 * 128 / 130); 1244 case PCIE_SPEED_5_0GT: 1245 return (5000 * 8 / 10); 1246 case PCIE_SPEED_2_5GT: 1247 return (2500 * 8 / 10); 1248 default: 1249 return (0); 1250 } 1251 } 1252 1253 static inline uint32_t 1254 pcie_bandwidth_available(struct pci_dev *pdev, 1255 struct pci_dev **limiting, 1256 enum pci_bus_speed *speed, 1257 enum pcie_link_width *width) 1258 { 1259 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1260 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1261 1262 if (speed) 1263 *speed = nspeed; 1264 if (width) 1265 *width = nwidth; 1266 1267 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1268 } 1269 1270 static inline bool 1271 pcie_aspm_enabled(struct pci_dev *pdev) 1272 { 1273 return (false); 1274 } 1275 1276 static inline struct pci_dev * 1277 pcie_find_root_port(struct pci_dev *pdev) 1278 { 1279 device_t root; 1280 1281 if (pdev->root != NULL) 1282 return (pdev->root); 1283 1284 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1285 if (root == NULL) 1286 return (NULL); 1287 1288 pdev->root = lkpinew_pci_dev(root); 1289 return (pdev->root); 1290 } 1291 1292 /* This is needed when people rip out the device "HotPlug". */ 1293 static inline void 1294 pci_lock_rescan_remove(void) 1295 { 1296 } 1297 1298 static inline void 1299 pci_unlock_rescan_remove(void) 1300 { 1301 } 1302 1303 static __inline void 1304 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1305 { 1306 } 1307 1308 static inline int 1309 pci_rescan_bus(struct pci_bus *pbus) 1310 { 1311 device_t *devlist, parent; 1312 int devcount, error; 1313 1314 if (!device_is_attached(pbus->self->dev.bsddev)) 1315 return (0); 1316 /* pci_rescan_method() will work on the pcib (parent). */ 1317 error = BUS_RESCAN(pbus->self->dev.bsddev); 1318 if (error != 0) 1319 return (0); 1320 1321 parent = device_get_parent(pbus->self->dev.bsddev); 1322 error = device_get_children(parent, &devlist, &devcount); 1323 if (error != 0) 1324 return (0); 1325 if (devcount != 0) 1326 free(devlist, M_TEMP); 1327 1328 return (devcount); 1329 } 1330 1331 /* 1332 * The following functions can be used to attach/detach the LinuxKPI's 1333 * PCI device runtime. The pci_driver and pci_device_id pointer is 1334 * allowed to be NULL. Other pointers must be all valid. 1335 * The pci_dev structure should be zero-initialized before passed 1336 * to the linux_pci_attach_device function. 1337 */ 1338 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1339 const struct pci_device_id *, struct pci_dev *); 1340 extern int linux_pci_detach_device(struct pci_dev *); 1341 1342 static inline int 1343 pci_dev_present(const struct pci_device_id *cur) 1344 { 1345 while (cur != NULL && (cur->vendor || cur->device)) { 1346 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1347 return (1); 1348 } 1349 cur++; 1350 } 1351 return (0); 1352 } 1353 1354 static inline bool 1355 pci_dev_is_disconnected(const struct pci_dev *pdev) 1356 { 1357 pr_debug("TODO: %s\n", __func__); 1358 return (false); 1359 } 1360 1361 static inline const struct pci_device_id * 1362 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev) 1363 { 1364 if (ids == NULL) 1365 return (NULL); 1366 1367 for (; 1368 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0; 1369 ids++) 1370 if ((ids->vendor == PCI_ANY_ID || 1371 ids->vendor == pdev->vendor) && 1372 (ids->device == PCI_ANY_ID || 1373 ids->device == pdev->device) && 1374 (ids->subvendor == PCI_ANY_ID || 1375 ids->subvendor == pdev->subsystem_vendor) && 1376 (ids->subdevice == PCI_ANY_ID || 1377 ids->subdevice == pdev->subsystem_device) && 1378 ((ids->class ^ pdev->class) & ids->class_mask) == 0) 1379 return (ids); 1380 1381 return (NULL); 1382 } 1383 1384 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1385 unsigned int bus, unsigned int devfn); 1386 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1387 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1388 1389 struct pci_dev *lkpi_pci_get_slot(struct pci_bus *, unsigned int); 1390 #ifndef WANT_NATIVE_PCI_GET_SLOT 1391 #define pci_get_slot(_pbus, _devfn) \ 1392 lkpi_pci_get_slot(_pbus, _devfn) 1393 #endif 1394 1395 static inline int 1396 pci_domain_nr(struct pci_bus *pbus) 1397 { 1398 1399 return (pbus->domain); 1400 } 1401 1402 static inline int 1403 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1404 int pos, uint32_t *val, int len) 1405 { 1406 1407 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1408 return (0); 1409 } 1410 1411 static inline int 1412 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1413 { 1414 uint32_t tmp; 1415 int ret; 1416 1417 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1418 *val = (u16)tmp; 1419 return (ret); 1420 } 1421 1422 static inline int 1423 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1424 { 1425 uint32_t tmp; 1426 int ret; 1427 1428 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1429 *val = (u8)tmp; 1430 return (ret); 1431 } 1432 1433 static inline int 1434 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1435 uint32_t val, int size) 1436 { 1437 1438 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1439 return (0); 1440 } 1441 1442 static inline int 1443 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1444 uint8_t val) 1445 { 1446 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1447 } 1448 1449 static inline int 1450 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1451 uint16_t val) 1452 { 1453 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1454 } 1455 1456 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1457 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1458 struct pci_dev *lkpi_pci_get_base_class(unsigned int class, 1459 struct pci_dev *from); 1460 #define pci_get_base_class(class, from) lkpi_pci_get_base_class(class, from) 1461 1462 /* -------------------------------------------------------------------------- */ 1463 1464 #define pcim_enable_device(pdev) \ 1465 linuxkpi_pcim_enable_device(pdev) 1466 #define pcim_iomap_table(pdev) \ 1467 linuxkpi_pcim_iomap_table(pdev) 1468 #define pcim_iomap_regions(pdev, mask, name) \ 1469 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1470 1471 static inline int 1472 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1473 { 1474 uint32_t requests, req_mask; 1475 int bar, error; 1476 1477 /* Request all the BARs ("regions") we do not iomap. */ 1478 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1479 for (bar = requests = 0; requests != req_mask; bar++) { 1480 if ((req_mask & (1 << bar)) == 0) 1481 continue; 1482 error = pci_request_region(pdev, bar, name); 1483 if (error != 0 && error != -ENODEV) 1484 goto err; 1485 requests |= (1 << bar); 1486 } 1487 1488 error = pcim_iomap_regions(pdev, mask, name); 1489 if (error != 0) 1490 goto err; 1491 1492 return (0); 1493 1494 err: 1495 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1496 if ((requests & (1 << bar)) != 0) 1497 pci_release_region(pdev, bar); 1498 } 1499 1500 return (-EINVAL); 1501 } 1502 1503 /* 1504 * We cannot simply re-define pci_get_device() as we would normally do 1505 * and then hide it in linux_pci.c as too many semi-native drivers still 1506 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1507 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1508 */ 1509 static inline struct pci_dev * 1510 linuxkpi_pci_get_device(uint32_t vendor, uint32_t device, struct pci_dev *odev) 1511 { 1512 1513 return (lkpi_pci_get_device(vendor, device, odev)); 1514 } 1515 1516 #define for_each_pci_dev(_pdev) \ 1517 while ((_pdev = linuxkpi_pci_get_device(PCI_ANY_ID, PCI_ANY_ID, _pdev)) != NULL) 1518 1519 /* This is a FreeBSD extension so we can use bus_*(). */ 1520 static inline void 1521 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1522 { 1523 pdev->want_iomap_res = true; 1524 } 1525 1526 static inline bool 1527 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1528 { 1529 1530 return (false); 1531 } 1532 1533 static inline void * 1534 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1535 { 1536 1537 return (NULL); 1538 } 1539 1540 static inline void 1541 pci_ignore_hotplug(struct pci_dev *pdev) 1542 { 1543 } 1544 1545 static inline const char * 1546 pci_power_name(pci_power_t state) 1547 { 1548 int pstate = state + 1; 1549 1550 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1551 return (pci_power_names[pstate]); 1552 else 1553 return (pci_power_names[0]); 1554 } 1555 1556 static inline int 1557 pcie_get_readrq(struct pci_dev *dev) 1558 { 1559 u16 ctl; 1560 1561 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1562 return (-EINVAL); 1563 1564 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1565 } 1566 1567 static inline bool 1568 pci_is_enabled(struct pci_dev *pdev) 1569 { 1570 1571 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1572 PCIM_CMD_BUSMASTEREN) != 0); 1573 } 1574 1575 static inline int 1576 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1577 { 1578 1579 return (0); 1580 } 1581 1582 static inline int 1583 pci_assign_resource(struct pci_dev *pdev, int bar) 1584 { 1585 1586 return (0); 1587 } 1588 1589 static inline int 1590 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1591 { 1592 1593 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1594 if (vector != 0) 1595 return (-EINVAL); 1596 return (pdev->irq); 1597 } 1598 1599 if (pdev->msix_enabled || pdev->msi_enabled) { 1600 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1601 return (-EINVAL); 1602 return (pdev->dev.irq_start + vector); 1603 } 1604 1605 return (-ENXIO); 1606 } 1607 1608 static inline int 1609 pci_msix_vec_count(struct pci_dev *pdev) 1610 { 1611 int avail; 1612 1613 avail = pci_msix_count(pdev->dev.bsddev); 1614 if (avail == 0) 1615 return (-EINVAL); 1616 return (avail); 1617 } 1618 1619 static inline int 1620 pci_wake_from_d3(struct pci_dev *pdev, bool enable) 1621 { 1622 1623 pr_debug("%s: TODO\n", __func__); 1624 return (0); 1625 } 1626 1627 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1628