1 /*-
2 * Copyright (c) 2010 Isilon Systems, Inc.
3 * Copyright (c) 2010 iX Systems, Inc.
4 * Copyright (c) 2010 Panasas, Inc.
5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
6 * All rights reserved.
7 * Copyright (c) 2020-2025 The FreeBSD Foundation
8 *
9 * Portions of this software were developed by Björn Zeeb
10 * under sponsorship from the FreeBSD Foundation.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice unmodified, this list of conditions, and the following
17 * disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33 #ifndef _LINUXKPI_LINUX_PCI_H_
34 #define _LINUXKPI_LINUX_PCI_H_
35
36 #define CONFIG_PCI_MSI
37
38 #include <linux/types.h>
39 #include <linux/device/driver.h>
40
41 #include <sys/param.h>
42 #include <sys/bus.h>
43 #include <sys/module.h>
44 #include <sys/nv.h>
45 #include <sys/pciio.h>
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pci_private.h>
49
50 #include <machine/resource.h>
51
52 #include <linux/list.h>
53 #include <linux/dmapool.h>
54 #include <linux/dma-mapping.h>
55 #include <linux/compiler.h>
56 #include <linux/errno.h>
57 #include <asm/atomic.h>
58 #include <asm/memtype.h>
59 #include <linux/device.h>
60 #include <linux/pci_ids.h>
61 #include <linux/pm.h>
62
63 #include <linux/kernel.h> /* pr_debug */
64
65 struct pci_device_id {
66 uint32_t vendor;
67 uint32_t device;
68 uint32_t subvendor;
69 uint32_t subdevice;
70 uint32_t class;
71 uint32_t class_mask;
72 uintptr_t driver_data;
73 };
74
75 #define MODULE_DEVICE_TABLE_BUS_pci(_bus, _table) \
76 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \
77 _bus, lkpi_ ## _table, _table, nitems(_table) - 1)
78
79 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */
80 #define MODULE_DEVICE_TABLE(_bus, _table) \
81 \
82 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \
83 DEVMETHOD_END \
84 }; \
85 \
86 static driver_t _ ## _bus ## _ ## _table ## _driver = { \
87 "lkpi_" #_bus #_table, \
88 _ ## _bus ## _ ## _table ## _methods, \
89 0 \
90 }; \
91 \
92 DRIVER_MODULE(lkpi_ ## _table, _bus, _ ## _bus ## _ ## _table ## _driver,\
93 0, 0); \
94 \
95 MODULE_DEVICE_TABLE_BUS_ ## _bus(_bus, _table)
96
97 #define PCI_ANY_ID -1U
98
99 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
100 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
101 #define PCI_FUNC(devfn) ((devfn) & 0x07)
102 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff)
103 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn))
104
105 #define PCI_VDEVICE(_vendor, _device) \
106 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \
107 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
108 #define PCI_DEVICE(_vendor, _device) \
109 .vendor = (_vendor), .device = (_device), \
110 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
111
112 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
113
114 #define PCI_STD_NUM_BARS 6
115 #define PCI_BASE_ADDRESS_0 PCIR_BARS
116 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64
117 #define PCI_VENDOR_ID PCIR_VENDOR
118 #define PCI_DEVICE_ID PCIR_DEVICE
119 #define PCI_COMMAND PCIR_COMMAND
120 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS
121 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN
122 #define PCI_PRIMARY_BUS PCIR_PRIBUS_1
123 #define PCI_SECONDARY_BUS PCIR_SECBUS_1
124 #define PCI_SUBORDINATE_BUS PCIR_SUBBUS_1
125 #define PCI_SEC_LATENCY_TIMER PCIR_SECLAT_1
126 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */
127 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */
128 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S
129 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1
130 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC
131 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */
132 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD
133 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */
134 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */
135 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */
136 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */
137 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */
138 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */
139 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */
140 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */
141 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */
142 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */
143 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */
144 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */
145 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */
146 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE
147 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE
148 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */
149 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */
150 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */
151 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */
152 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */
153 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */
154 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */
155 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */
156 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */
157 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */
158 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */
159 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED
160 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
161 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */
162 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */
163 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */
164 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */
165 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */
166 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */
167 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */
168 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */
169 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */
170 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */
171 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */
172 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */
173 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */
174 #define PCI_EXP_LNKCTL2_TLS 0x000f
175 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
176 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
177 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
178 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
179 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
180 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */
181 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
182 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
183
184 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR
185 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH
186 #define PCI_MSI_FLAGS PCIR_MSI_CTRL
187 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE
188 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL
189 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE
190
191 #define PCI_EXP_LNKCAP_CLKPM 0x00040000
192 #define PCI_EXP_DEVSTA_TRPND 0x0020
193
194 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY)
195 #define IORESOURCE_IO (1 << SYS_RES_IOPORT)
196 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ)
197
198 enum pci_bus_speed {
199 PCI_SPEED_UNKNOWN = -1,
200 PCIE_SPEED_2_5GT,
201 PCIE_SPEED_5_0GT,
202 PCIE_SPEED_8_0GT,
203 PCIE_SPEED_16_0GT,
204 PCIE_SPEED_32_0GT,
205 PCIE_SPEED_64_0GT,
206 };
207
208 enum pcie_link_width {
209 PCIE_LNK_WIDTH_RESRV = 0x00,
210 PCIE_LNK_X1 = 0x01,
211 PCIE_LNK_X2 = 0x02,
212 PCIE_LNK_X4 = 0x04,
213 PCIE_LNK_X8 = 0x08,
214 PCIE_LNK_X12 = 0x0c,
215 PCIE_LNK_X16 = 0x10,
216 PCIE_LNK_X32 = 0x20,
217 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
218 };
219
220 #define PCIE_LINK_STATE_L0S 0x00000001
221 #define PCIE_LINK_STATE_L1 0x00000002
222 #define PCIE_LINK_STATE_CLKPM 0x00000004
223
224 typedef int pci_power_t;
225
226 #define PCI_D0 PCI_POWERSTATE_D0
227 #define PCI_D1 PCI_POWERSTATE_D1
228 #define PCI_D2 PCI_POWERSTATE_D2
229 #define PCI_D3hot PCI_POWERSTATE_D3
230 #define PCI_D3cold 4
231
232 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN
233
234 extern const char *pci_power_names[6];
235
236 #define PCI_ERR_UNCOR_STATUS PCIR_AER_UC_STATUS
237 #define PCI_ERR_COR_STATUS PCIR_AER_COR_STATUS
238 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD
239 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID
240
241 #define PCI_EXT_CAP_ID_ERR PCIZ_AER
242 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM
243
244 #define PCI_L1SS_CTL1 0x8
245 #define PCI_L1SS_CTL1_L1SS_MASK 0xf
246
247 #define PCI_IRQ_INTX 0x01
248 #define PCI_IRQ_MSI 0x02
249 #define PCI_IRQ_MSIX 0x04
250 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_INTX)
251
252 #if defined(LINUXKPI_VERSION) && (LINUXKPI_VERSION <= 61000)
253 #define PCI_IRQ_LEGACY PCI_IRQ_INTX
254 #endif
255
256 struct pci_dev;
257
258 struct pci_driver {
259 struct list_head node;
260 char *name;
261 const struct pci_device_id *id_table;
262 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
263 void (*remove)(struct pci_dev *dev);
264 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
265 int (*resume) (struct pci_dev *dev); /* Device woken up */
266 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */
267 driver_t bsddriver;
268 devclass_t bsdclass;
269 struct device_driver driver;
270 const struct pci_error_handlers *err_handler;
271 bool isdrm;
272 int bsd_probe_return;
273 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs,
274 const nvlist_t *pf_config);
275 void (*bsd_iov_uninit)(device_t dev);
276 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum,
277 const nvlist_t *vf_config);
278 };
279
280 struct pci_bus {
281 struct pci_dev *self;
282 /* struct pci_bus *parent */
283 int domain;
284 int number;
285 };
286
287 extern struct list_head pci_drivers;
288 extern struct list_head pci_devices;
289 extern spinlock_t pci_lock;
290
291 #define __devexit_p(x) x
292
293 #define module_pci_driver(_drv) \
294 module_driver(_drv, linux_pci_register_driver, linux_pci_unregister_driver)
295
296 struct msi_msg {
297 uint32_t data;
298 };
299
300 struct pci_msi_desc {
301 struct {
302 bool is_64;
303 } msi_attrib;
304 };
305
306 struct msi_desc {
307 struct msi_msg msg;
308 struct pci_msi_desc pci;
309 };
310
311 struct msix_entry {
312 int entry;
313 int vector;
314 };
315
316 /*
317 * If we find drivers accessing this from multiple KPIs we may have to
318 * refcount objects of this structure.
319 */
320 struct resource;
321 struct pci_mmio_region {
322 TAILQ_ENTRY(pci_mmio_region) next;
323 struct resource *res;
324 int rid;
325 int type;
326 };
327
328 struct pci_dev {
329 struct device dev;
330 struct list_head links;
331 struct pci_driver *pdrv;
332 struct pci_bus *bus;
333 struct pci_dev *root;
334 pci_power_t current_state;
335 uint16_t device;
336 uint16_t vendor;
337 uint16_t subsystem_vendor;
338 uint16_t subsystem_device;
339 unsigned int irq;
340 unsigned int devfn;
341 uint32_t class;
342 uint8_t revision;
343 uint8_t msi_cap;
344 uint8_t msix_cap;
345 bool managed; /* devres "pcim_*(). */
346 bool want_iomap_res;
347 bool msi_enabled;
348 bool msix_enabled;
349 phys_addr_t rom;
350 size_t romlen;
351 struct msi_desc **msi_desc;
352 char *path_name;
353 spinlock_t pcie_cap_lock;
354
355 TAILQ_HEAD(, pci_mmio_region) mmio;
356 };
357
358 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name);
359 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv,
360 unsigned int flags);
361 bool pci_device_is_present(struct pci_dev *pdev);
362
363 int linuxkpi_pcim_enable_device(struct pci_dev *pdev);
364 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev);
365 void *linuxkpi_pci_iomap_range(struct pci_dev *, int,
366 unsigned long, unsigned long);
367 void *linuxkpi_pci_iomap(struct pci_dev *, int, unsigned long);
368 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res);
369 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask,
370 const char *name);
371 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name);
372 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar);
373 void linuxkpi_pci_release_regions(struct pci_dev *pdev);
374 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries,
375 int nreq);
376
377 /* Internal helper function(s). */
378 struct pci_dev *lkpinew_pci_dev(device_t);
379 void lkpi_pci_devres_release(struct device *, void *);
380 struct pci_dev *lkpi_pci_get_device(uint32_t, uint32_t, struct pci_dev *);
381 struct msi_desc *lkpi_pci_msi_desc_alloc(int);
382 struct device *lkpi_pci_find_irq_dev(unsigned int irq);
383 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec);
384
385 #define pci_err(pdev, fmt, ...) \
386 dev_err(&(pdev)->dev, fmt, ##__VA_ARGS__)
387 #define pci_info(pdev, fmt, ...) \
388 dev_info(&(pdev)->dev, fmt, ##__VA_ARGS__)
389
390 static inline bool
dev_is_pci(struct device * dev)391 dev_is_pci(struct device *dev)
392 {
393
394 return (device_get_devclass(dev->bsddev) == devclass_find("pci"));
395 }
396
397 static inline uint16_t
pci_dev_id(struct pci_dev * pdev)398 pci_dev_id(struct pci_dev *pdev)
399 {
400 return (PCI_DEVID(pdev->bus->number, pdev->devfn));
401 }
402
403 static inline int
pci_resource_type(struct pci_dev * pdev,int bar)404 pci_resource_type(struct pci_dev *pdev, int bar)
405 {
406 struct pci_map *pm;
407
408 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar));
409 if (!pm)
410 return (-1);
411
412 if (PCI_BAR_IO(pm->pm_value))
413 return (SYS_RES_IOPORT);
414 else
415 return (SYS_RES_MEMORY);
416 }
417
418 /*
419 * All drivers just seem to want to inspect the type not flags.
420 */
421 static inline int
pci_resource_flags(struct pci_dev * pdev,int bar)422 pci_resource_flags(struct pci_dev *pdev, int bar)
423 {
424 int type;
425
426 type = pci_resource_type(pdev, bar);
427 if (type < 0)
428 return (0);
429 return (1 << type);
430 }
431
432 static inline const char *
pci_name(struct pci_dev * d)433 pci_name(struct pci_dev *d)
434 {
435 return d->path_name;
436 }
437
438 static inline void *
pci_get_drvdata(struct pci_dev * pdev)439 pci_get_drvdata(struct pci_dev *pdev)
440 {
441
442 return dev_get_drvdata(&pdev->dev);
443 }
444
445 static inline void
pci_set_drvdata(struct pci_dev * pdev,void * data)446 pci_set_drvdata(struct pci_dev *pdev, void *data)
447 {
448
449 dev_set_drvdata(&pdev->dev, data);
450 }
451
452 static inline struct pci_dev *
pci_dev_get(struct pci_dev * pdev)453 pci_dev_get(struct pci_dev *pdev)
454 {
455
456 if (pdev != NULL)
457 get_device(&pdev->dev);
458 return (pdev);
459 }
460
461 static __inline void
pci_dev_put(struct pci_dev * pdev)462 pci_dev_put(struct pci_dev *pdev)
463 {
464
465 if (pdev != NULL)
466 put_device(&pdev->dev);
467 }
468
469 static inline int
pci_enable_device(struct pci_dev * pdev)470 pci_enable_device(struct pci_dev *pdev)
471 {
472
473 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT);
474 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY);
475 return (0);
476 }
477
478 static inline void
pci_disable_device(struct pci_dev * pdev)479 pci_disable_device(struct pci_dev *pdev)
480 {
481
482 pci_disable_busmaster(pdev->dev.bsddev);
483 }
484
485 static inline int
pci_set_master(struct pci_dev * pdev)486 pci_set_master(struct pci_dev *pdev)
487 {
488
489 pci_enable_busmaster(pdev->dev.bsddev);
490 return (0);
491 }
492
493 static inline int
pci_set_power_state(struct pci_dev * pdev,int state)494 pci_set_power_state(struct pci_dev *pdev, int state)
495 {
496
497 pci_set_powerstate(pdev->dev.bsddev, state);
498 return (0);
499 }
500
501 static inline int
pci_clear_master(struct pci_dev * pdev)502 pci_clear_master(struct pci_dev *pdev)
503 {
504
505 pci_disable_busmaster(pdev->dev.bsddev);
506 return (0);
507 }
508
509 static inline bool
pci_is_root_bus(struct pci_bus * pbus)510 pci_is_root_bus(struct pci_bus *pbus)
511 {
512
513 return (pbus->self == NULL);
514 }
515
516 static inline struct pci_dev *
pci_upstream_bridge(struct pci_dev * pdev)517 pci_upstream_bridge(struct pci_dev *pdev)
518 {
519
520 if (pci_is_root_bus(pdev->bus))
521 return (NULL);
522
523 /*
524 * If we do not have a (proper) "upstream bridge" set, e.g., we point
525 * to ourselves, try to handle this case on the fly like we do
526 * for pcie_find_root_port().
527 */
528 if (pdev == pdev->bus->self) {
529 device_t bridge;
530
531 /*
532 * In the case of DRM drivers, the passed device is a child of
533 * `vgapci`. We want to start the lookup from `vgapci`, so the
534 * parent of the passed `drmn`.
535 *
536 * We can use the `isdrm` flag to determine this.
537 */
538 bridge = pdev->dev.bsddev;
539 if (pdev->pdrv != NULL && pdev->pdrv->isdrm)
540 bridge = device_get_parent(bridge);
541 if (bridge == NULL)
542 goto done;
543
544 bridge = device_get_parent(bridge);
545 if (bridge == NULL)
546 goto done;
547 bridge = device_get_parent(bridge);
548 if (bridge == NULL)
549 goto done;
550 if (device_get_devclass(device_get_parent(bridge)) !=
551 devclass_find("pci"))
552 goto done;
553
554 /*
555 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev
556 * for it so it can be returned.
557 */
558 pdev->bus->self = lkpinew_pci_dev(bridge);
559 }
560 done:
561 return (pdev->bus->self);
562 }
563
564 #define pci_release_region(pdev, bar) \
565 linuxkpi_pci_release_region(pdev, bar)
566 #define pci_release_regions(pdev) \
567 linuxkpi_pci_release_regions(pdev)
568 #define pci_request_regions(pdev, res_name) \
569 linuxkpi_pci_request_regions(pdev, res_name)
570
571 static inline void
lkpi_pci_disable_msix(struct pci_dev * pdev)572 lkpi_pci_disable_msix(struct pci_dev *pdev)
573 {
574
575 pci_release_msi(pdev->dev.bsddev);
576
577 /*
578 * The MSIX IRQ numbers associated with this PCI device are no
579 * longer valid and might be re-assigned. Make sure
580 * lkpi_pci_find_irq_dev() does no longer see them by
581 * resetting their references to zero:
582 */
583 pdev->dev.irq_start = 0;
584 pdev->dev.irq_end = 0;
585 pdev->msix_enabled = false;
586 }
587 /* Only for consistency. No conflict on that one. */
588 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev)
589
590 static inline void
lkpi_pci_disable_msi(struct pci_dev * pdev)591 lkpi_pci_disable_msi(struct pci_dev *pdev)
592 {
593
594 pci_release_msi(pdev->dev.bsddev);
595
596 pdev->dev.irq_start = 0;
597 pdev->dev.irq_end = 0;
598 pdev->irq = pdev->dev.irq;
599 pdev->msi_enabled = false;
600 }
601 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev)
602 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev)
603
604 unsigned long pci_resource_start(struct pci_dev *pdev, int bar);
605 unsigned long pci_resource_len(struct pci_dev *pdev, int bar);
606
607 static inline bus_addr_t
pci_bus_address(struct pci_dev * pdev,int bar)608 pci_bus_address(struct pci_dev *pdev, int bar)
609 {
610
611 return (pci_resource_start(pdev, bar));
612 }
613
614 #define PCI_CAP_ID_EXP PCIY_EXPRESS
615 #define PCI_CAP_ID_PCIX PCIY_PCIX
616 #define PCI_CAP_ID_AGP PCIY_AGP
617 #define PCI_CAP_ID_PM PCIY_PMG
618
619 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL
620 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
621 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST
622 #define PCI_EXP_LNKCTL PCIER_LINK_CTL
623 #define PCI_EXP_LNKSTA PCIER_LINK_STA
624
625 static inline int
pci_find_capability(struct pci_dev * pdev,int capid)626 pci_find_capability(struct pci_dev *pdev, int capid)
627 {
628 int reg;
629
630 if (pci_find_cap(pdev->dev.bsddev, capid, ®))
631 return (0);
632 return (reg);
633 }
634
pci_pcie_cap(struct pci_dev * dev)635 static inline int pci_pcie_cap(struct pci_dev *dev)
636 {
637 return pci_find_capability(dev, PCI_CAP_ID_EXP);
638 }
639
640 static inline int
pci_find_ext_capability(struct pci_dev * pdev,int capid)641 pci_find_ext_capability(struct pci_dev *pdev, int capid)
642 {
643 int reg;
644
645 if (pci_find_extcap(pdev->dev.bsddev, capid, ®))
646 return (0);
647 return (reg);
648 }
649
650 #define PCIM_PCAP_PME_SHIFT 11
651 static __inline bool
pci_pme_capable(struct pci_dev * pdev,uint32_t flag)652 pci_pme_capable(struct pci_dev *pdev, uint32_t flag)
653 {
654 struct pci_devinfo *dinfo;
655 pcicfgregs *cfg;
656
657 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT))
658 return (false);
659
660 dinfo = device_get_ivars(pdev->dev.bsddev);
661 cfg = &dinfo->cfg;
662
663 if (cfg->pp.pp_cap == 0)
664 return (false);
665
666 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0)
667 return (true);
668
669 return (false);
670 }
671
672 static inline int
pci_disable_link_state(struct pci_dev * pdev,uint32_t flags)673 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags)
674 {
675
676 if (!pci_enable_aspm)
677 return (-EPERM);
678
679 return (-ENXIO);
680 }
681
682 static inline int
pci_read_config_byte(const struct pci_dev * pdev,int where,u8 * val)683 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val)
684 {
685
686 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1);
687 return (0);
688 }
689
690 static inline int
pci_read_config_word(const struct pci_dev * pdev,int where,u16 * val)691 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val)
692 {
693
694 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2);
695 return (0);
696 }
697
698 static inline int
pci_read_config_dword(const struct pci_dev * pdev,int where,u32 * val)699 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val)
700 {
701
702 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4);
703 return (0);
704 }
705
706 static inline int
pci_write_config_byte(const struct pci_dev * pdev,int where,u8 val)707 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val)
708 {
709
710 pci_write_config(pdev->dev.bsddev, where, val, 1);
711 return (0);
712 }
713
714 static inline int
pci_write_config_word(const struct pci_dev * pdev,int where,u16 val)715 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val)
716 {
717
718 pci_write_config(pdev->dev.bsddev, where, val, 2);
719 return (0);
720 }
721
722 static inline int
pci_write_config_dword(const struct pci_dev * pdev,int where,u32 val)723 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val)
724 {
725
726 pci_write_config(pdev->dev.bsddev, where, val, 4);
727 return (0);
728 }
729
730 int linux_pci_register_driver(struct pci_driver *pdrv);
731 int linux_pci_register_drm_driver(struct pci_driver *pdrv);
732 void linux_pci_unregister_driver(struct pci_driver *pdrv);
733 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv);
734
735 #define pci_register_driver(pdrv) \
736 linux_pci_register_driver(pdrv)
737 #define pci_unregister_driver(pdrv) \
738 linux_pci_unregister_driver(pdrv)
739
740 /*
741 * Enable msix, positive errors indicate actual number of available
742 * vectors. Negative errors are failures.
743 *
744 * NB: define added to prevent this definition of pci_enable_msix from
745 * clashing with the native FreeBSD version.
746 */
747 #define pci_enable_msix(...) \
748 linuxkpi_pci_enable_msix(__VA_ARGS__)
749
750 #define pci_enable_msix_range(...) \
751 linux_pci_enable_msix_range(__VA_ARGS__)
752
753 static inline int
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)754 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
755 int minvec, int maxvec)
756 {
757 int nvec = maxvec;
758 int rc;
759
760 if (maxvec < minvec)
761 return (-ERANGE);
762
763 do {
764 rc = pci_enable_msix(dev, entries, nvec);
765 if (rc < 0) {
766 return (rc);
767 } else if (rc > 0) {
768 if (rc < minvec)
769 return (-ENOSPC);
770 nvec = rc;
771 }
772 } while (rc);
773 return (nvec);
774 }
775
776 #define pci_enable_msi(pdev) \
777 linux_pci_enable_msi(pdev)
778
779 static inline int
pci_enable_msi(struct pci_dev * pdev)780 pci_enable_msi(struct pci_dev *pdev)
781 {
782
783 return (_lkpi_pci_enable_msi_range(pdev, 1, 1));
784 }
785
786 static inline int
pci_channel_offline(struct pci_dev * pdev)787 pci_channel_offline(struct pci_dev *pdev)
788 {
789
790 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID);
791 }
792
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)793 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
794 {
795 return -ENODEV;
796 }
797
pci_disable_sriov(struct pci_dev * dev)798 static inline void pci_disable_sriov(struct pci_dev *dev)
799 {
800 }
801
802 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \
803 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size)
804 #define pci_iomap(pdev, mmio_bar, mmio_size) \
805 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size)
806 #define pci_iounmap(pdev, res) \
807 linuxkpi_pci_iounmap(pdev, res)
808
809 static inline void
lkpi_pci_save_state(struct pci_dev * pdev)810 lkpi_pci_save_state(struct pci_dev *pdev)
811 {
812
813 pci_save_state(pdev->dev.bsddev);
814 }
815
816 static inline void
lkpi_pci_restore_state(struct pci_dev * pdev)817 lkpi_pci_restore_state(struct pci_dev *pdev)
818 {
819
820 pci_restore_state(pdev->dev.bsddev);
821 }
822
823 #define pci_save_state(dev) lkpi_pci_save_state(dev)
824 #define pci_restore_state(dev) lkpi_pci_restore_state(dev)
825
826 static inline int
pci_reset_function(struct pci_dev * pdev)827 pci_reset_function(struct pci_dev *pdev)
828 {
829
830 return (-ENOSYS);
831 }
832
833 #define DEFINE_PCI_DEVICE_TABLE(_table) \
834 const struct pci_device_id _table[] __devinitdata
835
836 /* XXX This should not be necessary. */
837 #define pcix_set_mmrbc(d, v) 0
838 #define pcix_get_max_mmrbc(d) 0
839 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v))
840
841 #define PCI_DMA_BIDIRECTIONAL 0
842 #define PCI_DMA_TODEVICE 1
843 #define PCI_DMA_FROMDEVICE 2
844 #define PCI_DMA_NONE 3
845
846 #define pci_pool dma_pool
847 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__)
848 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__)
849 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__)
850 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \
851 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc)
852 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \
853 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
854 _size, _vaddr, _dma_handle)
855 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \
856 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
857 _sg, _nents, (enum dma_data_direction)_dir)
858 #define pci_map_single(_hwdev, _ptr, _size, _dir) \
859 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
860 (_ptr), (_size), (enum dma_data_direction)_dir)
861 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \
862 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
863 _addr, _size, (enum dma_data_direction)_dir)
864 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \
865 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
866 _sg, _nents, (enum dma_data_direction)_dir)
867 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \
868 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\
869 _offset, _size, (enum dma_data_direction)_dir)
870 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \
871 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
872 _dma_address, _size, (enum dma_data_direction)_dir)
873 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask))
874 #define pci_dma_mapping_error(_pdev, _dma_addr) \
875 dma_mapping_error(&(_pdev)->dev, _dma_addr)
876 #define pci_set_consistent_dma_mask(_pdev, _mask) \
877 dma_set_coherent_mask(&(_pdev)->dev, (_mask))
878 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x);
879 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x);
880 #define pci_unmap_addr dma_unmap_addr
881 #define pci_unmap_addr_set dma_unmap_addr_set
882 #define pci_unmap_len dma_unmap_len
883 #define pci_unmap_len_set dma_unmap_len_set
884
885 typedef unsigned int __bitwise pci_channel_state_t;
886 typedef unsigned int __bitwise pci_ers_result_t;
887
888 enum pci_channel_state {
889 pci_channel_io_normal = 1,
890 pci_channel_io_frozen = 2,
891 pci_channel_io_perm_failure = 3,
892 };
893
894 enum pci_ers_result {
895 PCI_ERS_RESULT_NONE = 1,
896 PCI_ERS_RESULT_CAN_RECOVER = 2,
897 PCI_ERS_RESULT_NEED_RESET = 3,
898 PCI_ERS_RESULT_DISCONNECT = 4,
899 PCI_ERS_RESULT_RECOVERED = 5,
900 };
901
902 /* PCI bus error event callbacks */
903 struct pci_error_handlers {
904 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
905 enum pci_channel_state error);
906 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
907 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
908 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
909 void (*resume)(struct pci_dev *dev);
910 };
911
912 /* FreeBSD does not support SRIOV - yet */
pci_physfn(struct pci_dev * dev)913 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
914 {
915 return dev;
916 }
917
pci_is_pcie(struct pci_dev * dev)918 static inline bool pci_is_pcie(struct pci_dev *dev)
919 {
920 return !!pci_pcie_cap(dev);
921 }
922
pcie_flags_reg(struct pci_dev * dev)923 static inline u16 pcie_flags_reg(struct pci_dev *dev)
924 {
925 int pos;
926 u16 reg16;
927
928 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
929 if (!pos)
930 return 0;
931
932 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16);
933
934 return reg16;
935 }
936
pci_pcie_type(struct pci_dev * dev)937 static inline int pci_pcie_type(struct pci_dev *dev)
938 {
939 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
940 }
941
pcie_cap_version(struct pci_dev * dev)942 static inline int pcie_cap_version(struct pci_dev *dev)
943 {
944 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS;
945 }
946
pcie_cap_has_lnkctl(struct pci_dev * dev)947 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev)
948 {
949 int type = pci_pcie_type(dev);
950
951 return pcie_cap_version(dev) > 1 ||
952 type == PCI_EXP_TYPE_ROOT_PORT ||
953 type == PCI_EXP_TYPE_ENDPOINT ||
954 type == PCI_EXP_TYPE_LEG_END;
955 }
956
pcie_cap_has_devctl(const struct pci_dev * dev)957 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
958 {
959 return true;
960 }
961
pcie_cap_has_sltctl(struct pci_dev * dev)962 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev)
963 {
964 int type = pci_pcie_type(dev);
965
966 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
967 (type == PCI_EXP_TYPE_DOWNSTREAM &&
968 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT);
969 }
970
pcie_cap_has_rtctl(struct pci_dev * dev)971 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev)
972 {
973 int type = pci_pcie_type(dev);
974
975 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
976 type == PCI_EXP_TYPE_RC_EC;
977 }
978
pcie_capability_reg_implemented(struct pci_dev * dev,int pos)979 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
980 {
981 if (!pci_is_pcie(dev))
982 return false;
983
984 switch (pos) {
985 case PCI_EXP_FLAGS_TYPE:
986 return true;
987 case PCI_EXP_DEVCAP:
988 case PCI_EXP_DEVCTL:
989 case PCI_EXP_DEVSTA:
990 return pcie_cap_has_devctl(dev);
991 case PCI_EXP_LNKCAP:
992 case PCI_EXP_LNKCTL:
993 case PCI_EXP_LNKSTA:
994 return pcie_cap_has_lnkctl(dev);
995 case PCI_EXP_SLTCAP:
996 case PCI_EXP_SLTCTL:
997 case PCI_EXP_SLTSTA:
998 return pcie_cap_has_sltctl(dev);
999 case PCI_EXP_RTCTL:
1000 case PCI_EXP_RTCAP:
1001 case PCI_EXP_RTSTA:
1002 return pcie_cap_has_rtctl(dev);
1003 case PCI_EXP_DEVCAP2:
1004 case PCI_EXP_DEVCTL2:
1005 case PCI_EXP_LNKCAP2:
1006 case PCI_EXP_LNKCTL2:
1007 case PCI_EXP_LNKSTA2:
1008 return pcie_cap_version(dev) > 1;
1009 default:
1010 return false;
1011 }
1012 }
1013
1014 static inline int
pcie_capability_read_dword(struct pci_dev * dev,int pos,u32 * dst)1015 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
1016 {
1017 *dst = 0;
1018 if (pos & 3)
1019 return -EINVAL;
1020
1021 if (!pcie_capability_reg_implemented(dev, pos))
1022 return -EINVAL;
1023
1024 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst);
1025 }
1026
1027 static inline int
pcie_capability_read_word(struct pci_dev * dev,int pos,u16 * dst)1028 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst)
1029 {
1030 *dst = 0;
1031 if (pos & 3)
1032 return -EINVAL;
1033
1034 if (!pcie_capability_reg_implemented(dev, pos))
1035 return -EINVAL;
1036
1037 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst);
1038 }
1039
1040 static inline int
pcie_capability_write_word(struct pci_dev * dev,int pos,u16 val)1041 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
1042 {
1043 if (pos & 1)
1044 return -EINVAL;
1045
1046 if (!pcie_capability_reg_implemented(dev, pos))
1047 return 0;
1048
1049 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
1050 }
1051
1052 static inline int
pcie_capability_clear_and_set_word(struct pci_dev * dev,int pos,uint16_t clear,uint16_t set)1053 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1054 uint16_t clear, uint16_t set)
1055 {
1056 int error;
1057 uint16_t v;
1058
1059 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL)
1060 spin_lock(&dev->pcie_cap_lock);
1061
1062 error = pcie_capability_read_word(dev, pos, &v);
1063 if (error == 0) {
1064 v &= ~clear;
1065 v |= set;
1066 error = pcie_capability_write_word(dev, pos, v);
1067 }
1068
1069 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL)
1070 spin_unlock(&dev->pcie_cap_lock);
1071
1072 return (error);
1073 }
1074
1075 static inline int
pcie_capability_set_word(struct pci_dev * dev,int pos,uint16_t val)1076 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val)
1077 {
1078 return (pcie_capability_clear_and_set_word(dev, pos, 0, val));
1079 }
1080
1081 static inline int
pcie_capability_clear_word(struct pci_dev * dev,int pos,uint16_t val)1082 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val)
1083 {
1084 return (pcie_capability_clear_and_set_word(dev, pos, val, 0));
1085 }
1086
pcie_get_minimum_link(struct pci_dev * dev,enum pci_bus_speed * speed,enum pcie_link_width * width)1087 static inline int pcie_get_minimum_link(struct pci_dev *dev,
1088 enum pci_bus_speed *speed, enum pcie_link_width *width)
1089 {
1090 *speed = PCI_SPEED_UNKNOWN;
1091 *width = PCIE_LNK_WIDTH_UNKNOWN;
1092 return (0);
1093 }
1094
1095 static inline int
pci_num_vf(struct pci_dev * dev)1096 pci_num_vf(struct pci_dev *dev)
1097 {
1098 return (0);
1099 }
1100
1101 static inline enum pci_bus_speed
pcie_get_speed_cap(struct pci_dev * dev)1102 pcie_get_speed_cap(struct pci_dev *dev)
1103 {
1104 device_t root;
1105 uint32_t lnkcap, lnkcap2;
1106 int error, pos;
1107
1108 root = device_get_parent(dev->dev.bsddev);
1109 if (root == NULL)
1110 return (PCI_SPEED_UNKNOWN);
1111 root = device_get_parent(root);
1112 if (root == NULL)
1113 return (PCI_SPEED_UNKNOWN);
1114 root = device_get_parent(root);
1115 if (root == NULL)
1116 return (PCI_SPEED_UNKNOWN);
1117
1118 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA ||
1119 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS)
1120 return (PCI_SPEED_UNKNOWN);
1121
1122 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0)
1123 return (PCI_SPEED_UNKNOWN);
1124
1125 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4);
1126
1127 if (lnkcap2) { /* PCIe r3.0-compliant */
1128 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
1129 return (PCIE_SPEED_2_5GT);
1130 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
1131 return (PCIE_SPEED_5_0GT);
1132 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
1133 return (PCIE_SPEED_8_0GT);
1134 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
1135 return (PCIE_SPEED_16_0GT);
1136 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB)
1137 return (PCIE_SPEED_32_0GT);
1138 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB)
1139 return (PCIE_SPEED_64_0GT);
1140 } else { /* pre-r3.0 */
1141 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4);
1142 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
1143 return (PCIE_SPEED_2_5GT);
1144 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
1145 return (PCIE_SPEED_5_0GT);
1146 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
1147 return (PCIE_SPEED_8_0GT);
1148 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
1149 return (PCIE_SPEED_16_0GT);
1150 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB)
1151 return (PCIE_SPEED_32_0GT);
1152 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB)
1153 return (PCIE_SPEED_64_0GT);
1154 }
1155 return (PCI_SPEED_UNKNOWN);
1156 }
1157
1158 static inline enum pcie_link_width
pcie_get_width_cap(struct pci_dev * dev)1159 pcie_get_width_cap(struct pci_dev *dev)
1160 {
1161 uint32_t lnkcap;
1162
1163 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
1164 if (lnkcap)
1165 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4);
1166
1167 return (PCIE_LNK_WIDTH_UNKNOWN);
1168 }
1169
1170 static inline int
pcie_get_mps(struct pci_dev * dev)1171 pcie_get_mps(struct pci_dev *dev)
1172 {
1173 return (pci_get_max_payload(dev->dev.bsddev));
1174 }
1175
1176 static inline uint32_t
PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd)1177 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd)
1178 {
1179
1180 switch(spd) {
1181 case PCIE_SPEED_64_0GT:
1182 return (64000 * 128 / 130);
1183 case PCIE_SPEED_32_0GT:
1184 return (32000 * 128 / 130);
1185 case PCIE_SPEED_16_0GT:
1186 return (16000 * 128 / 130);
1187 case PCIE_SPEED_8_0GT:
1188 return (8000 * 128 / 130);
1189 case PCIE_SPEED_5_0GT:
1190 return (5000 * 8 / 10);
1191 case PCIE_SPEED_2_5GT:
1192 return (2500 * 8 / 10);
1193 default:
1194 return (0);
1195 }
1196 }
1197
1198 static inline uint32_t
pcie_bandwidth_available(struct pci_dev * pdev,struct pci_dev ** limiting,enum pci_bus_speed * speed,enum pcie_link_width * width)1199 pcie_bandwidth_available(struct pci_dev *pdev,
1200 struct pci_dev **limiting,
1201 enum pci_bus_speed *speed,
1202 enum pcie_link_width *width)
1203 {
1204 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev);
1205 enum pcie_link_width nwidth = pcie_get_width_cap(pdev);
1206
1207 if (speed)
1208 *speed = nspeed;
1209 if (width)
1210 *width = nwidth;
1211
1212 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed));
1213 }
1214
1215 static inline bool
pcie_aspm_enabled(struct pci_dev * pdev)1216 pcie_aspm_enabled(struct pci_dev *pdev)
1217 {
1218 return (false);
1219 }
1220
1221 static inline struct pci_dev *
pcie_find_root_port(struct pci_dev * pdev)1222 pcie_find_root_port(struct pci_dev *pdev)
1223 {
1224 device_t root;
1225
1226 if (pdev->root != NULL)
1227 return (pdev->root);
1228
1229 root = pci_find_pcie_root_port(pdev->dev.bsddev);
1230 if (root == NULL)
1231 return (NULL);
1232
1233 pdev->root = lkpinew_pci_dev(root);
1234 return (pdev->root);
1235 }
1236
1237 /* This is needed when people rip out the device "HotPlug". */
1238 static inline void
pci_lock_rescan_remove(void)1239 pci_lock_rescan_remove(void)
1240 {
1241 }
1242
1243 static inline void
pci_unlock_rescan_remove(void)1244 pci_unlock_rescan_remove(void)
1245 {
1246 }
1247
1248 static __inline void
pci_stop_and_remove_bus_device(struct pci_dev * pdev)1249 pci_stop_and_remove_bus_device(struct pci_dev *pdev)
1250 {
1251 }
1252
1253 static inline int
pci_rescan_bus(struct pci_bus * pbus)1254 pci_rescan_bus(struct pci_bus *pbus)
1255 {
1256 device_t *devlist, parent;
1257 int devcount, error;
1258
1259 if (!device_is_attached(pbus->self->dev.bsddev))
1260 return (0);
1261 /* pci_rescan_method() will work on the pcib (parent). */
1262 error = BUS_RESCAN(pbus->self->dev.bsddev);
1263 if (error != 0)
1264 return (0);
1265
1266 parent = device_get_parent(pbus->self->dev.bsddev);
1267 error = device_get_children(parent, &devlist, &devcount);
1268 if (error != 0)
1269 return (0);
1270 if (devcount != 0)
1271 free(devlist, M_TEMP);
1272
1273 return (devcount);
1274 }
1275
1276 /*
1277 * The following functions can be used to attach/detach the LinuxKPI's
1278 * PCI device runtime. The pci_driver and pci_device_id pointer is
1279 * allowed to be NULL. Other pointers must be all valid.
1280 * The pci_dev structure should be zero-initialized before passed
1281 * to the linux_pci_attach_device function.
1282 */
1283 extern int linux_pci_attach_device(device_t, struct pci_driver *,
1284 const struct pci_device_id *, struct pci_dev *);
1285 extern int linux_pci_detach_device(struct pci_dev *);
1286
1287 static inline int
pci_dev_present(const struct pci_device_id * cur)1288 pci_dev_present(const struct pci_device_id *cur)
1289 {
1290 while (cur != NULL && (cur->vendor || cur->device)) {
1291 if (pci_find_device(cur->vendor, cur->device) != NULL) {
1292 return (1);
1293 }
1294 cur++;
1295 }
1296 return (0);
1297 }
1298
1299 static inline const struct pci_device_id *
pci_match_id(const struct pci_device_id * ids,struct pci_dev * pdev)1300 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev)
1301 {
1302 if (ids == NULL)
1303 return (NULL);
1304
1305 for (;
1306 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0;
1307 ids++)
1308 if ((ids->vendor == PCI_ANY_ID ||
1309 ids->vendor == pdev->vendor) &&
1310 (ids->device == PCI_ANY_ID ||
1311 ids->device == pdev->device) &&
1312 (ids->subvendor == PCI_ANY_ID ||
1313 ids->subvendor == pdev->subsystem_vendor) &&
1314 (ids->subdevice == PCI_ANY_ID ||
1315 ids->subdevice == pdev->subsystem_device) &&
1316 ((ids->class ^ pdev->class) & ids->class_mask) == 0)
1317 return (ids);
1318
1319 return (NULL);
1320 }
1321
1322 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain,
1323 unsigned int bus, unsigned int devfn);
1324 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \
1325 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn)
1326
1327 static inline int
pci_domain_nr(struct pci_bus * pbus)1328 pci_domain_nr(struct pci_bus *pbus)
1329 {
1330
1331 return (pbus->domain);
1332 }
1333
1334 static inline int
pci_bus_read_config(struct pci_bus * bus,unsigned int devfn,int pos,uint32_t * val,int len)1335 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn,
1336 int pos, uint32_t *val, int len)
1337 {
1338
1339 *val = pci_read_config(bus->self->dev.bsddev, pos, len);
1340 return (0);
1341 }
1342
1343 static inline int
pci_bus_read_config_word(struct pci_bus * bus,unsigned int devfn,int pos,u16 * val)1344 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val)
1345 {
1346 uint32_t tmp;
1347 int ret;
1348
1349 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2);
1350 *val = (u16)tmp;
1351 return (ret);
1352 }
1353
1354 static inline int
pci_bus_read_config_byte(struct pci_bus * bus,unsigned int devfn,int pos,u8 * val)1355 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val)
1356 {
1357 uint32_t tmp;
1358 int ret;
1359
1360 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1);
1361 *val = (u8)tmp;
1362 return (ret);
1363 }
1364
1365 static inline int
pci_bus_write_config(struct pci_bus * bus,unsigned int devfn,int pos,uint32_t val,int size)1366 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos,
1367 uint32_t val, int size)
1368 {
1369
1370 pci_write_config(bus->self->dev.bsddev, pos, val, size);
1371 return (0);
1372 }
1373
1374 static inline int
pci_bus_write_config_byte(struct pci_bus * bus,unsigned int devfn,int pos,uint8_t val)1375 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos,
1376 uint8_t val)
1377 {
1378 return (pci_bus_write_config(bus, devfn, pos, val, 1));
1379 }
1380
1381 static inline int
pci_bus_write_config_word(struct pci_bus * bus,unsigned int devfn,int pos,uint16_t val)1382 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos,
1383 uint16_t val)
1384 {
1385 return (pci_bus_write_config(bus, devfn, pos, val, 2));
1386 }
1387
1388 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from);
1389 #define pci_get_class(class, from) lkpi_pci_get_class(class, from)
1390 struct pci_dev *lkpi_pci_get_base_class(unsigned int class,
1391 struct pci_dev *from);
1392 #define pci_get_base_class(class, from) lkpi_pci_get_base_class(class, from)
1393
1394 /* -------------------------------------------------------------------------- */
1395
1396 #define pcim_enable_device(pdev) \
1397 linuxkpi_pcim_enable_device(pdev)
1398 #define pcim_iomap_table(pdev) \
1399 linuxkpi_pcim_iomap_table(pdev)
1400 #define pcim_iomap_regions(pdev, mask, name) \
1401 linuxkpi_pcim_iomap_regions(pdev, mask, name)
1402
1403 static inline int
pcim_iomap_regions_request_all(struct pci_dev * pdev,uint32_t mask,char * name)1404 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name)
1405 {
1406 uint32_t requests, req_mask;
1407 int bar, error;
1408
1409 /* Request all the BARs ("regions") we do not iomap. */
1410 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask;
1411 for (bar = requests = 0; requests != req_mask; bar++) {
1412 if ((req_mask & (1 << bar)) == 0)
1413 continue;
1414 error = pci_request_region(pdev, bar, name);
1415 if (error != 0 && error != -ENODEV)
1416 goto err;
1417 requests |= (1 << bar);
1418 }
1419
1420 error = pcim_iomap_regions(pdev, mask, name);
1421 if (error != 0)
1422 goto err;
1423
1424 return (0);
1425
1426 err:
1427 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) {
1428 if ((requests & (1 << bar)) != 0)
1429 pci_release_region(pdev, bar);
1430 }
1431
1432 return (-EINVAL);
1433 }
1434
1435 /*
1436 * We cannot simply re-define pci_get_device() as we would normally do
1437 * and then hide it in linux_pci.c as too many semi-native drivers still
1438 * include linux/pci.h and run into the conflict with native PCI. Linux drivers
1439 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device().
1440 */
1441 static inline struct pci_dev *
linuxkpi_pci_get_device(uint32_t vendor,uint32_t device,struct pci_dev * odev)1442 linuxkpi_pci_get_device(uint32_t vendor, uint32_t device, struct pci_dev *odev)
1443 {
1444
1445 return (lkpi_pci_get_device(vendor, device, odev));
1446 }
1447
1448 /* This is a FreeBSD extension so we can use bus_*(). */
1449 static inline void
linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev * pdev)1450 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev)
1451 {
1452 pdev->want_iomap_res = true;
1453 }
1454
1455 static inline bool
pci_is_thunderbolt_attached(struct pci_dev * pdev)1456 pci_is_thunderbolt_attached(struct pci_dev *pdev)
1457 {
1458
1459 return (false);
1460 }
1461
1462 static inline void *
pci_platform_rom(struct pci_dev * pdev,size_t * size)1463 pci_platform_rom(struct pci_dev *pdev, size_t *size)
1464 {
1465
1466 return (NULL);
1467 }
1468
1469 static inline void
pci_ignore_hotplug(struct pci_dev * pdev)1470 pci_ignore_hotplug(struct pci_dev *pdev)
1471 {
1472 }
1473
1474 static inline const char *
pci_power_name(pci_power_t state)1475 pci_power_name(pci_power_t state)
1476 {
1477 int pstate = state + 1;
1478
1479 if (pstate >= 0 && pstate < nitems(pci_power_names))
1480 return (pci_power_names[pstate]);
1481 else
1482 return (pci_power_names[0]);
1483 }
1484
1485 static inline int
pcie_get_readrq(struct pci_dev * dev)1486 pcie_get_readrq(struct pci_dev *dev)
1487 {
1488 u16 ctl;
1489
1490 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl))
1491 return (-EINVAL);
1492
1493 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12));
1494 }
1495
1496 static inline bool
pci_is_enabled(struct pci_dev * pdev)1497 pci_is_enabled(struct pci_dev *pdev)
1498 {
1499
1500 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) &
1501 PCIM_CMD_BUSMASTEREN) != 0);
1502 }
1503
1504 static inline int
pci_wait_for_pending_transaction(struct pci_dev * pdev)1505 pci_wait_for_pending_transaction(struct pci_dev *pdev)
1506 {
1507
1508 return (0);
1509 }
1510
1511 static inline int
pci_assign_resource(struct pci_dev * pdev,int bar)1512 pci_assign_resource(struct pci_dev *pdev, int bar)
1513 {
1514
1515 return (0);
1516 }
1517
1518 static inline int
pci_irq_vector(struct pci_dev * pdev,unsigned int vector)1519 pci_irq_vector(struct pci_dev *pdev, unsigned int vector)
1520 {
1521
1522 if (!pdev->msix_enabled && !pdev->msi_enabled) {
1523 if (vector != 0)
1524 return (-EINVAL);
1525 return (pdev->irq);
1526 }
1527
1528 if (pdev->msix_enabled || pdev->msi_enabled) {
1529 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end)
1530 return (-EINVAL);
1531 return (pdev->dev.irq_start + vector);
1532 }
1533
1534 return (-ENXIO);
1535 }
1536
1537 static inline int
pci_wake_from_d3(struct pci_dev * pdev,bool enable)1538 pci_wake_from_d3(struct pci_dev *pdev, bool enable)
1539 {
1540
1541 pr_debug("%s: TODO\n", __func__);
1542 return (0);
1543 }
1544
1545 #endif /* _LINUXKPI_LINUX_PCI_H_ */
1546