1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _PCIIDE_H 28 #define _PCIIDE_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 37 /* 38 * Bus Mastering devices have a PCI class-code of 0x010180 to 0x0101ff 39 */ 40 #define PCIIDE_BM_CAP_MASK 0x80 41 #define PCIIDE_BM_CLASS ((PCI_CLASS_MASS << 16) | (PCI_MASS_IDE << 8) | 0x80) 42 #define PCIIDE_BM_CLASS_MASK 0xffffff80 43 44 45 #define PCIIDE_BMICX_REG 0 /* Bus Master IDE Command Register */ 46 47 #define PCIIDE_BMICX_SSBM 0x01 /* Start/Stop Bus Master */ 48 #define PCIIDE_BMICX_SSBM_E 0x01 /* 1=Start (Enable) */ 49 /* 0=Start (Disable) */ 50 51 /* 52 * NOTE: "read" and "write" are the actions of the DMA 53 * engine on the PCI bus. Not the DMA engine's action on the ATA 54 * BUS. Therefore for a ATA READ command, program the DMA engine to 55 * "write to memory" mode (and vice versa). 56 */ 57 #define PCIIDE_BMICX_RWCON 0x08 /* Read/Write Control */ 58 #define PCIIDE_BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */ 59 #define PCIIDE_BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */ 60 61 /* preserve these bits during updates */ 62 #define PCIIDE_BMICX_MASK (~(PCIIDE_BMICX_SSBM | PCIIDE_BMICX_RWCON)) 63 64 65 66 #define PCIIDE_BMISX_REG 2 /* Bus Master IDE Status Register */ 67 68 #define PCIIDE_BMISX_BMIDEA 0x01 /* Bus Master IDE Active */ 69 #define PCIIDE_BMISX_IDERR 0x02 /* IDE DMA Error */ 70 #define PCIIDE_BMISX_IDEINTS 0x04 /* IDE Interrupt Status */ 71 #define PCIIDE_BMISX_DMA0CAP 0x20 /* Drive 0 DMA Capable */ 72 #define PCIIDE_BMISX_DMA1CAP 0x40 /* Drive 1 DMA Capable */ 73 #define PCIIDE_BMISX_SIMPLEX 0x80 /* Simplex only */ 74 75 /* preserve these bits during updates */ 76 #define PCIIDE_BMISX_MASK 0xf8 77 78 #define PCIIDE_BMIDTPX_REG 4 /* Bus Master IDE Desc. Table Ptr */ 79 #define PCIIDE_BMIDTPX_MASK 0x00000003 /* must be zeros */ 80 81 82 typedef struct PhysicalRegionDescriptorTableEntry { 83 uint_t p_address; /* physical address */ 84 uint_t p_count; /* byte count, EOT in high order bit */ 85 } prde_t; 86 87 /* 88 * Some specs say the p_address must 32-bit aligned, and some claim 89 * 16-bit alignment. Use 32-bit alignment just to be safe. 90 */ 91 #ifdef __not_yet__ 92 #define PCIIDE_PRDE_ADDR_MASK ((uint_t)(sizeof (short) -1)) 93 #else 94 #define PCIIDE_PRDE_ADDR_MASK ((uint_t)(sizeof (int) -1)) 95 #endif 96 97 #define PCIIDE_PRDE_CNT_MASK ((uint_t)0x0001) /* must be even */ 98 #define PCIIDE_PRDE_CNT_MAX ((uint_t)0x10000) /* 0 == 64k */ 99 #define PCIIDE_PRDE_EOT ((uint_t)0x80000000) 100 101 #ifdef __cplusplus 102 } 103 #endif 104 105 #endif /* _PCIIDE_H */ 106