xref: /illumos-gate/usr/src/uts/common/sys/pcic_reg.h (revision 2d6eb4a5e0a47d30189497241345dc5466bb68ab)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 /*
28  * Intel 82365SL device and register definitions
29  */
30 
31 #ifndef _PCIC_REG_H
32 #define	_PCIC_REG_H
33 
34 #ifdef	__cplusplus
35 extern "C" {
36 #endif
37 
38 /*
39  * global information
40  */
41 #define	PCIC_MAX_CONTROLLERS	4 /* maximum of 4 chips in system */
42 
43 /*
44  * per socket information
45  */
46 
47 #define	PCIC_SOCKETS	2	/* number of sockets per PCIC chip */
48 #define	PCIC_MEMWINDOWS	5	/* number of memory windows per socket */
49 #define	PCIC_IOWINDOWS	2	/* number of I/O address windows per socket */
50 /* number of windows per chip */
51 #define	PCIC_NUMWINDOWS ((PCIC_MEMWINDOWS + PCIC_IOWINDOWS) * PCIC_SOCKETS)
52 /* number of windows per socket */
53 #define	PCIC_NUMWINSOCK	(PCIC_MEMWINDOWS+PCIC_IOWINDOWS)
54 
55 /*
56  * socket selection registers
57  *
58  * the PCIC allows up to 8 sockets per system
59  * this is done by having two sockets per chip and up to 4 chips per
60  * system.  There can be up to 4 sockets (2 PCIC chips) per I/O address.
61  * There are two possible I/O address (index register) values.
62  * socket#	I/O address	value to write to index register
63  *   0		INDEX_REG0	BASE0 + SOCKET_0 + register offset
64  *   1		INDEX_REG0	BASE0 + SOCKET_1 + register offset
65  *   2		INDEX_REG0	BASE1 + SOCKET_0 + register offset
66  *   3		INDEX_REG0	BASE1 + SOCKET_1 + register offset
67  * next 4 are based off of INDEX_REG1
68  */
69 
70 #define	PCIC_INDEX_REG0	0x3e0	/* first possible index register */
71 #define	PCIC_INDEX_REG1	0x3e2	/* second possible index register */
72 
73 #define	PCIC_BASE0	0x00	/* first set of sockets */
74 #define	PCIC_BASE1	0x80	/* second set of sockets */
75 
76 #define	PCIC_SOCKET_0	0x00	/* first socket */
77 #define	PCIC_SOCKET_1	0x40	/* second socket */
78 
79 #define	PCIC_DATA_REG0	(PCIC_INDEX_REG0+1)
80 #define	PCIC_DATA_REG1	(PCIC_INDEX_REG1+1)
81 
82 /*
83  * per socket register
84  * these are accessed by writing the offset value into the
85  * index register and adding the appropriate base offset and socket offset
86  * the register is then present in the data register.
87  */
88 
89 /* General Registers */
90 
91 #define	PCIC_CHIP_REVISION	0x00 /* identification and revision */
92 #define	PCIC_INTERFACE_STATUS	0x01 /* Interface status */
93 #define	PCIC_POWER_CONTROL	0x02 /* Power and RESETDRV control */
94 #define	PCIC_CARD_STATUS_CHANGE	0x04 /* card status change */
95 #define	PCIC_MAPPING_ENABLE	0x06 /* address window mapping enable */
96 #define	PCIC_CARD_DETECT	0x16 /* card detect&general control register */
97 #define	PCIC_MISC_CTL_1		0x16 /* CL version */
98 #define	PCIC_GLOBAL_CONTROL	0x1e /* global control register */
99 #define	PCIC_MISC_CTL_2		0x1e /* CL version */
100 #define	PCIC_CHIP_INFO		0x1f /* Cirrus Logic chip info register */
101 
102 /* Interrupt Registers */
103 
104 #define	PCIC_INTERRUPT		0x03 /* interrupt & general control register */
105 #define	PCIC_MANAGEMENT_INT	0x05 /* card status change interrupt register */
106 
107 /* I/O Registers */
108 
109 #define	PCIC_IO_CONTROL		0x07 /* I/O Control register */
110 #define	PCIC_IO_ADDR_0_STARTLOW	0x08 /* I/O address map 0 start low byte */
111 #define	PCIC_IO_ADDR_0_STARTHI	0x09 /* I/O address map 0 start high byte */
112 #define	PCIC_IO_ADDR_0_STOPLOW	0x0a /* I/O address map 0 stop low byte */
113 #define	PCIC_IO_ADDR_0_STOPHI	0x0b /* I/O address map 0 stop high byte */
114 #define	PCIC_IO_OFFSET_LOW	0x36 /* I/O Offset for CL */
115 #define	PCIC_IO_OFFSET_HI	0x37
116 #define	PCIC_IO_OFFSET_OFFSET	2
117 
118 #define	PCIC_IO_ADDR_1_OFFSET	5 /* offset to second I/O map register set */
119 #define	PCIC_IO_WIN_MASK	0xf
120 
121 /* Memory Registers */
122 				/* window 0 */
123 #define	PCIC_SYSMEM_0_STARTLOW	0x10 /* system memory map 0 start low byte */
124 #define	PCIC_SYSMEM_0_STARTHI	0x11 /* system memory map 0 start high byte */
125 #define	PCIC_SYSMEM_0_STOPLOW	0x12 /* system memory map 0 stop low byte */
126 #define	PCIC_SYSMEM_0_STOPHI	0x13 /* system memory map 0 stop high byte */
127 #define	PCIC_CARDMEM_0_LOW	0x14 /* card memory offset 0 low byte */
128 #define	PCIC_CARDMEM_0_HI	0x15 /* card memory offset 0 high byte */
129 
130 				/* window 1 */
131 #define	PCIC_SYSMEM_1_STARTLOW	0x18 /* system memory map 0 start low byte */
132 #define	PCIC_SYSMEM_1_STARTHI	0x19 /* system memory map 0 start high byte */
133 #define	PCIC_SYSMEM_1_STOPLOW	0x1a /* system memory map 0 stop low byte */
134 #define	PCIC_SYSMEM_1_STOPHI	0x1b /* system memory map 0 stop high byte */
135 #define	PCIC_CARDMEM_1_LOW	0x1c /* card memory offset 0 low byte */
136 #define	PCIC_CARDMEM_1_HI	0x1d /* card memory offset 0 high byte */
137 
138 #define	PCIC_MEM_1_OFFSET	8 /* offset to second memory map register set */
139 #define	PCIC_MEM_2_OFFSET	16
140 #define	PCIC_MEM_3_OFFSET	24
141 #define	PCIC_MEM_4_OFFSET	32
142 
143 #define	PCIC_IO_OFFSET		4 /* offset to next set of I/O map registers */
144 
145 /* Cirrus Logic specific registers */
146 #define	PCIC_TIME_SETUP_0	0x3A
147 #define	PCIC_TIME_SETUP_1	0x3D
148 #define	PCIC_TIME_COMMAND_0	0x3B
149 #define	PCIC_TIME_COMMAND_1	0x3E
150 #define	PCIC_TIME_RECOVER_0	0x3C
151 #define	PCIC_TIME_RECOVER_1	0x3F
152 #define	PCIC_ATA_CONTROL	0x26
153 #define	PCIC_FIFO_CONTROL	0x17
154 #define	PCIC_CL_EXINDEX		0x2e
155 #define	PCIC_CL_EXDATA		0x2f
156 
157 /*
158  * Cirrus Logic PCI-PCMCIA adapters extension register indicies
159  */
160 #define	PCIC_CLEXT_SCRATCH	0x00
161 #define	PCIC_CLEXT_DMASK_0	0x01
162 #define	PCIC_CLEXT_EXT_CTL_1	0x03
163 #define	PCIC_CLEXT_MMAP0_UA	0x05
164 #define	PCIC_CLEXT_MMAP1_UA	0x06
165 #define	PCIC_CLEXT_MMAP2_UA	0x07
166 #define	PCIC_CLEXT_MMAP3_UA	0x08
167 #define	PCIC_CLEXT_MMAP4_UA	0x09
168 #define	PCIC_CLEXT_EXDATA	0x0a
169 #define	PCIC_CLEXT_EXT_CTL_2	0x0b	/* 6729 */
170 #define	PCIC_CLEXT_MISC_CTL_3	0x25	/* 6730 */
171 #define	PCIC_CLEXT_SMB_CTL	0x26	/* 6730 */
172 
173 /* the 6832 is mapped into different offsets for extension regs */
174 
175 #define	PCIC_CBCLEXT_MMAP0_UA	0x40 /* minus the 0x800 */
176 #define	PCIC_CBCLEXT_MMAP1_UA	0x41
177 #define	PCIC_CBCLEXT_MMAP2_UA	0x42
178 #define	PCIC_CBCLEXT_MMAP3_UA	0x43
179 #define	PCIC_CBCLEXT_MMAP4_UA	0x44
180 #define	PCIC_CBCLEXT_MMAP5_UA	0x45
181 
182 #define	PCIC_CLEXT_MISC_CTL_3_REV_MASK	0xf0
183 
184 /*
185  * Cirrus Logic PCI-PCMCIA PCIC_CLEXT_EXT_CTL_1 reg bit definitions
186  */
187 #define	PCIC_CLEXT_IRQ_LVL_MODE	0x08
188 #define	PCIC_CLEXT_SMI_LVL_MODE	0x00 /* see errata 1.0 */
189 
190 /*
191  * Cirrus Logic PCI-PCMCIA PCIC_MISC_CTL_2 reg bit definitions
192  */
193 #define	PCIC_CL_LP_DYN_MODE	0x02	/* low-power dynamic mode */
194 #define	PCIC_CL_TIMER_CLK_DIV	0x10	/* PCI clock divide */
195 
196 /*
197  * Cirrus Logic PCI-PCMCIA PCIC_CLEXT_MISC_CTL_3 reg bit definitions
198  */
199 #define	PCIC_CLEXT_INT_PC_PCI	0x00
200 #define	PCIC_CLEXT_INT_EXT_HW	0x01
201 #define	PCIC_CLEXT_INT_PCI_WAY	0x10
202 #define	PCIC_CLEXT_INT_PCI	0x03 /* see errata 1.0 */
203 #define	PCIC_CLEXT_PWR_EXT_HW	0x00
204 #define	PCIC_CLEXT_PWR_RESERVED	0x04
205 #define	PCIC_CLEXT_PWR_TI	0x80
206 #define	PCIC_CLEXT_PWR_SMB	0xc0
207 
208 /*
209  * Intel 82092-AA reg and bit definitions
210  */
211 #define	PCIC_82092_PCICON	0x40	/* PCI configuration control */
212 #define	PCIC_82092_PCICLK_25MHZ	0x01	/* 25MHz PCI clock */
213 #define	PCIC_82092_SLOT_CONFIG	0x06	/* config mask */
214 #define	PCIC_82092_2_SOCKETS	0x00	/* 2 sockets */
215 #define	PCIC_82092_1_SOCKET	0x02	/* 1 socket + IDE */
216 #define	PCIC_82092_4_SOCKETS	0x04	/* 4 sockets + IDE */
217 #define	PCIC_82092_EN_TIMING	0x20	/* enhanced memory window timing */
218 #define	PCIC_82092_PWB		0x08	/* Post Write Buffering */
219 #define	PCIC_82092_RPFB		0x10	/* Read Prefetch Buffering */
220 #define	PCIC_82092_PPIRR	0x50	/* interrupt routing register */
221 #define	PCIC_82092_SMI_CTL(sock, state)	(state << (sock * 2))
222 #define	PCIC_82092_IRQ_CTL(sock, state)	(state << ((sock * 2) + 1))
223 #define	PCIC_82092_CTL_SMI	0x01
224 #define	PCIC_82092_CTL_IRQ	0x02
225 #define	PCIC_82092_INT_DISABLE	0x00
226 #define	PCIC_82092_INT_ENABLE	0x01
227 #define	PCIC_82092_CPAGE	0x26	/* CPAGE register */
228 
229 /*
230  * identification and revision register
231  */
232 #define	PCIC_REV_ID_MASK	0xc0
233 #define	PCIC_REV_ID_IO		0x00
234 #define	PCIC_REV_ID_MEM		0x40
235 #define	PCIC_REV_ID_BOTH	0x80
236 
237 /*
238  * interface status register bit definitions
239  */
240 #define	PCIC_ISTAT_CD_MASK	0xC /* card detect mask */
241 #define	PCIC_CD_PRESENT_OK	0xC /* card is present and fully seated */
242 #define	PCIC_CD_NOTPRESENT	0x0 /* card not present */
243 #define	PCIC_CD_NOTSEATED_1	0x8 /* card not fully seated */
244 #define	PCIC_CD1		0x8
245 #define	PCIC_CD_NOTSEATED_2	0x4 /* card not fully seated */
246 #define	PCIC_CD2		0x4
247 #define	PCIC_WRITE_PROTECT	0x10
248 #define	PCIC_READY		0x20
249 #define	PCIC_POWER_ON		0x40
250 #define	PCIC_VPP_VALID		0x80
251 #define	PCIC_BVD1		0x1
252 #define	PCIC_BVD2		0x2
253 
254 /*
255  * memory register definitions
256  */
257 #define	SYSMEM_LOW(x)		(((uint32_t)(x)>>12)&0xFF)
258 #define	SYSMEM_HIGH(x)		(((uint32_t)(x)>>20)&0xF)
259 #define	SYSMEM_EXT(x)		(((uint32_t)(x)>>24)&0xFF)
260 #define	SYSMEM_WINDOW(x)	(1<<(x))
261 #define	SYSMEM_ZERO_WAIT	0x40 /* zero wait state bit */
262 #define	SYSMEM_DATA_16		0x80 /* 16 bit memory bit */
263 #define	SYSMEM_MEM16		0x20 /* 16 bit memory in window enable */
264 #define	SYSMEM_CLTIMER_SET_0	0x00
265 #define	SYSMEM_CLTIMER_SET_1	0x80
266 
267 #define	SYSMEM_82092_600NS	0x0110
268 #define	SYSMEM_82092_250NS	0x0101
269 #define	SYSMEM_82092_200NS	0x0100
270 #define	SYSMEM_82092_150NS	0x0011
271 #define	SYSMEM_82092_100NS	0x0010
272 #define	SYSMEM_82092_80NS	0x0001
273 
274 #define	DEFAULT_AM_ADDR		0xd0000
275 
276 #define	CARDMEM_REG_ACTIVE	0x40
277 #define	CARDMEM_WRITE_PROTECT	0x80
278 
279 #define	CARDMEM_LOW(x)		(((uint32_t)((x))>>12)&0xFF)
280 #define	CARDMEM_HIGH(x)		(((uint32_t)((x))>>20)&0x3F)
281 
282 #define	POWER_CARD_ENABLE	0x10
283 #define	POWER_3VCARD_ENABLE	0x18
284 #define	POWER_OUTPUT_ENABLE	0x80
285 #define	POWER_VPP_VCC_ENABLE	0x01
286 #define	POWER_VPP_12V_ENABLE	0x02
287 
288 /* interrupt register definitions */
289 #define	PCIC_INTR_ENABLE	0x10
290 #define	PCIC_IO_CARD		0x20
291 #define	PCIC_RESET		0x40
292 #define	PCIC_INTR_MASK		0x0f
293 
294 /* card status change register definitions */
295 #define	PCIC_CD_DETECT		0x08
296 #define	PCIC_RD_DETECT		0x04
297 #define	PCIC_BW_DETECT		0x02
298 #define	PCIC_BD_DETECT		0x01
299 #define	PCIC_CHANGE_MASK	0x0f
300 
301 /* card status change interrupt register definitions */
302 #define	PCIC_CD_ENABLE		0x08 /* card detect enable */
303 #define	PCIC_RD_ENABLE		0x04 /* ready change enable */
304 #define	PCIC_BW_ENABLE		0x02 /* battery warning enable */
305 #define	PCIC_BD_ENABLE		0x01 /* battery deat enable */
306 #define	PCIC_GPI_CHANGE		0x10 /* general purpose interrupt */
307 #define	PCIC_CHANGE_DEFAULT	(PCIC_CD_ENABLE|PCIC_RD_ENABLE|\
308 					PCIC_BW_ENABLE|PCIC_BD_ENABLE)
309 
310 /* card detect change register */
311 #define	PCIC_GPI_ENABLE		0x04
312 #define	PCIC_GPI_TRANSITION	0x08
313 #define	PCIC_16MDI		0x01
314 #define	PCIC_SOFT_CD_INTR	0x20
315 
316 /* misc control 1 */
317 #define	PCIC_MC_5VDETECT	0x01
318 #define	PCIC_MC_3VCC		0x02
319 #define	PCIC_MC_PULSE_SMI	0x04
320 #define	PCIC_MC_PULSE_IRQ	0x08
321 #define	PCIC_MC_SPEAKER_ENB	0x10
322 #define	PCIC_MC_INPACK_ENB 	0x80
323 
324 /* global control registers definitions */
325 #define	PCIC_GC_POWERDOWN	0x01
326 #define	PCIC_GC_LEVELMODE	0x02
327 #define	PCIC_GC_CSC_WRITE	0x04
328 #define	PCIC_GC_IRQ1_PULSE	0x08
329 
330 /* misc control 2 */
331 #define	PCIC_MC_BYPASS_FS	0x01
332 #define	PCIC_MC_LOWPOWER	0x02
333 #define	PCIC_MC_SUSPEND 	0x04
334 #define	PCIC_5V_CORE		0x08
335 #define	PCIC_LED_ENABLE		0x10
336 #define	PCIC_THREESTATE		0x20
337 #define	PCIC_CL_DMA		0x40
338 #define	PCIC_IRQ15_RI_OUT	0x80
339 
340 /* chip info register (Cirrus) definitions */
341 #define	PCIC_CI_ID	0xc0
342 #define	PCIC_CI_SLOTS	0x20
343 
344 /* Vadem unique registers */
345 #define	PCIC_VADEM_P1	0x0E
346 #define	PCIC_VADEM_P2	0x37
347 
348 #define	PCIC_VG_VSENSE	0x1f
349 #define	PCIC_VG_VSELECT	0x2f
350 #define	PCIC_VG_CONTROL	0x38
351 #define	PCIC_VG_TIMER	0x39
352 #define	PCIC_VG_DMA	0x3A
353 #define	PCIC_VG_EXT_A	0x3C
354 #define	PCIC_VG_STATUS	0x3E
355 
356 /* Vadem DMA Register */
357 #define	PCIC_V_DMAWSB	0x04
358 #define	PCIC_V_VADEMREV	0x40
359 #define	PCIC_V_UNLOCK	0x80
360 
361 /* Vadem identification register */
362 #define	PCIC_VADEM_D3	0x8
363 #define	PCIC_VADEM_365	0x9
364 #define	PCIC_VADEM_465	0x8
365 #define	PCIC_VADEM_468	0xB
366 #define	PCIC_VADEM_469	0xC
367 
368 /* Vadem Voltage Select */
369 #define	PCIC_VSEL_EXTENDED	0x10 /* extended mode */
370 #define	PCIC_VSEL_BUSSEL	0x20 /* extended buffers on ISA */
371 
372 /* Vadem Control Register */
373 #define	PCIC_VC_DELAYENABLE	0x10
374 
375 /* Vadem Extended Mode Register A */
376 #define	PCIC_VEXT_CABLEMODE	0x08 /* enable external cable */
377 
378 #define	PCIC_YENTA_MEM_PAGE	0x40 /* yenta defined extended address byte */
379 
380 /* Ricoh Specific Registers */
381 #define	PCIC_RF_CHIP_IDENT	0x3A
382 #define	PCIC_RF_296		0x32
383 #define	PCIC_RF_396		0xB2
384 #define	PCIC_RF_MEM_PAGE	PCIC_YENTA_MEM_PAGE
385 
386 /* O2 Micro Specific registers */
387 #define	PCIC_CENTDMA	0x3C
388 #define	PCIC_MULTIFUNC	0x8C
389 #define	PCIC_O2_CTRL1	0xD0
390 #define	PCIC_O2_CTRL2	0xD4
391 
392 /* Texas Instruments specific Registers */
393 #define	PCIC_INTLINE_REG	0x3C
394 #define	PCIC_INTPIN_REG		0x3D
395 #define	PCIC_BRIDGE_CTL_REG	0x3e
396 #define	PCIC_FUN_INT_MOD_ISA	0x80
397 
398 /* for PCI1420 chip */
399 #define	PCIC_BRDGCTL_INTR_MASK	0x80
400 #define	PCIC_GPIO0_REG		0x88
401 #define	PCIC_GPIO1_REG		0x89
402 #define	PCIC_GPIO2_REG		0x8A
403 #define	PCIC_GPIO3_REG		0x8B
404 
405 #define	PCIC_MFROUTE_REG	0x8c
406 #define	PCIC_MFUNC0_MASK	0xF
407 #define	PCIC_MFUNC0_INTA	0x2
408 
409 #define	PCIC_DIAG_REG		0x93
410 #define	PCIC_GPIO_FMASK		0xC0
411 #define	PCIC_GPIO_INTENBL	0x10
412 #define	PCIC_GPIO_DELTA		0x08
413 #define	PCIC_GPIO_DOUT		0x02
414 #define	PCIC_GPIO_DIN		0x01
415 #define	PCIC_GPIO_FOUTPUT	0xC0
416 #define	PCIC_GPIO_FINPUT	0x80
417 #define	PCIC_GPIO2_IS_PCILOCK	0x00
418 #define	PCIC_GPIO3_IS_INTA	0x00
419 #define	PCIC_TI_WINDOW_PAGE	0x3C /* legacy */
420 #define	PCIC_TI_WINDOW_PAGE_PCI	0x40
421 
422 #define	PCIC_DIAG_REG		0x93 /* Diagnostic Register */
423 /* for PCI1225 chip */
424 #define	PCIC_DIAG_CSC		0x20 /* CSC Interrupt Routing Control */
425 /* for PCI1221 and PCI1225 chips */
426 #define	PCIC_DIAG_ASYNC		0x01 /* Async. interrupt enable */
427 
428 #define	PCIC_DEVCTL_REG		0x92 /* Device Control Register */
429 #define	PCIC_DEVCTL_INTR_MASK	0x06 /* to mask out mode */
430 #define	PCIC_DEVCTL_INTR_PCI	0x00 /* PCI style interrupts */
431 #define	PCIC_DEVCTL_INTR_ISA	0x02 /* ISA style interrupts */
432 #define	PCIC_DEVCTL_INTR_SER	0x04 /* serialize IRQ scheme */
433 #define	PCIC_DEVCTL_INTR_RSVD	0x06 /* reserved */
434 /* for PCI1221 and PCI1225 chips */
435 #define	PCIC_DEVCTL_3VCAPABLE	0x40 /* 3V socket capable force */
436 #define	PCIC_DEVCTL_INTR_DFLT	0x06 /* default interrupt mode */
437 
438 #define	PCIC_CRDCTL_REG		0x91 /* Card Control Register */
439 #define	PCIC_CRDCTL_RIENABLE    0x80 /* Ring indicate enable on TI1250a */
440 #define	PCIC_CRDCTL_ZVENABLE    0x40 /* Z buffer enable on TI1250a */
441 #define	PCIC_CRDCTL_PCIINTR	0x20 /* use PCI INT A/B */
442 #define	PCIC_CRDCTL_PCICSC	0x10 /* PCI intr for status */
443 #define	PCIC_CRDCTL_PCIFUNC	0x08 /* use PCI intr for cards */
444 #define	PCIC_CRDCTL_SPKR_ENBL	0x02 /* Enable speaker plumbing */
445 #define	PCIC_CRDCTL_IFG		0x01 /* card interrupt flag */
446 
447 #define	PCIC_SYSCTL_REG		0x80 /* System Control Register */
448 #define	PCIC_SYSCTL_INTRTIE	0x20 /* tie INTA and INTB */
449 
450 /* for Toshiba chips */
451 #define	PCIC_TOSHIBA_SLOT_CTL_REG	0xa0 /* slot control register */
452 #define	PCIC_TOSHIBA_SCR_SLOTON		0x80
453 #define	PCIC_TOSHIBA_SCR_SLOTEN		0x40
454 #define	PCIC_TOSHIBA_SCR_PRT_MASK	0xc
455 #define	PCIC_TOSHIBA_SCR_PRT_3E0	0x0
456 #define	PCIC_TOSHIBA_SCR_PRT_3E2	0x4
457 #define	PCIC_TOSHIBA_SCR_PRT_3E4	0x8
458 #define	PCIC_TOSHIBA_SCR_PRT_3E6	0xc
459 #define	PCIC_TOSHIBA_INTR_CTL_REG	0xa1 /* interrupt control register */
460 #define	PCIC_TOSHIBA_ICR_PIN_MASK	0x30
461 #define	PCIC_TOSHIBA_ICR_PIN_DISEN	0x0
462 #define	PCIC_TOSHIBA_ICR_PIN_INTA	0x10
463 #define	PCIC_TOSHIBA_ICR_PIN_INTB	0x20
464 #define	PCIC_TOSHIBA_ICR_MOD_CSC	0x4 /* CSC interrupt mode */
465 #define	PCIC_TOSHIBA_ICR_MOD_FUN	0x2 /* Funtional interrupt mode */
466 #define	PCIC_TOSHIBA_ICR_SRC		0x1 /* INTA or IRQ */
467 
468 /* for Ricoh chips */
469 #define	PCIC_RICOH_MISC_CTL	0x82
470 #define	PCIC_RICOH_SIRQ_EN	0x80	/* serialized IRQ */
471 #define	PCIC_RICOH_MISC_CTL_2	0xa0	/* ricoh */
472 #define	PCIC_RICOH_CSC_INT_MOD	0x80	/* csc to ISA */
473 #define	PCIC_RICOH_FUN_INT_MOD	0x40	/* cint to ISA */
474 
475 /* for o2micro */
476 #define	PCIC_O2MICRO_MISC_CTL	0x28
477 #define	PCIC_O2MICRO_INT_MOD_MASK	0x300
478 #define	PCIC_O2MICRO_INT_MOD_PCI	0x300
479 #define	PCIC_O2MICRO_ISA_LEGACY		0x800
480 /*  */
481 
482 /* SMC 34C90 specific registers */
483 #define	PCIC_SMC_MEM_PAGE	0x40
484 
485 /* available interrupts and interrupt mask */
486 #define	PCIC_IRQ(irq)	(1 << (irq))
487 #define	PCIC_IRQ03	PCIC_IRQ(3)
488 #define	PCIC_IRQ04	PCIC_IRQ(4)
489 #define	PCIC_IRQ05	PCIC_IRQ(5)
490 #define	PCIC_IRQ07	PCIC_IRQ(7)
491 #define	PCIC_IRQ09	PCIC_IRQ(9)
492 #define	PCIC_IRQ10	PCIC_IRQ(10)
493 #define	PCIC_IRQ11	PCIC_IRQ(11)
494 #define	PCIC_IRQ12	PCIC_IRQ(12)
495 #define	PCIC_IRQ14	PCIC_IRQ(14)
496 #define	PCIC_IRQ15	PCIC_IRQ(15)
497 
498 #define	PCIC_AVAIL_IRQS	(PCIC_IRQ03|PCIC_IRQ04|PCIC_IRQ05|PCIC_IRQ07|\
499 				PCIC_IRQ09|PCIC_IRQ10|PCIC_IRQ11|PCIC_IRQ12|\
500 				PCIC_IRQ14|PCIC_IRQ15)
501 
502 /* page size used for window mapping and memory resource page size */
503 #define	PCIC_PAGE	4096
504 
505 /* used in I/O window mapping */
506 #define	HIGH_BYTE(x)	(uchar_t)((((ushort_t)(x)) >> 8) & 0xFF)
507 #define	LOW_BYTE(x)	(uchar_t)(((ushort_t)(x)) & 0xFF)
508 #define	PCIC_IO_0_MASK	0x0f
509 #define	PCIC_IO_1_MASK	0xf0
510 #define	IOMEM_WINDOW(x)	(1<<((x)+6))
511 
512 #define	IOMEM_16BIT		0x01
513 #define	IOMEM_IOCS16		0x02
514 #define	IOMEM_ZERO_WAIT		0x04
515 #define	IOMEM_CLTIMER_SET_0	0x00	/* CL timer set selection */
516 #define	IOMEM_CLTIMER_SET_1	0x08	/* CL timer set selection */
517 #define	IOMEM_WAIT16		0x08
518 #define	IOMEM_SETWIN(w, x)	((x) << ((w)*4))
519 
520 #define	IOMEM_FIRST	0	/* First I/O address */
521 #define	IOMEM_LAST	0xFFFF	/* Last I/O address */
522 #define	IOMEM_MIN	1	/* minimum I/O window size */
523 #define	IOMEM_MAX	0x10000	/* maximum I/O window size */
524 #define	IOMEM_GRAN	1	/* granularity of request */
525 #define	IOMEM_DECODE	16	/* number of address lines decoded */
526 
527 #define	MEM_FIRST	0x10000	/* first memory address */
528 #define	MEM_LAST	0xFFFFF	/* last memory address */
529 #define	MEM_MIN		PCIC_PAGE /* minimum window size */
530 #define	MEM_MAX		0x10000	/* maximum window size */
531 #define	PAGE_SHIFT	12	/* bits to shift */
532 
533 #define	SYSCLK		120	/* sysclk min time (ns) */
534 #define	MEM_SPEED_MIN	(SYSCLK*2)
535 #define	MEM_SPEED_MAX	(SYSCLK*6)
536 
537 /* CardBus (Yenta) specific values */
538 #define	CB_R2_OFFSET	0x800	/* R2 is always at offset 0x800 */
539 #define	CB_CLEXT_OFFSET	0x900	/* Cirrus Logic extended at offset 0x900 */
540 #define	CB_CB_OFFSET	0x00	/* Cardbus registers at offset 0 */
541 
542 /* Cardbus registers in TI 1250A/Cirrus 6832 and probably others.  */
543 /* Register offsets (these are 32 bit registers).  */
544 #define	CB_STATUS_EVENT		0x00
545 #define	CB_STATUS_MASK		0x04
546 #define	CB_PRESENT_STATE	0x08
547 #define	CB_EVENT_FORCE		0x0c
548 #define	CB_CONTROL		0x10
549 
550 /* TI1420 */
551 #define	CB_SOCKET_POWER		0x20
552 
553 /* Cardbus registers in 02 0Z6912.  */
554 #define	CB_SZVCTRL		0x20
555 #define	CB_SIMDCTRL		0x24
556 #define	CB_MISCCTRL		0x28
557 
558 /* Register bit definitions.  */
559 #define	BYTE_3(x)		((x)<<24)
560 #define	BYTE_2(x)		((x)<<16)
561 #define	BYTE_1(x)		((x)<<8)
562 #define	BYTE_0(x)		(x)
563 
564 #define	CB_SE_POWER_CYCLE	BYTE_0(0x08)
565 #define	CB_SE_CCDMASK		BYTE_0(0x06)
566 #define	CB_SE_CCD2		BYTE_0(0x04)
567 #define	CB_SE_CCD1		BYTE_0(0x02)
568 #define	CB_SE_CSTSCHG		BYTE_0(0x01)
569 
570 #define	CB_SM_POWER_CYCLE	BYTE_0(0x08)
571 #define	CB_SM_CCDMASK		BYTE_0(0x06)
572 #define	CB_SM_CCD2		BYTE_0(0x04)
573 #define	CB_SM_CCD1		BYTE_0(0x02)
574 #define	CB_SM_CSTSCHG		BYTE_0(0x01)
575 
576 #define	CB_PS_CSTSCHG		BYTE_0(0x01)
577 #define	CB_PS_CCDMASK		BYTE_0(0x06)
578 #define	CB_PS_NCCD1		BYTE_0(0x02)
579 #define	CB_PS_NCCD2		BYTE_0(0x04)
580 #define	CB_PS_POWER_CYCLE	BYTE_0(0x08)
581 #define	CB_PS_16BITCARD		BYTE_0(0x10)
582 #define	CB_PS_CBCARD		BYTE_0(0x20)
583 #define	CB_PS_INTERRUPT		BYTE_0(0x40)
584 #define	CB_PS_NOTACARD		BYTE_0(0x80)
585 
586 #define	CB_PS_DATALOST		BYTE_1(0x01)
587 #define	CB_PS_BADVCC		BYTE_1(0x02)
588 #define	CB_PS_50VCARD		BYTE_1(0x04)
589 #define	CB_PS_33VCARD		BYTE_1(0x08)
590 #define	CB_PS_XVCARD		BYTE_1(0x10)
591 #define	CB_PS_YVCARD		BYTE_1(0x20)
592 
593 #define	CB_PS_50VSOCKET		BYTE_3(0x10)
594 #define	CB_PS_33VSOCKET		BYTE_3(0x20)
595 #define	CB_PS_XVSOCKET		BYTE_3(0x40)
596 #define	CB_PS_YVSOCKET		BYTE_3(0x80)
597 
598 #define	CB_EF_CSTSCHG		BYTE_0(0x01)
599 #define	CB_EF_CCD1		BYTE_0(0x02)
600 #define	CB_EF_CCD2		BYTE_0(0x04)
601 #define	CB_EF_POWER_CYCLE	BYTE_0(0x08)
602 #define	CB_EF_16BITCARD		BYTE_0(0x10)
603 #define	CB_EF_CBCARD		BYTE_0(0x20)
604 #define	CB_EF_NOTACARD		BYTE_0(0x80)
605 
606 #define	CB_EF_DATALOST		BYTE_1(0x01)
607 #define	CB_EF_BADVCC		BYTE_1(0x02)
608 #define	CB_EF_50V		BYTE_1(0x04)
609 #define	CB_EF_33V		BYTE_1(0x08)
610 #define	CB_EF_XV		BYTE_1(0x10)
611 #define	CB_EF_YV		BYTE_1(0x20)
612 #define	CB_EF_CVTEST		BYTE_1(0x40)
613 
614 #define	CB_C_VPPMASK		BYTE_0(0x07)
615 #define	CB_C_VCCMASK		BYTE_0(0x70)
616 
617 #define	CB_C_VPP0V		BYTE_0(0x00)
618 #define	CB_C_VPP12V		BYTE_0(0x01)
619 #define	CB_C_VPPVCC		BYTE_0(0x03)
620 
621 #define	CB_C_VCC0V		BYTE_0(0x00)
622 #define	CB_C_VCC50V		BYTE_0(0x20)
623 #define	CB_C_VCC33V		BYTE_0(0x30)
624 
625 #ifdef	__cplusplus
626 }
627 #endif
628 
629 #endif	/* _PCIC_REG_H */
630