xref: /linux/drivers/gpu/drm/i2c/ch7006_mode.c (revision 4b4193256c8d3bc3a5397b5cd9494c2ad386317d)
1 /*
2  * Copyright (C) 2009 Francisco Jerez.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining
6  * a copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sublicense, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the
14  * next paragraph) shall be included in all copies or substantial
15  * portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24  *
25  */
26 
27 #include "ch7006_priv.h"
28 
29 const char * const ch7006_tv_norm_names[] = {
30 	[TV_NORM_PAL] = "PAL",
31 	[TV_NORM_PAL_M] = "PAL-M",
32 	[TV_NORM_PAL_N] = "PAL-N",
33 	[TV_NORM_PAL_NC] = "PAL-Nc",
34 	[TV_NORM_PAL_60] = "PAL-60",
35 	[TV_NORM_NTSC_M] = "NTSC-M",
36 	[TV_NORM_NTSC_J] = "NTSC-J",
37 };
38 
39 #define NTSC_LIKE_TIMINGS .vrefresh = 60 * fixed1/1.001,		\
40 		.vdisplay = 480,					\
41 		.vtotal = 525,						\
42 		.hvirtual = 660
43 
44 #define PAL_LIKE_TIMINGS .vrefresh = 50 * fixed1,		\
45 		.vdisplay = 576,				\
46 		.vtotal = 625,					\
47 		.hvirtual = 810
48 
49 const struct ch7006_tv_norm_info ch7006_tv_norms[] = {
50 	[TV_NORM_NTSC_M] = {
51 		NTSC_LIKE_TIMINGS,
52 		.black_level = 0.339 * fixed1,
53 		.subc_freq = 3579545 * fixed1,
54 		.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, NTSC),
55 		.voffset = 0,
56 	},
57 	[TV_NORM_NTSC_J] = {
58 		NTSC_LIKE_TIMINGS,
59 		.black_level = 0.286 * fixed1,
60 		.subc_freq = 3579545 * fixed1,
61 		.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, NTSC_J),
62 		.voffset = 0,
63 	},
64 	[TV_NORM_PAL] = {
65 		PAL_LIKE_TIMINGS,
66 		.black_level = 0.3 * fixed1,
67 		.subc_freq = 4433618.75 * fixed1,
68 		.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL),
69 		.voffset = 0,
70 	},
71 	[TV_NORM_PAL_M] = {
72 		NTSC_LIKE_TIMINGS,
73 		.black_level = 0.339 * fixed1,
74 		.subc_freq = 3575611.433 * fixed1,
75 		.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL_M),
76 		.voffset = 16,
77 	},
78 
79 	/* The following modes seem to work right but they're
80 	 * undocumented */
81 
82 	[TV_NORM_PAL_N] = {
83 		PAL_LIKE_TIMINGS,
84 		.black_level = 0.339 * fixed1,
85 		.subc_freq = 4433618.75 * fixed1,
86 		.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL),
87 		.voffset = 0,
88 	},
89 	[TV_NORM_PAL_NC] = {
90 		PAL_LIKE_TIMINGS,
91 		.black_level = 0.3 * fixed1,
92 		.subc_freq = 3582056.25 * fixed1,
93 		.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL),
94 		.voffset = 0,
95 	},
96 	[TV_NORM_PAL_60] = {
97 		NTSC_LIKE_TIMINGS,
98 		.black_level = 0.3 * fixed1,
99 		.subc_freq = 4433618.75 * fixed1,
100 		.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL_M),
101 		.voffset = 16,
102 	},
103 };
104 
105 #define __MODE(f, hd, vd, ht, vt, hsynp, vsynp,				\
106 	       subc, scale, scale_mask, norm_mask, e_hd, e_vd) {	\
107 		.mode = {						\
108 			.name = #hd "x" #vd,				\
109 			.status = 0,					\
110 			.type = DRM_MODE_TYPE_DRIVER,			\
111 			.clock = f,					\
112 			.hdisplay = hd,					\
113 			.hsync_start = e_hd + 16,			\
114 			.hsync_end = e_hd + 80,				\
115 			.htotal = ht,					\
116 			.hskew = 0,					\
117 			.vdisplay = vd,					\
118 			.vsync_start = vd + 10,				\
119 			.vsync_end = vd + 26,				\
120 			.vtotal = vt,					\
121 			.vscan = 0,					\
122 			.flags = DRM_MODE_FLAG_##hsynp##HSYNC |		\
123 				DRM_MODE_FLAG_##vsynp##VSYNC,		\
124 		},							\
125 		.enc_hdisp = e_hd,					\
126 		.enc_vdisp = e_vd,					\
127 		.subc_coeff = subc * fixed1,				\
128 		.dispmode = bitfs(CH7006_DISPMODE_SCALING_RATIO, scale) | \
129 			    bitfs(CH7006_DISPMODE_INPUT_RES, e_hd##x##e_vd), \
130 		.valid_scales = scale_mask,				\
131 		.valid_norms = norm_mask				\
132 	 }
133 
134 #define MODE(f, hd, vd, ht, vt, hsynp, vsynp,				\
135 	     subc, scale, scale_mask, norm_mask)			\
136 	__MODE(f, hd, vd, ht, vt, hsynp, vsynp, subc, scale,		\
137 	       scale_mask, norm_mask, hd, vd)
138 
139 #define NTSC_LIKE (1 << TV_NORM_NTSC_M | 1 << TV_NORM_NTSC_J |		\
140 		   1 << TV_NORM_PAL_M | 1 << TV_NORM_PAL_60)
141 
142 #define PAL_LIKE (1 << TV_NORM_PAL | 1 << TV_NORM_PAL_N | 1 << TV_NORM_PAL_NC)
143 
144 const struct ch7006_mode ch7006_modes[] = {
145 	MODE(21000, 512, 384, 840, 500, N, N, 181.797557582, 5_4, 0x6, PAL_LIKE),
146 	MODE(26250, 512, 384, 840, 625, N, N, 145.438046066, 1_1, 0x1, PAL_LIKE),
147 	MODE(20140, 512, 384, 800, 420, N, N, 213.257083791, 5_4, 0x4, NTSC_LIKE),
148 	MODE(24671, 512, 384, 784, 525, N, N, 174.0874153, 1_1, 0x3, NTSC_LIKE),
149 	MODE(28125, 720, 400, 1125, 500, N, N, 135.742176298, 5_4, 0x6, PAL_LIKE),
150 	MODE(34875, 720, 400, 1116, 625, N, N, 109.469496898, 1_1, 0x1, PAL_LIKE),
151 	MODE(23790, 720, 400, 945, 420, N, N, 160.475642016, 5_4, 0x4, NTSC_LIKE),
152 	MODE(29455, 720, 400, 936, 525, N, N, 129.614941843, 1_1, 0x3, NTSC_LIKE),
153 	MODE(25000, 640, 400, 1000, 500, N, N, 152.709948279, 5_4, 0x6, PAL_LIKE),
154 	MODE(31500, 640, 400, 1008, 625, N, N, 121.198371646, 1_1, 0x1, PAL_LIKE),
155 	MODE(21147, 640, 400, 840, 420, N, N, 180.535097338, 5_4, 0x4, NTSC_LIKE),
156 	MODE(26434, 640, 400, 840, 525, N, N, 144.42807787, 1_1, 0x2, NTSC_LIKE),
157 	MODE(30210, 640, 400, 840, 600, N, N, 126.374568276, 7_8, 0x1, NTSC_LIKE),
158 	MODE(21000, 640, 480, 840, 500, N, N, 181.797557582, 5_4, 0x4, PAL_LIKE),
159 	MODE(26250, 640, 480, 840, 625, N, N, 145.438046066, 1_1, 0x2, PAL_LIKE),
160 	MODE(31500, 640, 480, 840, 750, N, N, 121.198371646, 5_6, 0x1, PAL_LIKE),
161 	MODE(24671, 640, 480, 784, 525, N, N, 174.0874153, 1_1, 0x4, NTSC_LIKE),
162 	MODE(28196, 640, 480, 784, 600, N, N, 152.326488422, 7_8, 0x2, NTSC_LIKE),
163 	MODE(30210, 640, 480, 800, 630, N, N, 142.171389101, 5_6, 0x1, NTSC_LIKE),
164 	__MODE(29500, 720, 576, 944, 625, P, P, 145.592111636, 1_1, 0x7, PAL_LIKE, 800, 600),
165 	MODE(36000, 800, 600, 960, 750, P, P, 119.304647022, 5_6, 0x6, PAL_LIKE),
166 	MODE(39000, 800, 600, 936, 836, P, P, 110.127366499, 3_4, 0x1, PAL_LIKE),
167 	MODE(39273, 800, 600, 1040, 630, P, P, 145.816809399, 5_6, 0x4, NTSC_LIKE),
168 	MODE(43636, 800, 600, 1040, 700, P, P, 131.235128487, 3_4, 0x2, NTSC_LIKE),
169 	MODE(47832, 800, 600, 1064, 750, P, P, 119.723275165, 7_10, 0x1, NTSC_LIKE),
170 	{}
171 };
172 
ch7006_lookup_mode(struct drm_encoder * encoder,const struct drm_display_mode * drm_mode)173 const struct ch7006_mode *ch7006_lookup_mode(struct drm_encoder *encoder,
174 					     const struct drm_display_mode *drm_mode)
175 {
176 	struct ch7006_priv *priv = to_ch7006_priv(encoder);
177 	const struct ch7006_mode *mode;
178 
179 	for (mode = ch7006_modes; mode->mode.clock; mode++) {
180 
181 		if (~mode->valid_norms & 1<<priv->norm)
182 			continue;
183 
184 		if (mode->mode.hdisplay != drm_mode->hdisplay ||
185 		    mode->mode.vdisplay != drm_mode->vdisplay ||
186 		    mode->mode.vtotal != drm_mode->vtotal ||
187 		    mode->mode.htotal != drm_mode->htotal ||
188 		    mode->mode.clock != drm_mode->clock)
189 			continue;
190 
191 		return mode;
192 	}
193 
194 	return NULL;
195 }
196 
197 /* Some common HW state calculation code */
198 
ch7006_setup_levels(struct drm_encoder * encoder)199 void ch7006_setup_levels(struct drm_encoder *encoder)
200 {
201 	struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
202 	struct ch7006_priv *priv = to_ch7006_priv(encoder);
203 	uint8_t *regs = priv->state.regs;
204 	const struct ch7006_tv_norm_info *norm = &ch7006_tv_norms[priv->norm];
205 	int gain;
206 	int black_level;
207 
208 	/* Set DAC_GAIN if the voltage drop between white and black is
209 	 * high enough. */
210 	if (norm->black_level < 339*fixed1/1000) {
211 		gain = 76;
212 
213 		regs[CH7006_INPUT_FORMAT] |= CH7006_INPUT_FORMAT_DAC_GAIN;
214 	} else {
215 		gain = 71;
216 
217 		regs[CH7006_INPUT_FORMAT] &= ~CH7006_INPUT_FORMAT_DAC_GAIN;
218 	}
219 
220 	black_level = round_fixed(norm->black_level*26625)/gain;
221 
222 	/* Correct it with the specified brightness. */
223 	black_level = interpolate(90, black_level, 208, priv->brightness);
224 
225 	regs[CH7006_BLACK_LEVEL] = bitf(CH7006_BLACK_LEVEL_0, black_level);
226 
227 	ch7006_dbg(client, "black level: %d\n", black_level);
228 }
229 
ch7006_setup_subcarrier(struct drm_encoder * encoder)230 void ch7006_setup_subcarrier(struct drm_encoder *encoder)
231 {
232 	struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
233 	struct ch7006_priv *priv = to_ch7006_priv(encoder);
234 	struct ch7006_state *state = &priv->state;
235 	const struct ch7006_tv_norm_info *norm = &ch7006_tv_norms[priv->norm];
236 	const struct ch7006_mode *mode = priv->mode;
237 	uint32_t subc_inc;
238 
239 	subc_inc = round_fixed((mode->subc_coeff >> 8)
240 			       * (norm->subc_freq >> 24));
241 
242 	setbitf(state, CH7006_SUBC_INC0, 28, subc_inc);
243 	setbitf(state, CH7006_SUBC_INC1, 24, subc_inc);
244 	setbitf(state, CH7006_SUBC_INC2, 20, subc_inc);
245 	setbitf(state, CH7006_SUBC_INC3, 16, subc_inc);
246 	setbitf(state, CH7006_SUBC_INC4, 12, subc_inc);
247 	setbitf(state, CH7006_SUBC_INC5, 8, subc_inc);
248 	setbitf(state, CH7006_SUBC_INC6, 4, subc_inc);
249 	setbitf(state, CH7006_SUBC_INC7, 0, subc_inc);
250 
251 	ch7006_dbg(client, "subcarrier inc: %u\n", subc_inc);
252 }
253 
ch7006_setup_pll(struct drm_encoder * encoder)254 void ch7006_setup_pll(struct drm_encoder *encoder)
255 {
256 	struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
257 	struct ch7006_priv *priv = to_ch7006_priv(encoder);
258 	uint8_t *regs = priv->state.regs;
259 	const struct ch7006_mode *mode = priv->mode;
260 	int n, best_n = 0;
261 	int m, best_m = 0;
262 	int freq, best_freq = 0;
263 
264 	for (n = 0; n < CH7006_MAXN; n++) {
265 		for (m = 0; m < CH7006_MAXM; m++) {
266 			freq = CH7006_FREQ0*(n+2)/(m+2);
267 
268 			if (abs(freq - mode->mode.clock) <
269 			    abs(best_freq - mode->mode.clock)) {
270 				best_freq = freq;
271 				best_n = n;
272 				best_m = m;
273 			}
274 		}
275 	}
276 
277 	regs[CH7006_PLLOV] = bitf(CH7006_PLLOV_N_8, best_n) |
278 		bitf(CH7006_PLLOV_M_8, best_m);
279 
280 	regs[CH7006_PLLM] = bitf(CH7006_PLLM_0, best_m);
281 	regs[CH7006_PLLN] = bitf(CH7006_PLLN_0, best_n);
282 
283 	if (best_n < 108)
284 		regs[CH7006_PLL_CONTROL] |= CH7006_PLL_CONTROL_CAPACITOR;
285 	else
286 		regs[CH7006_PLL_CONTROL] &= ~CH7006_PLL_CONTROL_CAPACITOR;
287 
288 	ch7006_dbg(client, "n=%d m=%d f=%d c=%d\n",
289 		   best_n, best_m, best_freq, best_n < 108);
290 }
291 
ch7006_setup_power_state(struct drm_encoder * encoder)292 void ch7006_setup_power_state(struct drm_encoder *encoder)
293 {
294 	struct ch7006_priv *priv = to_ch7006_priv(encoder);
295 	uint8_t *power = &priv->state.regs[CH7006_POWER];
296 	int subconnector;
297 
298 	subconnector = priv->select_subconnector ? priv->select_subconnector :
299 							priv->subconnector;
300 
301 	*power = CH7006_POWER_RESET;
302 
303 	if (priv->last_dpms == DRM_MODE_DPMS_ON) {
304 		switch (subconnector) {
305 		case DRM_MODE_SUBCONNECTOR_SVIDEO:
306 			*power |= bitfs(CH7006_POWER_LEVEL, CVBS_OFF);
307 			break;
308 		case DRM_MODE_SUBCONNECTOR_Composite:
309 			*power |= bitfs(CH7006_POWER_LEVEL, SVIDEO_OFF);
310 			break;
311 		case DRM_MODE_SUBCONNECTOR_SCART:
312 			*power |= bitfs(CH7006_POWER_LEVEL, NORMAL) |
313 				CH7006_POWER_SCART;
314 			break;
315 		}
316 
317 	} else {
318 		if (priv->chip_version >= 0x20)
319 			*power |= bitfs(CH7006_POWER_LEVEL, FULL_POWER_OFF);
320 		else
321 			*power |= bitfs(CH7006_POWER_LEVEL, POWER_OFF);
322 	}
323 }
324 
ch7006_setup_properties(struct drm_encoder * encoder)325 void ch7006_setup_properties(struct drm_encoder *encoder)
326 {
327 	struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
328 	struct ch7006_priv *priv = to_ch7006_priv(encoder);
329 	struct ch7006_state *state = &priv->state;
330 	const struct ch7006_tv_norm_info *norm = &ch7006_tv_norms[priv->norm];
331 	const struct ch7006_mode *ch_mode = priv->mode;
332 	const struct drm_display_mode *mode = &ch_mode->mode;
333 	uint8_t *regs = state->regs;
334 	int flicker, contrast, hpos, vpos;
335 	uint64_t scale, aspect;
336 
337 	flicker = interpolate(0, 2, 3, priv->flicker);
338 	regs[CH7006_FFILTER] = bitf(CH7006_FFILTER_TEXT, flicker) |
339 		bitf(CH7006_FFILTER_LUMA, flicker) |
340 		bitf(CH7006_FFILTER_CHROMA, 1);
341 
342 	contrast = interpolate(0, 5, 7, priv->contrast);
343 	regs[CH7006_CONTRAST] = bitf(CH7006_CONTRAST_0, contrast);
344 
345 	scale = norm->vtotal*fixed1;
346 	do_div(scale, mode->vtotal);
347 
348 	aspect = ch_mode->enc_hdisp*fixed1;
349 	do_div(aspect, ch_mode->enc_vdisp);
350 
351 	hpos = round_fixed((norm->hvirtual * aspect - mode->hdisplay * scale)
352 			   * priv->hmargin * mode->vtotal) / norm->vtotal / 100 / 4;
353 
354 	setbitf(state, CH7006_POV, HPOS_8, hpos);
355 	setbitf(state, CH7006_HPOS, 0, hpos);
356 
357 	vpos = max(0, norm->vdisplay - round_fixed(mode->vdisplay*scale)
358 		   + norm->voffset) * priv->vmargin / 100 / 2;
359 
360 	setbitf(state, CH7006_POV, VPOS_8, vpos);
361 	setbitf(state, CH7006_VPOS, 0, vpos);
362 
363 	ch7006_dbg(client, "hpos: %d, vpos: %d\n", hpos, vpos);
364 }
365 
366 /* HW access functions */
367 
ch7006_write(struct i2c_client * client,uint8_t addr,uint8_t val)368 void ch7006_write(struct i2c_client *client, uint8_t addr, uint8_t val)
369 {
370 	uint8_t buf[] = {addr, val};
371 	int ret;
372 
373 	ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
374 	if (ret < 0)
375 		ch7006_err(client, "Error %d writing to subaddress 0x%x\n",
376 			   ret, addr);
377 }
378 
ch7006_read(struct i2c_client * client,uint8_t addr)379 uint8_t ch7006_read(struct i2c_client *client, uint8_t addr)
380 {
381 	uint8_t val;
382 	int ret;
383 
384 	ret = i2c_master_send(client, &addr, sizeof(addr));
385 	if (ret < 0)
386 		goto fail;
387 
388 	ret = i2c_master_recv(client, &val, sizeof(val));
389 	if (ret < 0)
390 		goto fail;
391 
392 	return val;
393 
394 fail:
395 	ch7006_err(client, "Error %d reading from subaddress 0x%x\n",
396 		   ret, addr);
397 	return 0;
398 }
399 
ch7006_state_load(struct i2c_client * client,struct ch7006_state * state)400 void ch7006_state_load(struct i2c_client *client,
401 		       struct ch7006_state *state)
402 {
403 	ch7006_load_reg(client, state, CH7006_POWER);
404 
405 	ch7006_load_reg(client, state, CH7006_DISPMODE);
406 	ch7006_load_reg(client, state, CH7006_FFILTER);
407 	ch7006_load_reg(client, state, CH7006_BWIDTH);
408 	ch7006_load_reg(client, state, CH7006_INPUT_FORMAT);
409 	ch7006_load_reg(client, state, CH7006_CLKMODE);
410 	ch7006_load_reg(client, state, CH7006_START_ACTIVE);
411 	ch7006_load_reg(client, state, CH7006_POV);
412 	ch7006_load_reg(client, state, CH7006_BLACK_LEVEL);
413 	ch7006_load_reg(client, state, CH7006_HPOS);
414 	ch7006_load_reg(client, state, CH7006_VPOS);
415 	ch7006_load_reg(client, state, CH7006_INPUT_SYNC);
416 	ch7006_load_reg(client, state, CH7006_DETECT);
417 	ch7006_load_reg(client, state, CH7006_CONTRAST);
418 	ch7006_load_reg(client, state, CH7006_PLLOV);
419 	ch7006_load_reg(client, state, CH7006_PLLM);
420 	ch7006_load_reg(client, state, CH7006_PLLN);
421 	ch7006_load_reg(client, state, CH7006_BCLKOUT);
422 	ch7006_load_reg(client, state, CH7006_SUBC_INC0);
423 	ch7006_load_reg(client, state, CH7006_SUBC_INC1);
424 	ch7006_load_reg(client, state, CH7006_SUBC_INC2);
425 	ch7006_load_reg(client, state, CH7006_SUBC_INC3);
426 	ch7006_load_reg(client, state, CH7006_SUBC_INC4);
427 	ch7006_load_reg(client, state, CH7006_SUBC_INC5);
428 	ch7006_load_reg(client, state, CH7006_SUBC_INC6);
429 	ch7006_load_reg(client, state, CH7006_SUBC_INC7);
430 	ch7006_load_reg(client, state, CH7006_PLL_CONTROL);
431 	ch7006_load_reg(client, state, CH7006_CALC_SUBC_INC0);
432 }
433 
ch7006_state_save(struct i2c_client * client,struct ch7006_state * state)434 void ch7006_state_save(struct i2c_client *client,
435 		       struct ch7006_state *state)
436 {
437 	ch7006_save_reg(client, state, CH7006_POWER);
438 
439 	ch7006_save_reg(client, state, CH7006_DISPMODE);
440 	ch7006_save_reg(client, state, CH7006_FFILTER);
441 	ch7006_save_reg(client, state, CH7006_BWIDTH);
442 	ch7006_save_reg(client, state, CH7006_INPUT_FORMAT);
443 	ch7006_save_reg(client, state, CH7006_CLKMODE);
444 	ch7006_save_reg(client, state, CH7006_START_ACTIVE);
445 	ch7006_save_reg(client, state, CH7006_POV);
446 	ch7006_save_reg(client, state, CH7006_BLACK_LEVEL);
447 	ch7006_save_reg(client, state, CH7006_HPOS);
448 	ch7006_save_reg(client, state, CH7006_VPOS);
449 	ch7006_save_reg(client, state, CH7006_INPUT_SYNC);
450 	ch7006_save_reg(client, state, CH7006_DETECT);
451 	ch7006_save_reg(client, state, CH7006_CONTRAST);
452 	ch7006_save_reg(client, state, CH7006_PLLOV);
453 	ch7006_save_reg(client, state, CH7006_PLLM);
454 	ch7006_save_reg(client, state, CH7006_PLLN);
455 	ch7006_save_reg(client, state, CH7006_BCLKOUT);
456 	ch7006_save_reg(client, state, CH7006_SUBC_INC0);
457 	ch7006_save_reg(client, state, CH7006_SUBC_INC1);
458 	ch7006_save_reg(client, state, CH7006_SUBC_INC2);
459 	ch7006_save_reg(client, state, CH7006_SUBC_INC3);
460 	ch7006_save_reg(client, state, CH7006_SUBC_INC4);
461 	ch7006_save_reg(client, state, CH7006_SUBC_INC5);
462 	ch7006_save_reg(client, state, CH7006_SUBC_INC6);
463 	ch7006_save_reg(client, state, CH7006_SUBC_INC7);
464 	ch7006_save_reg(client, state, CH7006_PLL_CONTROL);
465 	ch7006_save_reg(client, state, CH7006_CALC_SUBC_INC0);
466 
467 	state->regs[CH7006_FFILTER] = (state->regs[CH7006_FFILTER] & 0xf0) |
468 		(state->regs[CH7006_FFILTER] & 0x0c) >> 2 |
469 		(state->regs[CH7006_FFILTER] & 0x03) << 2;
470 }
471