| /freebsd/contrib/llvm-project/llvm/tools/llvm-tapi-diff/ |
| H A D | DiffEngine.cpp | |
| H A D | DiffEngine.h | |
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.h | 32 ArrayRef<MCPhysReg> Order; variable
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder()
|
| H A D | RegAllocGreedy.cpp | 532 AllocationOrder &Order, in tryAssign()
666 const AllocationOrder &Order, in getOrderLimit()
712 AllocationOrder &Order, in tryEvict()
1003 const AllocationOrder &Order) { in calcGlobalSplitCost()
1196 AllocationOrder &Order, in tryRegionSplit()
1230 AllocationOrder &Order, in calculateRegionSplitCostAroundReg()
1307 AllocationOrder &Order, in calculateRegionSplitCost()
1369 AllocationOrder &Order) { in trySplitAroundHintReg()
1429 AllocationOrder &Order, in tryBlockSplit()
1551 AllocationOrder &Order, in tryInstructionSplit()
[all …]
|
| H A D | AllocationOrder.cpp | 34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create() local
|
| H A D | LocalStackSlotAllocation.cpp | 59 unsigned Order; member in __anon7165d95d0111::FrameRef
321 unsigned Order = 0; in insertFrameReferenceRegisters() local
|
| H A D | RegAllocBasic.cpp | 264 auto Order = in selectOrSplit() local
|
| H A D | BreakFalseDeps.cpp | 155 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef() local
|
| H A D | RegAllocEvictionAdvisor.cpp | 332 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate()
|
| H A D | TargetRegisterInfo.cpp | 286 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); in getAllocatableSetForRC() local
466 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
|
| H A D | CriticalAntiDepBreaker.cpp | 398 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXUtilities.h | 128 inline std::string OrderingToString(Ordering Order) { in OrderingToString()
|
| /freebsd/contrib/llvm-project/llvm/lib/Support/ |
| H A D | DynamicLibrary.cpp | 81 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup()
96 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SDNodeDbgValue.h | 150 unsigned Order; variable
245 unsigned Order; variable
|
| H A D | ScheduleDAGSDNodes.cpp | 739 InstrEmitter::VRBaseMapType &VRBaseMap, unsigned Order) { in ProcessSDDbgValues()
787 unsigned Order = N->getIROrder(); in ProcessSourceNode() local
995 unsigned Order = Orders[i].first; in EmitSchedule() local
1041 unsigned Order = InstrOrder.first; in EmitSchedule() local
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 37 std::unique_ptr<MCPhysReg[]> Order; member
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 57 static void addHints(ArrayRef<MCPhysReg> Order, in addHints()
74 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
|
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.h | 596 unsigned Order = 0; // Cache the sort key. member
847 unsigned getRegSetIDAt(unsigned Order) const { in getRegSetIDAt()
851 const RegUnitSet &getRegSetAt(unsigned Order) const { in getRegSetAt()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/Frontend/OpenMP/ |
| H A D | OMPIRBuilder.h | 264 explicit OffloadEntryInfo(OffloadingEntryInfoKinds Kind, unsigned Order, in OffloadEntryInfo()
290 unsigned Order = ~0u; variable
320 explicit OffloadEntryInfoTargetRegion(unsigned Order, Constant *Addr, in OffloadEntryInfoTargetRegion()
410 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, in OffloadEntryInfoDeviceGlobalVar()
413 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, Constant *Addr, in OffloadEntryInfoDeviceGlobalVar()
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | CodeLayout.cpp | 1001 std::vector<uint64_t> Order; in concatChains() local
1368 std::vector<uint64_t> Order; in concatChains() local
1428 double codelayout::calcExtTspScore(ArrayRef<uint64_t> Order, in calcExtTspScore()
1451 SmallVector<uint64_t> Order(NodeSizes.size()); in calcExtTspScore() local
|
| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGAtomic.cpp | 530 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp()
788 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp()
894 llvm::Value *Order = EmitScalarExpr(E->getOrder()); in EmitAtomicExpr() local
2083 llvm::Value *Val, llvm::AtomicOrdering Order, in emitAtomicRMWInst()
|
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 1046 ArrayRef<const Record *> Order = RC.getOrder(); in runMCDesc() local
1082 ArrayRef<const Record *> Order = RC.getOrder(); in runMCDesc() local
1249 ArrayRef<const Record *> Order = RC.getOrder(); in runTargetDesc() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVUtils.h | 83 std::vector<BasicBlock *> Order = {}; variable
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMemoryLegalizer.cpp | 2609 const AtomicOrdering Order = MOI.getOrdering(); in expandLoad() local
2697 const AtomicOrdering Order = MOI.getOrdering(); in expandAtomicFence() local
2742 const AtomicOrdering Order = MOI.getOrdering(); in expandAtomicCmpxchgOrRmw() local
|
| H A D | AMDGPUInsertDelayAlu.cpp | 262 SmallVector<const_iterator, 8> Order; in dump() local
|