| /freebsd/contrib/llvm-project/llvm/tools/llvm-tapi-diff/ |
| H A D | DiffEngine.cpp | |
| H A D | DiffEngine.h | |
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.h | 32 ArrayRef<MCPhysReg> Order; variable
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder()
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| H A D | RegAllocGreedy.cpp | 398 AllocationOrder &Order, in tryAssign()
532 const AllocationOrder &Order, in getOrderLimit()
578 AllocationOrder &Order, in tryEvict()
869 const AllocationOrder &Order) { in calcGlobalSplitCost()
1061 AllocationOrder &Order, in tryRegionSplit()
1095 AllocationOrder &Order, in calculateRegionSplitCostAroundReg()
1172 AllocationOrder &Order, in calculateRegionSplitCost()
1234 AllocationOrder &Order) { in trySplitAroundHintReg()
1294 AllocationOrder &Order, in tryBlockSplit()
1415 AllocationOrder &Order, in tryInstructionSplit()
[all …]
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| H A D | AllocationOrder.cpp | 34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create() local
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| H A D | LocalStackSlotAllocation.cpp | 59 unsigned Order; member in __anon7165d95d0111::FrameRef
323 unsigned Order = 0; in insertFrameReferenceRegisters() local
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| H A D | RegAllocBasic.cpp | 261 auto Order = in selectOrSplit() local
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| H A D | BreakFalseDeps.cpp | 156 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef() local
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| H A D | RegAllocEvictionAdvisor.cpp | 277 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate()
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| H A D | TargetRegisterInfo.cpp | 248 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); in getAllocatableSetForRC() local
420 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
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| H A D | CriticalAntiDepBreaker.cpp | 399 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister() local
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| H A D | MLRegallocEvictAdvisor.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Support/ |
| H A D | DynamicLibrary.cpp | 81 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup()
96 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SDNodeDbgValue.h | 149 unsigned Order; variable
245 unsigned Order; variable
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| H A D | ScheduleDAGSDNodes.cpp | 740 DenseMap<SDValue, Register> &VRBaseMap, unsigned Order) { in ProcessSDDbgValues()
788 unsigned Order = N->getIROrder(); in ProcessSourceNode() local
992 unsigned Order = Orders[i].first; in EmitSchedule() local
1038 unsigned Order = InstrOrder.first; in EmitSchedule() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 36 std::unique_ptr<MCPhysReg[]> Order; member
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 57 static void addHints(ArrayRef<MCPhysReg> Order, in addHints() argument
75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.h | 569 unsigned Order = 0; // Cache the sort key. member
803 unsigned getRegSetIDAt(unsigned Order) const { in getRegSetIDAt()
807 const RegUnitSet &getRegSetAt(unsigned Order) const { in getRegSetAt()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Frontend/OpenMP/ |
| H A D | OMPIRBuilder.h | 246 explicit OffloadEntryInfo(OffloadingEntryInfoKinds Kind, unsigned Order, in OffloadEntryInfo()
272 unsigned Order = ~0u; variable
302 explicit OffloadEntryInfoTargetRegion(unsigned Order, Constant *Addr, in OffloadEntryInfoTargetRegion()
390 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, in OffloadEntryInfoDeviceGlobalVar()
393 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, Constant *Addr, in OffloadEntryInfoDeviceGlobalVar()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULowerBufferFatPointers.cpp | 1032 void SplitPtrStructs::insertPreMemOpFence(AtomicOrdering Order, in insertPreMemOpFence()
1045 void SplitPtrStructs::insertPostMemOpFence(AtomicOrdering Order, in insertPostMemOpFence()
1060 AtomicOrdering Order, bool IsVolatile, in handleMemoryInst()
1215 AtomicOrdering Order = AI.getMergedOrdering(); in visitAtomicCmpXchgInst() local
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| H A D | AMDGPUInsertDelayAlu.cpp | 247 SmallVector<const_iterator, 8> Order; in dump() local
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | CodeLayout.cpp | 919 concatChains(std::vector<uint64_t> & Order) concatChains() argument
1008 calcExtTspScore(const std::vector<uint64_t> & Order,const std::vector<uint64_t> & NodeSizes,const std::vector<uint64_t> & NodeCounts,const std::vector<EdgeCountT> & EdgeCounts) calcExtTspScore() argument
1039 std::vector<uint64_t> Order(NodeSizes.size()); calcExtTspScore() local
[all...] |
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 1009 ArrayRef<Record *> Order = RC.getOrder(); in runMCDesc() local
1045 ArrayRef<Record *> Order = RC.getOrder(); in runMCDesc() local
1211 ArrayRef<Record *> Order = RC.getOrder(); in runTargetDesc() local
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGAtomic.cpp | 528 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp()
762 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp()
855 llvm::Value *Order = EmitScalarExpr(E->getOrder()); in EmitAtomicExpr() local
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| /freebsd/contrib/llvm-project/clang/lib/Format/ |
| H A D | QualifierAlignmentFixer.cpp | 582 const std::vector<std::string> &Order, std::vector<std::string> &LeftOrder, in prepareLeftRightOrderingForQualifierAlignmentFixer()
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