| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 412 bool isSALU(uint16_t Opcode) const { in isSALU()
420 bool isVALU(uint16_t Opcode) const { in isVALU()
428 bool isImage(uint16_t Opcode) const { in isImage()
436 bool isVMEM(uint16_t Opcode) const { in isVMEM()
444 bool isSOP1(uint16_t Opcode) const { in isSOP1()
452 bool isSOP2(uint16_t Opcode) const { in isSOP2()
460 bool isSOPC(uint16_t Opcode) const { in isSOPC()
468 bool isSOPK(uint16_t Opcode) const { in isSOPK()
476 bool isSOPP(uint16_t Opcode) const { in isSOPP()
484 bool isPacked(uint16_t Opcode) const { in isPacked()
[all …]
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/LoongArch/ |
| H A D | EmulateInstructionLoongArch.h | 66 struct Opcode { struct
74 Opcode *GetOpcodeForInstruction(uint32_t inst); argument
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/PPC64/ |
| H A D | EmulateInstructionPPC64.h | 71 struct Opcode { struct
80 Opcode *GetOpcodeForInstruction(uint32_t opcode); argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 97 static bool isST(unsigned Opcode) { in isST()
102 static bool isSTX32(unsigned Opcode) { in isSTX32()
106 static bool isSTX64(unsigned Opcode) { in isSTX64()
111 static bool isLDX32(unsigned Opcode) { in isLDX32()
115 static bool isLDX64(unsigned Opcode) { in isLDX64()
120 static bool isLDSX(unsigned Opcode) { in isLDSX()
124 bool BPFMISimplifyPatchable::isLoadInst(unsigned Opcode) { in isLoadInst()
144 unsigned Opcode = DefInst->getOpcode(); in checkADDrr() local
178 unsigned Opcode) { in checkShift()
208 unsigned Opcode = I->getParent()->getOpcode(); in processCandidate() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVMakeCompressible.cpp | 98 static unsigned log2LdstWidth(unsigned Opcode) { in log2LdstWidth()
123 static unsigned offsetMask(unsigned Opcode) { in offsetMask()
148 static uint8_t compressedLDSTOffsetMask(unsigned Opcode) { in compressedLDSTOffsetMask()
154 static bool compressibleSPOffset(int64_t Offset, unsigned Opcode) { in compressibleSPOffset()
168 static int64_t getBaseAdjustForCompression(int64_t Offset, unsigned Opcode) { in getBaseAdjustForCompression()
234 const unsigned Opcode = MI.getOpcode(); in getRegImmPairPreventingCompression() local
341 unsigned Opcode = MI.getOpcode(); in updateOperands() local
419 unsigned Opcode = RISCV::FPR32RegClass.contains(RegImm.Reg) in runOnMachineFunction() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.h | 146 static inline bool isSPLSOpcode(unsigned Opcode) { in isSPLSOpcode()
160 static inline bool isRMOpcode(unsigned Opcode) { in isRMOpcode()
170 static inline bool isRRMOpcode(unsigned Opcode) { in isRRMOpcode()
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| H A D | LanaiRegisterInfo.cpp | 69 static bool isALUArithLoOpcode(unsigned Opcode) { in isALUArithLoOpcode()
85 static unsigned getOppositeALULoOpcode(unsigned Opcode) { in getOppositeALULoOpcode()
108 static unsigned getRRMOpcodeVariant(unsigned Opcode) { in getRRMOpcodeVariant()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetOpcodes.h | 30 inline bool isPreISelGenericOpcode(unsigned Opcode) { in isPreISelGenericOpcode()
36 inline bool isTargetSpecificOpcode(unsigned Opcode) { in isTargetSpecificOpcode()
42 inline bool isPreISelGenericOptimizationHint(unsigned Opcode) { in isPreISelGenericOptimizationHint()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | MatchContext.h | 32 bool match(SDValue OpN, unsigned Opcode) const { in match()
74 std::optional<unsigned> Opcode = ISD::getBaseOpcodeForVP( in getRootBaseOpcode() local
111 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand) { in getNode()
119 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode()
127 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode()
136 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand, in getNode()
145 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode()
154 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZShortenInst.cpp | 110 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) { in shortenOn0()
120 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) { in shortenOn01()
132 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) { in shortenOn001()
145 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) { in shortenOn001AddCC()
158 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) { in shortenFPConv()
180 bool SystemZShortenInst::shortenFusedFPOp(MachineInstr &MI, unsigned Opcode) { in shortenFusedFPOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMUnwindOpAsm.h | 72 void EmitInt8(unsigned Opcode) { in EmitInt8()
77 void EmitInt16(unsigned Opcode) { in EmitInt16()
83 void emitBytes(const uint8_t *Opcode, size_t Size) { in emitBytes()
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| /freebsd/contrib/llvm-project/llvm/tools/llvm-readobj/ |
| H A D | ARMEHABIPrinter.h | 99 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local
105 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local
124 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local
129 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local
134 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_1001nnnn() local
139 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10100nnn() local
146 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10101nnn() local
153 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110000() local
169 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110010_uleb128() local
196 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_101101nn() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCPredicates.cpp | 18 switch (Opcode) { in InvertPredicate() argument
52 switch (Opcode) { in getSwappedPredicate() argument
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| /freebsd/contrib/llvm-project/lldb/include/lldb/Core/ |
| H A D | Opcode.h | 43 Opcode(uint8_t inst, lldb::ByteOrder order) in Opcode() function
48 Opcode(uint16_t inst, lldb::ByteOrder order) in Opcode() function
53 Opcode(uint32_t inst, lldb::ByteOrder order) in Opcode() function
58 Opcode(uint64_t inst, lldb::ByteOrder order) in Opcode() function
63 Opcode(uint8_t *bytes, size_t length) in Opcode() function
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| /freebsd/sys/contrib/dev/acpica/components/executer/ |
| H A D | exmisc.c | 277 UINT16 Opcode, in AcpiExDoMathOp()
372 UINT16 Opcode, in AcpiExDoLogicalNumericOp()
445 UINT16 Opcode, in AcpiExDoLogicalOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPostLegalizer.cpp | 56 static bool isMetaInstrGET(unsigned Opcode) { in isMetaInstrGET()
64 static bool mayBeInserted(unsigned Opcode) { in mayBeInserted()
86 const unsigned Opcode = I.getOpcode(); in processNewInstrs() local
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| /freebsd/sys/contrib/dev/acpica/components/parser/ |
| H A D | psopinfo.c | 181 UINT16 Opcode) in AcpiPsGetOpcodeInfo()
278 UINT16 Opcode) in AcpiPsGetOpcodeName()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegacyLegalizerInfo.h | 85 unsigned Opcode; member
180 void setLegalizeScalarToDifferentSizeStrategy(const unsigned Opcode, in setLegalizeScalarToDifferentSizeStrategy()
191 void setLegalizeVectorElementToDifferentSizeStrategy(const unsigned Opcode, in setLegalizeVectorElementToDifferentSizeStrategy()
311 void setScalarAction(const unsigned Opcode, const unsigned TypeIndex, in setScalarAction()
317 void setPointerAction(const unsigned Opcode, const unsigned TypeIndex, in setPointerAction()
334 void setScalarInVectorAction(const unsigned Opcode, const unsigned TypeIndex, in setScalarInVectorAction()
345 void setVectorNumElementAction(const unsigned Opcode, in setVectorNumElementAction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | LeonPasses.cpp | 48 unsigned Opcode = MI.getOpcode(); runOnMachineFunction() local
81 unsigned Opcode = MI.getOpcode(); runOnMachineFunction() local
132 unsigned Opcode = MI.getOpcode(); runOnMachineFunction() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetTransformInfo.cpp | 164 InstructionCost HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost()
222 HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, in getMaskedMemoryOpCost()
239 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, in getGatherScatterOpCost()
246 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, in getInterleavedMemoryOpCost()
258 InstructionCost HexagonTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, in getCmpSelInstrCost()
274 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost()
294 InstructionCost HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy, in getCastInstrCost()
321 InstructionCost HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, in getVectorInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetTransformInfo.cpp | 230 InstructionCost PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst()
553 InstructionCost PPCTTIImpl::vectorCostAdjustmentFactor(unsigned Opcode, in vectorCostAdjustmentFactor()
585 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost()
629 InstructionCost PPCTTIImpl::getCFInstrCost(unsigned Opcode, in getCFInstrCost()
638 InstructionCost PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, in getCastInstrCost()
658 InstructionCost PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, in getCmpSelInstrCost()
676 InstructionCost PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, in getVectorInstrCost()
766 InstructionCost PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost()
856 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, in getInterleavedMemoryOpCost()
1015 bool PPCTTIImpl::hasActiveVectorLength(unsigned Opcode, Type *DataType, in hasActiveVectorLength()
[all …]
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| /freebsd/contrib/bearssl/T0/ |
| H A D | Opcode.cs | 28 abstract class Opcode { class
30 internal Opcode() in Opcode() method in Opcode
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrInfo.h | 63 const MCInstrDesc &get(unsigned Opcode) const { in get()
70 StringRef getName(unsigned Opcode) const { in getName()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreFrameLowering.cpp | 106 int Opcode = isImmU6(OpImm) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; in IfNeededExtSP() local
128 int Opcode = isImmU6(OpImm) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in IfNeededLDAWSP() local
201 int Opcode = isImmU6(Offset) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in RestoreSpillList() local
261 int Opcode = isImmU6(Adjusted) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6; in emitPrologue() local
286 int Opcode = isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in emitPrologue() local
399 int Opcode = isImmU6(RemainingAdj) ? XCore::RETSP_u6 : XCore::RETSP_lu6; in emitEpilogue() local
406 int Opcode = isImmU6(RemainingAdj) ? XCore::LDAWSP_ru6 : in emitEpilogue() local
511 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; in eliminateCallFramePseudoInstr() local
515 int Opcode = isU6 ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in eliminateCallFramePseudoInstr() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/ |
| H A D | RISCVCustomBehaviour.cpp | 169 getEEWAndEMUL(unsigned Opcode, RISCVII::VLMUL LMUL, uint8_t SEW) { in getEEWAndEMUL()
208 bool opcodeHasEEWAndEMULInfo(unsigned short Opcode) { in opcodeHasEEWAndEMULInfo()
223 unsigned short Opcode = MCI.getOpcode(); in getSchedClassID() local
|