| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 431 bool isSALU(uint16_t Opcode) const { in isSALU()
439 bool isVALU(uint16_t Opcode) const { in isVALU()
447 bool isImage(uint16_t Opcode) const { in isImage()
455 bool isVMEM(uint16_t Opcode) const { in isVMEM()
463 bool isSOP1(uint16_t Opcode) const { in isSOP1()
471 bool isSOP2(uint16_t Opcode) const { in isSOP2()
479 bool isSOPC(uint16_t Opcode) const { in isSOPC()
487 bool isSOPK(uint16_t Opcode) const { in isSOPK()
495 bool isSOPP(uint16_t Opcode) const { in isSOPP()
503 bool isPacked(uint16_t Opcode) const { in isPacked()
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/PPC64/ |
| H A D | EmulateInstructionPPC64.h | 71 struct Opcode { struct
80 Opcode *GetOpcodeForInstruction(uint32_t opcode); argument
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/LoongArch/ |
| H A D | EmulateInstructionLoongArch.h | 64 struct Opcode { struct
72 Opcode *GetOpcodeForInstruction(uint32_t inst); argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 95 static bool isStoreImm(unsigned Opcode) { in isStoreImm()
100 static bool isStore32(unsigned Opcode) { in isStore32()
106 static bool isStore64(unsigned Opcode) { in isStore64()
111 static bool isLoad32(unsigned Opcode) { in isLoad32()
117 static bool isLoad64(unsigned Opcode) { in isLoad64()
122 static bool isLoadSext(unsigned Opcode) { in isLoadSext()
126 bool BPFMISimplifyPatchable::isLoadInst(unsigned Opcode) { in isLoadInst()
146 unsigned Opcode = DefInst->getOpcode(); in checkADDrr() local
180 unsigned Opcode) { in checkShift()
210 unsigned Opcode = I->getParent()->getOpcode(); in processCandidate() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.h | 148 static inline bool isSPLSOpcode(unsigned Opcode) { in isSPLSOpcode()
162 static inline bool isRMOpcode(unsigned Opcode) { in isRMOpcode()
172 static inline bool isRRMOpcode(unsigned Opcode) { in isRRMOpcode()
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| H A D | LanaiRegisterInfo.cpp | 66 static bool isALUArithLoOpcode(unsigned Opcode) { in isALUArithLoOpcode()
82 static unsigned getOppositeALULoOpcode(unsigned Opcode) { in getOppositeALULoOpcode()
105 static unsigned getRRMOpcodeVariant(unsigned Opcode) { in getRRMOpcodeVariant()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVMakeCompressible.cpp | 98 static unsigned log2LdstWidth(unsigned Opcode) { in log2LdstWidth()
129 static unsigned offsetMask(unsigned Opcode) { in offsetMask()
160 static uint8_t compressedLDSTOffsetMask(unsigned Opcode) { in compressedLDSTOffsetMask()
166 static bool compressibleSPOffset(int64_t Offset, unsigned Opcode) { in compressibleSPOffset()
180 static int64_t getBaseAdjustForCompression(int64_t Offset, unsigned Opcode) { in getBaseAdjustForCompression()
257 const unsigned Opcode = MI.getOpcode(); in getRegImmPairPreventingCompression() local
372 unsigned Opcode = MI.getOpcode(); in updateOperands() local
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| H A D | RISCVSelectionDAGInfo.h | 37 bool hasPassthruOp(unsigned Opcode) const { in hasPassthruOp()
41 bool hasMaskOp(unsigned Opcode) const { in hasMaskOp()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetOpcodes.h | 30 inline bool isPreISelGenericOpcode(unsigned Opcode) { in isPreISelGenericOpcode()
36 inline bool isTargetSpecificOpcode(unsigned Opcode) { in isTargetSpecificOpcode()
42 inline bool isPreISelGenericOptimizationHint(unsigned Opcode) { in isPreISelGenericOptimizationHint()
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| H A D | SelectionDAGTargetInfo.h | 41 virtual const char *getTargetNodeName(unsigned Opcode) const { in getTargetNodeName()
48 virtual bool isTargetMemoryOpcode(unsigned Opcode) const { return false; } in isTargetMemoryOpcode()
52 virtual bool isTargetStrictFPOpcode(unsigned Opcode) const { return false; } in isTargetStrictFPOpcode()
202 const char *getTargetNodeName(unsigned Opcode) const override { in getTargetNodeName()
208 bool isTargetMemoryOpcode(unsigned Opcode) const override { in isTargetMemoryOpcode()
214 bool isTargetStrictFPOpcode(unsigned Opcode) const override { in isTargetStrictFPOpcode()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | MatchContext.h | 31 bool match(SDValue OpN, unsigned Opcode) const { in match()
75 std::optional<unsigned> Opcode = ISD::getBaseOpcodeForVP( in getRootBaseOpcode() local
112 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand) { in getNode()
120 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode()
128 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode()
137 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand, in getNode()
146 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode()
155 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZShortenInst.cpp | 107 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) { in shortenOn0()
117 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) { in shortenOn01()
129 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) { in shortenOn001()
142 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) { in shortenOn001AddCC()
155 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) { in shortenFPConv()
177 bool SystemZShortenInst::shortenFusedFPOp(MachineInstr &MI, unsigned Opcode) { in shortenFusedFPOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMUnwindOpAsm.h | 73 void EmitInt8(unsigned Opcode) { in EmitInt8()
78 void EmitInt16(unsigned Opcode) { in EmitInt16()
84 void emitBytes(const uint8_t *Opcode, size_t Size) { in emitBytes()
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| /freebsd/contrib/llvm-project/llvm/tools/llvm-readobj/ |
| H A D | ARMEHABIPrinter.h | 99 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local
105 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local
124 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local
129 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local
134 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_1001nnnn() local
139 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10100nnn() local
146 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10101nnn() local
153 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110000() local
169 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110010_uleb128() local
196 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_101101nn() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCPredicates.cpp | 18 switch (Opcode) { in InvertPredicate() argument
52 switch (Opcode) { in getSwappedPredicate() argument
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| /freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/DWARF/LowLevel/ |
| H A D | DWARFCFIProgram.h | 45 uint8_t Opcode; member
90 uint8_t Opcode = Data.getRelocatedValue(C, 1); in parse() local
258 void addInstruction(uint8_t Opcode) { in addInstruction()
263 void addInstruction(uint8_t Opcode, uint64_t Operand1) { in addInstruction()
269 void addInstruction(uint8_t Opcode, uint64_t Operand1, uint64_t Operand2) { in addInstruction()
276 void addInstruction(uint8_t Opcode, uint64_t Operand1, uint64_t Operand2, in addInstruction()
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| /freebsd/sys/contrib/dev/acpica/components/executer/ |
| H A D | exmisc.c | 277 UINT16 Opcode, in AcpiExDoMathOp()
372 UINT16 Opcode, in AcpiExDoLogicalNumericOp()
445 UINT16 Opcode, in AcpiExDoLogicalOp()
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| /freebsd/sys/contrib/dev/acpica/components/parser/ |
| H A D | psopinfo.c | 181 UINT16 Opcode) in AcpiPsGetOpcodeInfo()
278 UINT16 Opcode) in AcpiPsGetOpcodeName()
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| /freebsd/contrib/llvm-project/lldb/include/lldb/Core/ |
| H A D | Opcode.h | 46 Opcode(uint8_t inst, lldb::ByteOrder order) in Opcode() function
51 Opcode(uint16_t inst, lldb::ByteOrder order) in Opcode() function
56 Opcode(uint32_t inst, lldb::ByteOrder order) in Opcode() function
61 Opcode(uint64_t inst, lldb::ByteOrder order) in Opcode() function
66 Opcode(uint8_t *bytes, size_t length, Opcode::Type type, in Opcode() function
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegacyLegalizerInfo.h | 86 unsigned Opcode; member
181 void setLegalizeScalarToDifferentSizeStrategy(const unsigned Opcode, in setLegalizeScalarToDifferentSizeStrategy()
192 void setLegalizeVectorElementToDifferentSizeStrategy(const unsigned Opcode, in setLegalizeVectorElementToDifferentSizeStrategy()
312 void setScalarAction(const unsigned Opcode, const unsigned TypeIndex, in setScalarAction()
318 void setPointerAction(const unsigned Opcode, const unsigned TypeIndex, in setPointerAction()
332 void setScalarInVectorAction(const unsigned Opcode, const unsigned TypeIndex, in setScalarInVectorAction()
343 void setVectorNumElementAction(const unsigned Opcode, in setVectorNumElementAction()
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| /freebsd/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/LowLevel/ |
| H A D | DWARFExpression.cpp | 115 static Desc getDescImpl(ArrayRef<Desc> Descriptions, unsigned Opcode) { in getDescImpl()
122 static Desc getOpDesc(unsigned Opcode) { in getOpDesc()
138 static Desc getSubOpDesc(unsigned Opcode, unsigned SubOpcode) { in getSubOpDesc()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyTargetTransformInfo.cpp | 54 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost()
83 unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, in getCastInstrCost()
145 unsigned Opcode, Type *Ty, Align Alignment, unsigned AddressSpace, in getMemoryOpCost()
186 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, in getVectorInstrCost()
199 unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType, in getPartialReductionCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetTransformInfo.cpp | 165 InstructionCost HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost()
222 HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, in getMaskedMemoryOpCost()
239 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, in getGatherScatterOpCost()
246 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, in getInterleavedMemoryOpCost()
258 unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, in getCmpSelInstrCost()
273 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost()
292 InstructionCost HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy, in getCastInstrCost()
319 InstructionCost HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, in getVectorInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 383 bool isXFormMemOp(unsigned Opcode) const { in isXFormMemOp()
386 bool isPrefixed(unsigned Opcode) const { in isPrefixed()
389 bool isSExt32To64(unsigned Opcode) const { in isSExt32To64()
392 bool isZExt32To64(unsigned Opcode) const { in isZExt32To64()
395 bool isMemriOp(unsigned Opcode) const { in isMemriOp()
399 static bool isSameClassPhysRegCopy(unsigned Opcode) { in isSameClassPhysRegCopy()
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| /freebsd/contrib/bearssl/T0/ |
| H A D | Opcode.cs | 28 abstract class Opcode { class
30 internal Opcode() in Opcode() method in Opcode
|