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Searched defs:Opc (Results 1 – 25 of 306) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCTargetDesc.h148 inline unsigned GetDefaultP2AlignAny(unsigned Opc) { in GetDefaultP2AlignAny()
279 inline unsigned GetDefaultP2Align(unsigned Opc) { in GetDefaultP2Align()
287 inline bool isConst(unsigned Opc) { in isConst()
315 inline bool isScalarConst(unsigned Opc) { in isScalarConst()
331 inline bool isArgument(unsigned Opc) { in isArgument()
367 inline bool isCopy(unsigned Opc) { in isCopy()
391 inline bool isTee(unsigned Opc) { in isTee()
415 inline bool isCallDirect(unsigned Opc) { in isCallDirect()
427 inline bool isCallIndirect(unsigned Opc) { in isCallIndirect()
439 inline bool isBrTable(unsigned Opc) { in isBrTable()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h584 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode()
591 static inline bool isVPTOpcode(int Opc) { in isVPTOpcode()
660 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
664 static inline bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode()
671 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode()
676 int Opc = MI.getOpcode(); in isIndirectCall() local
730 static inline bool isSpeculationBarrierEndBBOpcode(int Opc) { in isSpeculationBarrierEndBBOpcode()
737 static inline bool isPopOpcode(int Opc) { in isPopOpcode()
743 static inline bool isPushOpcode(int Opc) { in isPushOpcode()
748 static inline bool isSubImmOpcode(int Opc) { in isSubImmOpcode()
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H A DARMFastISel.cpp422 unsigned Opc; in ARMMaterializeFP() local
443 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP() local
461 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; in ARMMaterializeInt() local
477 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; in ARMMaterializeInt() local
545 unsigned Opc; in ARMMaterializeGV() local
574 unsigned Opc = IsPositionIndependent ? ARM::t2LDRpci_pic : ARM::t2LDRpci; in ARMMaterializeGV() local
590 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD; in ARMMaterializeGV() local
656 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in fastMaterializeAlloca() local
834 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in ARMSimplifyAddress() local
901 unsigned Opc; in ARMEmitLoad() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp161 static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; } in isUncondBranchOpcode()
163 static bool isI32CondBranchOpcode(int Opc) { in isI32CondBranchOpcode()
168 static bool isI64CondBranchOpcode(int Opc) { in isI64CondBranchOpcode()
173 static bool isRegCondBranchOpcode(int Opc) { in isRegCondBranchOpcode()
178 static bool isFCondBranchOpcode(int Opc) { in isFCondBranchOpcode()
183 static bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
188 static bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode()
194 unsigned Opc = LastInst->getOpcode(); in parseCondBranch() local
346 unsigned Opc = Cond[0].getImm(); in insertBranch() local
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DNoFolder.h48 Value *FoldBinOp(Instruction::BinaryOps Opc, Value *LHS, in FoldBinOp()
53 Value *FoldExactBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldExactBinOp()
58 Value *FoldNoWrapBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldNoWrapBinOp()
63 Value *FoldBinOpFMF(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldBinOpFMF()
68 Value *FoldUnOpFMF(Instruction::UnaryOps Opc, Value *V, in FoldUnOpFMF()
H A DConstantFolder.h43 Value *FoldBinOp(Instruction::BinaryOps Opc, Value *LHS, in FoldBinOp()
55 Value *FoldExactBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldExactBinOp()
68 Value *FoldNoWrapBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldNoWrapBinOp()
86 Value *FoldBinOpFMF(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldBinOpFMF()
91 Value *FoldUnOpFMF(Instruction::UnaryOps Opc, Value *V, in FoldUnOpFMF()
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DInstSimplifyFolder.h50 Value *FoldBinOp(Instruction::BinaryOps Opc, Value *LHS, in FoldBinOp()
55 Value *FoldExactBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldExactBinOp()
60 Value *FoldNoWrapBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldNoWrapBinOp()
65 Value *FoldBinOpFMF(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldBinOpFMF()
70 Value *FoldUnOpFMF(Instruction::UnaryOps Opc, Value *V, in FoldUnOpFMF()
H A DTargetFolder.h54 Value *FoldBinOp(Instruction::BinaryOps Opc, Value *LHS, in FoldBinOp()
66 Value *FoldExactBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldExactBinOp()
79 Value *FoldNoWrapBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldNoWrapBinOp()
97 Value *FoldBinOpFMF(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldBinOpFMF()
110 Value *FoldUnOpFMF(Instruction::UnaryOps Opc, Value *V, in FoldUnOpFMF()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CompressEVEX.cpp119 unsigned Opc = MI.getOpcode(); in performCustomAdjustments() local
188 auto IsRedundantNewDataDest = [&](unsigned &Opc) { in CompressEVEXImpl()
225 unsigned Opc = MI.getOpcode(); in CompressEVEXImpl() local
230 auto GetCompressedOpc = [&](unsigned Opc) -> unsigned { in CompressEVEXImpl()
H A DX86FastISel.cpp333 unsigned Opc = 0; in X86FastEmitLoad() local
490 unsigned Opc = 0; in X86FastEmitStore() local
661 unsigned Opc = 0; in X86FastEmitStore() local
699 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend()
768 unsigned Opc = 0; in handleConstantAddresses() local
2138 unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(*RC) / 8, false, in X86FastEmitCMoveSelect() local
2252 const uint16_t *Opc = nullptr; in X86FastEmitSSESelect() local
2275 unsigned Opc; in X86FastEmitPseudoSelect() local
2491 unsigned Opc = in X86SelectFPExt() local
2505 unsigned Opc = in X86SelectFPTrunc() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp317 unsigned Opc = getLocalGetOpcode(RC); in runOnMachineFunction() local
327 unsigned Opc = getLocalTeeOpcode(RC); in runOnMachineFunction() local
348 unsigned Opc = getDropOpcode(RC); in runOnMachineFunction() local
358 unsigned Opc = getLocalSetOpcode(RC); in runOnMachineFunction() local
418 unsigned Opc = getLocalGetOpcode(RC); in runOnMachineFunction() local
H A DWebAssemblyFastISel.cpp393 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 in materializeLoadStoreOperands() local
613 unsigned Opc = in fastMaterializeAlloca() local
632 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 in fastMaterializeConstant() local
670 unsigned Opc; in fastLowerArguments() local
784 unsigned Opc = IsDirect ? WebAssembly::CALL : WebAssembly::CALL_INDIRECT; in selectCall() local
932 unsigned Opc; in selectSelect() local
1037 unsigned Opc; in selectICmp() local
1106 unsigned Opc; in selectFCmp() local
1205 unsigned Opc; in selectLoad() local
1264 unsigned Opc; in selectStore() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.h30 unsigned Opc; variable
34 Inst(unsigned Opc, int64_t I) : Opc(Opc), Imm(I) { in Inst()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp62 static bool IsConditionalBranch(int Opc) { in IsConditionalBranch()
77 static bool IsUnconditionalJump(int Opc) { in IsUnconditionalJump()
126 int Opc = MI.getOpcode(); in runOnMachineFunction() local
H A DHexagonGenPredicate.cpp144 unsigned HexagonGenPredicate::getPredForm(unsigned Opc) { in getPredForm()
189 unsigned Opc = MI->getOpcode(); in isConvertibleToPredForm() local
210 unsigned Opc = MI.getOpcode(); in collectPredicateGPR() local
256 unsigned Opc = DefI->getOpcode(); in getPredRegFor() local
285 bool HexagonGenPredicate::isScalarCmp(unsigned Opc) { in isScalarCmp()
370 unsigned Opc = MI->getOpcode(); in convertToPredForm() local
H A DHexagonGenMemAbsolute.cpp96 int Opc = MI->getOpcode(); in runOnMachineFunction() local
217 bool HexagonGenMemAbsolute::isValidIndexedLoad(int &Opc, int &NewOpc) { in isValidIndexedLoad()
246 bool HexagonGenMemAbsolute::isValidIndexedStore(int &Opc, int &NewOpc) { in isValidIndexedStore()
H A DHexagonBitSimplify.cpp492 bool HexagonBitSimplify::getUsedBitsInStore(unsigned Opc, BitVector &Bits, in getUsedBitsInStore()
651 bool HexagonBitSimplify::getUsedBits(unsigned Opc, unsigned OpN, in getUsedBits()
1030 unsigned Opc = MI->getOpcode(); in runOnNode() local
1112 unsigned Opc = MI.getOpcode(); in isLossyShiftLeft() local
1172 unsigned Opc = MI.getOpcode(); in isLossyShiftRight() local
1280 unsigned Opc = MI.getOpcode(); in computeUsedBits() local
1423 unsigned Opc = MI.getOpcode(); in isTfrConst() local
1460 unsigned Opc = isInt<8>(Lo) ? Hexagon::A2_combineii in genTfrConst() local
1480 unsigned Opc; in genTfrConst() local
1632 unsigned Opc = I->getOpcode(); in processBlock() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp47 unsigned Opc = MI.getOpcode(); in isLoadFromStackSlot() local
69 unsigned Opc = MI.getOpcode(); in isStoreToStackSlot() local
87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
222 unsigned Opc = 0; in storeRegToStack() local
295 unsigned Opc = 0; in loadRegFromStack() local
376 unsigned Opc; in expandPostRAPseudo() local
575 unsigned Opc = ABI.GetPtrAdduOp(); in adjustStackPtr() local
680 MipsSEInstrInfo::compareOpndSize(unsigned Opc, in compareOpndSize()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp136 unsigned Opc = ARC::SUB_rrlimm; in emitPrologue() local
253 unsigned Opc = ARC::SUB_rrlimm; in emitEpilogue() local
281 unsigned Opc = ARC::ADD_rrlimm; in emitEpilogue() local
296 unsigned Opc = ARC::ADD_rrlimm; in emitEpilogue() local
323 unsigned Opc = ARC::ADD_rrlimm; in emitEpilogue() local
453 unsigned Opc; in emitRegUpdate() local
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCTRLoopsVerify.cpp115 unsigned Opc = I->getOpcode(); in verifyCTRBranch() local
173 unsigned Opc = MII->getOpcode(); in runOnMachineFunction() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp281 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc) { in getMIMGBaseOpcode()
286 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels) { in getMaskedMIMGOp()
422 int getMTBUFBaseOpcode(unsigned Opc) { in getMTBUFBaseOpcode()
432 int getMTBUFElements(unsigned Opc) { in getMTBUFElements()
437 bool getMTBUFHasVAddr(unsigned Opc) { in getMTBUFHasVAddr()
442 bool getMTBUFHasSrsrc(unsigned Opc) { in getMTBUFHasSrsrc()
447 bool getMTBUFHasSoffset(unsigned Opc) { in getMTBUFHasSoffset()
452 int getMUBUFBaseOpcode(unsigned Opc) { in getMUBUFBaseOpcode()
462 int getMUBUFElements(unsigned Opc) { in getMUBUFElements()
467 bool getMUBUFHasVAddr(unsigned Opc) { in getMUBUFHasVAddr()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEMIRBuilder.cpp113 void CSEMIRBuilder::profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps, in profileEverything()
175 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc, in buildInstr()
330 constexpr unsigned Opc = TargetOpcode::G_CONSTANT; in buildConstant() local
357 constexpr unsigned Opc = TargetOpcode::G_FCONSTANT; in buildFConstant() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ConditionOptimizer.cpp218 static int getComplementOpc(int Opc) { in getComplementOpc()
245 unsigned Opc = CmpMI->getOpcode(); in adjustCmp() local
274 unsigned Opc; in modifyCmp() local
H A DAArch64FastISel.cpp407 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi; in materializeFP() local
438 unsigned Opc = Is64Bit ? AArch64::LDRDui : AArch64::LDRSui; in materializeFP() local
574 unsigned Opc = Is64Bit ? AArch64::FMOVXDr : AArch64::FMOVWSr; in fastMaterializeFloatZero() local
1318 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_rr() local
1360 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_ri() local
1404 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_rs() local
1445 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_rx() local
1516 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri; in emitFCmp() local
1526 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr; in emitFCmp() local
1670 unsigned Opc; in emitLogicalOp_ri() local
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCSEConfigBase.h23 virtual bool shouldCSEOpc(unsigned Opc) { return false; } in shouldCSEOpc()

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