| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVISelLowering.cpp | 107 inline Register getTypeReg(MachineRegisterInfo *MRI, Register OpReg) { in getTypeReg()
116 Register OpReg, unsigned OpIdx, in doInsertBitcast()
156 Register OpReg = I.getOperand(OpIdx).getReg(); in validatePtrTypes() local
190 Register OpReg = I.getOperand(OpIdx).getReg(); in validateGroupWaitEventsPtr() local
211 Register OpReg = I.getOperand(OpIdx).getReg(); in validateGroupAsyncCopyPtr() local
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| H A D | SPIRVInstructionSelector.cpp | 713 Register OpReg = I.getOperand(1).getReg(); in selectBitcast() local
1371 Register OpReg = I.getOperand(1).getReg(); in selectFreeze() local
1432 Register OpReg = ResType->getOperand(2).getReg(); in getArrayComponentCount() local
1488 static bool isConstReg(MachineRegisterInfo *MRI, Register OpReg) { in isConstReg()
1511 Register OpReg = I.getOperand(OpIdx).getReg(); in selectSplatVector() local
1915 Register OpReg = I.getOperand(i).getReg(); in wrapIntoSpecConstantOp() local
2004 for (Register OpReg : CompositeArgs) in selectIntrinsic() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineConvergenceVerifier.cpp | 57 Register OpReg = MO.getReg(); in findAndCheckConvergenceTokenUsed() local
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| H A D | MachineInstr.cpp | 2069 Register OpReg = MO.getReg(); in clearRegisterKills() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/ |
| H A D | AMDGPUCustomBehaviour.cpp | 191 const MCAOperand *OpReg = Inst.getOperand(0); in computeWaitCnt() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 1733 Register OpReg = getRegForValue(TI->getOperand(0)); in X86SelectBranch() local
1768 Register OpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1790 unsigned CReg = 0, OpReg = 0; in X86SelectShift() local
2362 Register OpReg = getRegForValue(Opnd); in X86SelectSelect() local
2407 Register OpReg = getRegForValue(I->getOperand(0)); in X86SelectIntToFP() local
2461 Register OpReg = getRegForValue(I->getOperand(0)); in X86SelectFPExtOrFPTrunc() local
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| H A D | X86SpeculativeLoadHardening.cpp | 1652 Register OpReg = Op->getReg(); in hardenLoadAddr() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 297 Register OpReg = MO.getReg(); in optimizeSDPattern() local
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| H A D | ARMInstructionSelector.cpp | 1054 Register OpReg = I.getOperand(2).getReg(); in select() local
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| H A D | ARMFastISel.cpp | 1263 Register OpReg = getRegForValue(TI->getOperand(0)); in SelectBranch() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86InstComments.cpp | 241 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4611 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSge() local
4748 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSle() local
5439 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSeq() local
5520 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSne() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 1725 Register OpReg = getRegForValue(In); in selectFNeg() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 879 Register OpReg = Op.getReg(); in executeInWaterfallLoop() local
3599 Register OpReg = MI.getOperand(I).getReg(); in getImageMapping() local
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| H A D | AMDGPUInstructionSelector.cpp | 2641 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FNEG() local
2679 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FABS() local
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| H A D | GCNHazardRecognizer.cpp | 2844 Register OpReg = Op.getReg(); in fixVALUMaskWriteHazard() local
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| H A D | SIInstrInfo.cpp | 6223 Register OpReg = Op.getReg(); in legalizeGenericOperand() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6043 Register OpReg = MI.getOperand(0).getReg(); in narrowScalarExtract() local
6109 Register OpReg = MI.getOperand(2).getReg(); in narrowScalarInsert() local
8549 Register OpReg = MI.getOperand(1).getReg(); in lowerAbsToAddXor() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 5789 Register OpReg = I.getOperand(i).getReg(); in selectBuildVector() local
7883 Register OpReg = MO.getReg(); in fixupPHIOpBanks() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 7467 unsigned OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList() local
7481 unsigned OpReg = Inst.getOperand(i).getReg(); in listContainsReg() local
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