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Searched defs:Op0 (Results 1 – 25 of 155) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DInstructionSimplify.cpp300 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS); in simplifyAssociativeBinOp() local
608 Value *&Op0, Value *&Op1, in foldOrCommuteConstant()
635 static Value *simplifyAddInst(Value *Op0, Value *Op1, bool IsNSW, bool IsNUW, in simplifyAddInst()
702 Value *llvm::simplifyAddInst(Value *Op0, Value *Op1, bool IsNSW, bool IsNUW, in simplifyAddInst()
753 static Value *simplifyByDomEq(unsigned Opcode, Value *Op0, Value *Op1, in simplifyByDomEq()
787 static Value *simplifySubInst(Value *Op0, Value *Op1, bool IsNSW, bool IsNUW, in simplifySubInst()
923 Value *llvm::simplifySubInst(Value *Op0, Value *Op1, bool IsNSW, bool IsNUW, in simplifySubInst()
930 static Value *simplifyMulInst(Value *Op0, Value *Op1, bool IsNSW, bool IsNUW, in simplifyMulInst()
995 Value *llvm::simplifyMulInst(Value *Op0, Value *Op1, bool IsNSW, bool IsNUW, in simplifyMulInst()
1078 static Value *simplifyDivRem(Instruction::BinaryOps Opcode, Value *Op0, in simplifyDivRem()
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H A DOverflowInstAnalysis.cpp21 bool llvm::isCheckForZeroAndMulWithOverflow(Value *Op0, Value *Op1, bool IsAnd, in isCheckForZeroAndMulWithOverflow()
67 bool llvm::isCheckForZeroAndMulWithOverflow(Value *Op0, Value *Op1, in isCheckForZeroAndMulWithOverflow()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineMulDivRem.cpp196 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitMul() local
576 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldFPSignBitOps() local
633 Value *Op0 = I.getOperand(0); in foldPowiReassoc() local
676 Value *Op0 = I.getOperand(0); in foldFMulReassoc() local
884 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitFMul() local
1087 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldIDivShl() local
1169 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonIDivTransforms() local
1526 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitUDiv() local
1595 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitSDiv() local
1805 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldFDivPowDivisor() local
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H A DInstCombineAndOrXor.cpp1527 Value *Op0, Value *Op1) { in foldLogicOfIsFPClass()
1618 Value *Op0 = BO.getOperand(0), *Op1 = BO.getOperand(1), *X; in reassociateFCmps() local
1665 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in matchDeMorgansLaws() local
1747 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldCastedBitwiseLogic() local
1754 Value *Op1) -> Instruction * { in foldCastedBitwiseLogic()
1844 Value *Op0 = I.getOperand(0); in foldAndToXor() local
1870 Value *Op0 = I.getOperand(0); in foldOrToXor() local
1916 Value *Op0 = And.getOperand(0), *Op1 = And.getOperand(1); in narrowMaskedBinOp() local
1960 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldComplexAndOrPatterns() local
2131 Value *Op0 = I.getOperand(0); in canonicalizeLogicFirst() local
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H A DInstCombineCompares.cpp1297 Value *Op0 = Cmp.getOperand(0), *Op1 = Cmp.getOperand(1); in foldICmpWithConstant() local
2969 static Value *createLogicFromTable(const std::bitset<4> &Table, Value *Op0, in createLogicFromTable()
3026 Value *Op0, *Op1; in foldICmpAddConstant() local
3721 Value *Op0 = Cmp.getOperand(0); in foldICmpIntrinsicWithIntrinsic() local
3873 Value *Op0 = II->getOperand(0); in foldICmpUSubSatOrUAddSatWithConstant() local
4092 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldICmpInstWithConstantNotInt() local
4289 static Value *foldICmpWithLowBitMaskedVal(ICmpInst::Predicate Pred, Value *Op0, in foldICmpWithLowBitMaskedVal()
4771 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1), *A; in foldICmpAndXX() local
4833 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1), *A; in foldICmpOrXX() local
4868 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1), *A; in foldICmpXorXX() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTDC.cpp127 Value *Op0 = I.getOperand(0); in convertFCmp() local
237 Value *Op0 = I.getOperand(0); in convertICmp() local
292 Value *Op0, *Op1; in convertLogicOp() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DExpandVectorPredication.cpp261 Value *Op0 = VPI.getOperand(0); in expandPredicationInBinaryOperator() local
297 Value *Op0 = VPI.getOperand(0); in expandPredicationToIntCall() local
326 Value *Op0 = VPI.getOperand(0); in expandPredicationToFPCall() local
335 Value *Op0 = VPI.getOperand(0); in expandPredicationToFPCall() local
347 Value *Op0 = VPI.getOperand(0); in expandPredicationToFPCall() local
642 Value *Op0 = VPI.getOperand(0); in expandPredicationInComparison() local
H A DCodeGenCommonISel.cpp278 auto Op0 = salvageDebugInfoImpl(MRI, MI, Ops); in salvageDebugInfoForDbgValue() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp184 void MachineIRBuilder::validateUnaryOp(const LLT Res, const LLT Op0) { in validateUnaryOp()
189 void MachineIRBuilder::validateBinaryOp(const LLT Res, const LLT Op0, in validateBinaryOp()
195 void MachineIRBuilder::validateShiftOp(const LLT Res, const LLT Op0, in validateShiftOp()
202 MachineIRBuilder::buildPtrAdd(const DstOp &Res, const SrcOp &Op0, in buildPtrAdd()
212 MachineIRBuilder::materializePtrAdd(Register &Res, Register Op0, in materializePtrAdd()
228 const SrcOp &Op0, in buildMaskLowPtrBits()
239 const SrcOp &Op0) { in buildPadVectorWithUndefElements()
270 const SrcOp &Op0) { in buildDeleteTrailingVectorElements()
900 const SrcOp &Op0, in buildICmp()
907 const SrcOp &Op0, in buildFCmp()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp485 Register Op0 = getRegForValue(I->getOperand(0)); in selectBinaryOp() local
1542 Register Op0 = getRegForValue(I->getOperand(0)); in selectBitCast() local
1780 const Value *Op0 = EVI->getOperand(0); in selectExtractValue() local
1985 Register FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, in fastEmit_ri_()
2051 const TargetRegisterClass *RC, unsigned Op0) { in fastEmitInst_r()
2072 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rr()
2096 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rrr()
2123 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_ri()
2146 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rii()
2191 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rri()
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H A DLegalizeFloatTypes.cpp1048 SDValue Op0 = GetSoftenedFloat(N->getOperand(0)); in SoftenFloatOp_BITCAST() local
1202 SDValue Op0 = N->getOperand(IsStrict ? 1 : 0); in SoftenFloatOp_SETCC() local
2520 SDValue Op0 = GetPromotedFloat(N->getOperand(0)); in PromoteFloatOp_SETCC() local
2781 SDValue Op0 = GetPromotedFloat(N->getOperand(0)); in PromoteFloatRes_FCOPYSIGN() local
2805 SDValue Op0 = GetPromotedFloat(N->getOperand(0)); in PromoteFloatRes_BinOp() local
2813 SDValue Op0 = GetPromotedFloat(N->getOperand(0)); in PromoteFloatRes_FMAD() local
2824 SDValue Op0 = GetPromotedFloat(N->getOperand(0)); in PromoteFloatRes_ExpOp() local
3190 SDValue Op0 = GetSoftPromotedHalf(N->getOperand(0)); in SoftPromoteHalfRes_FMAD() local
3210 SDValue Op0 = GetSoftPromotedHalf(N->getOperand(0)); in SoftPromoteHalfRes_ExpOp() local
3342 SDValue Op0 = GetSoftPromotedHalf(N->getOperand(0)); in SoftPromoteHalfRes_BinOp() local
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h531 MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, in buildPtrMask()
593 const SrcOp &Op0, const SrcOp &Op1) { in buildUAddo()
599 const SrcOp &Op0, const SrcOp &Op1) { in buildUSubo()
605 const SrcOp &Op0, const SrcOp &Op1) { in buildSAddo()
611 const SrcOp &Op0, const SrcOp &Op1) { in buildSSubo()
630 const SrcOp &Op0, const SrcOp &Op1, in buildUAdde()
638 const SrcOp &Op0, const SrcOp &Op1, in buildUSube()
646 const SrcOp &Op0, const SrcOp &Op1, in buildSAdde()
654 const SrcOp &Op0, const SrcOp &Op1, in buildSSube()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DScalarizer.cpp645 Value *Op0 = VOp0[Frag]; in splitBinary() local
776 Value *Op0 = VOp0[I]; in visitSelectInst() local
783 Value *Op0 = SI.getOperand(0); in visitSelectInst() local
869 Scatterer Op0 = scatter(&CI, CI.getOperand(0), *SrcVS); in visitCastInst() local
893 Scatterer Op0 = scatter(&BCI, BCI.getOperand(0), *SrcVS); in visitBitCastInst() local
968 Scatterer Op0 = scatter(&IEI, IEI.getOperand(0), *VS); in visitInsertElementInst() local
1019 Scatterer Op0 = scatter(&EEI, EEI.getOperand(0), *VS); in visitExtractElementInst() local
1060 Scatterer Op0 = scatter(&SVI, SVI.getOperand(0), *VSOp); in visitShuffleVectorInst() local
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp1579 static Value *emitX86Select(IRBuilder<> &Builder, Value *Mask, Value *Op0, in emitX86Select()
1591 static Value *emitX86ScalarSelect(IRBuilder<> &Builder, Value *Mask, Value *Op0, in emitX86ScalarSelect()
1608 static Value *upgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, in upgradeX86ALIGNIntrinsics()
1717 Value *Op0 = CI.getOperand(0); in upgradeX86BinaryIntrinsics() local
1799 Value *Op0 = CI.getArgOperand(0); in upgradeX86ConcatShift() local
1876 Value *Op0 = CI.getArgOperand(0); in upgradeAbs() local
1938 Value *Op0 = CI.getArgOperand(0); in upgradeMaskedCompare() local
2366 Value *Op0 = CI->getArgOperand(0); in upgradeX86IntrinsicCall() local
2929 Value *Op0 = CI->getArgOperand(0); in upgradeX86IntrinsicCall() local
2943 Value *Op0 = CI->getArgOperand(0); in upgradeX86IntrinsicCall() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.cpp158 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
172 uint32_t Op0 = (Bits >> 14) & 0x3; in genericRegisterString() local
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterBankInfo.cpp
H A DX86InstCombineIntrinsic.cpp1800 static Value *simplifyX86extrq(IntrinsicInst &II, Value *Op0, in simplifyX86extrq()
1891 static Value *simplifyX86insertq(IntrinsicInst &II, Value *Op0, Value *Op1, in simplifyX86insertq()
2720 Value *Op0 = II.getArgOperand(0); in instCombineIntrinsic() local
2762 Value *Op0 = II.getArgOperand(0); in instCombineIntrinsic() local
2785 Value *Op0 = II.getArgOperand(0); in instCombineIntrinsic() local
2821 Value *Op0 = II.getArgOperand(0); in instCombineIntrinsic() local
2866 Value *Op0 = II.getArgOperand(0); in instCombineIntrinsic() local
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFAdjustOpt.cpp107 Value *Op0 = Icmp->getOperand(0); in adjustICmpToBuiltin() local
163 Value *Op0, *Op1; in serializeICMPInBB() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp697 MachineOperand &Op0 = MI->getOperand(0); in splitImmediate() local
724 MachineOperand &Op0 = MI->getOperand(0); in splitCombine() local
754 MachineOperand &Op0 = MI->getOperand(0); in splitExt() local
776 MachineOperand &Op0 = MI->getOperand(0); in splitShift() local
900 MachineOperand &Op0 = MI->getOperand(0); in splitAslOr() local
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86RegisterBankInfo.cpp329 auto &Op0 = MI.getOperand(0); in getInstrMapping() local
358 auto &Op0 = MI.getOperand(0); in getInstrMapping() local
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DGetElementPtrTypeIterator.h147 gep_type_begin(Type * Op0,ArrayRef<T> A) gep_type_begin() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyTargetTransformInfo.cpp86 unsigned Index, Value *Op0, Value *Op1) { in getVectorInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp307 auto Op0 = N->getOperand(0); in selectAddCarry() local
350 auto Op0 = N->getOperand(0); in selectSubCarry() local
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp3875 Value *Op0 = EmitScalarExpr(E->getArg(0)); in EmitBuiltinExpr() local
3893 Value *Op0 = EmitScalarExpr(E->getArg(0)); in EmitBuiltinExpr() local
3909 Value *Op0 = EmitScalarExpr(E->getArg(0)); in EmitBuiltinExpr() local
11847 Value *Op0 = Builder.CreateExtractElement(Vec, Idx0, "lane0"); in EmitAArch64BuiltinExpr() local
11859 Value *Op0 = Builder.CreateExtractElement(Vec, Idx0, "lane0"); in EmitAArch64BuiltinExpr() local
11871 Value *Op0 = Builder.CreateExtractElement(Vec, Idx0, "lane0"); in EmitAArch64BuiltinExpr() local
13721 static Value *EmitX86FunnelShift(CodeGenFunction &CGF, Value *Op0, Value *Op1, in EmitX86FunnelShift()
13741 Value *Op0 = Ops[0]; in EmitX86vpcom() local
13780 Value *Mask, Value *Op0, Value *Op1) { in EmitX86Select()
13794 Value *Mask, Value *Op0, Value *Op1) { in EmitX86ScalarSelect()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600TargetTransformInfo.cpp112 unsigned Index, Value *Op0, in getVectorInstrCost()

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