1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides ARM specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "ARMMCTargetDesc.h"
14 #include "ARMAddressingModes.h"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMMCAsmInfo.h"
18 #include "TargetInfo/ARMTargetInfo.h"
19 #include "llvm/DebugInfo/CodeView/CodeView.h"
20 #include "llvm/MC/MCAsmBackend.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCELFStreamer.h"
23 #include "llvm/MC/MCInstrAnalysis.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCObjectWriter.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/MC/TargetRegistry.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/TargetParser/Triple.h"
33
34 using namespace llvm;
35
36 #define GET_REGINFO_MC_DESC
37 #include "ARMGenRegisterInfo.inc"
38
getMCRDeprecationInfo(MCInst & MI,const MCSubtargetInfo & STI,std::string & Info)39 static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
40 std::string &Info) {
41 if (STI.hasFeature(llvm::ARM::HasV7Ops) &&
42 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
43 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
44 // Checks for the deprecated CP15ISB encoding:
45 // mcr p15, #0, rX, c7, c5, #4
46 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
47 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
48 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
49 Info = "deprecated since v7, use 'isb'";
50 return true;
51 }
52
53 // Checks for the deprecated CP15DSB encoding:
54 // mcr p15, #0, rX, c7, c10, #4
55 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
56 Info = "deprecated since v7, use 'dsb'";
57 return true;
58 }
59 }
60 // Checks for the deprecated CP15DMB encoding:
61 // mcr p15, #0, rX, c7, c10, #5
62 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
63 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
64 Info = "deprecated since v7, use 'dmb'";
65 return true;
66 }
67 }
68 if (STI.hasFeature(llvm::ARM::HasV7Ops) &&
69 ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
70 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
71 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
72 "point instructions";
73 return true;
74 }
75 return false;
76 }
77
getMRCDeprecationInfo(MCInst & MI,const MCSubtargetInfo & STI,std::string & Info)78 static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
79 std::string &Info) {
80 if (STI.hasFeature(llvm::ARM::HasV7Ops) &&
81 ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 10) ||
82 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 11))) {
83 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
84 "point instructions";
85 return true;
86 }
87 return false;
88 }
89
getARMStoreDeprecationInfo(MCInst & MI,const MCSubtargetInfo & STI,std::string & Info)90 static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
91 std::string &Info) {
92 assert(!STI.hasFeature(llvm::ARM::ModeThumb) &&
93 "cannot predicate thumb instructions");
94
95 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
96 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
97 assert(MI.getOperand(OI).isReg() && "expected register");
98 if (MI.getOperand(OI).getReg() == ARM::PC) {
99 Info = "use of PC in the list is deprecated";
100 return true;
101 }
102 }
103 return false;
104 }
105
getARMLoadDeprecationInfo(MCInst & MI,const MCSubtargetInfo & STI,std::string & Info)106 static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
107 std::string &Info) {
108 assert(!STI.hasFeature(llvm::ARM::ModeThumb) &&
109 "cannot predicate thumb instructions");
110
111 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
112 bool ListContainsPC = false, ListContainsLR = false;
113 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
114 assert(MI.getOperand(OI).isReg() && "expected register");
115 switch (MI.getOperand(OI).getReg().id()) {
116 default:
117 break;
118 case ARM::LR:
119 ListContainsLR = true;
120 break;
121 case ARM::PC:
122 ListContainsPC = true;
123 break;
124 }
125 }
126
127 if (ListContainsPC && ListContainsLR) {
128 Info = "use of LR and PC simultaneously in the list is deprecated";
129 return true;
130 }
131
132 return false;
133 }
134
135 #define GET_INSTRINFO_MC_DESC
136 #define ENABLE_INSTR_PREDICATE_VERIFIER
137 #include "ARMGenInstrInfo.inc"
138
139 #define GET_SUBTARGETINFO_MC_DESC
140 #include "ARMGenSubtargetInfo.inc"
141
ParseARMTriple(const Triple & TT,StringRef CPU)142 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
143 std::string ARMArchFeature;
144
145 ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName());
146 if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic"))
147 ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str();
148
149 if (TT.isThumb()) {
150 if (!ARMArchFeature.empty())
151 ARMArchFeature += ",";
152 ARMArchFeature += "+thumb-mode,+v4t";
153 }
154
155 if (TT.isOSNaCl()) {
156 if (!ARMArchFeature.empty())
157 ARMArchFeature += ",";
158 ARMArchFeature += "+nacl-trap";
159 }
160
161 if (TT.isOSWindows()) {
162 if (!ARMArchFeature.empty())
163 ARMArchFeature += ",";
164 ARMArchFeature += "+noarm";
165 }
166
167 return ARMArchFeature;
168 }
169
isPredicated(const MCInst & MI,const MCInstrInfo * MCII)170 bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
171 const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
172 int PredOpIdx = Desc.findFirstPredOperandIdx();
173 return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;
174 }
175
isCPSRDefined(const MCInst & MI,const MCInstrInfo * MCII)176 bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) {
177 const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
178 for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
179 const MCOperand &MO = MI.getOperand(I);
180 if (MO.isReg() && MO.getReg() == ARM::CPSR &&
181 Desc.operands()[I].isOptionalDef())
182 return true;
183 }
184 return false;
185 }
186
evaluateBranchTarget(const MCInstrDesc & InstDesc,uint64_t Addr,int64_t Imm)187 uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc,
188 uint64_t Addr, int64_t Imm) {
189 // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
190 // is 4 bytes.
191 uint64_t Offset =
192 ((InstDesc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8;
193
194 // A Thumb instruction BLX(i) can be 16-bit aligned while targets Arm code
195 // which is 32-bit aligned. The target address for the case is calculated as
196 // targetAddress = Align(PC,4) + imm32;
197 // where
198 // Align(x, y) = y * (x DIV y);
199 if (InstDesc.getOpcode() == ARM::tBLXi)
200 Addr &= ~0x3;
201
202 return Addr + Imm + Offset;
203 }
204
createARMMCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)205 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
206 StringRef CPU, StringRef FS) {
207 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
208 if (!FS.empty()) {
209 if (!ArchFS.empty())
210 ArchFS = (Twine(ArchFS) + "," + FS).str();
211 else
212 ArchFS = std::string(FS);
213 }
214
215 return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
216 }
217
createARMMCInstrInfo()218 static MCInstrInfo *createARMMCInstrInfo() {
219 MCInstrInfo *X = new MCInstrInfo();
220 InitARMMCInstrInfo(X);
221 return X;
222 }
223
initLLVMToCVRegMapping(MCRegisterInfo * MRI)224 void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
225 // Mapping from CodeView to MC register id.
226 static const struct {
227 codeview::RegisterId CVReg;
228 MCPhysReg Reg;
229 } RegMap[] = {
230 {codeview::RegisterId::ARM_R0, ARM::R0},
231 {codeview::RegisterId::ARM_R1, ARM::R1},
232 {codeview::RegisterId::ARM_R2, ARM::R2},
233 {codeview::RegisterId::ARM_R3, ARM::R3},
234 {codeview::RegisterId::ARM_R4, ARM::R4},
235 {codeview::RegisterId::ARM_R5, ARM::R5},
236 {codeview::RegisterId::ARM_R6, ARM::R6},
237 {codeview::RegisterId::ARM_R7, ARM::R7},
238 {codeview::RegisterId::ARM_R8, ARM::R8},
239 {codeview::RegisterId::ARM_R9, ARM::R9},
240 {codeview::RegisterId::ARM_R10, ARM::R10},
241 {codeview::RegisterId::ARM_R11, ARM::R11},
242 {codeview::RegisterId::ARM_R12, ARM::R12},
243 {codeview::RegisterId::ARM_SP, ARM::SP},
244 {codeview::RegisterId::ARM_LR, ARM::LR},
245 {codeview::RegisterId::ARM_PC, ARM::PC},
246 {codeview::RegisterId::ARM_CPSR, ARM::CPSR},
247 {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
248 {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},
249 {codeview::RegisterId::ARM_FS0, ARM::S0},
250 {codeview::RegisterId::ARM_FS1, ARM::S1},
251 {codeview::RegisterId::ARM_FS2, ARM::S2},
252 {codeview::RegisterId::ARM_FS3, ARM::S3},
253 {codeview::RegisterId::ARM_FS4, ARM::S4},
254 {codeview::RegisterId::ARM_FS5, ARM::S5},
255 {codeview::RegisterId::ARM_FS6, ARM::S6},
256 {codeview::RegisterId::ARM_FS7, ARM::S7},
257 {codeview::RegisterId::ARM_FS8, ARM::S8},
258 {codeview::RegisterId::ARM_FS9, ARM::S9},
259 {codeview::RegisterId::ARM_FS10, ARM::S10},
260 {codeview::RegisterId::ARM_FS11, ARM::S11},
261 {codeview::RegisterId::ARM_FS12, ARM::S12},
262 {codeview::RegisterId::ARM_FS13, ARM::S13},
263 {codeview::RegisterId::ARM_FS14, ARM::S14},
264 {codeview::RegisterId::ARM_FS15, ARM::S15},
265 {codeview::RegisterId::ARM_FS16, ARM::S16},
266 {codeview::RegisterId::ARM_FS17, ARM::S17},
267 {codeview::RegisterId::ARM_FS18, ARM::S18},
268 {codeview::RegisterId::ARM_FS19, ARM::S19},
269 {codeview::RegisterId::ARM_FS20, ARM::S20},
270 {codeview::RegisterId::ARM_FS21, ARM::S21},
271 {codeview::RegisterId::ARM_FS22, ARM::S22},
272 {codeview::RegisterId::ARM_FS23, ARM::S23},
273 {codeview::RegisterId::ARM_FS24, ARM::S24},
274 {codeview::RegisterId::ARM_FS25, ARM::S25},
275 {codeview::RegisterId::ARM_FS26, ARM::S26},
276 {codeview::RegisterId::ARM_FS27, ARM::S27},
277 {codeview::RegisterId::ARM_FS28, ARM::S28},
278 {codeview::RegisterId::ARM_FS29, ARM::S29},
279 {codeview::RegisterId::ARM_FS30, ARM::S30},
280 {codeview::RegisterId::ARM_FS31, ARM::S31},
281 {codeview::RegisterId::ARM_ND0, ARM::D0},
282 {codeview::RegisterId::ARM_ND1, ARM::D1},
283 {codeview::RegisterId::ARM_ND2, ARM::D2},
284 {codeview::RegisterId::ARM_ND3, ARM::D3},
285 {codeview::RegisterId::ARM_ND4, ARM::D4},
286 {codeview::RegisterId::ARM_ND5, ARM::D5},
287 {codeview::RegisterId::ARM_ND6, ARM::D6},
288 {codeview::RegisterId::ARM_ND7, ARM::D7},
289 {codeview::RegisterId::ARM_ND8, ARM::D8},
290 {codeview::RegisterId::ARM_ND9, ARM::D9},
291 {codeview::RegisterId::ARM_ND10, ARM::D10},
292 {codeview::RegisterId::ARM_ND11, ARM::D11},
293 {codeview::RegisterId::ARM_ND12, ARM::D12},
294 {codeview::RegisterId::ARM_ND13, ARM::D13},
295 {codeview::RegisterId::ARM_ND14, ARM::D14},
296 {codeview::RegisterId::ARM_ND15, ARM::D15},
297 {codeview::RegisterId::ARM_ND16, ARM::D16},
298 {codeview::RegisterId::ARM_ND17, ARM::D17},
299 {codeview::RegisterId::ARM_ND18, ARM::D18},
300 {codeview::RegisterId::ARM_ND19, ARM::D19},
301 {codeview::RegisterId::ARM_ND20, ARM::D20},
302 {codeview::RegisterId::ARM_ND21, ARM::D21},
303 {codeview::RegisterId::ARM_ND22, ARM::D22},
304 {codeview::RegisterId::ARM_ND23, ARM::D23},
305 {codeview::RegisterId::ARM_ND24, ARM::D24},
306 {codeview::RegisterId::ARM_ND25, ARM::D25},
307 {codeview::RegisterId::ARM_ND26, ARM::D26},
308 {codeview::RegisterId::ARM_ND27, ARM::D27},
309 {codeview::RegisterId::ARM_ND28, ARM::D28},
310 {codeview::RegisterId::ARM_ND29, ARM::D29},
311 {codeview::RegisterId::ARM_ND30, ARM::D30},
312 {codeview::RegisterId::ARM_ND31, ARM::D31},
313 {codeview::RegisterId::ARM_NQ0, ARM::Q0},
314 {codeview::RegisterId::ARM_NQ1, ARM::Q1},
315 {codeview::RegisterId::ARM_NQ2, ARM::Q2},
316 {codeview::RegisterId::ARM_NQ3, ARM::Q3},
317 {codeview::RegisterId::ARM_NQ4, ARM::Q4},
318 {codeview::RegisterId::ARM_NQ5, ARM::Q5},
319 {codeview::RegisterId::ARM_NQ6, ARM::Q6},
320 {codeview::RegisterId::ARM_NQ7, ARM::Q7},
321 {codeview::RegisterId::ARM_NQ8, ARM::Q8},
322 {codeview::RegisterId::ARM_NQ9, ARM::Q9},
323 {codeview::RegisterId::ARM_NQ10, ARM::Q10},
324 {codeview::RegisterId::ARM_NQ11, ARM::Q11},
325 {codeview::RegisterId::ARM_NQ12, ARM::Q12},
326 {codeview::RegisterId::ARM_NQ13, ARM::Q13},
327 {codeview::RegisterId::ARM_NQ14, ARM::Q14},
328 {codeview::RegisterId::ARM_NQ15, ARM::Q15},
329 };
330 for (const auto &I : RegMap)
331 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
332 }
333
createARMMCRegisterInfo(const Triple & Triple)334 static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
335 MCRegisterInfo *X = new MCRegisterInfo();
336 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
337 ARM_MC::initLLVMToCVRegMapping(X);
338 return X;
339 }
340
createARMMCAsmInfo(const MCRegisterInfo & MRI,const Triple & TheTriple,const MCTargetOptions & Options)341 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
342 const Triple &TheTriple,
343 const MCTargetOptions &Options) {
344 MCAsmInfo *MAI;
345 if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
346 MAI = new ARMMCAsmInfoDarwin(TheTriple);
347 else if (TheTriple.isWindowsMSVCEnvironment())
348 MAI = new ARMCOFFMCAsmInfoMicrosoft();
349 else if (TheTriple.isOSWindows())
350 MAI = new ARMCOFFMCAsmInfoGNU();
351 else
352 MAI = new ARMELFMCAsmInfo(TheTriple);
353
354 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
355 MAI->addInitialFrameState(MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0));
356
357 return MAI;
358 }
359
createELFStreamer(const Triple & T,MCContext & Ctx,std::unique_ptr<MCAsmBackend> && MAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter)360 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
361 std::unique_ptr<MCAsmBackend> &&MAB,
362 std::unique_ptr<MCObjectWriter> &&OW,
363 std::unique_ptr<MCCodeEmitter> &&Emitter) {
364 return createARMELFStreamer(
365 Ctx, std::move(MAB), std::move(OW), std::move(Emitter),
366 (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb),
367 T.isAndroid());
368 }
369
370 static MCStreamer *
createARMMachOStreamer(MCContext & Ctx,std::unique_ptr<MCAsmBackend> && MAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter)371 createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB,
372 std::unique_ptr<MCObjectWriter> &&OW,
373 std::unique_ptr<MCCodeEmitter> &&Emitter) {
374 return createMachOStreamer(Ctx, std::move(MAB), std::move(OW),
375 std::move(Emitter), false);
376 }
377
createARMMCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)378 static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
379 unsigned SyntaxVariant,
380 const MCAsmInfo &MAI,
381 const MCInstrInfo &MII,
382 const MCRegisterInfo &MRI) {
383 if (SyntaxVariant == 0)
384 return new ARMInstPrinter(MAI, MII, MRI);
385 return nullptr;
386 }
387
createARMMCRelocationInfo(const Triple & TT,MCContext & Ctx)388 static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
389 MCContext &Ctx) {
390 if (TT.isOSBinFormatMachO())
391 return createARMMachORelocationInfo(Ctx);
392 // Default to the stock relocation info.
393 return llvm::createMCRelocationInfo(TT, Ctx);
394 }
395
396 namespace {
397
398 class ARMMCInstrAnalysis : public MCInstrAnalysis {
399 public:
ARMMCInstrAnalysis(const MCInstrInfo * Info)400 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
401
isUnconditionalBranch(const MCInst & Inst) const402 bool isUnconditionalBranch(const MCInst &Inst) const override {
403 // BCCs with the "always" predicate are unconditional branches.
404 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
405 return true;
406 return MCInstrAnalysis::isUnconditionalBranch(Inst);
407 }
408
isConditionalBranch(const MCInst & Inst) const409 bool isConditionalBranch(const MCInst &Inst) const override {
410 // BCCs with the "always" predicate are unconditional branches.
411 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
412 return false;
413 return MCInstrAnalysis::isConditionalBranch(Inst);
414 }
415
evaluateBranch(const MCInst & Inst,uint64_t Addr,uint64_t Size,uint64_t & Target) const416 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
417 uint64_t &Target) const override {
418 const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
419
420 // Find the PC-relative immediate operand in the instruction.
421 for (unsigned OpNum = 0; OpNum < Desc.getNumOperands(); ++OpNum) {
422 if (Inst.getOperand(OpNum).isImm() &&
423 Desc.operands()[OpNum].OperandType == MCOI::OPERAND_PCREL) {
424 int64_t Imm = Inst.getOperand(OpNum).getImm();
425 Target = ARM_MC::evaluateBranchTarget(Desc, Addr, Imm);
426 return true;
427 }
428 }
429 return false;
430 }
431
432 std::optional<uint64_t>
433 evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI,
434 uint64_t Addr, uint64_t Size) const override;
435
436 std::vector<std::pair<uint64_t, uint64_t>>
437 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
438 const MCSubtargetInfo &STI) const override;
439 };
440
441 } // namespace
442
443 static std::optional<uint64_t>
444 // NOLINTNEXTLINE(readability-identifier-naming)
evaluateMemOpAddrForAddrMode_i12(const MCInst & Inst,const MCInstrDesc & Desc,unsigned MemOpIndex,uint64_t Addr)445 evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc,
446 unsigned MemOpIndex, uint64_t Addr) {
447 if (MemOpIndex + 1 >= Desc.getNumOperands())
448 return std::nullopt;
449
450 const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
451 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
452 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
453 return std::nullopt;
454
455 int32_t OffImm = (int32_t)MO2.getImm();
456 // Special value for #-0. All others are normal.
457 if (OffImm == INT32_MIN)
458 OffImm = 0;
459 return Addr + OffImm;
460 }
461
462 static std::optional<uint64_t>
evaluateMemOpAddrForAddrMode3(const MCInst & Inst,const MCInstrDesc & Desc,unsigned MemOpIndex,uint64_t Addr)463 evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc,
464 unsigned MemOpIndex, uint64_t Addr) {
465 if (MemOpIndex + 2 >= Desc.getNumOperands())
466 return std::nullopt;
467
468 const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
469 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
470 const MCOperand &MO3 = Inst.getOperand(MemOpIndex + 2);
471 if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm())
472 return std::nullopt;
473
474 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
475 ARM_AM::AddrOpc Op = ARM_AM::getAM3Op(MO3.getImm());
476
477 if (Op == ARM_AM::sub)
478 return Addr - ImmOffs;
479 return Addr + ImmOffs;
480 }
481
482 static std::optional<uint64_t>
evaluateMemOpAddrForAddrMode5(const MCInst & Inst,const MCInstrDesc & Desc,unsigned MemOpIndex,uint64_t Addr)483 evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc,
484 unsigned MemOpIndex, uint64_t Addr) {
485 if (MemOpIndex + 1 >= Desc.getNumOperands())
486 return std::nullopt;
487
488 const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
489 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
490 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
491 return std::nullopt;
492
493 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
494 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm());
495
496 if (Op == ARM_AM::sub)
497 return Addr - ImmOffs * 4;
498 return Addr + ImmOffs * 4;
499 }
500
501 static std::optional<uint64_t>
evaluateMemOpAddrForAddrMode5FP16(const MCInst & Inst,const MCInstrDesc & Desc,unsigned MemOpIndex,uint64_t Addr)502 evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc,
503 unsigned MemOpIndex, uint64_t Addr) {
504 if (MemOpIndex + 1 >= Desc.getNumOperands())
505 return std::nullopt;
506
507 const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
508 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
509 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
510 return std::nullopt;
511
512 unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());
513 ARM_AM::AddrOpc Op = ARM_AM::getAM5FP16Op(MO2.getImm());
514
515 if (Op == ARM_AM::sub)
516 return Addr - ImmOffs * 2;
517 return Addr + ImmOffs * 2;
518 }
519
520 static std::optional<uint64_t>
521 // NOLINTNEXTLINE(readability-identifier-naming)
evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst & Inst,const MCInstrDesc & Desc,unsigned MemOpIndex,uint64_t Addr)522 evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc,
523 unsigned MemOpIndex, uint64_t Addr) {
524 if (MemOpIndex + 1 >= Desc.getNumOperands())
525 return std::nullopt;
526
527 const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
528 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
529 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
530 return std::nullopt;
531
532 int32_t OffImm = (int32_t)MO2.getImm();
533 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
534
535 // Special value for #-0. All others are normal.
536 if (OffImm == INT32_MIN)
537 OffImm = 0;
538 return Addr + OffImm;
539 }
540
541 static std::optional<uint64_t>
542 // NOLINTNEXTLINE(readability-identifier-naming)
evaluateMemOpAddrForAddrModeT2_pc(const MCInst & Inst,const MCInstrDesc & Desc,unsigned MemOpIndex,uint64_t Addr)543 evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc,
544 unsigned MemOpIndex, uint64_t Addr) {
545 const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
546 if (!MO1.isImm())
547 return std::nullopt;
548
549 int32_t OffImm = (int32_t)MO1.getImm();
550
551 // Special value for #-0. All others are normal.
552 if (OffImm == INT32_MIN)
553 OffImm = 0;
554 return Addr + OffImm;
555 }
556
557 static std::optional<uint64_t>
558 // NOLINTNEXTLINE(readability-identifier-naming)
evaluateMemOpAddrForAddrModeT1_s(const MCInst & Inst,const MCInstrDesc & Desc,unsigned MemOpIndex,uint64_t Addr)559 evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc,
560 unsigned MemOpIndex, uint64_t Addr) {
561 return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex, Addr);
562 }
563
evaluateMemoryOperandAddress(const MCInst & Inst,const MCSubtargetInfo * STI,uint64_t Addr,uint64_t Size) const564 std::optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(
565 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
566 uint64_t Size) const {
567 const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
568
569 // Only load instructions can have PC-relative memory addressing.
570 if (!Desc.mayLoad())
571 return std::nullopt;
572
573 // PC-relative addressing does not update the base register.
574 uint64_t TSFlags = Desc.TSFlags;
575 unsigned IndexMode =
576 (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
577 if (IndexMode != ARMII::IndexModeNone)
578 return std::nullopt;
579
580 // Find the memory addressing operand in the instruction.
581 unsigned OpIndex = Desc.NumDefs;
582 while (OpIndex < Desc.getNumOperands() &&
583 Desc.operands()[OpIndex].OperandType != MCOI::OPERAND_MEMORY)
584 ++OpIndex;
585 if (OpIndex == Desc.getNumOperands())
586 return std::nullopt;
587
588 // Base address for PC-relative addressing is always 32-bit aligned.
589 Addr &= ~0x3;
590
591 // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
592 // is 4 bytes.
593 switch (Desc.TSFlags & ARMII::FormMask) {
594 default:
595 Addr += 8;
596 break;
597 case ARMII::ThumbFrm:
598 Addr += 4;
599 break;
600 // VLDR* instructions share the same opcode (and thus the same form) for Arm
601 // and Thumb. Use a bit longer route through STI in that case.
602 case ARMII::VFPLdStFrm:
603 Addr += STI->hasFeature(ARM::ModeThumb) ? 4 : 8;
604 break;
605 }
606
607 // Eveluate the address depending on the addressing mode
608 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
609 switch (AddrMode) {
610 default:
611 return std::nullopt;
612 case ARMII::AddrMode_i12:
613 return evaluateMemOpAddrForAddrMode_i12(Inst, Desc, OpIndex, Addr);
614 case ARMII::AddrMode3:
615 return evaluateMemOpAddrForAddrMode3(Inst, Desc, OpIndex, Addr);
616 case ARMII::AddrMode5:
617 return evaluateMemOpAddrForAddrMode5(Inst, Desc, OpIndex, Addr);
618 case ARMII::AddrMode5FP16:
619 return evaluateMemOpAddrForAddrMode5FP16(Inst, Desc, OpIndex, Addr);
620 case ARMII::AddrModeT2_i8s4:
621 return evaluateMemOpAddrForAddrModeT2_i8s4(Inst, Desc, OpIndex, Addr);
622 case ARMII::AddrModeT2_pc:
623 return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, OpIndex, Addr);
624 case ARMII::AddrModeT1_s:
625 return evaluateMemOpAddrForAddrModeT1_s(Inst, Desc, OpIndex, Addr);
626 }
627 }
628
629 template <typename T, size_t N>
instructionsMatch(const T (& Insns)[N],const uint8_t * Buf,llvm::endianness E)630 static bool instructionsMatch(const T (&Insns)[N], const uint8_t *Buf,
631 llvm::endianness E) {
632 for (size_t I = 0; I < N; ++I) {
633 T Val = support::endian::read<T>(Buf + I * sizeof(T), E);
634 if (Val != Insns[I])
635 return false;
636 }
637 return true;
638 }
639
640 std::vector<std::pair<uint64_t, uint64_t>>
findPltEntries(uint64_t PltSectionVA,ArrayRef<uint8_t> PltContents,const MCSubtargetInfo & STI) const641 ARMMCInstrAnalysis::findPltEntries(uint64_t PltSectionVA,
642 ArrayRef<uint8_t> PltContents,
643 const MCSubtargetInfo &STI) const {
644 llvm::endianness DataEndianness = STI.getTargetTriple().isLittleEndian()
645 ? endianness::little
646 : endianness::big;
647 llvm::endianness InstrEndianness =
648 STI.checkFeatures("+big-endian-instructions") ? endianness::big
649 : endianness::little;
650
651 // Do a lightweight parsing of PLT entries.
652 std::vector<std::pair<uint64_t, uint64_t>> Result;
653 if (STI.checkFeatures("+thumb-mode")) {
654 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 12 < End;
655 Byte += 16) {
656 // Expected instruction sequence:
657 //
658 // movw ip, #lower16
659 // movt ip, #upper16
660 // add ip, pc
661 // ldr.w pc, [ip]
662 // b . -4
663
664 uint32_t MovwPart1 =
665 support::endian::read16(PltContents.data() + Byte, InstrEndianness);
666 if ((MovwPart1 & 0xffb0) != 0xf200)
667 continue;
668
669 uint32_t MovwPart2 = support::endian::read16(
670 PltContents.data() + Byte + 2, InstrEndianness);
671 if ((MovwPart2 & 0x8f00) != 0xc00)
672 continue;
673
674 uint64_t OffsetLower = (MovwPart2 & 0xff) + ((MovwPart2 & 0x7000) >> 4) +
675 ((MovwPart1 & 0x400) << 1) +
676 ((MovwPart1 & 0xf) << 12);
677
678 uint32_t MovtPart1 = support::endian::read16(
679 PltContents.data() + Byte + 4, InstrEndianness);
680 if ((MovtPart1 & 0xfbf0) != 0xf2c0)
681 continue;
682
683 uint32_t MovtPart2 = support::endian::read16(
684 PltContents.data() + Byte + 6, InstrEndianness);
685 if ((MovtPart2 & 0x8f00) != 0xc00)
686 continue;
687
688 uint64_t OffsetHigher =
689 ((MovtPart2 & 0xff) << 16) + ((MovtPart2 & 0x7000) << 12) +
690 ((MovtPart1 & 0x400) << 17) + ((MovtPart1 & 0xf) << 28);
691
692 const uint16_t Insns[] = {
693 0x44fc, // add ip, pc
694 0xf8dc, 0xf000, // ldr.w pc, [ip]
695 0xe7fc, // b . -4
696 };
697
698 if (!instructionsMatch(Insns, PltContents.data() + Byte + 8,
699 InstrEndianness))
700 continue;
701
702 // add ip, pc at Byte + 8 + thumb-pc-bias = 12
703 uint64_t Offset = (PltSectionVA + Byte + 12) + OffsetLower + OffsetHigher;
704 Result.emplace_back(PltSectionVA + Byte, Offset);
705 }
706 } else {
707 const uint32_t LongEntryInsns[] = {
708 0xe59fc004, // ldr ip, L2
709 0xe08cc00f, // L1: add ip, ip, pc
710 0xe59cf000, // ldr pc, [ip]
711 };
712
713 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 12 < End;
714 Byte += 4) {
715 // Is it a long entry?
716 if (instructionsMatch(LongEntryInsns, PltContents.data() + Byte,
717 InstrEndianness)) {
718 // Expected instruction sequence:
719 //
720 // ldr ip, L2
721 // L1: add ip, ip, pc
722 // ldr pc, [ip]
723 // L2: .word Offset(&(.got.plt) - L1 - 8
724
725 uint64_t Offset = (PltSectionVA + Byte + 12) +
726 support::endian::read32(
727 PltContents.data() + Byte + 12, DataEndianness);
728 Result.emplace_back(PltSectionVA + Byte, Offset);
729 Byte += 12;
730 } else {
731 // Expected instruction sequence:
732 //
733 // L1: add ip, pc, #0x0NN00000 Offset(&(.got.plt) - L1 - 8
734 // add ip, ip, #0x000NN000 Offset(&(.got.plt) - L1 - 8
735 // ldr pc, [ip, #0x00000NNN] Offset(&(.got.plt) - L1 - 8
736
737 uint32_t Add1 =
738 support::endian::read32(PltContents.data() + Byte, InstrEndianness);
739 if ((Add1 & 0xe28fc600) != 0xe28fc600)
740 continue;
741 uint32_t Add2 = support::endian::read32(PltContents.data() + Byte + 4,
742 InstrEndianness);
743 if ((Add2 & 0xe28cca00) != 0xe28cca00)
744 continue;
745 uint32_t Ldr = support::endian::read32(PltContents.data() + Byte + 8,
746 InstrEndianness);
747 if ((Ldr & 0xe5bcf000) != 0xe5bcf000)
748 continue;
749
750 // add ip, pc, #offset at Byte + 0 + arm-pc-bias = 8
751 uint64_t Offset = (PltSectionVA + Byte + 8) + ((Add1 & 0xff) << 20) +
752 ((Add2 & 0xff) << 12) + (Ldr & 0xfff);
753 Result.emplace_back(PltSectionVA + Byte, Offset);
754 Byte += 8;
755 }
756 }
757 }
758 return Result;
759 }
760
createARMMCInstrAnalysis(const MCInstrInfo * Info)761 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
762 return new ARMMCInstrAnalysis(Info);
763 }
764
isCDECoproc(size_t Coproc,const MCSubtargetInfo & STI)765 bool ARM::isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI) {
766 // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
767 // to rely on feature bits.
768 if (Coproc >= 8)
769 return false;
770 return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc];
771 }
772
773 // Force static initialization.
LLVMInitializeARMTargetMC()774 extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC() {
775 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),
776 &getTheThumbLETarget(), &getTheThumbBETarget()}) {
777 // Register the MC asm info.
778 RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
779
780 // Register the MC instruction info.
781 TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo);
782
783 // Register the MC register info.
784 TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo);
785
786 // Register the MC subtarget info.
787 TargetRegistry::RegisterMCSubtargetInfo(*T,
788 ARM_MC::createARMMCSubtargetInfo);
789
790 TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
791 TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer);
792 TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer);
793
794 // Register the obj target streamer.
795 TargetRegistry::RegisterObjectTargetStreamer(*T,
796 createARMObjectTargetStreamer);
797
798 // Register the asm streamer.
799 TargetRegistry::RegisterAsmTargetStreamer(*T, createARMTargetAsmStreamer);
800
801 // Register the null TargetStreamer.
802 TargetRegistry::RegisterNullTargetStreamer(*T, createARMNullTargetStreamer);
803
804 // Register the MCInstPrinter.
805 TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter);
806
807 // Register the MC relocation info.
808 TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo);
809 }
810
811 // Register the MC instruction analyzer.
812 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),
813 &getTheThumbLETarget(), &getTheThumbBETarget()})
814 TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis);
815
816 for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) {
817 TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter);
818 TargetRegistry::RegisterMCAsmBackend(*T, createARMLEAsmBackend);
819 }
820 for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) {
821 TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter);
822 TargetRegistry::RegisterMCAsmBackend(*T, createARMBEAsmBackend);
823 }
824 }
825