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Searched defs:Offset0 (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp190 int64_t Offset0 = 0; in getHazardType() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp394 int64_t Offset0; in apply() local
H A DHexagonISelLoweringHVX.cpp2233 SDValue Offset0 = DAG.getTargetConstant(0, dl, ty(Base)); in LowerHvxMaskedOp() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp1266 bool AMDGPUDAGToDAGISel::isDSOffset2Legal(SDValue Base, unsigned Offset0, in isDSOffset2Legal()
1360 SDValue &Offset0, in SelectDS64Bit4ByteAligned()
1366 SDValue &Offset0, in SelectDS128Bit8ByteAligned()
1372 SDValue &Offset0, SDValue &Offset1, in SelectDSReadWrite2()
H A DSIInstrInfo.cpp237 int64_t &Offset0, in areLoadsFromSameBasePtr()
403 unsigned Offset0 = Offset0Op->getImm() & 0xff; in getMemOperandsWithOffsetWidth() local
612 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear()
3826 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local
H A DAMDGPUInstructionSelector.cpp1802 unsigned Offset0 = OrderedCountIndex << 2; in selectDSOrderedIntrinsic() local
5734 bool AMDGPUInstructionSelector::isDSOffset2Legal(Register Base, int64_t Offset0, in isDSOffset2Legal()
H A DSIISelLowering.cpp9474 unsigned Offset0 = OrderedCountIndex << 2; in LowerINTRINSIC_W_CHAIN() local
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DConstantFolding.cpp1273 APInt Offset0(IndexWidth, 0); in ConstantFoldCompareInstOperands() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp19630 const APInt &Offset0 = CN->getAPIntValue(); in CombineToPreIndexedLoadStore() local
21961 int64_t Offset0 = LoadNodes[0].OffsetFromBase; in tryStoreMergeOfLoads() local
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp6413 bool Offset0 = false, Offset1 = false; in getFauxShuffleMask() local