xref: /illumos-gate/usr/src/uts/common/io/dmfe/dmfe.h (revision 2d6eb4a5e0a47d30189497241345dc5466bb68ab)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _SYS_DMFE_H
27 #define	_SYS_DMFE_H
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
33 /* Chip ID */
34 #define	DAVICOM_VENDOR_ID	0x1282
35 #define	DEVICE_ID_9100		0x9100
36 #define	DEVICE_ID_9132		0x9132
37 /* The 9102 and 9102A are distinguished by revision ID */
38 #define	DEVICE_ID_9102		0x9102
39 #define	DEVICE_ID_9102A		0x9102
40 
41 /* Streams */
42 #define	DMFEHIWAT		32768	/* driver flow control high water */
43 #define	DMFELOWAT		4096	/* driver flow control low water */
44 #define	DMFEIDNUM		0	/* DMFE Id; zero works */
45 
46 /* Size/count parameters */
47 #define	SROM_SIZE		128
48 #define	SETUPBUF_SIZE		192	/* Setup buffer size in bytes */
49 #define	MCASTBUF_SIZE		512	/* multicast hash table size in bits */
50 #define	HASH_POLY		0x04C11DB6
51 #define	HASH_CRC		0xFFFFFFFFU
52 #define	SETUPBUF_PHYS		39	/* word offset of station physical */
53 					/* address within setup buffer */
54 
55 
56 /*
57  * Tx/Rx descriptor ring entry formats
58  *
59  * These structures are not actually used; they are just here to show
60  * the layout of the descriptor entries used by the DMFE chip hardware
61  * (we do use "sizeof" these structures).  The code uses the #defined
62  * offsets below to access the various members of the descriptors, via
63  * the DDI access functions (remember the DMFE h/w is little-endian).
64  */
65 
66 struct rx_desc_type {
67 	uint32_t	desc0;
68 	uint32_t	desc1;
69 	uint32_t	buffer1;
70 	uint32_t	rd_next;
71 };
72 
73 struct tx_desc_type {
74 	uint32_t	desc0;
75 	uint32_t	desc1;
76 	uint32_t	buffer1;
77 	uint32_t	td_next;
78 };
79 
80 /*
81  * Offsets & sizes for tx/rx descriptors, expressed in (d)words
82  */
83 #define	DESC0			0
84 #define	DESC1			1
85 #define	BUFFER1			2
86 #define	RD_NEXT			3
87 #define	TD_NEXT			3
88 #define	DESC_SIZE		4
89 
90 /*
91  * Receive descriptor description
92  */
93 /* desc0 bit definitions */
94 #define	RX_OVERFLOW		(1UL<<0)
95 #define	RX_CRC			(1UL<<1)
96 #define	RX_DRIBBLING		(1UL<<2)
97 #define	RX_MII_ERR		(1UL<<3)
98 #define	RX_RCV_WD_TO		(1UL<<4)
99 #define	RX_FRAME_TYPE		(1UL<<5)
100 #define	RX_COLLISION		(1UL<<6)
101 #define	RX_FRAME2LONG		(1UL<<7)
102 #define	RX_LAST_DESC		(1UL<<8)
103 #define	RX_FIRST_DESC		(1UL<<9)
104 #define	RX_MULTI_FRAME		(1UL<<10)
105 #define	RX_RUNT_FRAME		(1UL<<11)
106 #define	RX_LOOP_MODE		(3UL<<12)
107 #define	RX_DESC_ERR		(1UL<<14)
108 #define	RX_ERR_SUMMARY		(1UL<<15)
109 #define	RX_FRAME_LEN		(0x3fffUL<<16)
110 #define	RX_FILTER_FAIL		(1UL<<30)
111 #define	RX_OWN			(1UL<<31)
112 
113 /* desc1 bit definitions */
114 #define	RX_BUFFER_SIZE		(0x7ff)
115 #define	RX_CHAINING		(1UL<<24)
116 #define	RX_END_OF_RING		(1UL<<25)
117 
118 /*
119  * Transmit descriptor description
120  */
121 /* desc0 bit definitions */
122 #define	TX_DEFERRED		(1UL<<0)
123 #define	TX_UNDERFLOW		(1UL<<1)
124 #define	TX_LINK_FAIL		(1UL<<2)
125 #define	TX_COLL_COUNT		(0xfUL<<3)
126 #define	TX_HEARTBEAT_FAIL	(1UL<<7)
127 #define	TX_EXCESS_COLL		(1UL<<8)
128 #define	TX_LATE_COLL		(1UL<<9)
129 #define	TX_NO_CARRIER		(1UL<<10)
130 #define	TX_CARRIER_LOSS		(1UL<<11)
131 #define	TX_JABBER_TO		(1UL<<14)
132 #define	TX_ERR_SUMMARY		(1UL<<15)
133 #define	TX_SPARE		(0x7fffUL<<16)
134 #define	TX_OWN			(1UL<<31)
135 
136 /* desc1 bit definitions */
137 #define	TX_BUFFER_SIZE1		(0x7ffUL<<0)
138 #define	TX_BUFFER_SIZE2		(0x7ffUL<<11)
139 #define	TX_FILTER_TYPE0		(1UL<<22)
140 #define	TX_DISABLE_PAD		(1UL<<23)
141 #define	TX_CHAINING		(1UL<<24)
142 #define	TX_END_OF_RING		(1UL<<25)
143 #define	TX_CRC_DISABLE		(1UL<<26)
144 #define	TX_SETUP_PACKET		(1UL<<27)
145 #define	TX_FILTER_TYPE1		(1UL<<28)
146 #define	TX_FIRST_DESC		(1UL<<29)
147 #define	TX_LAST_DESC		(1UL<<30)
148 #define	TX_INT_ON_COMP		(1UL<<31)
149 
150 
151 /* Device-defined PCI config space registers */
152 #define	PCI_DMFE_CONF_CFDD	0x40
153 #define	CFDD_SNOOZE		(1UL<<30)
154 #define	CFDD_SLEEP		(1UL<<31)
155 
156 
157 /* Operating registers in I/O or MEMORY space */
158 #define	BUS_MODE_REG		0x00
159 #define	TX_POLL_REG		0x08
160 #define	RX_POLL_REG		0x10
161 #define	RX_BASE_ADDR_REG	0x18
162 #define	TX_BASE_ADDR_REG	0x20
163 #define	STATUS_REG		0x28
164 #define	OPN_MODE_REG		0x30
165 #define	INT_MASK_REG		0x38
166 #define	MISSED_FRAME_REG	0x40
167 #define	ETHER_ROM_REG		0x48
168 #define	BOOT_ROM_REG		0x50
169 #define	GP_TIMER_REG		0x58
170 #define	PHY_STATUS_REG		0x60
171 #define	FRAME_ACCESS_REG	0x68
172 #define	FRAME_DATA_REG		0x70
173 #define	W_J_TIMER_REG		0x78
174 
175 
176 /* Bit descriptions of CSR registers */
177 
178 /* BUS_MODE_REG, CSR0 */
179 #define	SW_RESET		0x00000001
180 #define	BURST_SIZE		0		/* unlimited burst length */
181 #define	CACHE_ALIGN		(3 << 14)	/* 32 Dwords		*/
182 #define	TX_POLL_INTVL		(1 << 17)	/* 200us polling	*/
183 #define	READ_MULTIPLE		(1 << 21) 	/* use Memory Read	*/
184 						/* Multiple PCI cycles	*/
185 
186 /* STATUS_REG, CSR5 */
187 #define	TX_PKTDONE_INT		0x00000001UL
188 #define	TX_STOPPED_INT		0x00000002UL
189 #define	TX_ALLDONE_INT		0x00000004UL
190 #define	TX_JABBER_INT		0x00000008UL
191 #define	TX_RESERVED_INT		0x00000010UL
192 #define	TX_UNDERFLOW_INT	0x00000020UL
193 
194 #define	RX_PKTDONE_INT		0x00000040UL
195 #define	RX_UNAVAIL_INT		0x00000080UL
196 #define	RX_STOPPED_INT		0x00000100UL
197 #define	RX_WATCHDOG_INT		0x00000200UL
198 
199 #define	TX_EARLY_INT		0x00000400UL
200 #define	GP_TIMER_INT		0x00000800UL
201 #define	LINK_STATUS_INT		0x00001000UL
202 #define	SYSTEM_ERR_INT		0x00002000UL
203 #define	RX_EARLY_INT		0x00004000UL
204 
205 #define	ABNORMAL_SUMMARY_INT	0x00008000UL
206 #define	NORMAL_SUMMARY_INT	0x00010000UL
207 #define	INT_STATUS_MASK		0x0001ffffUL
208 
209 #define	RX_PROCESS_STOPPED	0x00000000UL
210 #define	RX_PROCESS_FETCH_DESC	0x00020000UL
211 #define	RX_PROCESS_WAIT_PKT	0x00040000UL
212 #define	RX_PROCESS_STORE_DATA	0x00060000UL
213 #define	RX_PROCESS_CLOSE_OWNER	0x00080000UL
214 #define	RX_PROCESS_CLOSE_STATUS	0x000a0000UL
215 #define	RX_PROCESS_SUSPEND	0x000c0000UL
216 #define	RX_PROCESS_PURGE	0x000e0000UL
217 #define	RX_PROCESS_STATE_MASK	0x000e0000UL
218 #define	TX_PROCESS_STOPPED	0x00000000UL
219 #define	TX_PROCESS_FETCH_DESC	0x00100000UL
220 #define	TX_PROCESS_FETCH_SETUP	0x00200000UL
221 #define	TX_PROCESS_FETCH_DATA	0x00300000UL
222 #define	TX_PROCESS_CLOSE_OWNER	0x00400000UL
223 #define	TX_PROCESS_WAIT_END	0x00500000UL
224 #define	TX_PROCESS_CLOSE_STATUS	0x00600000UL
225 #define	TX_PROCESS_SUSPEND	0x00700000UL
226 #define	TX_PROCESS_STATE_MASK	0x00700000UL
227 #define	SYSTEM_ERR_BITS		0x03800000UL
228 #define	SYSTEM_ERR_PARITY	0x00000000UL
229 #define	SYSTEM_ERR_M_ABORT	0x00800000UL
230 #define	SYSTEM_ERR_T_ABORT	0x01000000UL
231 
232 #define	RX_PROCESS_STATE(csr5)	(((csr5) & RX_PROCESS_STATE_MASK) >> 17)
233 #define	RX_PROCESS_MAX_STATE	7
234 #define	TX_PROCESS_STATE(csr5)	(((csr5) & TX_PROCESS_STATE_MASK) >> 20)
235 #define	TX_PROCESS_MAX_STATE	7
236 
237 /* OPN_REG , CSR6 */
238 #define	HASH_FILTERING		(1UL<<0)
239 #define	START_RECEIVE		(1UL<<1)
240 #define	HASH_ONLY		(1UL<<2)
241 #define	PASSBAD			(1UL<<3)
242 #define	INV_FILTER		(1UL<<4)
243 #define	PROMISC_MODE		(1UL<<6)
244 #define	PASS_MULTICAST		(1UL<<7)
245 #define	FULL_DUPLEX		(1UL<<9)
246 #define	LOOPBACK_OFF		(0UL<<10)
247 #define	LOOPBACK_INTERNAL	(1UL<<10)
248 #define	LOOPBACK_PHY_D		(2UL<<10)
249 #define	LOOPBACK_PHY_A		(3UL<<10)
250 #define	LOOPBACK_MODE_MASK	(3UL<<10)
251 #define	FORCE_COLLISION		(1UL<<12)
252 #define	START_TRANSMIT 		(1UL<<13)
253 #define	TX_THRESHOLD_LOW	(0UL<<14)
254 #define	TX_THRESHOLD_MID	(1UL<<14)
255 #define	TX_THRESHOLD_HI		(2UL<<14)
256 #define	TX_THRESHOLD_MASK	(3UL<<14)
257 #define	ONE_PKT_MODE		(1UL<<16)
258 #define	EXT_MII_IF		(1UL<<18)
259 #define	START_TX_IMMED		(1UL<<20)
260 #define	STORE_AND_FORWARD	(1UL<<21)
261 #define	TX_THRESHOLD_MODE	(1UL<<22)
262 #define	OPN_25_MB1		(1UL<<25)
263 #define	NO_RX_PURGE		(1UL<<29)
264 #define	RECEIVEALL		(1UL<<30)
265 
266 /* INT_MASK_REG , CSR7 */
267 /*
268  * Use the values defined for the INT_STATUS_MASK bits (0..16)
269  * of CSR5.  The remaining bits (17..31) are not used.
270  */
271 
272 /* MISSED_FRAME_REG, CSR8 */
273 #define	MISSED_FRAME_MASK	0x00000ffffUL
274 #define	MISSED_OVERFLOW		0x000010000UL
275 #define	PURGED_PACKET_MASK	0x07ffe0000UL
276 #define	PURGED_OVERFLOW		0x080000000UL
277 
278 /* Serial ROM/MII Register CSR9 */
279 #define	SEL_CHIP		0x00000001UL
280 #define	SEL_CLK			0x00000002UL
281 #define	DATA_IN			0x00000004UL
282 #define	DATA_OUT		0x00000008UL
283 #define	SER_8_MB1		0x00000300UL
284 #define	SEL_XRS			0x00000400UL
285 #define	SEL_EEPROM		0x00000800UL
286 #define	SEL_BOOTROM		0x00001000UL
287 #define	WRITE_OP		0x00002000UL
288 #define	READ_OP			0x00004000UL
289 #define	SER_15_MB1		0x00008000UL
290 #define	READ_EEPROM		(READ_OP | SEL_EEPROM)
291 #define	READ_EEPROM_CS		(READ_OP | SEL_EEPROM | SEL_CHIP)
292 
293 #define	MII_CLOCK		0x00010000UL
294 #define	MII_DATA_OUT		0x00020000UL
295 #define	MII_DATA_OUT_SHIFT	17
296 #define	MII_READ		0x00040000UL
297 #define	MII_TRISTATE		0x00040000UL
298 #define	MII_WRITE		0x00000000UL
299 #define	MII_DATA_IN		0x00080000UL
300 #define	MII_DATA_IN_SHIFT	19
301 
302 #define	RELOAD_EEPROM		0x00100000UL
303 #define	LOADED_EEPROM		0x00200000UL
304 
305 /* GPR Timer reg, CSR11 */
306 #define	GPTIMER_CONT		(1UL<<16)
307 
308 /* PHY Status reg, CSR12 */
309 #define	GPS_LINK_10		0x00000001UL
310 #define	GPS_LINK_100		0x00000002UL
311 #define	GPS_FULL_DUPLEX		0x00000004UL
312 #define	GPS_LINK_STATUS		0x00000008UL
313 #define	GPS_RX_LOCK		0x00000010UL
314 #define	GPS_SIGNAL_DETECT	0x00000020UL
315 #define	GPS_UTP_SIG		0x00000040UL
316 #define	GPS_PHY_RESET		0x00000080UL
317 #define	GPS_WRITE_ENABLE	0x00000100UL
318 
319 /* Sample Frame Access reg, CSR13 */
320 #define	TX_FIFO_ACCESS		(0x32<<3)
321 #define	RX_FIFO_ACCESS		(0x35<<3)
322 #define	DIAG_RESET		(0x38<<3)
323 
324 /* Sample Frame Data reg, CSR14, when CSR13 is set to DIAG_RESET */
325 #define	DIAG_TX_FIFO_WRITE_0	0x00000001UL
326 #define	DIAG_TX_FIFO_READ_0	0x00000002UL
327 #define	DIAG_RX_FIFO_WRITE_0	0x00000004UL
328 #define	DIAG_RX_FIFO_READ_0	0x00000008UL
329 #define	DIAG_TX_FIFO_WRITE_100	0x00000020UL
330 #define	DIAG_RX_FIFO_WRITE_100	0x00000040UL
331 
332 /* CSR15 */
333 #define	TX_JABBER_DISABLE	0x00000001UL
334 #define	UNJABBER_INTERVAL	0x00000002UL
335 #define	JABBER_CLOCK		0x00000004UL
336 #define	WD_TIMER_DISABLE	0x00000010UL
337 #define	WD_TIMER_RELEASE	0x00000020UL
338 #define	VLAN_ENABLE		0x00000040UL
339 #define	PAUSE_STATUS_1		0x00000080UL
340 #define	PAUSE_STATUS_2		0x00000200UL
341 #define	FLOW_CONTROL		0x00000400UL
342 #define	PAUSE_ENABLE_1		0x00000800UL
343 #define	PAUSE_ENABLE_2		0x00001000UL
344 #define	PAUSE_TX_FFFF		0x00002000UL
345 #define	PAUSE_TX_0000		0x00004000UL
346 #define	PAUSE_CONDITION		0x00008000UL
347 #define	RX_FIFO_THRES_MASK	0x003f0000UL
348 #define	RX_EARLY_THRES_MASK	0x01c00000UL
349 
350 
351 /* SROM access definitions */
352 #define	HIGH_ADDRESS_BIT	0x20			/* 6 bits */
353 #define	HIGH_CMD_BIT		0x4			/* 3 bits */
354 #define	HIGH_DATA_BIT		0x8000			/* 16 bits */
355 #define	SROM_DELAY		5			/* 5 microseconds */
356 #define	EEPROM_READ_CMD		6
357 #define	EEPROM_EN_ADDR		20
358 
359 /* MII access definitions */
360 #define	MII_REG_ADDR_SHIFT	18
361 #define	MII_PHY_ADDR_SHIFT	23
362 #define	MII_DELAY		1			/* 1 microsecond */
363 #define	MII_PREAMBLE		0xffffffffUL
364 #define	MII_READ_FRAME		0x60000000UL
365 #define	MII_WRITE_FRAME		0x50020000UL
366 
367 
368 /* DMFE IOCTLS */
369 #define	ND_BASE			('N' << 8)	/* base */
370 #define	ND_GET			(ND_BASE + 0)	/* Get a value */
371 #define	ND_SET			(ND_BASE + 1)	/* Set a value */
372 
373 #define	DMFE_ND_GET		ND_GET
374 #define	DMFE_ND_SET		ND_SET
375 
376 #define	DMFEIOC			('G' << 8)
377 #define	DMFE_SET_LOOP_MODE	(DMFEIOC|1)
378 #define	DMFE_GET_LOOP_MODE	(DMFEIOC|2)
379 
380 /* argument structure for above */
381 typedef struct {
382 	int loopback;
383 } loopback_t;
384 
385 #define	DMFE_LOOPBACK_OFF	0
386 #define	DMFE_PHY_A_LOOPBACK_ON	1
387 #define	DMFE_PHY_D_LOOPBACK_ON	2
388 #define	DMFE_INT_LOOPBACK_ON	4
389 #define	DMFE_LOOPBACK_MODES	7	/* Bitwise OR of above	*/
390 
391 #ifdef __cplusplus
392 }
393 #endif
394 
395 #endif	/* _SYS_DMFE_H */
396