1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the SelectionDAGISel class, which is used as the common 10 // base class for SelectionDAG-based instruction selectors. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H 15 #define LLVM_CODEGEN_SELECTIONDAGISEL_H 16 17 #include "llvm/Analysis/AliasAnalysis.h" 18 #include "llvm/CodeGen/MachineFunctionPass.h" 19 #include "llvm/CodeGen/MachinePassManager.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/IR/BasicBlock.h" 22 #include <memory> 23 24 namespace llvm { 25 class AAResults; 26 class AssumptionCache; 27 class TargetInstrInfo; 28 class TargetMachine; 29 class SSPLayoutInfo; 30 class SelectionDAGBuilder; 31 class SDValue; 32 class MachineRegisterInfo; 33 class MachineFunction; 34 class OptimizationRemarkEmitter; 35 class TargetLowering; 36 class TargetLibraryInfo; 37 class TargetTransformInfo; 38 class FunctionLoweringInfo; 39 class SwiftErrorValueTracking; 40 class GCFunctionInfo; 41 class ScheduleDAGSDNodes; 42 43 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based 44 /// pattern-matching instruction selectors. 45 class SelectionDAGISel { 46 public: 47 TargetMachine &TM; 48 const TargetLibraryInfo *LibInfo; 49 std::unique_ptr<FunctionLoweringInfo> FuncInfo; 50 std::unique_ptr<SwiftErrorValueTracking> SwiftError; 51 MachineFunction *MF; 52 MachineModuleInfo *MMI; 53 MachineRegisterInfo *RegInfo; 54 SelectionDAG *CurDAG; 55 std::unique_ptr<SelectionDAGBuilder> SDB; 56 mutable std::optional<BatchAAResults> BatchAA; 57 AssumptionCache *AC = nullptr; 58 GCFunctionInfo *GFI = nullptr; 59 SSPLayoutInfo *SP = nullptr; 60 TargetTransformInfo *TTI = nullptr; 61 CodeGenOptLevel OptLevel; 62 const TargetInstrInfo *TII; 63 const TargetLowering *TLI; 64 bool FastISelFailed; 65 SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs; 66 67 /// Current optimization remark emitter. 68 /// Used to report things like combines and FastISel failures. 69 std::unique_ptr<OptimizationRemarkEmitter> ORE; 70 71 /// True if the function currently processing is in the function printing list 72 /// (i.e. `-filter-print-funcs`). 73 /// This is primarily used by ISEL_DUMP, which spans in multiple member 74 /// functions. Storing the filter result here so that we only need to do the 75 /// filtering once. 76 bool MatchFilterFuncName = false; 77 StringRef FuncName; 78 79 explicit SelectionDAGISel(TargetMachine &tm, 80 CodeGenOptLevel OL = CodeGenOptLevel::Default); 81 virtual ~SelectionDAGISel(); 82 83 /// Returns a (possibly null) pointer to the current BatchAAResults. getBatchAA()84 BatchAAResults *getBatchAA() const { 85 if (BatchAA.has_value()) 86 return &BatchAA.value(); 87 return nullptr; 88 } 89 getTargetLowering()90 const TargetLowering *getTargetLowering() const { return TLI; } 91 92 void initializeAnalysisResults(MachineFunctionAnalysisManager &MFAM); 93 void initializeAnalysisResults(MachineFunctionPass &MFP); 94 95 virtual bool runOnMachineFunction(MachineFunction &mf); 96 emitFunctionEntryCode()97 virtual void emitFunctionEntryCode() {} 98 99 /// PreprocessISelDAG - This hook allows targets to hack on the graph before 100 /// instruction selection starts. PreprocessISelDAG()101 virtual void PreprocessISelDAG() {} 102 103 /// PostprocessISelDAG() - This hook allows the target to hack on the graph 104 /// right after selection. PostprocessISelDAG()105 virtual void PostprocessISelDAG() {} 106 107 /// Main hook for targets to transform nodes into machine nodes. 108 virtual void Select(SDNode *N) = 0; 109 110 /// SelectInlineAsmMemoryOperand - Select the specified address as a target 111 /// addressing mode, according to the specified constraint. If this does 112 /// not match or is not implemented, return true. The resultant operands 113 /// (which will appear in the machine instruction) should be added to the 114 /// OutOps vector. 115 virtual bool SelectInlineAsmMemoryOperand(const SDValue & Op,InlineAsm::ConstraintCode ConstraintID,std::vector<SDValue> & OutOps)116 SelectInlineAsmMemoryOperand(const SDValue &Op, 117 InlineAsm::ConstraintCode ConstraintID, 118 std::vector<SDValue> &OutOps) { 119 return true; 120 } 121 122 /// IsProfitableToFold - Returns true if it's profitable to fold the specific 123 /// operand node N of U during instruction selection that starts at Root. 124 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const; 125 126 /// IsLegalToFold - Returns true if the specific operand node N of 127 /// U can be folded during instruction selection that starts at Root. 128 /// FIXME: This is a static member function because the MSP430/X86 129 /// targets, which uses it during isel. This could become a proper member. 130 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 131 CodeGenOptLevel OptLevel, 132 bool IgnoreChains = false); 133 134 static void InvalidateNodeId(SDNode *N); 135 static int getUninvalidatedNodeId(SDNode *N); 136 137 static void EnforceNodeIdInvariant(SDNode *N); 138 139 // Opcodes used by the DAG state machine: 140 enum BuiltinOpcodes { 141 OPC_Scope, 142 OPC_RecordNode, 143 OPC_RecordChild0, 144 OPC_RecordChild1, 145 OPC_RecordChild2, 146 OPC_RecordChild3, 147 OPC_RecordChild4, 148 OPC_RecordChild5, 149 OPC_RecordChild6, 150 OPC_RecordChild7, 151 OPC_RecordMemRef, 152 OPC_CaptureGlueInput, 153 OPC_MoveChild, 154 OPC_MoveChild0, 155 OPC_MoveChild1, 156 OPC_MoveChild2, 157 OPC_MoveChild3, 158 OPC_MoveChild4, 159 OPC_MoveChild5, 160 OPC_MoveChild6, 161 OPC_MoveChild7, 162 OPC_MoveSibling, 163 OPC_MoveSibling0, 164 OPC_MoveSibling1, 165 OPC_MoveSibling2, 166 OPC_MoveSibling3, 167 OPC_MoveSibling4, 168 OPC_MoveSibling5, 169 OPC_MoveSibling6, 170 OPC_MoveSibling7, 171 OPC_MoveParent, 172 OPC_CheckSame, 173 OPC_CheckChild0Same, 174 OPC_CheckChild1Same, 175 OPC_CheckChild2Same, 176 OPC_CheckChild3Same, 177 OPC_CheckPatternPredicate, 178 OPC_CheckPatternPredicate0, 179 OPC_CheckPatternPredicate1, 180 OPC_CheckPatternPredicate2, 181 OPC_CheckPatternPredicate3, 182 OPC_CheckPatternPredicate4, 183 OPC_CheckPatternPredicate5, 184 OPC_CheckPatternPredicate6, 185 OPC_CheckPatternPredicate7, 186 OPC_CheckPatternPredicateTwoByte, 187 OPC_CheckPredicate, 188 OPC_CheckPredicate0, 189 OPC_CheckPredicate1, 190 OPC_CheckPredicate2, 191 OPC_CheckPredicate3, 192 OPC_CheckPredicate4, 193 OPC_CheckPredicate5, 194 OPC_CheckPredicate6, 195 OPC_CheckPredicate7, 196 OPC_CheckPredicateWithOperands, 197 OPC_CheckOpcode, 198 OPC_SwitchOpcode, 199 OPC_CheckType, 200 // Space-optimized forms that implicitly encode VT. 201 OPC_CheckTypeI32, 202 OPC_CheckTypeI64, 203 OPC_CheckTypeRes, 204 OPC_SwitchType, 205 OPC_CheckChild0Type, 206 OPC_CheckChild1Type, 207 OPC_CheckChild2Type, 208 OPC_CheckChild3Type, 209 OPC_CheckChild4Type, 210 OPC_CheckChild5Type, 211 OPC_CheckChild6Type, 212 OPC_CheckChild7Type, 213 214 OPC_CheckChild0TypeI32, 215 OPC_CheckChild1TypeI32, 216 OPC_CheckChild2TypeI32, 217 OPC_CheckChild3TypeI32, 218 OPC_CheckChild4TypeI32, 219 OPC_CheckChild5TypeI32, 220 OPC_CheckChild6TypeI32, 221 OPC_CheckChild7TypeI32, 222 223 OPC_CheckChild0TypeI64, 224 OPC_CheckChild1TypeI64, 225 OPC_CheckChild2TypeI64, 226 OPC_CheckChild3TypeI64, 227 OPC_CheckChild4TypeI64, 228 OPC_CheckChild5TypeI64, 229 OPC_CheckChild6TypeI64, 230 OPC_CheckChild7TypeI64, 231 232 OPC_CheckInteger, 233 OPC_CheckChild0Integer, 234 OPC_CheckChild1Integer, 235 OPC_CheckChild2Integer, 236 OPC_CheckChild3Integer, 237 OPC_CheckChild4Integer, 238 OPC_CheckCondCode, 239 OPC_CheckChild2CondCode, 240 OPC_CheckValueType, 241 OPC_CheckComplexPat, 242 OPC_CheckComplexPat0, 243 OPC_CheckComplexPat1, 244 OPC_CheckComplexPat2, 245 OPC_CheckComplexPat3, 246 OPC_CheckComplexPat4, 247 OPC_CheckComplexPat5, 248 OPC_CheckComplexPat6, 249 OPC_CheckComplexPat7, 250 OPC_CheckAndImm, 251 OPC_CheckOrImm, 252 OPC_CheckImmAllOnesV, 253 OPC_CheckImmAllZerosV, 254 OPC_CheckFoldableChainNode, 255 256 OPC_EmitInteger, 257 // Space-optimized forms that implicitly encode integer VT. 258 OPC_EmitInteger8, 259 OPC_EmitInteger16, 260 OPC_EmitInteger32, 261 OPC_EmitInteger64, 262 OPC_EmitStringInteger, 263 // Space-optimized forms that implicitly encode integer VT. 264 OPC_EmitStringInteger32, 265 OPC_EmitRegister, 266 OPC_EmitRegisterI32, 267 OPC_EmitRegisterI64, 268 OPC_EmitRegister2, 269 OPC_EmitConvertToTarget, 270 OPC_EmitConvertToTarget0, 271 OPC_EmitConvertToTarget1, 272 OPC_EmitConvertToTarget2, 273 OPC_EmitConvertToTarget3, 274 OPC_EmitConvertToTarget4, 275 OPC_EmitConvertToTarget5, 276 OPC_EmitConvertToTarget6, 277 OPC_EmitConvertToTarget7, 278 OPC_EmitMergeInputChains, 279 OPC_EmitMergeInputChains1_0, 280 OPC_EmitMergeInputChains1_1, 281 OPC_EmitMergeInputChains1_2, 282 OPC_EmitCopyToReg, 283 OPC_EmitCopyToReg0, 284 OPC_EmitCopyToReg1, 285 OPC_EmitCopyToReg2, 286 OPC_EmitCopyToReg3, 287 OPC_EmitCopyToReg4, 288 OPC_EmitCopyToReg5, 289 OPC_EmitCopyToReg6, 290 OPC_EmitCopyToReg7, 291 OPC_EmitCopyToRegTwoByte, 292 OPC_EmitNodeXForm, 293 OPC_EmitNode, 294 // Space-optimized forms that implicitly encode number of result VTs. 295 OPC_EmitNode0, 296 OPC_EmitNode1, 297 OPC_EmitNode2, 298 // Space-optimized forms that implicitly encode EmitNodeInfo. 299 OPC_EmitNode0None, 300 OPC_EmitNode1None, 301 OPC_EmitNode2None, 302 OPC_EmitNode0Chain, 303 OPC_EmitNode1Chain, 304 OPC_EmitNode2Chain, 305 OPC_MorphNodeTo, 306 // Space-optimized forms that implicitly encode number of result VTs. 307 OPC_MorphNodeTo0, 308 OPC_MorphNodeTo1, 309 OPC_MorphNodeTo2, 310 // Space-optimized forms that implicitly encode EmitNodeInfo. 311 OPC_MorphNodeTo0None, 312 OPC_MorphNodeTo1None, 313 OPC_MorphNodeTo2None, 314 OPC_MorphNodeTo0Chain, 315 OPC_MorphNodeTo1Chain, 316 OPC_MorphNodeTo2Chain, 317 OPC_MorphNodeTo0GlueInput, 318 OPC_MorphNodeTo1GlueInput, 319 OPC_MorphNodeTo2GlueInput, 320 OPC_MorphNodeTo0GlueOutput, 321 OPC_MorphNodeTo1GlueOutput, 322 OPC_MorphNodeTo2GlueOutput, 323 OPC_CompleteMatch, 324 // Contains 32-bit offset in table for pattern being selected 325 OPC_Coverage 326 }; 327 328 enum { 329 OPFL_None = 0, // Node has no chain or glue input and isn't variadic. 330 OPFL_Chain = 1, // Node has a chain input. 331 OPFL_GlueInput = 2, // Node has a glue input. 332 OPFL_GlueOutput = 4, // Node has a glue output. 333 OPFL_MemRefs = 8, // Node gets accumulated MemRefs. 334 OPFL_Variadic0 = 1 << 4, // Node is variadic, root has 0 fixed inputs. 335 OPFL_Variadic1 = 2 << 4, // Node is variadic, root has 1 fixed inputs. 336 OPFL_Variadic2 = 3 << 4, // Node is variadic, root has 2 fixed inputs. 337 OPFL_Variadic3 = 4 << 4, // Node is variadic, root has 3 fixed inputs. 338 OPFL_Variadic4 = 5 << 4, // Node is variadic, root has 4 fixed inputs. 339 OPFL_Variadic5 = 6 << 4, // Node is variadic, root has 5 fixed inputs. 340 OPFL_Variadic6 = 7 << 4, // Node is variadic, root has 6 fixed inputs. 341 OPFL_Variadic7 = 8 << 4, // Node is variadic, root has 7 fixed inputs. 342 343 OPFL_VariadicInfo = 15 << 4 // Mask for extracting the OPFL_VariadicN bits. 344 }; 345 346 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the 347 /// number of fixed arity values that should be skipped when copying from the 348 /// root. getNumFixedFromVariadicInfo(unsigned Flags)349 static inline int getNumFixedFromVariadicInfo(unsigned Flags) { 350 return ((Flags&OPFL_VariadicInfo) >> 4)-1; 351 } 352 353 354 protected: 355 /// DAGSize - Size of DAG being instruction selected. 356 /// 357 unsigned DAGSize = 0; 358 359 /// ReplaceUses - replace all uses of the old node F with the use 360 /// of the new node T. ReplaceUses(SDValue F,SDValue T)361 void ReplaceUses(SDValue F, SDValue T) { 362 CurDAG->ReplaceAllUsesOfValueWith(F, T); 363 EnforceNodeIdInvariant(T.getNode()); 364 } 365 366 /// ReplaceUses - replace all uses of the old nodes F with the use 367 /// of the new nodes T. ReplaceUses(const SDValue * F,const SDValue * T,unsigned Num)368 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) { 369 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num); 370 for (unsigned i = 0; i < Num; ++i) 371 EnforceNodeIdInvariant(T[i].getNode()); 372 } 373 374 /// ReplaceUses - replace all uses of the old node F with the use 375 /// of the new node T. ReplaceUses(SDNode * F,SDNode * T)376 void ReplaceUses(SDNode *F, SDNode *T) { 377 CurDAG->ReplaceAllUsesWith(F, T); 378 EnforceNodeIdInvariant(T); 379 } 380 381 /// Replace all uses of \c F with \c T, then remove \c F from the DAG. ReplaceNode(SDNode * F,SDNode * T)382 void ReplaceNode(SDNode *F, SDNode *T) { 383 CurDAG->ReplaceAllUsesWith(F, T); 384 EnforceNodeIdInvariant(T); 385 CurDAG->RemoveDeadNode(F); 386 } 387 388 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 389 /// by tblgen. Others should not call it. 390 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, 391 const SDLoc &DL); 392 393 /// getPatternForIndex - Patterns selected by tablegen during ISEL getPatternForIndex(unsigned index)394 virtual StringRef getPatternForIndex(unsigned index) { 395 llvm_unreachable("Tblgen should generate the implementation of this!"); 396 } 397 398 /// getIncludePathForIndex - get the td source location of pattern instantiation getIncludePathForIndex(unsigned index)399 virtual StringRef getIncludePathForIndex(unsigned index) { 400 llvm_unreachable("Tblgen should generate the implementation of this!"); 401 } 402 shouldOptForSize(const MachineFunction * MF)403 bool shouldOptForSize(const MachineFunction *MF) const { 404 return CurDAG->shouldOptForSize(); 405 } 406 407 public: 408 // Calls to these predicates are generated by tblgen. 409 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 410 int64_t DesiredMaskS) const; 411 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 412 int64_t DesiredMaskS) const; 413 414 415 /// CheckPatternPredicate - This function is generated by tblgen in the 416 /// target. It runs the specified pattern predicate and returns true if it 417 /// succeeds or false if it fails. The number is a private implementation 418 /// detail to the code tblgen produces. CheckPatternPredicate(unsigned PredNo)419 virtual bool CheckPatternPredicate(unsigned PredNo) const { 420 llvm_unreachable("Tblgen should generate the implementation of this!"); 421 } 422 423 /// CheckNodePredicate - This function is generated by tblgen in the target. 424 /// It runs node predicate number PredNo and returns true if it succeeds or 425 /// false if it fails. The number is a private implementation 426 /// detail to the code tblgen produces. CheckNodePredicate(SDValue Op,unsigned PredNo)427 virtual bool CheckNodePredicate(SDValue Op, unsigned PredNo) const { 428 llvm_unreachable("Tblgen should generate the implementation of this!"); 429 } 430 431 /// CheckNodePredicateWithOperands - This function is generated by tblgen in 432 /// the target. 433 /// It runs node predicate number PredNo and returns true if it succeeds or 434 /// false if it fails. The number is a private implementation detail to the 435 /// code tblgen produces. 436 virtual bool CheckNodePredicateWithOperands(SDValue Op,unsigned PredNo,ArrayRef<SDValue> Operands)437 CheckNodePredicateWithOperands(SDValue Op, unsigned PredNo, 438 ArrayRef<SDValue> Operands) const { 439 llvm_unreachable("Tblgen should generate the implementation of this!"); 440 } 441 CheckComplexPattern(SDNode * Root,SDNode * Parent,SDValue N,unsigned PatternNo,SmallVectorImpl<std::pair<SDValue,SDNode * >> & Result)442 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, 443 unsigned PatternNo, 444 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) { 445 llvm_unreachable("Tblgen should generate the implementation of this!"); 446 } 447 RunSDNodeXForm(SDValue V,unsigned XFormNo)448 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) { 449 llvm_unreachable("Tblgen should generate this!"); 450 } 451 452 void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 453 unsigned TableSize); 454 455 /// Return true if complex patterns for this target can mutate the 456 /// DAG. ComplexPatternFuncMutatesDAG()457 virtual bool ComplexPatternFuncMutatesDAG() const { 458 return false; 459 } 460 461 /// Return whether the node may raise an FP exception. 462 bool mayRaiseFPException(SDNode *Node) const; 463 464 bool isOrEquivalentToAdd(const SDNode *N) const; 465 466 private: 467 468 // Calls to these functions are generated by tblgen. 469 void Select_INLINEASM(SDNode *N); 470 void Select_READ_REGISTER(SDNode *Op); 471 void Select_WRITE_REGISTER(SDNode *Op); 472 void Select_UNDEF(SDNode *N); 473 void Select_FAKE_USE(SDNode *N); 474 void CannotYetSelect(SDNode *N); 475 476 void Select_FREEZE(SDNode *N); 477 void Select_ARITH_FENCE(SDNode *N); 478 void Select_MEMBARRIER(SDNode *N); 479 480 void Select_CONVERGENCECTRL_ANCHOR(SDNode *N); 481 void Select_CONVERGENCECTRL_ENTRY(SDNode *N); 482 void Select_CONVERGENCECTRL_LOOP(SDNode *N); 483 484 void pushStackMapLiveVariable(SmallVectorImpl<SDValue> &Ops, SDValue Operand, 485 SDLoc DL); 486 void Select_STACKMAP(SDNode *N); 487 void Select_PATCHPOINT(SDNode *N); 488 489 void Select_JUMP_TABLE_DEBUG_INFO(SDNode *N); 490 491 private: 492 void DoInstructionSelection(); 493 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 494 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo); 495 496 /// Prepares the landing pad to take incoming values or do other EH 497 /// personality specific tasks. Returns true if the block should be 498 /// instruction selected, false if no code should be emitted for it. 499 bool PrepareEHLandingPad(); 500 501 // Mark and Report IPToState for each Block under AsynchEH 502 void reportIPToStateForBlocks(MachineFunction *Fn); 503 504 /// Perform instruction selection on all basic blocks in the function. 505 void SelectAllBasicBlocks(const Function &Fn); 506 507 /// Perform instruction selection on a single basic block, for 508 /// instructions between \p Begin and \p End. \p HadTailCall will be set 509 /// to true if a call in the block was translated as a tail call. 510 void SelectBasicBlock(BasicBlock::const_iterator Begin, 511 BasicBlock::const_iterator End, 512 bool &HadTailCall); 513 void FinishBasicBlock(); 514 515 void CodeGenAndEmitDAG(); 516 517 /// Generate instructions for lowering the incoming arguments of the 518 /// given function. 519 void LowerArguments(const Function &F); 520 521 void ComputeLiveOutVRegInfo(); 522 523 /// Create the scheduler. If a specific scheduler was specified 524 /// via the SchedulerRegistry, use it, otherwise select the 525 /// one preferred by the target. 526 /// 527 ScheduleDAGSDNodes *CreateScheduler(); 528 529 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel 530 /// state machines that start with a OPC_SwitchOpcode node. 531 std::vector<unsigned> OpcodeOffset; 532 533 void UpdateChains(SDNode *NodeToMatch, SDValue InputChain, 534 SmallVectorImpl<SDNode *> &ChainNodesMatched, 535 bool isMorphNodeTo); 536 }; 537 538 class SelectionDAGISelLegacy : public MachineFunctionPass { 539 std::unique_ptr<SelectionDAGISel> Selector; 540 541 public: 542 SelectionDAGISelLegacy(char &ID, std::unique_ptr<SelectionDAGISel> S); 543 544 ~SelectionDAGISelLegacy() override = default; 545 546 void getAnalysisUsage(AnalysisUsage &AU) const override; 547 548 bool runOnMachineFunction(MachineFunction &MF) override; 549 }; 550 551 class SelectionDAGISelPass : public PassInfoMixin<SelectionDAGISelPass> { 552 std::unique_ptr<SelectionDAGISel> Selector; 553 554 protected: SelectionDAGISelPass(std::unique_ptr<SelectionDAGISel> Selector)555 SelectionDAGISelPass(std::unique_ptr<SelectionDAGISel> Selector) 556 : Selector(std::move(Selector)) {} 557 558 public: 559 PreservedAnalyses run(MachineFunction &MF, 560 MachineFunctionAnalysisManager &MFAM); isRequired()561 static bool isRequired() { return true; } 562 }; 563 } 564 565 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */ 566