1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the SelectionDAGISel class, which is used as the common 10 // base class for SelectionDAG-based instruction selectors. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H 15 #define LLVM_CODEGEN_SELECTIONDAGISEL_H 16 17 #include "llvm/CodeGen/MachineFunctionPass.h" 18 #include "llvm/CodeGen/MachinePassManager.h" 19 #include "llvm/CodeGen/SelectionDAG.h" 20 #include "llvm/IR/BasicBlock.h" 21 #include <memory> 22 23 namespace llvm { 24 class AAResults; 25 class AssumptionCache; 26 class TargetInstrInfo; 27 class TargetMachine; 28 class SSPLayoutInfo; 29 class SelectionDAGBuilder; 30 class SDValue; 31 class MachineRegisterInfo; 32 class MachineFunction; 33 class OptimizationRemarkEmitter; 34 class TargetLowering; 35 class TargetLibraryInfo; 36 class TargetTransformInfo; 37 class FunctionLoweringInfo; 38 class SwiftErrorValueTracking; 39 class GCFunctionInfo; 40 class ScheduleDAGSDNodes; 41 42 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based 43 /// pattern-matching instruction selectors. 44 class SelectionDAGISel { 45 public: 46 TargetMachine &TM; 47 const TargetLibraryInfo *LibInfo; 48 std::unique_ptr<FunctionLoweringInfo> FuncInfo; 49 SwiftErrorValueTracking *SwiftError; 50 MachineFunction *MF; 51 MachineRegisterInfo *RegInfo; 52 SelectionDAG *CurDAG; 53 std::unique_ptr<SelectionDAGBuilder> SDB; 54 AAResults *AA = nullptr; 55 AssumptionCache *AC = nullptr; 56 GCFunctionInfo *GFI = nullptr; 57 SSPLayoutInfo *SP = nullptr; 58 #if !defined(NDEBUG) && LLVM_ENABLE_ABI_BREAKING_CHECKS 59 TargetTransformInfo *TTI = nullptr; 60 #endif 61 CodeGenOptLevel OptLevel; 62 const TargetInstrInfo *TII; 63 const TargetLowering *TLI; 64 bool FastISelFailed; 65 SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs; 66 67 /// Current optimization remark emitter. 68 /// Used to report things like combines and FastISel failures. 69 std::unique_ptr<OptimizationRemarkEmitter> ORE; 70 71 /// True if the function currently processing is in the function printing list 72 /// (i.e. `-filter-print-funcs`). 73 /// This is primarily used by ISEL_DUMP, which spans in multiple member 74 /// functions. Storing the filter result here so that we only need to do the 75 /// filtering once. 76 bool MatchFilterFuncName = false; 77 StringRef FuncName; 78 79 explicit SelectionDAGISel(TargetMachine &tm, 80 CodeGenOptLevel OL = CodeGenOptLevel::Default); 81 virtual ~SelectionDAGISel(); 82 getTargetLowering()83 const TargetLowering *getTargetLowering() const { return TLI; } 84 85 void initializeAnalysisResults(MachineFunctionAnalysisManager &MFAM); 86 void initializeAnalysisResults(MachineFunctionPass &MFP); 87 88 virtual bool runOnMachineFunction(MachineFunction &mf); 89 emitFunctionEntryCode()90 virtual void emitFunctionEntryCode() {} 91 92 /// PreprocessISelDAG - This hook allows targets to hack on the graph before 93 /// instruction selection starts. PreprocessISelDAG()94 virtual void PreprocessISelDAG() {} 95 96 /// PostprocessISelDAG() - This hook allows the target to hack on the graph 97 /// right after selection. PostprocessISelDAG()98 virtual void PostprocessISelDAG() {} 99 100 /// Main hook for targets to transform nodes into machine nodes. 101 virtual void Select(SDNode *N) = 0; 102 103 /// SelectInlineAsmMemoryOperand - Select the specified address as a target 104 /// addressing mode, according to the specified constraint. If this does 105 /// not match or is not implemented, return true. The resultant operands 106 /// (which will appear in the machine instruction) should be added to the 107 /// OutOps vector. 108 virtual bool SelectInlineAsmMemoryOperand(const SDValue & Op,InlineAsm::ConstraintCode ConstraintID,std::vector<SDValue> & OutOps)109 SelectInlineAsmMemoryOperand(const SDValue &Op, 110 InlineAsm::ConstraintCode ConstraintID, 111 std::vector<SDValue> &OutOps) { 112 return true; 113 } 114 115 /// IsProfitableToFold - Returns true if it's profitable to fold the specific 116 /// operand node N of U during instruction selection that starts at Root. 117 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const; 118 119 /// IsLegalToFold - Returns true if the specific operand node N of 120 /// U can be folded during instruction selection that starts at Root. 121 /// FIXME: This is a static member function because the MSP430/X86 122 /// targets, which uses it during isel. This could become a proper member. 123 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 124 CodeGenOptLevel OptLevel, 125 bool IgnoreChains = false); 126 127 static void InvalidateNodeId(SDNode *N); 128 static int getUninvalidatedNodeId(SDNode *N); 129 130 static void EnforceNodeIdInvariant(SDNode *N); 131 132 // Opcodes used by the DAG state machine: 133 enum BuiltinOpcodes { 134 OPC_Scope, 135 OPC_RecordNode, 136 OPC_RecordChild0, 137 OPC_RecordChild1, 138 OPC_RecordChild2, 139 OPC_RecordChild3, 140 OPC_RecordChild4, 141 OPC_RecordChild5, 142 OPC_RecordChild6, 143 OPC_RecordChild7, 144 OPC_RecordMemRef, 145 OPC_CaptureGlueInput, 146 OPC_MoveChild, 147 OPC_MoveChild0, 148 OPC_MoveChild1, 149 OPC_MoveChild2, 150 OPC_MoveChild3, 151 OPC_MoveChild4, 152 OPC_MoveChild5, 153 OPC_MoveChild6, 154 OPC_MoveChild7, 155 OPC_MoveSibling, 156 OPC_MoveSibling0, 157 OPC_MoveSibling1, 158 OPC_MoveSibling2, 159 OPC_MoveSibling3, 160 OPC_MoveSibling4, 161 OPC_MoveSibling5, 162 OPC_MoveSibling6, 163 OPC_MoveSibling7, 164 OPC_MoveParent, 165 OPC_CheckSame, 166 OPC_CheckChild0Same, 167 OPC_CheckChild1Same, 168 OPC_CheckChild2Same, 169 OPC_CheckChild3Same, 170 OPC_CheckPatternPredicate, 171 OPC_CheckPatternPredicate0, 172 OPC_CheckPatternPredicate1, 173 OPC_CheckPatternPredicate2, 174 OPC_CheckPatternPredicate3, 175 OPC_CheckPatternPredicate4, 176 OPC_CheckPatternPredicate5, 177 OPC_CheckPatternPredicate6, 178 OPC_CheckPatternPredicate7, 179 OPC_CheckPatternPredicateTwoByte, 180 OPC_CheckPredicate, 181 OPC_CheckPredicate0, 182 OPC_CheckPredicate1, 183 OPC_CheckPredicate2, 184 OPC_CheckPredicate3, 185 OPC_CheckPredicate4, 186 OPC_CheckPredicate5, 187 OPC_CheckPredicate6, 188 OPC_CheckPredicate7, 189 OPC_CheckPredicateWithOperands, 190 OPC_CheckOpcode, 191 OPC_SwitchOpcode, 192 OPC_CheckType, 193 // Space-optimized forms that implicitly encode VT. 194 OPC_CheckTypeI32, 195 OPC_CheckTypeI64, 196 OPC_CheckTypeRes, 197 OPC_SwitchType, 198 OPC_CheckChild0Type, 199 OPC_CheckChild1Type, 200 OPC_CheckChild2Type, 201 OPC_CheckChild3Type, 202 OPC_CheckChild4Type, 203 OPC_CheckChild5Type, 204 OPC_CheckChild6Type, 205 OPC_CheckChild7Type, 206 207 OPC_CheckChild0TypeI32, 208 OPC_CheckChild1TypeI32, 209 OPC_CheckChild2TypeI32, 210 OPC_CheckChild3TypeI32, 211 OPC_CheckChild4TypeI32, 212 OPC_CheckChild5TypeI32, 213 OPC_CheckChild6TypeI32, 214 OPC_CheckChild7TypeI32, 215 216 OPC_CheckChild0TypeI64, 217 OPC_CheckChild1TypeI64, 218 OPC_CheckChild2TypeI64, 219 OPC_CheckChild3TypeI64, 220 OPC_CheckChild4TypeI64, 221 OPC_CheckChild5TypeI64, 222 OPC_CheckChild6TypeI64, 223 OPC_CheckChild7TypeI64, 224 225 OPC_CheckInteger, 226 OPC_CheckChild0Integer, 227 OPC_CheckChild1Integer, 228 OPC_CheckChild2Integer, 229 OPC_CheckChild3Integer, 230 OPC_CheckChild4Integer, 231 OPC_CheckCondCode, 232 OPC_CheckChild2CondCode, 233 OPC_CheckValueType, 234 OPC_CheckComplexPat, 235 OPC_CheckComplexPat0, 236 OPC_CheckComplexPat1, 237 OPC_CheckComplexPat2, 238 OPC_CheckComplexPat3, 239 OPC_CheckComplexPat4, 240 OPC_CheckComplexPat5, 241 OPC_CheckComplexPat6, 242 OPC_CheckComplexPat7, 243 OPC_CheckAndImm, 244 OPC_CheckOrImm, 245 OPC_CheckImmAllOnesV, 246 OPC_CheckImmAllZerosV, 247 OPC_CheckFoldableChainNode, 248 249 OPC_EmitInteger, 250 // Space-optimized forms that implicitly encode integer VT. 251 OPC_EmitInteger8, 252 OPC_EmitInteger16, 253 OPC_EmitInteger32, 254 OPC_EmitInteger64, 255 OPC_EmitStringInteger, 256 // Space-optimized forms that implicitly encode integer VT. 257 OPC_EmitStringInteger32, 258 OPC_EmitRegister, 259 OPC_EmitRegisterI32, 260 OPC_EmitRegisterI64, 261 OPC_EmitRegister2, 262 OPC_EmitConvertToTarget, 263 OPC_EmitConvertToTarget0, 264 OPC_EmitConvertToTarget1, 265 OPC_EmitConvertToTarget2, 266 OPC_EmitConvertToTarget3, 267 OPC_EmitConvertToTarget4, 268 OPC_EmitConvertToTarget5, 269 OPC_EmitConvertToTarget6, 270 OPC_EmitConvertToTarget7, 271 OPC_EmitMergeInputChains, 272 OPC_EmitMergeInputChains1_0, 273 OPC_EmitMergeInputChains1_1, 274 OPC_EmitMergeInputChains1_2, 275 OPC_EmitCopyToReg, 276 OPC_EmitCopyToReg0, 277 OPC_EmitCopyToReg1, 278 OPC_EmitCopyToReg2, 279 OPC_EmitCopyToReg3, 280 OPC_EmitCopyToReg4, 281 OPC_EmitCopyToReg5, 282 OPC_EmitCopyToReg6, 283 OPC_EmitCopyToReg7, 284 OPC_EmitCopyToRegTwoByte, 285 OPC_EmitNodeXForm, 286 OPC_EmitNode, 287 // Space-optimized forms that implicitly encode number of result VTs. 288 OPC_EmitNode0, 289 OPC_EmitNode1, 290 OPC_EmitNode2, 291 // Space-optimized forms that implicitly encode EmitNodeInfo. 292 OPC_EmitNode0None, 293 OPC_EmitNode1None, 294 OPC_EmitNode2None, 295 OPC_EmitNode0Chain, 296 OPC_EmitNode1Chain, 297 OPC_EmitNode2Chain, 298 OPC_MorphNodeTo, 299 // Space-optimized forms that implicitly encode number of result VTs. 300 OPC_MorphNodeTo0, 301 OPC_MorphNodeTo1, 302 OPC_MorphNodeTo2, 303 // Space-optimized forms that implicitly encode EmitNodeInfo. 304 OPC_MorphNodeTo0None, 305 OPC_MorphNodeTo1None, 306 OPC_MorphNodeTo2None, 307 OPC_MorphNodeTo0Chain, 308 OPC_MorphNodeTo1Chain, 309 OPC_MorphNodeTo2Chain, 310 OPC_MorphNodeTo0GlueInput, 311 OPC_MorphNodeTo1GlueInput, 312 OPC_MorphNodeTo2GlueInput, 313 OPC_MorphNodeTo0GlueOutput, 314 OPC_MorphNodeTo1GlueOutput, 315 OPC_MorphNodeTo2GlueOutput, 316 OPC_CompleteMatch, 317 // Contains offset in table for pattern being selected 318 OPC_Coverage 319 }; 320 321 enum { 322 OPFL_None = 0, // Node has no chain or glue input and isn't variadic. 323 OPFL_Chain = 1, // Node has a chain input. 324 OPFL_GlueInput = 2, // Node has a glue input. 325 OPFL_GlueOutput = 4, // Node has a glue output. 326 OPFL_MemRefs = 8, // Node gets accumulated MemRefs. 327 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs. 328 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs. 329 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs. 330 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs. 331 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs. 332 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs. 333 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs. 334 335 OPFL_VariadicInfo = OPFL_Variadic6 336 }; 337 338 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the 339 /// number of fixed arity values that should be skipped when copying from the 340 /// root. getNumFixedFromVariadicInfo(unsigned Flags)341 static inline int getNumFixedFromVariadicInfo(unsigned Flags) { 342 return ((Flags&OPFL_VariadicInfo) >> 4)-1; 343 } 344 345 346 protected: 347 /// DAGSize - Size of DAG being instruction selected. 348 /// 349 unsigned DAGSize = 0; 350 351 /// ReplaceUses - replace all uses of the old node F with the use 352 /// of the new node T. ReplaceUses(SDValue F,SDValue T)353 void ReplaceUses(SDValue F, SDValue T) { 354 CurDAG->ReplaceAllUsesOfValueWith(F, T); 355 EnforceNodeIdInvariant(T.getNode()); 356 } 357 358 /// ReplaceUses - replace all uses of the old nodes F with the use 359 /// of the new nodes T. ReplaceUses(const SDValue * F,const SDValue * T,unsigned Num)360 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) { 361 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num); 362 for (unsigned i = 0; i < Num; ++i) 363 EnforceNodeIdInvariant(T[i].getNode()); 364 } 365 366 /// ReplaceUses - replace all uses of the old node F with the use 367 /// of the new node T. ReplaceUses(SDNode * F,SDNode * T)368 void ReplaceUses(SDNode *F, SDNode *T) { 369 CurDAG->ReplaceAllUsesWith(F, T); 370 EnforceNodeIdInvariant(T); 371 } 372 373 /// Replace all uses of \c F with \c T, then remove \c F from the DAG. ReplaceNode(SDNode * F,SDNode * T)374 void ReplaceNode(SDNode *F, SDNode *T) { 375 CurDAG->ReplaceAllUsesWith(F, T); 376 EnforceNodeIdInvariant(T); 377 CurDAG->RemoveDeadNode(F); 378 } 379 380 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 381 /// by tblgen. Others should not call it. 382 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, 383 const SDLoc &DL); 384 385 /// getPatternForIndex - Patterns selected by tablegen during ISEL getPatternForIndex(unsigned index)386 virtual StringRef getPatternForIndex(unsigned index) { 387 llvm_unreachable("Tblgen should generate the implementation of this!"); 388 } 389 390 /// getIncludePathForIndex - get the td source location of pattern instantiation getIncludePathForIndex(unsigned index)391 virtual StringRef getIncludePathForIndex(unsigned index) { 392 llvm_unreachable("Tblgen should generate the implementation of this!"); 393 } 394 shouldOptForSize(const MachineFunction * MF)395 bool shouldOptForSize(const MachineFunction *MF) const { 396 return CurDAG->shouldOptForSize(); 397 } 398 399 public: 400 // Calls to these predicates are generated by tblgen. 401 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 402 int64_t DesiredMaskS) const; 403 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 404 int64_t DesiredMaskS) const; 405 406 407 /// CheckPatternPredicate - This function is generated by tblgen in the 408 /// target. It runs the specified pattern predicate and returns true if it 409 /// succeeds or false if it fails. The number is a private implementation 410 /// detail to the code tblgen produces. CheckPatternPredicate(unsigned PredNo)411 virtual bool CheckPatternPredicate(unsigned PredNo) const { 412 llvm_unreachable("Tblgen should generate the implementation of this!"); 413 } 414 415 /// CheckNodePredicate - This function is generated by tblgen in the target. 416 /// It runs node predicate number PredNo and returns true if it succeeds or 417 /// false if it fails. The number is a private implementation 418 /// detail to the code tblgen produces. CheckNodePredicate(SDNode * N,unsigned PredNo)419 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const { 420 llvm_unreachable("Tblgen should generate the implementation of this!"); 421 } 422 423 /// CheckNodePredicateWithOperands - This function is generated by tblgen in 424 /// the target. 425 /// It runs node predicate number PredNo and returns true if it succeeds or 426 /// false if it fails. The number is a private implementation detail to the 427 /// code tblgen produces. CheckNodePredicateWithOperands(SDNode * N,unsigned PredNo,const SmallVectorImpl<SDValue> & Operands)428 virtual bool CheckNodePredicateWithOperands( 429 SDNode *N, unsigned PredNo, 430 const SmallVectorImpl<SDValue> &Operands) const { 431 llvm_unreachable("Tblgen should generate the implementation of this!"); 432 } 433 CheckComplexPattern(SDNode * Root,SDNode * Parent,SDValue N,unsigned PatternNo,SmallVectorImpl<std::pair<SDValue,SDNode * >> & Result)434 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, 435 unsigned PatternNo, 436 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) { 437 llvm_unreachable("Tblgen should generate the implementation of this!"); 438 } 439 RunSDNodeXForm(SDValue V,unsigned XFormNo)440 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) { 441 llvm_unreachable("Tblgen should generate this!"); 442 } 443 444 void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 445 unsigned TableSize); 446 447 /// Return true if complex patterns for this target can mutate the 448 /// DAG. ComplexPatternFuncMutatesDAG()449 virtual bool ComplexPatternFuncMutatesDAG() const { 450 return false; 451 } 452 453 /// Return whether the node may raise an FP exception. 454 bool mayRaiseFPException(SDNode *Node) const; 455 456 bool isOrEquivalentToAdd(const SDNode *N) const; 457 458 private: 459 460 // Calls to these functions are generated by tblgen. 461 void Select_INLINEASM(SDNode *N); 462 void Select_READ_REGISTER(SDNode *Op); 463 void Select_WRITE_REGISTER(SDNode *Op); 464 void Select_UNDEF(SDNode *N); 465 void CannotYetSelect(SDNode *N); 466 467 void Select_FREEZE(SDNode *N); 468 void Select_ARITH_FENCE(SDNode *N); 469 void Select_MEMBARRIER(SDNode *N); 470 471 void Select_CONVERGENCECTRL_ANCHOR(SDNode *N); 472 void Select_CONVERGENCECTRL_ENTRY(SDNode *N); 473 void Select_CONVERGENCECTRL_LOOP(SDNode *N); 474 475 void pushStackMapLiveVariable(SmallVectorImpl<SDValue> &Ops, SDValue Operand, 476 SDLoc DL); 477 void Select_STACKMAP(SDNode *N); 478 void Select_PATCHPOINT(SDNode *N); 479 480 void Select_JUMP_TABLE_DEBUG_INFO(SDNode *N); 481 482 private: 483 void DoInstructionSelection(); 484 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 485 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo); 486 487 /// Prepares the landing pad to take incoming values or do other EH 488 /// personality specific tasks. Returns true if the block should be 489 /// instruction selected, false if no code should be emitted for it. 490 bool PrepareEHLandingPad(); 491 492 // Mark and Report IPToState for each Block under AsynchEH 493 void reportIPToStateForBlocks(MachineFunction *Fn); 494 495 /// Perform instruction selection on all basic blocks in the function. 496 void SelectAllBasicBlocks(const Function &Fn); 497 498 /// Perform instruction selection on a single basic block, for 499 /// instructions between \p Begin and \p End. \p HadTailCall will be set 500 /// to true if a call in the block was translated as a tail call. 501 void SelectBasicBlock(BasicBlock::const_iterator Begin, 502 BasicBlock::const_iterator End, 503 bool &HadTailCall); 504 void FinishBasicBlock(); 505 506 void CodeGenAndEmitDAG(); 507 508 /// Generate instructions for lowering the incoming arguments of the 509 /// given function. 510 void LowerArguments(const Function &F); 511 512 void ComputeLiveOutVRegInfo(); 513 514 /// Create the scheduler. If a specific scheduler was specified 515 /// via the SchedulerRegistry, use it, otherwise select the 516 /// one preferred by the target. 517 /// 518 ScheduleDAGSDNodes *CreateScheduler(); 519 520 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel 521 /// state machines that start with a OPC_SwitchOpcode node. 522 std::vector<unsigned> OpcodeOffset; 523 524 void UpdateChains(SDNode *NodeToMatch, SDValue InputChain, 525 SmallVectorImpl<SDNode *> &ChainNodesMatched, 526 bool isMorphNodeTo); 527 }; 528 529 class SelectionDAGISelLegacy : public MachineFunctionPass { 530 std::unique_ptr<SelectionDAGISel> Selector; 531 532 public: 533 SelectionDAGISelLegacy(char &ID, std::unique_ptr<SelectionDAGISel> S); 534 535 ~SelectionDAGISelLegacy() override = default; 536 537 void getAnalysisUsage(AnalysisUsage &AU) const override; 538 539 bool runOnMachineFunction(MachineFunction &MF) override; 540 }; 541 542 class SelectionDAGISelPass : public PassInfoMixin<SelectionDAGISelPass> { 543 std::unique_ptr<SelectionDAGISel> Selector; 544 545 protected: SelectionDAGISelPass(std::unique_ptr<SelectionDAGISel> Selector)546 SelectionDAGISelPass(std::unique_ptr<SelectionDAGISel> Selector) 547 : Selector(std::move(Selector)) {} 548 549 public: 550 PreservedAnalyses run(MachineFunction &MF, 551 MachineFunctionAnalysisManager &MFAM); 552 }; 553 } 554 555 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */ 556