1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (C) 2013 Emulex
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the Emulex Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * Contact Information:
34 * freebsd-drivers@emulex.com
35 *
36 * Emulex
37 * 3333 Susan Street
38 * Costa Mesa, CA 92626
39 */
40
41
42 #include <sys/param.h>
43 #include <sys/endian.h>
44 #include <sys/epoch.h>
45 #include <sys/eventhandler.h>
46 #include <sys/malloc.h>
47 #include <sys/module.h>
48 #include <sys/kernel.h>
49 #include <sys/bus.h>
50 #include <sys/mbuf.h>
51 #include <sys/priv.h>
52 #include <sys/rman.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
55 #include <sys/sockopt.h>
56 #include <sys/queue.h>
57 #include <sys/taskqueue.h>
58 #include <sys/lock.h>
59 #include <sys/mutex.h>
60 #include <sys/sysctl.h>
61 #include <sys/random.h>
62 #include <sys/firmware.h>
63 #include <sys/systm.h>
64 #include <sys/proc.h>
65
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
68
69 #include <net/bpf.h>
70 #include <net/ethernet.h>
71 #include <net/if.h>
72 #include <net/if_var.h>
73 #include <net/if_types.h>
74 #include <net/if_media.h>
75 #include <net/if_vlan_var.h>
76 #include <net/if_dl.h>
77
78 #include <netinet/in.h>
79 #include <netinet/in_systm.h>
80 #include <netinet/in_var.h>
81 #include <netinet/if_ether.h>
82 #include <netinet/ip.h>
83 #include <netinet/ip6.h>
84 #include <netinet6/in6_var.h>
85 #include <netinet6/ip6_mroute.h>
86
87 #include <netinet/udp.h>
88 #include <netinet/tcp.h>
89 #include <netinet/sctp.h>
90 #include <netinet/tcp_lro.h>
91 #include <netinet/icmp6.h>
92
93 #include <machine/bus.h>
94
95 #include "oce_hw.h"
96
97 /* OCE device driver module component revision informaiton */
98 #define COMPONENT_REVISION "11.0.50.0"
99
100 /* OCE devices supported by this driver */
101 #define PCI_VENDOR_EMULEX 0x10df /* Emulex */
102 #define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */
103 #define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */
104 #define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */
105 #define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */
106 #define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */
107 #define PCI_PRODUCT_SH 0x0720 /* Skyhawk network adapter */
108
109 #define IS_BE(sc) (((sc->flags & OCE_FLAGS_BE3) | \
110 (sc->flags & OCE_FLAGS_BE2))? 1:0)
111 #define IS_BE3(sc) (sc->flags & OCE_FLAGS_BE3)
112 #define IS_BE2(sc) (sc->flags & OCE_FLAGS_BE2)
113 #define IS_XE201(sc) ((sc->flags & OCE_FLAGS_XE201) ? 1:0)
114 #define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0)
115 #define IS_SH(sc) ((sc->flags & OCE_FLAGS_SH) ? 1 : 0)
116
117 #define is_be_mode_mc(sc) ((sc->function_mode & FNM_FLEX10_MODE) || \
118 (sc->function_mode & FNM_UMC_MODE) || \
119 (sc->function_mode & FNM_VNIC_MODE))
120 #define OCE_FUNCTION_CAPS_SUPER_NIC 0x40
121 #define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC)
122
123 /* proportion Service Level Interface queues */
124 #define OCE_MAX_UNITS 2
125 #define OCE_MAX_PPORT OCE_MAX_UNITS
126 #define OCE_MAX_VPORT OCE_MAX_UNITS
127
128 extern int mp_ncpus; /* system's total active cpu cores */
129 #define OCE_NCPUS mp_ncpus
130
131 /* This should be powers of 2. Like 2,4,8 & 16 */
132 #define OCE_MAX_RSS 8
133 #define OCE_LEGACY_MODE_RSS 4 /* For BE3 Legacy mode*/
134 #define is_rss_enabled(sc) ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc))
135
136 #define OCE_MIN_RQ 1
137 #define OCE_MIN_WQ 1
138
139 #define OCE_MAX_RQ OCE_MAX_RSS + 1 /* one default queue */
140 #define OCE_MAX_WQ 8
141
142 #define OCE_MAX_EQ 32
143 #define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */
144 #define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */
145
146 #define OCE_DEFAULT_WQ_EQD 16
147 #define OCE_MAX_PACKET_Q 16
148 #define OCE_LSO_MAX_SIZE (64 * 1024)
149 #define LONG_TIMEOUT 30
150 #define OCE_MAX_JUMBO_FRAME_SIZE 9018
151 #define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \
152 ETHER_VLAN_ENCAP_LEN - \
153 ETHER_HDR_LEN)
154
155 #define OCE_RDMA_VECTORS 2
156
157 #define OCE_MAX_TX_ELEMENTS 29
158 #define OCE_MAX_TX_DESC 1024
159 #define OCE_MAX_TX_SIZE 65535
160 #define OCE_MAX_TSO_SIZE (65535 - ETHER_HDR_LEN)
161 #define OCE_MAX_RX_SIZE 4096
162 #define OCE_MAX_RQ_POSTS 255
163 #define OCE_HWLRO_MAX_RQ_POSTS 64
164 #define OCE_DEFAULT_PROMISCUOUS 0
165
166 #define RSS_ENABLE_IPV4 0x1
167 #define RSS_ENABLE_TCP_IPV4 0x2
168 #define RSS_ENABLE_IPV6 0x4
169 #define RSS_ENABLE_TCP_IPV6 0x8
170
171 #define INDIRECTION_TABLE_ENTRIES 128
172
173 /* flow control definitions */
174 #define OCE_FC_NONE 0x00000000
175 #define OCE_FC_TX 0x00000001
176 #define OCE_FC_RX 0x00000002
177 #define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX)
178
179 /* Interface capabilities to give device when creating interface */
180 #define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \
181 MBX_RX_IFACE_FLAGS_UNTAGGED | \
182 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \
183 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS | \
184 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \
185 MBX_RX_IFACE_FLAGS_RSS | \
186 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
187
188 /* Interface capabilities to enable by default (others set dynamically) */
189 #define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \
190 MBX_RX_IFACE_FLAGS_UNTAGGED | \
191 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
192
193 #define OCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP)
194 #define OCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
195 IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \
196 IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU)
197 #define OCE_IF_HWASSIST_NONE 0
198 #define OCE_IF_CAPABILITIES_NONE 0
199
200 #define MAX_VLANFILTER_SIZE 64
201 #define MAX_VLANS 4096
202
203 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
204 #define BSWAP_8(x) ((x) & 0xff)
205 #define BSWAP_16(x) ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8))
206 #define BSWAP_32(x) ((BSWAP_16(x) << 16) | \
207 BSWAP_16((x) >> 16))
208 #define BSWAP_64(x) ((BSWAP_32(x) << 32) | \
209 BSWAP_32((x) >> 32))
210
211 #define for_all_wq_queues(sc, wq, i) \
212 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i])
213 #define for_all_rq_queues(sc, rq, i) \
214 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i])
215 #define for_all_rss_queues(sc, rq, i) \
216 for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \
217 i++, rq = sc->rq[i + 1])
218 #define for_all_evnt_queues(sc, eq, i) \
219 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i])
220 #define for_all_cq_queues(sc, cq, i) \
221 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i])
222
223 /* Flash specific */
224 #define IOCTL_COOKIE "SERVERENGINES CORP"
225 #define MAX_FLASH_COMP 32
226
227 #define IMG_ISCSI 160
228 #define IMG_REDBOOT 224
229 #define IMG_BIOS 34
230 #define IMG_PXEBIOS 32
231 #define IMG_FCOEBIOS 33
232 #define IMG_ISCSI_BAK 176
233 #define IMG_FCOE 162
234 #define IMG_FCOE_BAK 178
235 #define IMG_NCSI 16
236 #define IMG_PHY 192
237 #define FLASHROM_OPER_FLASH 1
238 #define FLASHROM_OPER_SAVE 2
239 #define FLASHROM_OPER_REPORT 4
240 #define FLASHROM_OPER_FLASH_PHY 9
241 #define FLASHROM_OPER_SAVE_PHY 10
242 #define TN_8022 13
243
244 enum {
245 PHY_TYPE_CX4_10GB = 0,
246 PHY_TYPE_XFP_10GB,
247 PHY_TYPE_SFP_1GB,
248 PHY_TYPE_SFP_PLUS_10GB,
249 PHY_TYPE_KR_10GB,
250 PHY_TYPE_KX4_10GB,
251 PHY_TYPE_BASET_10GB,
252 PHY_TYPE_BASET_1GB,
253 PHY_TYPE_BASEX_1GB,
254 PHY_TYPE_SGMII,
255 PHY_TYPE_DISABLED = 255
256 };
257
258 /**
259 * @brief Define and hold all necessary info for a single interrupt
260 */
261 #define OCE_MAX_MSI 32 /* Message Signaled Interrupts */
262 #define OCE_MAX_MSIX 2048 /* PCI Express MSI Interrrupts */
263
264 typedef struct oce_intr_info {
265 void *tag; /* cookie returned by bus_setup_intr */
266 struct resource *intr_res; /* PCI resource container */
267 int irq_rr; /* resource id for the interrupt */
268 struct oce_softc *sc; /* pointer to the parent soft c */
269 struct oce_eq *eq; /* pointer to the connected EQ */
270 struct taskqueue *tq; /* Associated task queue */
271 struct task task; /* task queue task */
272 char task_name[32]; /* task name */
273 int vector; /* interrupt vector number */
274 } OCE_INTR_INFO, *POCE_INTR_INFO;
275
276 /* Ring related */
277 #define GET_Q_NEXT(_START, _STEP, _END) \
278 (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \
279 : (((_START) + (_STEP)) - (_END)))
280
281 #define DBUF_PA(obj) ((obj)->addr)
282 #define DBUF_VA(obj) ((obj)->ptr)
283 #define DBUF_TAG(obj) ((obj)->tag)
284 #define DBUF_MAP(obj) ((obj)->map)
285 #define DBUF_SYNC(obj, flags) \
286 (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags))
287
288 #define RING_NUM_PENDING(ring) ring->num_used
289 #define RING_FULL(ring) (ring->num_used == ring->num_items)
290 #define RING_EMPTY(ring) (ring->num_used == 0)
291 #define RING_NUM_FREE(ring) \
292 (uint32_t)(ring->num_items - ring->num_used)
293 #define RING_GET(ring, n) \
294 ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items)
295 #define RING_PUT(ring, n) \
296 ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items)
297
298 #define RING_GET_CONSUMER_ITEM_VA(ring, type) \
299 (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx)
300 #define RING_GET_CONSUMER_ITEM_PA(ring, type) \
301 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx)
302 #define RING_GET_PRODUCER_ITEM_VA(ring, type) \
303 (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx)
304 #define RING_GET_PRODUCER_ITEM_PA(ring, type) \
305 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx)
306
307 #define OCE_DMAPTR(o, c) ((c *)(o)->ptr)
308
309 struct oce_packet_desc {
310 struct mbuf *mbuf;
311 bus_dmamap_t map;
312 int nsegs;
313 uint32_t wqe_idx;
314 };
315
316 typedef struct oce_dma_mem {
317 bus_dma_tag_t tag;
318 bus_dmamap_t map;
319 void *ptr;
320 bus_addr_t paddr;
321 } OCE_DMA_MEM, *POCE_DMA_MEM;
322
323 typedef struct oce_ring_buffer_s {
324 uint16_t cidx; /* Get ptr */
325 uint16_t pidx; /* Put Ptr */
326 size_t item_size;
327 size_t num_items;
328 uint32_t num_used;
329 OCE_DMA_MEM dma;
330 } oce_ring_buffer_t;
331
332 /* Stats */
333 #define OCE_UNICAST_PACKET 0
334 #define OCE_MULTICAST_PACKET 1
335 #define OCE_BROADCAST_PACKET 2
336 #define OCE_RSVD_PACKET 3
337
338 struct oce_rx_stats {
339 /* Total Receive Stats*/
340 uint64_t t_rx_pkts;
341 uint64_t t_rx_bytes;
342 uint32_t t_rx_frags;
343 uint32_t t_rx_mcast_pkts;
344 uint32_t t_rx_ucast_pkts;
345 uint32_t t_rxcp_errs;
346 };
347 struct oce_tx_stats {
348 /*Total Transmit Stats */
349 uint64_t t_tx_pkts;
350 uint64_t t_tx_bytes;
351 uint32_t t_tx_reqs;
352 uint32_t t_tx_stops;
353 uint32_t t_tx_wrbs;
354 uint32_t t_tx_compl;
355 uint32_t t_ipv6_ext_hdr_tx_drop;
356 };
357
358 struct oce_be_stats {
359 uint8_t be_on_die_temperature;
360 uint32_t be_tx_events;
361 uint32_t eth_red_drops;
362 uint32_t rx_drops_no_pbuf;
363 uint32_t rx_drops_no_txpb;
364 uint32_t rx_drops_no_erx_descr;
365 uint32_t rx_drops_no_tpre_descr;
366 uint32_t rx_drops_too_many_frags;
367 uint32_t rx_drops_invalid_ring;
368 uint32_t forwarded_packets;
369 uint32_t rx_drops_mtu;
370 uint32_t rx_crc_errors;
371 uint32_t rx_alignment_symbol_errors;
372 uint32_t rx_pause_frames;
373 uint32_t rx_priority_pause_frames;
374 uint32_t rx_control_frames;
375 uint32_t rx_in_range_errors;
376 uint32_t rx_out_range_errors;
377 uint32_t rx_frame_too_long;
378 uint32_t rx_address_match_errors;
379 uint32_t rx_dropped_too_small;
380 uint32_t rx_dropped_too_short;
381 uint32_t rx_dropped_header_too_small;
382 uint32_t rx_dropped_tcp_length;
383 uint32_t rx_dropped_runt;
384 uint32_t rx_ip_checksum_errs;
385 uint32_t rx_tcp_checksum_errs;
386 uint32_t rx_udp_checksum_errs;
387 uint32_t rx_switched_unicast_packets;
388 uint32_t rx_switched_multicast_packets;
389 uint32_t rx_switched_broadcast_packets;
390 uint32_t tx_pauseframes;
391 uint32_t tx_priority_pauseframes;
392 uint32_t tx_controlframes;
393 uint32_t rxpp_fifo_overflow_drop;
394 uint32_t rx_input_fifo_overflow_drop;
395 uint32_t pmem_fifo_overflow_drop;
396 uint32_t jabber_events;
397 };
398
399 struct oce_xe201_stats {
400 uint64_t tx_pkts;
401 uint64_t tx_unicast_pkts;
402 uint64_t tx_multicast_pkts;
403 uint64_t tx_broadcast_pkts;
404 uint64_t tx_bytes;
405 uint64_t tx_unicast_bytes;
406 uint64_t tx_multicast_bytes;
407 uint64_t tx_broadcast_bytes;
408 uint64_t tx_discards;
409 uint64_t tx_errors;
410 uint64_t tx_pause_frames;
411 uint64_t tx_pause_on_frames;
412 uint64_t tx_pause_off_frames;
413 uint64_t tx_internal_mac_errors;
414 uint64_t tx_control_frames;
415 uint64_t tx_pkts_64_bytes;
416 uint64_t tx_pkts_65_to_127_bytes;
417 uint64_t tx_pkts_128_to_255_bytes;
418 uint64_t tx_pkts_256_to_511_bytes;
419 uint64_t tx_pkts_512_to_1023_bytes;
420 uint64_t tx_pkts_1024_to_1518_bytes;
421 uint64_t tx_pkts_1519_to_2047_bytes;
422 uint64_t tx_pkts_2048_to_4095_bytes;
423 uint64_t tx_pkts_4096_to_8191_bytes;
424 uint64_t tx_pkts_8192_to_9216_bytes;
425 uint64_t tx_lso_pkts;
426 uint64_t rx_pkts;
427 uint64_t rx_unicast_pkts;
428 uint64_t rx_multicast_pkts;
429 uint64_t rx_broadcast_pkts;
430 uint64_t rx_bytes;
431 uint64_t rx_unicast_bytes;
432 uint64_t rx_multicast_bytes;
433 uint64_t rx_broadcast_bytes;
434 uint32_t rx_unknown_protos;
435 uint64_t rx_discards;
436 uint64_t rx_errors;
437 uint64_t rx_crc_errors;
438 uint64_t rx_alignment_errors;
439 uint64_t rx_symbol_errors;
440 uint64_t rx_pause_frames;
441 uint64_t rx_pause_on_frames;
442 uint64_t rx_pause_off_frames;
443 uint64_t rx_frames_too_long;
444 uint64_t rx_internal_mac_errors;
445 uint32_t rx_undersize_pkts;
446 uint32_t rx_oversize_pkts;
447 uint32_t rx_fragment_pkts;
448 uint32_t rx_jabbers;
449 uint64_t rx_control_frames;
450 uint64_t rx_control_frames_unknown_opcode;
451 uint32_t rx_in_range_errors;
452 uint32_t rx_out_of_range_errors;
453 uint32_t rx_address_match_errors;
454 uint32_t rx_vlan_mismatch_errors;
455 uint32_t rx_dropped_too_small;
456 uint32_t rx_dropped_too_short;
457 uint32_t rx_dropped_header_too_small;
458 uint32_t rx_dropped_invalid_tcp_length;
459 uint32_t rx_dropped_runt;
460 uint32_t rx_ip_checksum_errors;
461 uint32_t rx_tcp_checksum_errors;
462 uint32_t rx_udp_checksum_errors;
463 uint32_t rx_non_rss_pkts;
464 uint64_t rx_ipv4_pkts;
465 uint64_t rx_ipv6_pkts;
466 uint64_t rx_ipv4_bytes;
467 uint64_t rx_ipv6_bytes;
468 uint64_t rx_nic_pkts;
469 uint64_t rx_tcp_pkts;
470 uint64_t rx_iscsi_pkts;
471 uint64_t rx_management_pkts;
472 uint64_t rx_switched_unicast_pkts;
473 uint64_t rx_switched_multicast_pkts;
474 uint64_t rx_switched_broadcast_pkts;
475 uint64_t num_forwards;
476 uint32_t rx_fifo_overflow;
477 uint32_t rx_input_fifo_overflow;
478 uint64_t rx_drops_too_many_frags;
479 uint32_t rx_drops_invalid_queue;
480 uint64_t rx_drops_mtu;
481 uint64_t rx_pkts_64_bytes;
482 uint64_t rx_pkts_65_to_127_bytes;
483 uint64_t rx_pkts_128_to_255_bytes;
484 uint64_t rx_pkts_256_to_511_bytes;
485 uint64_t rx_pkts_512_to_1023_bytes;
486 uint64_t rx_pkts_1024_to_1518_bytes;
487 uint64_t rx_pkts_1519_to_2047_bytes;
488 uint64_t rx_pkts_2048_to_4095_bytes;
489 uint64_t rx_pkts_4096_to_8191_bytes;
490 uint64_t rx_pkts_8192_to_9216_bytes;
491 };
492
493 struct oce_drv_stats {
494 struct oce_rx_stats rx;
495 struct oce_tx_stats tx;
496 union {
497 struct oce_be_stats be;
498 struct oce_xe201_stats xe201;
499 } u0;
500 };
501
502 #define INTR_RATE_HWM 15000
503 #define INTR_RATE_LWM 10000
504
505 #define OCE_MAX_EQD 128u
506 #define OCE_MIN_EQD 0u
507
508 struct oce_set_eqd {
509 uint32_t eq_id;
510 uint32_t phase;
511 uint32_t delay_multiplier;
512 };
513
514 struct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
515 boolean_t enable;
516 uint32_t min_eqd; /* in usecs */
517 uint32_t max_eqd; /* in usecs */
518 uint32_t cur_eqd; /* in usecs */
519 uint32_t et_eqd; /* configured value when aic is off */
520 uint64_t ticks;
521 uint64_t prev_rxpkts;
522 uint64_t prev_txreqs;
523 };
524
525 #define MAX_LOCK_DESC_LEN 32
526 struct oce_lock {
527 struct mtx mutex;
528 char name[MAX_LOCK_DESC_LEN+1];
529 };
530 #define OCE_LOCK struct oce_lock
531
532 #define LOCK_CREATE(lock, desc) { \
533 strncpy((lock)->name, (desc), MAX_LOCK_DESC_LEN); \
534 (lock)->name[MAX_LOCK_DESC_LEN] = '\0'; \
535 mtx_init(&(lock)->mutex, (lock)->name, NULL, MTX_DEF); \
536 }
537 #define LOCK_DESTROY(lock) \
538 if (mtx_initialized(&(lock)->mutex))\
539 mtx_destroy(&(lock)->mutex)
540 #define TRY_LOCK(lock) mtx_trylock(&(lock)->mutex)
541 #define LOCK(lock) mtx_lock(&(lock)->mutex)
542 #define LOCKED(lock) mtx_owned(&(lock)->mutex)
543 #define UNLOCK(lock) mtx_unlock(&(lock)->mutex)
544
545 #define DEFAULT_MQ_MBOX_TIMEOUT (5 * 1000 * 1000)
546 #define MBX_READY_TIMEOUT (1 * 1000 * 1000)
547 #define DEFAULT_DRAIN_TIME 200
548 #define MBX_TIMEOUT_SEC 5
549 #define STAT_TIMEOUT 2000000
550
551 /* size of the packet descriptor array in a transmit queue */
552 #define OCE_TX_RING_SIZE 2048
553 #define OCE_RX_RING_SIZE 1024
554 #define OCE_WQ_PACKET_ARRAY_SIZE (OCE_TX_RING_SIZE/2)
555 #define OCE_RQ_PACKET_ARRAY_SIZE (OCE_RX_RING_SIZE)
556
557 struct oce_dev;
558
559 enum eq_len {
560 EQ_LEN_256 = 256,
561 EQ_LEN_512 = 512,
562 EQ_LEN_1024 = 1024,
563 EQ_LEN_2048 = 2048,
564 EQ_LEN_4096 = 4096
565 };
566
567 enum eqe_size {
568 EQE_SIZE_4 = 4,
569 EQE_SIZE_16 = 16
570 };
571
572 enum qtype {
573 QTYPE_EQ,
574 QTYPE_MQ,
575 QTYPE_WQ,
576 QTYPE_RQ,
577 QTYPE_CQ,
578 QTYPE_RSS
579 };
580
581 typedef enum qstate_e {
582 QDELETED = 0x0,
583 QCREATED = 0x1
584 } qstate_t;
585
586 struct eq_config {
587 enum eq_len q_len;
588 enum eqe_size item_size;
589 uint32_t q_vector_num;
590 uint8_t min_eqd;
591 uint8_t max_eqd;
592 uint8_t cur_eqd;
593 uint8_t pad;
594 };
595
596 struct oce_eq {
597 uint32_t eq_id;
598 void *parent;
599 void *cb_context;
600 oce_ring_buffer_t *ring;
601 uint32_t ref_count;
602 qstate_t qstate;
603 struct oce_cq *cq[OCE_MAX_CQ_EQ];
604 int cq_valid;
605 struct eq_config eq_cfg;
606 int vector;
607 uint64_t intr;
608 };
609
610 enum cq_len {
611 CQ_LEN_256 = 256,
612 CQ_LEN_512 = 512,
613 CQ_LEN_1024 = 1024,
614 CQ_LEN_2048 = 2048
615 };
616
617 struct cq_config {
618 enum cq_len q_len;
619 uint32_t item_size;
620 boolean_t is_eventable;
621 boolean_t sol_eventable;
622 boolean_t nodelay;
623 uint16_t dma_coalescing;
624 };
625
626 typedef uint16_t(*cq_handler_t) (void *arg1);
627
628 struct oce_cq {
629 uint32_t cq_id;
630 void *parent;
631 struct oce_eq *eq;
632 cq_handler_t cq_handler;
633 void *cb_arg;
634 oce_ring_buffer_t *ring;
635 qstate_t qstate;
636 struct cq_config cq_cfg;
637 uint32_t ref_count;
638 };
639
640 struct mq_config {
641 uint32_t eqd;
642 uint8_t q_len;
643 uint8_t pad[3];
644 };
645
646 struct oce_mq {
647 void *parent;
648 oce_ring_buffer_t *ring;
649 uint32_t mq_id;
650 struct oce_cq *cq;
651 struct oce_cq *async_cq;
652 uint32_t mq_free;
653 qstate_t qstate;
654 struct mq_config cfg;
655 };
656
657 struct oce_mbx_ctx {
658 struct oce_mbx *mbx;
659 void (*cb) (void *ctx);
660 void *cb_ctx;
661 };
662
663 struct wq_config {
664 uint8_t wq_type;
665 uint16_t buf_size;
666 uint8_t pad[1];
667 uint32_t q_len;
668 uint16_t pd_id;
669 uint16_t pci_fn_num;
670 uint32_t eqd; /* interrupt delay */
671 uint32_t nbufs;
672 uint32_t nhdl;
673 };
674
675 struct oce_tx_queue_stats {
676 uint64_t tx_pkts;
677 uint64_t tx_bytes;
678 uint32_t tx_reqs;
679 uint32_t tx_stops; /* number of times TX Q was stopped */
680 uint32_t tx_wrbs;
681 uint32_t tx_compl;
682 uint32_t tx_rate;
683 uint32_t ipv6_ext_hdr_tx_drop;
684 };
685
686 struct oce_wq {
687 OCE_LOCK tx_lock;
688 OCE_LOCK tx_compl_lock;
689 void *parent;
690 oce_ring_buffer_t *ring;
691 struct oce_cq *cq;
692 bus_dma_tag_t tag;
693 struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE];
694 uint32_t pkt_desc_tail;
695 uint32_t pkt_desc_head;
696 uint32_t wqm_used;
697 boolean_t resched;
698 uint32_t wq_free;
699 uint32_t tx_deferd;
700 uint32_t pkt_drops;
701 qstate_t qstate;
702 uint16_t wq_id;
703 struct wq_config cfg;
704 int queue_index;
705 struct oce_tx_queue_stats tx_stats;
706 struct buf_ring *br;
707 struct task txtask;
708 uint32_t db_offset;
709 };
710
711 struct rq_config {
712 uint32_t q_len;
713 uint32_t frag_size;
714 uint32_t mtu;
715 uint32_t if_id;
716 uint32_t is_rss_queue;
717 uint32_t eqd;
718 uint32_t nbufs;
719 };
720
721 struct oce_rx_queue_stats {
722 uint32_t rx_post_fail;
723 uint32_t rx_ucast_pkts;
724 uint32_t rx_compl;
725 uint64_t rx_bytes;
726 uint64_t rx_bytes_prev;
727 uint64_t rx_pkts;
728 uint32_t rx_rate;
729 uint32_t rx_mcast_pkts;
730 uint32_t rxcp_err;
731 uint32_t rx_frags;
732 uint32_t prev_rx_frags;
733 uint32_t rx_fps;
734 uint32_t rx_drops_no_frags; /* HW has no fetched frags */
735 };
736
737 struct oce_rq {
738 struct rq_config cfg;
739 uint32_t rq_id;
740 int queue_index;
741 uint32_t rss_cpuid;
742 void *parent;
743 oce_ring_buffer_t *ring;
744 struct oce_cq *cq;
745 void *pad1;
746 bus_dma_tag_t tag;
747 struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE];
748 uint32_t pending;
749 #ifdef notdef
750 struct mbuf *head;
751 struct mbuf *tail;
752 int fragsleft;
753 #endif
754 qstate_t qstate;
755 OCE_LOCK rx_lock;
756 struct oce_rx_queue_stats rx_stats;
757 struct lro_ctrl lro;
758 int lro_pkts_queued;
759 int islro;
760 struct nic_hwlro_cqe_part1 *cqe_firstpart;
761
762 };
763
764 struct link_status {
765 uint8_t phys_port_speed;
766 uint8_t logical_link_status;
767 uint16_t qos_link_speed;
768 };
769
770 #define OCE_FLAGS_PCIX 0x00000001
771 #define OCE_FLAGS_PCIE 0x00000002
772 #define OCE_FLAGS_MSI_CAPABLE 0x00000004
773 #define OCE_FLAGS_MSIX_CAPABLE 0x00000008
774 #define OCE_FLAGS_USING_MSI 0x00000010
775 #define OCE_FLAGS_USING_MSIX 0x00000020
776 #define OCE_FLAGS_FUNCRESET_RQD 0x00000040
777 #define OCE_FLAGS_VIRTUAL_PORT 0x00000080
778 #define OCE_FLAGS_MBOX_ENDIAN_RQD 0x00000100
779 #define OCE_FLAGS_BE3 0x00000200
780 #define OCE_FLAGS_XE201 0x00000400
781 #define OCE_FLAGS_BE2 0x00000800
782 #define OCE_FLAGS_SH 0x00001000
783 #define OCE_FLAGS_OS2BMC 0x00002000
784
785 #define OCE_DEV_BE2_CFG_BAR 1
786 #define OCE_DEV_CFG_BAR 0
787 #define OCE_PCI_CSR_BAR 2
788 #define OCE_PCI_DB_BAR 4
789
790 typedef struct oce_softc {
791 device_t dev;
792 OCE_LOCK dev_lock;
793
794 uint32_t flags;
795
796 uint32_t pcie_link_speed;
797 uint32_t pcie_link_width;
798
799 uint8_t fn; /* PCI function number */
800
801 struct resource *devcfg_res;
802 bus_space_tag_t devcfg_btag;
803 bus_space_handle_t devcfg_bhandle;
804 void *devcfg_vhandle;
805
806 struct resource *csr_res;
807 bus_space_tag_t csr_btag;
808 bus_space_handle_t csr_bhandle;
809 void *csr_vhandle;
810
811 struct resource *db_res;
812 bus_space_tag_t db_btag;
813 bus_space_handle_t db_bhandle;
814 void *db_vhandle;
815
816 OCE_INTR_INFO intrs[OCE_MAX_EQ];
817 int intr_count;
818 int roce_intr_count;
819
820 if_t ifp;
821
822 struct ifmedia media;
823 uint8_t link_status;
824 uint8_t link_speed;
825 uint8_t duplex;
826 uint32_t qos_link_speed;
827 uint32_t speed;
828 uint32_t enable_hwlro;
829
830 char fw_version[32];
831 struct mac_address_format macaddr;
832
833 OCE_DMA_MEM bsmbx;
834 OCE_LOCK bmbx_lock;
835
836 uint32_t config_number;
837 uint32_t asic_revision;
838 uint32_t port_id;
839 uint32_t function_mode;
840 uint32_t function_caps;
841 uint32_t max_tx_rings;
842 uint32_t max_rx_rings;
843
844 struct oce_wq *wq[OCE_MAX_WQ]; /* TX work queues */
845 struct oce_rq *rq[OCE_MAX_RQ]; /* RX work queues */
846 struct oce_cq *cq[OCE_MAX_CQ]; /* Completion queues */
847 struct oce_eq *eq[OCE_MAX_EQ]; /* Event queues */
848 struct oce_mq *mq; /* Mailbox queue */
849
850 uint32_t neqs;
851 uint32_t ncqs;
852 uint32_t nrqs;
853 uint32_t nwqs;
854 uint32_t nrssqs;
855
856 uint32_t tx_ring_size;
857 uint32_t rx_ring_size;
858 uint32_t rq_frag_size;
859
860 uint32_t if_id; /* interface ID */
861 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */
862 uint32_t pmac_id; /* PMAC id */
863
864 uint32_t if_cap_flags;
865
866 uint32_t flow_control;
867 uint8_t promisc;
868
869 struct oce_aic_obj aic_obj[OCE_MAX_EQ];
870
871 /*Vlan Filtering related */
872 eventhandler_tag vlan_attach;
873 eventhandler_tag vlan_detach;
874 uint16_t vlans_added;
875 uint8_t vlan_tag[MAX_VLANS];
876 /*stats */
877 OCE_DMA_MEM stats_mem;
878 struct oce_drv_stats oce_stats_info;
879 struct callout timer;
880 int8_t be3_native;
881 uint8_t hw_error;
882 uint16_t qnq_debug_event;
883 uint16_t qnqid;
884 uint32_t pvid;
885 uint32_t max_vlans;
886 uint32_t bmc_filt_mask;
887
888 void *rdma_context;
889 uint32_t rdma_flags;
890 struct oce_softc *next;
891
892 } OCE_SOFTC, *POCE_SOFTC;
893
894 #define OCE_RDMA_FLAG_SUPPORTED 0x00000001
895
896 /**************************************************
897 * BUS memory read/write macros
898 * BE3: accesses three BAR spaces (CFG, CSR, DB)
899 * Lancer: accesses one BAR space (CFG)
900 **************************************************/
901 #define OCE_READ_CSR_MPU(sc, space, o) \
902 ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \
903 (sc)->space##_bhandle,o)) \
904 : (bus_space_read_4((sc)->devcfg_btag, \
905 (sc)->devcfg_bhandle,o)))
906 #define OCE_READ_REG32(sc, space, o) \
907 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \
908 (sc)->space##_bhandle,o)) \
909 : (bus_space_read_4((sc)->devcfg_btag, \
910 (sc)->devcfg_bhandle,o)))
911 #define OCE_READ_REG16(sc, space, o) \
912 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \
913 (sc)->space##_bhandle,o)) \
914 : (bus_space_read_2((sc)->devcfg_btag, \
915 (sc)->devcfg_bhandle,o)))
916 #define OCE_READ_REG8(sc, space, o) \
917 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \
918 (sc)->space##_bhandle,o)) \
919 : (bus_space_read_1((sc)->devcfg_btag, \
920 (sc)->devcfg_bhandle,o)))
921
922 #define OCE_WRITE_CSR_MPU(sc, space, o, v) \
923 ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \
924 (sc)->space##_bhandle,o,v)) \
925 : (bus_space_write_4((sc)->devcfg_btag, \
926 (sc)->devcfg_bhandle,o,v)))
927 #define OCE_WRITE_REG32(sc, space, o, v) \
928 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \
929 (sc)->space##_bhandle,o,v)) \
930 : (bus_space_write_4((sc)->devcfg_btag, \
931 (sc)->devcfg_bhandle,o,v)))
932 #define OCE_WRITE_REG16(sc, space, o, v) \
933 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \
934 (sc)->space##_bhandle,o,v)) \
935 : (bus_space_write_2((sc)->devcfg_btag, \
936 (sc)->devcfg_bhandle,o,v)))
937 #define OCE_WRITE_REG8(sc, space, o, v) \
938 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \
939 (sc)->space##_bhandle,o,v)) \
940 : (bus_space_write_1((sc)->devcfg_btag, \
941 (sc)->devcfg_bhandle,o,v)))
942
943 void oce_rx_flush_lro(struct oce_rq *rq);
944 /***********************************************************
945 * DMA memory functions
946 ***********************************************************/
947 #define oce_dma_sync(d, f) bus_dmamap_sync((d)->tag, (d)->map, f)
948 int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags);
949 void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma);
950 void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error);
951 void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring);
952 oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc,
953 uint32_t q_len, uint32_t num_entries);
954 /************************************************************
955 * oce_hw_xxx functions
956 ************************************************************/
957 int oce_clear_rx_buf(struct oce_rq *rq);
958 int oce_hw_pci_alloc(POCE_SOFTC sc);
959 int oce_hw_init(POCE_SOFTC sc);
960 int oce_hw_start(POCE_SOFTC sc);
961 int oce_create_nw_interface(POCE_SOFTC sc);
962 int oce_pci_soft_reset(POCE_SOFTC sc);
963 int oce_hw_update_multicast(POCE_SOFTC sc);
964 void oce_delete_nw_interface(POCE_SOFTC sc);
965 void oce_hw_shutdown(POCE_SOFTC sc);
966 void oce_hw_intr_enable(POCE_SOFTC sc);
967 void oce_hw_intr_disable(POCE_SOFTC sc);
968 void oce_hw_pci_free(POCE_SOFTC sc);
969
970 /***********************************************************
971 * oce_queue_xxx functions
972 ***********************************************************/
973 int oce_queue_init_all(POCE_SOFTC sc);
974 int oce_start_rq(struct oce_rq *rq);
975 int oce_start_wq(struct oce_wq *wq);
976 int oce_start_mq(struct oce_mq *mq);
977 int oce_start_rx(POCE_SOFTC sc);
978 void oce_arm_eq(POCE_SOFTC sc,
979 int16_t qid, int npopped, uint32_t rearm, uint32_t clearint);
980 void oce_queue_release_all(POCE_SOFTC sc);
981 void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm);
982 void oce_drain_eq(struct oce_eq *eq);
983 void oce_drain_mq_cq(void *arg);
984 void oce_drain_rq_cq(struct oce_rq *rq);
985 void oce_drain_wq_cq(struct oce_wq *wq);
986
987 uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list);
988
989 /***********************************************************
990 * cleanup functions
991 ***********************************************************/
992 void oce_stop_rx(POCE_SOFTC sc);
993 void oce_discard_rx_comp(struct oce_rq *rq, int num_frags);
994 void oce_rx_cq_clean(struct oce_rq *rq);
995 void oce_rx_cq_clean_hwlro(struct oce_rq *rq);
996 void oce_intr_free(POCE_SOFTC sc);
997 void oce_free_posted_rxbuf(struct oce_rq *rq);
998 #if defined(INET6) || defined(INET)
999 void oce_free_lro(POCE_SOFTC sc);
1000 #endif
1001
1002 /************************************************************
1003 * Mailbox functions
1004 ************************************************************/
1005 int oce_fw_clean(POCE_SOFTC sc);
1006 int oce_wait_ready(POCE_SOFTC sc);
1007 int oce_reset_fun(POCE_SOFTC sc);
1008 int oce_mbox_init(POCE_SOFTC sc);
1009 int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec);
1010 int oce_get_fw_version(POCE_SOFTC sc);
1011 int oce_first_mcc_cmd(POCE_SOFTC sc);
1012
1013 int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm,
1014 uint8_t type, struct mac_address_format *mac);
1015 int oce_get_fw_config(POCE_SOFTC sc);
1016 int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags,
1017 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id);
1018 int oce_if_del(POCE_SOFTC sc, uint32_t if_id);
1019 int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id,
1020 struct normal_vlan *vtag_arr, uint8_t vtag_cnt,
1021 uint32_t untagged, uint32_t enable_promisc);
1022 int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control);
1023 int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss);
1024 int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable);
1025 int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl);
1026 int oce_get_link_status(POCE_SOFTC sc, struct link_status *link);
1027 int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1028 int oce_mbox_get_nic_stats_v1(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1029 int oce_mbox_get_nic_stats_v2(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1030 int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1031 uint32_t reset_stats);
1032 int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1033 uint32_t req_size, uint32_t reset_stats);
1034 int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem);
1035 int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size);
1036 int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id);
1037 int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1038 uint32_t if_id, uint32_t *pmac_id);
1039 int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1040 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1041 uint64_t pattern);
1042
1043 int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1044 uint8_t loopback_type, uint8_t enable);
1045
1046 int oce_mbox_check_native_mode(POCE_SOFTC sc);
1047 int oce_mbox_post(POCE_SOFTC sc,
1048 struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx);
1049 int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1050 POCE_DMA_MEM pdma_mem, uint32_t num_bytes);
1051 int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1052 uint32_t data_offset,POCE_DMA_MEM pdma_mem,
1053 uint32_t *written_data, uint32_t *additional_status);
1054
1055 int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1056 uint32_t offset, uint32_t optype);
1057 int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info);
1058 int oce_mbox_create_rq(struct oce_rq *rq);
1059 int oce_mbox_create_wq(struct oce_wq *wq);
1060 int oce_mbox_create_eq(struct oce_eq *eq);
1061 int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce,
1062 uint32_t is_eventable);
1063 int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num);
1064 void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1065 int num);
1066 int oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss);
1067 int oce_get_func_config(POCE_SOFTC sc);
1068 void mbx_common_req_hdr_init(struct mbx_hdr *hdr,
1069 uint8_t dom,
1070 uint8_t port,
1071 uint8_t subsys,
1072 uint8_t opcode,
1073 uint32_t timeout, uint32_t pyld_len,
1074 uint8_t version);
1075
1076 uint16_t oce_mq_handler(void *arg);
1077
1078 /************************************************************
1079 * Transmit functions
1080 ************************************************************/
1081 uint16_t oce_wq_handler(void *arg);
1082 void oce_start(if_t ifp);
1083 void oce_tx_task(void *arg, int npending);
1084
1085 /************************************************************
1086 * Receive functions
1087 ************************************************************/
1088 int oce_alloc_rx_bufs(struct oce_rq *rq, int count);
1089 uint16_t oce_rq_handler(void *arg);
1090
1091 /* Sysctl functions */
1092 void oce_add_sysctls(POCE_SOFTC sc);
1093 void oce_refresh_queue_stats(POCE_SOFTC sc);
1094 int oce_refresh_nic_stats(POCE_SOFTC sc);
1095 int oce_stats_init(POCE_SOFTC sc);
1096 void oce_stats_free(POCE_SOFTC sc);
1097
1098 /* hw lro functions */
1099 int oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags);
1100 int oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable);
1101 int oce_mbox_create_rq_v2(struct oce_rq *rq);
1102
1103 /* Capabilities */
1104 #define OCE_MODCAP_RSS 1
1105 #define OCE_MAX_RSP_HANDLED 64
1106 extern uint32_t oce_max_rsp_handled; /* max responses */
1107 extern uint32_t oce_rq_buf_size;
1108
1109 #define OCE_MAC_LOOPBACK 0x0
1110 #define OCE_PHY_LOOPBACK 0x1
1111 #define OCE_ONE_PORT_EXT_LOOPBACK 0x2
1112 #define OCE_NO_LOOPBACK 0xff
1113
1114 #undef IFM_40G_SR4
1115 #define IFM_40G_SR4 28
1116
1117 #define atomic_inc_32(x) atomic_add_32(x, 1)
1118 #define atomic_dec_32(x) atomic_subtract_32(x, 1)
1119
1120 #define LE_64(x) htole64(x)
1121 #define LE_32(x) htole32(x)
1122 #define LE_16(x) htole16(x)
1123 #define HOST_64(x) le64toh(x)
1124 #define HOST_32(x) le32toh(x)
1125 #define HOST_16(x) le16toh(x)
1126 #define DW_SWAP(x, l)
1127 #define IS_ALIGNED(x,a) ((x % a) == 0)
1128 #define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32))
1129 #define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff));
1130
1131 #define IF_LRO_ENABLED(sc) ((if_getcapenable((sc)->ifp) & IFCAP_LRO) ? 1:0)
1132 #define IF_LSO_ENABLED(sc) ((if_getcapenable((sc)->ifp) & IFCAP_TSO4) ? 1:0)
1133 #define IF_CSUM_ENABLED(sc) ((if_getcapenable((sc)->ifp) & IFCAP_HWCSUM) ? 1:0)
1134
1135 #define OCE_LOG2(x) (oce_highbit(x))
oce_highbit(uint32_t x)1136 static inline uint32_t oce_highbit(uint32_t x)
1137 {
1138 int i;
1139 int c;
1140 int b;
1141
1142 c = 0;
1143 b = 0;
1144
1145 for (i = 0; i < 32; i++) {
1146 if ((1 << i) & x) {
1147 c++;
1148 b = i;
1149 }
1150 }
1151
1152 if (c == 1)
1153 return b;
1154
1155 return 0;
1156 }
1157
MPU_EP_SEMAPHORE(POCE_SOFTC sc)1158 static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc)
1159 {
1160 if (IS_BE(sc))
1161 return MPU_EP_SEMAPHORE_BE3;
1162 else if (IS_SH(sc))
1163 return MPU_EP_SEMAPHORE_SH;
1164 else
1165 return MPU_EP_SEMAPHORE_XE201;
1166 }
1167
1168 #define TRANSCEIVER_DATA_NUM_ELE 64
1169 #define TRANSCEIVER_DATA_SIZE 256
1170 #define TRANSCEIVER_A0_SIZE 128
1171 #define TRANSCEIVER_A2_SIZE 128
1172 #define PAGE_NUM_A0 0xa0
1173 #define PAGE_NUM_A2 0xa2
1174 #define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\
1175 || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE)))
1176 extern uint8_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_SIZE];
1177
1178 struct oce_rdma_info;
1179 extern struct oce_rdma_if *oce_rdma_if;
1180
1181 /* OS2BMC related */
1182
1183 #define DHCP_CLIENT_PORT 68
1184 #define DHCP_SERVER_PORT 67
1185 #define NET_BIOS_PORT1 137
1186 #define NET_BIOS_PORT2 138
1187 #define DHCPV6_RAS_PORT 547
1188
1189 #define BMC_FILT_BROADCAST_ARP ((uint32_t)(1))
1190 #define BMC_FILT_BROADCAST_DHCP_CLIENT ((uint32_t)(1 << 1))
1191 #define BMC_FILT_BROADCAST_DHCP_SERVER ((uint32_t)(1 << 2))
1192 #define BMC_FILT_BROADCAST_NET_BIOS ((uint32_t)(1 << 3))
1193 #define BMC_FILT_BROADCAST ((uint32_t)(1 << 4))
1194 #define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER ((uint32_t)(1 << 5))
1195 #define BMC_FILT_MULTICAST_IPV6_RA ((uint32_t)(1 << 6))
1196 #define BMC_FILT_MULTICAST_IPV6_RAS ((uint32_t)(1 << 7))
1197 #define BMC_FILT_MULTICAST ((uint32_t)(1 << 8))
1198
1199 #define ND_ROUTER_ADVERT 134
1200 #define ND_NEIGHBOR_ADVERT 136
1201
1202 #define is_mc_allowed_on_bmc(sc, eh) \
1203 (!is_multicast_filt_enabled(sc) && \
1204 ETHER_IS_MULTICAST(eh->ether_dhost) && \
1205 !ETHER_IS_BROADCAST(eh->ether_dhost))
1206
1207 #define is_bc_allowed_on_bmc(sc, eh) \
1208 (!is_broadcast_filt_enabled(sc) && \
1209 ETHER_IS_BROADCAST(eh->ether_dhost))
1210
1211 #define is_arp_allowed_on_bmc(sc, et) \
1212 (is_arp(et) && is_arp_filt_enabled(sc))
1213
1214 #define is_arp(et) (et == ETHERTYPE_ARP)
1215
1216 #define is_arp_filt_enabled(sc) \
1217 (sc->bmc_filt_mask & (BMC_FILT_BROADCAST_ARP))
1218
1219 #define is_dhcp_client_filt_enabled(sc) \
1220 (sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_CLIENT)
1221
1222 #define is_dhcp_srvr_filt_enabled(sc) \
1223 (sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_SERVER)
1224
1225 #define is_nbios_filt_enabled(sc) \
1226 (sc->bmc_filt_mask & BMC_FILT_BROADCAST_NET_BIOS)
1227
1228 #define is_ipv6_na_filt_enabled(sc) \
1229 (sc->bmc_filt_mask & \
1230 BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER)
1231
1232 #define is_ipv6_ra_filt_enabled(sc) \
1233 (sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RA)
1234
1235 #define is_ipv6_ras_filt_enabled(sc) \
1236 (sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RAS)
1237
1238 #define is_broadcast_filt_enabled(sc) \
1239 (sc->bmc_filt_mask & BMC_FILT_BROADCAST)
1240
1241 #define is_multicast_filt_enabled(sc) \
1242 (sc->bmc_filt_mask & BMC_FILT_MULTICAST)
1243
1244 #define is_os2bmc_enabled(sc) (sc->flags & OCE_FLAGS_OS2BMC)
1245
1246 #define LRO_FLAGS_HASH_MODE 0x00000001
1247 #define LRO_FLAGS_RSS_MODE 0x00000004
1248 #define LRO_FLAGS_CLSC_IPV4 0x00000010
1249 #define LRO_FLAGS_CLSC_IPV6 0x00000020
1250 #define NIC_RQ_FLAGS_RSS 0x0001
1251 #define NIC_RQ_FLAGS_LRO 0x0020
1252