Searched defs:NumVecs (Results 1 – 9 of 9) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 1466 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable() 1678 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectLoad() 1707 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs, in SelectPostLoad() 1861 void AArch64DAGToDAGISel::SelectCVTIntrinsic(SDNode *N, unsigned NumVecs, in SelectCVTIntrinsic() 1877 unsigned NumVecs, in SelectDestructiveMultiIntrinsic() 1915 void AArch64DAGToDAGISel::SelectPredicatedLoad(SDNode *N, unsigned NumVecs, in SelectPredicatedLoad() 1949 unsigned NumVecs, in SelectContiguousMultiVectorLoad() 1983 void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N, unsigned NumVecs, in SelectFrintFromVT() 2018 void AArch64DAGToDAGISel::SelectClamp(SDNode *N, unsigned NumVecs, in SelectClamp() 2067 void AArch64DAGToDAGISel::SelectMultiVectorMove(SDNode *N, unsigned NumVecs, in SelectMultiVectorMove() [all …]
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H A D | AArch64TargetTransformInfo.cpp | 4065 unsigned NumVecs = (TpNumElts + LTNumElts - 1) / LTNumElts; in getShuffleCost() local
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H A D | AArch64ISelLowering.cpp | 23218 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | VectorUtils.cpp | 921 unsigned NumVecs) { in createInterleaveMask() 996 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 1945 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() 2110 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement() 2115 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD() 2257 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVST() 2412 unsigned NumVecs, in SelectVLDSTLane() 2791 void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs, in SelectMVE_VLD() 2954 bool isUpdating, unsigned NumVecs, in SelectVLDDup()
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H A D | ARMISelLowering.cpp | 15803 unsigned NumVecs = 0; in TryCombineBaseUpdate() local 16295 unsigned NumVecs = 0; in PerformMVEVLDCombine() local 16388 unsigned NumVecs = 0; in CombineVLDDUP() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64InstructionSelector.cpp | 5855 unsigned NumVecs, in selectVectorLoadIntrinsic() 5884 unsigned Opc, unsigned NumVecs, MachineInstr &I) { in selectVectorLoadLaneIntrinsic() 5937 unsigned NumVecs, in selectVectorStoreIntrinsic() 5955 MachineInstr &I, unsigned NumVecs, unsigned Opc) { in selectVectorStoreLaneIntrinsic()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 10974 int NumVecs = 2; in LowerINTRINSIC_WO_CHAIN() local 11557 unsigned NumVecs = VT.getSizeInBits() / 128; in LowerVectorLoad() local 11603 unsigned NumVecs = 2; in LowerVectorStore() local
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/freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | CGBuiltin.cpp | 17860 unsigned NumVecs = 2; in EmitPPCBuiltinExpr() local
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