| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1470 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable()
1729 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectLoad()
1758 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs, in SelectPostLoad()
1912 void AArch64DAGToDAGISel::SelectCVTIntrinsic(SDNode *N, unsigned NumVecs, in SelectCVTIntrinsic()
1927 void AArch64DAGToDAGISel::SelectCVTIntrinsicFP8(SDNode *N, unsigned NumVecs, in SelectCVTIntrinsicFP8()
1949 unsigned NumVecs, in SelectDestructiveMultiIntrinsic()
1986 void AArch64DAGToDAGISel::SelectPredicatedLoad(SDNode *N, unsigned NumVecs, in SelectPredicatedLoad()
2020 unsigned NumVecs, in SelectContiguousMultiVectorLoad()
2054 void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N, unsigned NumVecs, in SelectFrintFromVT()
2119 void AArch64DAGToDAGISel::SelectClamp(SDNode *N, unsigned NumVecs, in SelectClamp()
[all …]
|
| H A D | AArch64TargetTransformInfo.cpp | 5520 unsigned NumVecs = (TpNumElts + LTNumElts - 1) / LTNumElts; in getShuffleCost() local
|
| H A D | AArch64ISelLowering.cpp | 24374 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1936 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign()
2101 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement()
2106 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD()
2248 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVST()
2403 unsigned NumVecs, in SelectVLDSTLane()
2782 void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs, in SelectMVE_VLD()
2945 bool isUpdating, unsigned NumVecs, in SelectVLDDup()
|
| H A D | ARMISelLowering.cpp | 15898 unsigned NumVecs = 0; in TryCombineBaseUpdate() local
16372 unsigned NumVecs = 0; in PerformMVEVLDCombine() local
16465 unsigned NumVecs = 0; in CombineVLDDUP() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | VectorUtils.cpp | 1162 unsigned NumVecs) { in createInterleaveMask()
1237 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
|
| /freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/ |
| H A D | PPC.cpp | 1094 unsigned NumVecs = 2; in EmitPPCBuiltinExpr() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 6015 unsigned NumVecs, in selectVectorLoadIntrinsic()
6044 unsigned Opc, unsigned NumVecs, MachineInstr &I) { in selectVectorLoadLaneIntrinsic()
6097 unsigned NumVecs, in selectVectorStoreIntrinsic()
6115 MachineInstr &I, unsigned NumVecs, unsigned Opc) { in selectVectorStoreLaneIntrinsic()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11221 int NumVecs = 2; in LowerINTRINSIC_WO_CHAIN() local
12000 unsigned NumVecs = VT.getSizeInBits() / 256; in LowerDMFVectorLoad() local
12088 unsigned NumVecs = VT.getSizeInBits() / 128; in LowerVectorLoad() local
12211 unsigned NumVecs = VT.getSizeInBits() / 256; in LowerDMFVectorStore() local
12255 unsigned NumVecs = 2; in LowerVectorStore() local
|