1 //===- MIParser.h - Machine Instructions Parser -----------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares the function that parses the machine instructions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CODEGEN_MIRPARSER_MIPARSER_H 14 #define LLVM_CODEGEN_MIRPARSER_MIPARSER_H 15 16 #include "llvm/ADT/DenseMap.h" 17 #include "llvm/ADT/StringMap.h" 18 #include "llvm/CodeGen/MachineMemOperand.h" 19 #include "llvm/CodeGen/Register.h" 20 #include "llvm/IR/TrackingMDRef.h" 21 #include "llvm/Support/Allocator.h" 22 #include "llvm/Support/SMLoc.h" 23 #include <map> 24 #include <utility> 25 26 namespace llvm { 27 28 class MachineBasicBlock; 29 class MachineFunction; 30 class MDNode; 31 class RegisterBank; 32 struct SlotMapping; 33 class SMDiagnostic; 34 class SourceMgr; 35 class StringRef; 36 class TargetRegisterClass; 37 class TargetSubtargetInfo; 38 39 struct VRegInfo { 40 enum uint8_t { 41 UNKNOWN, NORMAL, GENERIC, REGBANK 42 } Kind = UNKNOWN; 43 bool Explicit = false; ///< VReg was explicitly specified in the .mir file. 44 union { 45 const TargetRegisterClass *RC; 46 const RegisterBank *RegBank; 47 } D; 48 Register VReg; 49 Register PreferredReg; 50 }; 51 52 using Name2RegClassMap = StringMap<const TargetRegisterClass *>; 53 using Name2RegBankMap = StringMap<const RegisterBank *>; 54 55 struct PerTargetMIParsingState { 56 private: 57 const TargetSubtargetInfo &Subtarget; 58 59 /// Maps from instruction names to op codes. 60 StringMap<unsigned> Names2InstrOpCodes; 61 62 /// Maps from register names to registers. 63 StringMap<Register> Names2Regs; 64 65 /// Maps from register mask names to register masks. 66 StringMap<const uint32_t *> Names2RegMasks; 67 68 /// Maps from subregister names to subregister indices. 69 StringMap<unsigned> Names2SubRegIndices; 70 71 /// Maps from target index names to target indices. 72 StringMap<int> Names2TargetIndices; 73 74 /// Maps from direct target flag names to the direct target flag values. 75 StringMap<unsigned> Names2DirectTargetFlags; 76 77 /// Maps from direct target flag names to the bitmask target flag values. 78 StringMap<unsigned> Names2BitmaskTargetFlags; 79 80 /// Maps from MMO target flag names to MMO target flag values. 81 StringMap<MachineMemOperand::Flags> Names2MMOTargetFlags; 82 83 /// Maps from register class names to register classes. 84 Name2RegClassMap Names2RegClasses; 85 86 /// Maps from register bank names to register banks. 87 Name2RegBankMap Names2RegBanks; 88 89 void initNames2InstrOpCodes(); 90 void initNames2Regs(); 91 void initNames2RegMasks(); 92 void initNames2SubRegIndices(); 93 void initNames2TargetIndices(); 94 void initNames2DirectTargetFlags(); 95 void initNames2BitmaskTargetFlags(); 96 void initNames2MMOTargetFlags(); 97 98 void initNames2RegClasses(); 99 void initNames2RegBanks(); 100 101 public: 102 /// Try to convert an instruction name to an opcode. Return true if the 103 /// instruction name is invalid. 104 bool parseInstrName(StringRef InstrName, unsigned &OpCode); 105 106 /// Try to convert a register name to a register number. Return true if the 107 /// register name is invalid. 108 bool getRegisterByName(StringRef RegName, Register &Reg); 109 110 /// Check if the given identifier is a name of a register mask. 111 /// 112 /// Return null if the identifier isn't a register mask. 113 const uint32_t *getRegMask(StringRef Identifier); 114 115 /// Check if the given identifier is a name of a subregister index. 116 /// 117 /// Return 0 if the name isn't a subregister index class. 118 unsigned getSubRegIndex(StringRef Name); 119 120 /// Try to convert a name of target index to the corresponding target index. 121 /// 122 /// Return true if the name isn't a name of a target index. 123 bool getTargetIndex(StringRef Name, int &Index); 124 125 /// Try to convert a name of a direct target flag to the corresponding 126 /// target flag. 127 /// 128 /// Return true if the name isn't a name of a direct flag. 129 bool getDirectTargetFlag(StringRef Name, unsigned &Flag); 130 131 /// Try to convert a name of a bitmask target flag to the corresponding 132 /// target flag. 133 /// 134 /// Return true if the name isn't a name of a bitmask target flag. 135 bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag); 136 137 /// Try to convert a name of a MachineMemOperand target flag to the 138 /// corresponding target flag. 139 /// 140 /// Return true if the name isn't a name of a target MMO flag. 141 bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag); 142 143 /// Check if the given identifier is a name of a register class. 144 /// 145 /// Return null if the name isn't a register class. 146 const TargetRegisterClass *getRegClass(StringRef Name); 147 148 /// Check if the given identifier is a name of a register bank. 149 /// 150 /// Return null if the name isn't a register bank. 151 const RegisterBank *getRegBank(StringRef Name); 152 153 PerTargetMIParsingState(const TargetSubtargetInfo &STI) 154 : Subtarget(STI) { 155 initNames2RegClasses(); 156 initNames2RegBanks(); 157 } 158 159 ~PerTargetMIParsingState() = default; 160 161 void setTarget(const TargetSubtargetInfo &NewSubtarget); 162 }; 163 164 struct PerFunctionMIParsingState { 165 BumpPtrAllocator Allocator; 166 MachineFunction &MF; 167 SourceMgr *SM; 168 const SlotMapping &IRSlots; 169 PerTargetMIParsingState &Target; 170 171 std::map<unsigned, TrackingMDNodeRef> MachineMetadataNodes; 172 std::map<unsigned, std::pair<TempMDTuple, SMLoc>> MachineForwardRefMDNodes; 173 174 DenseMap<unsigned, MachineBasicBlock *> MBBSlots; 175 DenseMap<Register, VRegInfo *> VRegInfos; 176 StringMap<VRegInfo *> VRegInfosNamed; 177 DenseMap<unsigned, int> FixedStackObjectSlots; 178 DenseMap<unsigned, int> StackObjectSlots; 179 DenseMap<unsigned, unsigned> ConstantPoolSlots; 180 DenseMap<unsigned, unsigned> JumpTableSlots; 181 182 /// Maps from slot numbers to function's unnamed values. 183 DenseMap<unsigned, const Value *> Slots2Values; 184 185 PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM, 186 const SlotMapping &IRSlots, 187 PerTargetMIParsingState &Target); 188 189 VRegInfo &getVRegInfo(Register Num); 190 VRegInfo &getVRegInfoNamed(StringRef RegName); 191 const Value *getIRValue(unsigned Slot); 192 }; 193 194 /// Parse the machine basic block definitions, and skip the machine 195 /// instructions. 196 /// 197 /// This function runs the first parsing pass on the machine function's body. 198 /// It parses only the machine basic block definitions and creates the machine 199 /// basic blocks in the given machine function. 200 /// 201 /// The machine instructions aren't parsed during the first pass because all 202 /// the machine basic blocks aren't defined yet - this makes it impossible to 203 /// resolve the machine basic block references. 204 /// 205 /// Return true if an error occurred. 206 bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS, 207 StringRef Src, SMDiagnostic &Error); 208 209 /// Parse the machine instructions. 210 /// 211 /// This function runs the second parsing pass on the machine function's body. 212 /// It skips the machine basic block definitions and parses only the machine 213 /// instructions and basic block attributes like liveins and successors. 214 /// 215 /// The second parsing pass assumes that the first parsing pass already ran 216 /// on the given source string. 217 /// 218 /// Return true if an error occurred. 219 bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src, 220 SMDiagnostic &Error); 221 222 bool parseMBBReference(PerFunctionMIParsingState &PFS, 223 MachineBasicBlock *&MBB, StringRef Src, 224 SMDiagnostic &Error); 225 226 bool parseRegisterReference(PerFunctionMIParsingState &PFS, 227 Register &Reg, StringRef Src, 228 SMDiagnostic &Error); 229 230 bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, 231 StringRef Src, SMDiagnostic &Error); 232 233 bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS, 234 VRegInfo *&Info, StringRef Src, 235 SMDiagnostic &Error); 236 237 bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI, 238 StringRef Src, SMDiagnostic &Error); 239 240 bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src, 241 SMDiagnostic &Error); 242 243 bool parseMachineMetadata(PerFunctionMIParsingState &PFS, StringRef Src, 244 SMRange SourceRange, SMDiagnostic &Error); 245 246 } // end namespace llvm 247 248 #endif // LLVM_CODEGEN_MIRPARSER_MIPARSER_H 249