xref: /illumos-gate/usr/src/uts/common/io/nxge/npi/npi_txc.h (revision 2d6eb4a5e0a47d30189497241345dc5466bb68ab)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _NPI_TXC_H
27 #define	_NPI_TXC_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #include <npi.h>
34 #include <nxge_txc_hw.h>
35 
36 /*
37  * Transmit Controller (TXC) NPI error codes
38  */
39 #define	TXC_ER_ST			(TXC_BLK_ID << NPI_BLOCK_ID_SHIFT)
40 #define	TXC_ID_SHIFT(n)			(n << NPI_PORT_CHAN_SHIFT)
41 
42 #define	NPI_TXC_PORT_INVALID(n)		(TXC_ID_SHIFT(n) | IS_PORT |\
43 					TXC_ER_ST | PORT_INVALID)
44 
45 #define	NPI_TXC_CHANNEL_INVALID(n)	(TXC_ID_SHIFT(n) | IS_PORT |\
46 					TXC_ER_ST | CHANNEL_INVALID)
47 
48 #define	NPI_TXC_OPCODE_INVALID(n)	(TXC_ID_SHIFT(n) | IS_PORT |\
49 					TXC_ER_ST | OPCODE_INVALID)
50 
51 /*
52  * Register offset (0x1000 bytes for each channel) for TXC registers.
53  */
54 #define	NXGE_TXC_FZC_OFFSET(x, cn)	(x + TXC_FZC_CHANNEL_OFFSET(cn))
55 
56 /*
57  * Register offset (0x100 bytes for each port) for TXC Function zero
58  * control registers.
59  */
60 #define	NXGE_TXC_FZC_CNTL_OFFSET(x, port) (x + \
61 			TXC_FZC_CNTL_PORT_OFFSET(port))
62 /*
63  * PIO macros to read and write the transmit control registers.
64  */
65 #define	TXC_FZC_REG_READ64(handle, reg, cn, val_p)	\
66 		NXGE_REG_RD64(handle, \
67 		(NXGE_TXC_FZC_OFFSET(reg, cn)), val_p)
68 
69 #define	TXC_FZC_REG_WRITE64(handle, reg, cn, data)	\
70 		NXGE_REG_WR64(handle, \
71 		(NXGE_TXC_FZC_OFFSET(reg, cn)), data)
72 
73 #define	TXC_FZC_CNTL_REG_READ64(handle, reg, port, val_p)	\
74 		NXGE_REG_RD64(handle, \
75 		(NXGE_TXC_FZC_CNTL_OFFSET(reg, port)), val_p)
76 
77 #define	TXC_FZC_CNTL_REG_WRITE64(handle, reg, port, data)	\
78 		NXGE_REG_WR64(handle, \
79 		(NXGE_TXC_FZC_CNTL_OFFSET(reg, port)), data)
80 
81 /*
82  * TXC (Transmit Controller) prototypes.
83  */
84 npi_status_t npi_txc_dma_max_burst(npi_handle_t, io_op_t,
85 		uint8_t, uint32_t *);
86 npi_status_t npi_txc_dma_max_burst_set(npi_handle_t, uint8_t,
87 		uint32_t);
88 npi_status_t npi_txc_dma_bytes_transmitted(npi_handle_t,
89 		uint8_t, uint32_t *);
90 npi_status_t npi_txc_control(npi_handle_t, io_op_t,
91 		p_txc_control_t);
92 npi_status_t npi_txc_global_enable(npi_handle_t);
93 npi_status_t npi_txc_global_disable(npi_handle_t);
94 npi_status_t npi_txc_control_clear(npi_handle_t, uint8_t);
95 npi_status_t npi_txc_training_set(npi_handle_t, uint32_t);
96 npi_status_t npi_txc_training_get(npi_handle_t, uint32_t *);
97 npi_status_t npi_txc_port_control_get(npi_handle_t, uint8_t,
98 		uint32_t *);
99 npi_status_t npi_txc_port_enable(npi_handle_t, uint8_t);
100 npi_status_t npi_txc_port_disable(npi_handle_t, uint8_t);
101 npi_status_t npi_txc_dma_max_burst(npi_handle_t, io_op_t,
102 		uint8_t, uint32_t *);
103 npi_status_t npi_txc_port_dma_enable(npi_handle_t, uint8_t,
104 		uint32_t);
105 npi_status_t npi_txc_port_dma_list_get(npi_handle_t, uint8_t,
106 		uint32_t *);
107 npi_status_t npi_txc_port_dma_channel_enable(npi_handle_t, uint8_t,
108 		uint8_t);
109 npi_status_t npi_txc_port_dma_channel_disable(npi_handle_t, uint8_t,
110 		uint8_t);
111 
112 npi_status_t npi_txc_pkt_stuffed_get(npi_handle_t, uint8_t,
113 		uint32_t *, uint32_t *);
114 npi_status_t npi_txc_pkt_xmt_to_mac_get(npi_handle_t, uint8_t,
115 		uint32_t *, uint32_t *);
116 npi_status_t npi_txc_reorder_get(npi_handle_t, uint8_t,
117 		uint32_t *);
118 npi_status_t npi_txc_dump_tdc_fzc_regs(npi_handle_t, uint8_t);
119 npi_status_t npi_txc_dump_fzc_regs(npi_handle_t);
120 npi_status_t npi_txc_dump_port_fzc_regs(npi_handle_t, uint8_t);
121 npi_status_t npi_txc_ro_states_get(npi_handle_t, uint8_t,
122 		txc_ro_states_t *);
123 npi_status_t npi_txc_ro_ecc_state_clr(npi_handle_t, uint8_t);
124 npi_status_t npi_txc_sf_states_get(npi_handle_t, uint8_t,
125 		txc_sf_states_t *);
126 npi_status_t npi_txc_sf_ecc_state_clr(npi_handle_t, uint8_t);
127 void npi_txc_global_istatus_get(npi_handle_t, txc_int_stat_t *);
128 void npi_txc_global_istatus_clear(npi_handle_t, uint64_t);
129 void npi_txc_global_imask_set(npi_handle_t, uint8_t,
130 		uint8_t);
131 
132 #ifdef	__cplusplus
133 }
134 #endif
135 
136 #endif	/* _NPI_TXC_H */
137