1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2012-2014 Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #ifndef __NVME_PRIVATE_H__
30 #define __NVME_PRIVATE_H__
31
32 #include <sys/param.h>
33 #include <sys/bio.h>
34 #include <sys/bus.h>
35 #include <sys/counter.h>
36 #include <sys/kernel.h>
37 #include <sys/lock.h>
38 #include <sys/malloc.h>
39 #include <sys/memdesc.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/rman.h>
43 #include <sys/systm.h>
44 #include <sys/taskqueue.h>
45
46 #include <vm/uma.h>
47
48 #include <machine/bus.h>
49
50 #include "nvme.h"
51
52 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev))
53
54 MALLOC_DECLARE(M_NVME);
55
56 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */
57 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */
58
59 #define NVME_ADMIN_TRACKERS (16)
60 #define NVME_ADMIN_ENTRIES (128)
61
62 /*
63 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion
64 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we
65 * will allow outstanding on an I/O qpair at any time. The only advantage in
66 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping
67 * the contents of the submission and completion queues, it will show a longer
68 * history of data.
69 */
70 #define NVME_IO_ENTRIES (256)
71 #define NVME_IO_TRACKERS (128)
72 #define NVME_MIN_IO_TRACKERS (4)
73 #define NVME_MAX_IO_TRACKERS (1024)
74
75 #define NVME_INT_COAL_TIME (0) /* disabled */
76 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */
77
78 #define NVME_MAX_NAMESPACES (16)
79 #define NVME_MAX_ASYNC_EVENTS (8)
80
81 #define NVME_ADMIN_TIMEOUT_PERIOD (60) /* in seconds */
82 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */
83 #define NVME_MIN_TIMEOUT_PERIOD (5)
84 #define NVME_MAX_TIMEOUT_PERIOD (120)
85
86 #define NVME_DEFAULT_RETRY_COUNT (4)
87
88 /* Maximum log page size to fetch for AERs. */
89 #define NVME_MAX_AER_LOG_SIZE (4096)
90
91 /*
92 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define
93 * it.
94 */
95 #ifndef CACHE_LINE_SIZE
96 #define CACHE_LINE_SIZE (64)
97 #endif
98
99 #define NVME_GONE 0xfffffffful
100
101 extern int32_t nvme_retry_count;
102 extern bool nvme_verbose_cmd_dump;
103
104 struct nvme_completion_poll_status {
105 struct nvme_completion cpl;
106 int done;
107 };
108
109 struct nvme_request {
110 struct nvme_command cmd;
111 struct nvme_qpair *qpair;
112 struct memdesc payload;
113 nvme_cb_fn_t cb_fn;
114 void *cb_arg;
115 int32_t retries;
116 bool payload_valid;
117 bool timeout;
118 bool spare[2]; /* Future use */
119 STAILQ_ENTRY(nvme_request) stailq;
120 };
121
122 struct nvme_async_event_request {
123 struct nvme_controller *ctrlr;
124 struct nvme_request *req;
125 struct task task;
126 struct mtx mtx;
127 struct nvme_completion cpl;
128 uint32_t log_page_id;
129 uint32_t log_page_size;
130 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE];
131 };
132
133 struct nvme_tracker {
134 TAILQ_ENTRY(nvme_tracker) tailq;
135 struct nvme_request *req;
136 struct nvme_qpair *qpair;
137 sbintime_t deadline;
138 bus_dmamap_t payload_dma_map;
139 uint16_t cid;
140
141 uint64_t *prp;
142 bus_addr_t prp_bus_addr;
143 };
144
145 enum nvme_recovery {
146 RECOVERY_NONE = 0, /* Normal operations */
147 RECOVERY_WAITING, /* waiting for the reset to complete */
148 };
149 struct nvme_qpair {
150 struct nvme_controller *ctrlr;
151 uint32_t id;
152 int domain;
153 int cpu;
154
155 uint16_t vector;
156 int rid;
157 struct resource *res;
158 void *tag;
159
160 struct callout timer; /* recovery lock */
161 bool timer_armed; /* recovery lock */
162 enum nvme_recovery recovery_state; /* recovery lock */
163
164 uint32_t num_entries;
165 uint32_t num_trackers;
166 uint32_t sq_tdbl_off;
167 uint32_t cq_hdbl_off;
168
169 uint32_t phase;
170 uint32_t sq_head;
171 uint32_t sq_tail;
172 uint32_t cq_head;
173
174 int64_t num_cmds;
175 int64_t num_intr_handler_calls;
176 int64_t num_retries;
177 int64_t num_failures;
178 int64_t num_ignored;
179 int64_t num_recovery_nolock;
180
181 struct nvme_command *cmd;
182 struct nvme_completion *cpl;
183
184 bus_dma_tag_t dma_tag;
185 bus_dma_tag_t dma_tag_payload;
186
187 bus_dmamap_t queuemem_map;
188 uint64_t cmd_bus_addr;
189 uint64_t cpl_bus_addr;
190
191 TAILQ_HEAD(, nvme_tracker) free_tr;
192 TAILQ_HEAD(, nvme_tracker) outstanding_tr;
193 STAILQ_HEAD(, nvme_request) queued_req;
194
195 struct nvme_tracker **act_tr;
196
197 struct mtx_padalign lock;
198 struct mtx_padalign recovery;
199 } __aligned(CACHE_LINE_SIZE);
200
201 struct nvme_namespace {
202 struct nvme_controller *ctrlr;
203 struct nvme_namespace_data data;
204 uint32_t id;
205 uint32_t flags;
206 struct cdev *cdev;
207 uint32_t boundary;
208 struct mtx lock;
209 };
210
211 /*
212 * One of these per allocated PCI device.
213 */
214 struct nvme_controller {
215 device_t dev;
216
217 struct mtx lock;
218 int domain;
219 uint32_t ready_timeout_in_ms;
220 uint32_t quirks;
221 #define QUIRK_DELAY_B4_CHK_RDY 1 /* Can't touch MMIO on disable */
222 #define QUIRK_DISABLE_TIMEOUT 2 /* Disable broken completion timeout feature */
223 #define QUIRK_INTEL_ALIGNMENT 4 /* Pre NVMe 1.3 performance alignment */
224 #define QUIRK_AHCI 8 /* Attached via AHCI redirect */
225
226 bus_space_tag_t bus_tag;
227 bus_space_handle_t bus_handle;
228 int resource_id;
229 struct resource *resource;
230
231 /*
232 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5,
233 * separate from the control registers which are in BAR 0/1. These
234 * members track the mapping of BAR 4/5 for that reason.
235 */
236 int msix_table_resource_id;
237 struct resource *msix_table_resource;
238 int msix_pba_resource_id;
239 struct resource *msix_pba_resource;
240
241 int msi_count;
242 uint32_t enable_aborts;
243
244 uint32_t num_io_queues;
245 uint32_t max_hw_pend_io;
246
247 /* Fields for tracking progress during controller initialization. */
248 struct intr_config_hook config_hook;
249 uint32_t ns_identified;
250 uint32_t queues_created;
251
252 struct task reset_task;
253 struct taskqueue *taskqueue;
254
255 /* For shared legacy interrupt. */
256 int rid;
257 struct resource *res;
258 void *tag;
259
260 /** maximum i/o size in bytes */
261 uint32_t max_xfer_size;
262
263 /** LO and HI capacity mask */
264 uint32_t cap_lo;
265 uint32_t cap_hi;
266
267 /** Page size and log2(page_size) - 12 that we're currently using */
268 uint32_t page_size;
269 uint32_t mps;
270
271 /** interrupt coalescing time period (in microseconds) */
272 uint32_t int_coal_time;
273
274 /** interrupt coalescing threshold */
275 uint32_t int_coal_threshold;
276
277 /** timeout period in seconds */
278 uint32_t admin_timeout_period;
279 uint32_t timeout_period;
280
281 /** doorbell stride */
282 uint32_t dstrd;
283
284 struct nvme_qpair adminq;
285 struct nvme_qpair *ioq;
286
287 struct nvme_registers *regs;
288
289 struct nvme_controller_data cdata;
290 struct nvme_namespace ns[NVME_MAX_NAMESPACES];
291
292 struct cdev *cdev;
293
294 /** bit mask of event types currently enabled for async events */
295 uint32_t async_event_config;
296
297 uint32_t num_aers;
298 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS];
299
300 uint32_t is_resetting;
301 u_int fail_on_reset;
302
303 bool is_failed;
304 bool is_failed_admin;
305 bool is_dying;
306 bool isr_warned;
307 bool is_initialized;
308
309 /* Host Memory Buffer */
310 int hmb_nchunks;
311 size_t hmb_chunk;
312 bus_dma_tag_t hmb_tag;
313 struct nvme_hmb_chunk {
314 bus_dmamap_t hmbc_map;
315 void *hmbc_vaddr;
316 uint64_t hmbc_paddr;
317 } *hmb_chunks;
318 bus_dma_tag_t hmb_desc_tag;
319 bus_dmamap_t hmb_desc_map;
320 struct nvme_hmb_desc *hmb_desc_vaddr;
321 uint64_t hmb_desc_paddr;
322
323 /* Statistics */
324 counter_u64_t alignment_splits;
325 };
326
327 #define nvme_mmio_offsetof(reg) \
328 offsetof(struct nvme_registers, reg)
329
330 #define nvme_mmio_read_4(sc, reg) \
331 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \
332 nvme_mmio_offsetof(reg))
333
334 #define nvme_mmio_write_4(sc, reg, val) \
335 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
336 nvme_mmio_offsetof(reg), val)
337
338 #define nvme_mmio_write_8(sc, reg, val) \
339 do { \
340 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
341 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \
342 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
343 nvme_mmio_offsetof(reg)+4, \
344 (val & 0xFFFFFFFF00000000ULL) >> 32); \
345 } while (0);
346
347 #define nvme_printf(ctrlr, fmt, args...) \
348 device_printf(ctrlr->dev, fmt, ##args)
349
350 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg);
351
352 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr,
353 void *payload,
354 nvme_cb_fn_t cb_fn, void *cb_arg);
355 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr,
356 uint32_t nsid, void *payload,
357 nvme_cb_fn_t cb_fn, void *cb_arg);
358 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr,
359 uint32_t microseconds,
360 uint32_t threshold,
361 nvme_cb_fn_t cb_fn,
362 void *cb_arg);
363 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr,
364 struct nvme_error_information_entry *payload,
365 uint32_t num_entries, /* 0 = max */
366 nvme_cb_fn_t cb_fn,
367 void *cb_arg);
368 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr,
369 uint32_t nsid,
370 struct nvme_health_information_page *payload,
371 nvme_cb_fn_t cb_fn,
372 void *cb_arg);
373 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr,
374 struct nvme_firmware_page *payload,
375 nvme_cb_fn_t cb_fn,
376 void *cb_arg);
377 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr,
378 struct nvme_qpair *io_que,
379 nvme_cb_fn_t cb_fn, void *cb_arg);
380 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr,
381 struct nvme_qpair *io_que,
382 nvme_cb_fn_t cb_fn, void *cb_arg);
383 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr,
384 struct nvme_qpair *io_que,
385 nvme_cb_fn_t cb_fn, void *cb_arg);
386 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr,
387 struct nvme_qpair *io_que,
388 nvme_cb_fn_t cb_fn, void *cb_arg);
389 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr,
390 uint32_t num_queues, nvme_cb_fn_t cb_fn,
391 void *cb_arg);
392 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr,
393 uint32_t state,
394 nvme_cb_fn_t cb_fn, void *cb_arg);
395 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid,
396 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg);
397
398 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl);
399
400 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev);
401 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev);
402 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr);
403 void nvme_ctrlr_reset(struct nvme_controller *ctrlr);
404 /* ctrlr defined as void * to allow use with config_intrhook. */
405 void nvme_ctrlr_start_config_hook(void *ctrlr_arg);
406 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr,
407 struct nvme_request *req);
408 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
409 struct nvme_request *req);
410
411 int nvme_qpair_construct(struct nvme_qpair *qpair,
412 uint32_t num_entries, uint32_t num_trackers,
413 struct nvme_controller *ctrlr);
414 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair,
415 struct nvme_tracker *tr);
416 bool nvme_qpair_process_completions(struct nvme_qpair *qpair);
417 void nvme_qpair_submit_request(struct nvme_qpair *qpair,
418 struct nvme_request *req);
419 void nvme_qpair_reset(struct nvme_qpair *qpair);
420 void nvme_qpair_fail(struct nvme_qpair *qpair);
421
422 void nvme_admin_qpair_enable(struct nvme_qpair *qpair);
423 void nvme_admin_qpair_disable(struct nvme_qpair *qpair);
424 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair);
425
426 void nvme_io_qpair_enable(struct nvme_qpair *qpair);
427 void nvme_io_qpair_disable(struct nvme_qpair *qpair);
428 void nvme_io_qpair_destroy(struct nvme_qpair *qpair);
429
430 int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id,
431 struct nvme_controller *ctrlr);
432 void nvme_ns_destruct(struct nvme_namespace *ns);
433
434 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr);
435
436 void nvme_qpair_print_command(struct nvme_qpair *qpair,
437 struct nvme_command *cmd);
438 void nvme_qpair_print_completion(struct nvme_qpair *qpair,
439 struct nvme_completion *cpl);
440
441 int nvme_attach(device_t dev);
442 int nvme_shutdown(device_t dev);
443 int nvme_detach(device_t dev);
444
445 /*
446 * Wait for a command to complete using the nvme_completion_poll_cb. Used in
447 * limited contexts where the caller knows it's OK to block briefly while the
448 * command runs. The ISR will run the callback which will set status->done to
449 * true, usually within microseconds. If not, then after one second timeout
450 * handler should reset the controller and abort all outstanding requests
451 * including this polled one. If still not after ten seconds, then something is
452 * wrong with the driver, and panic is the only way to recover.
453 *
454 * Most commands using this interface aren't actual I/O to the drive's media so
455 * complete within a few microseconds. Adaptively spin for one tick to catch the
456 * vast majority of these without waiting for a tick plus scheduling delays. Since
457 * these are on startup, this drastically reduces startup time.
458 */
459 static __inline void
nvme_completion_poll(struct nvme_completion_poll_status * status)460 nvme_completion_poll(struct nvme_completion_poll_status *status)
461 {
462 int timeout = ticks + 10 * hz;
463 sbintime_t delta = SBT_1US;
464
465 while (!atomic_load_acq_int(&status->done)) {
466 if (timeout - ticks < 0)
467 panic("NVME polled command failed to complete within 10s.");
468 pause_sbt("nvme", delta, 0, C_PREL(1));
469 delta = min(SBT_1MS, delta + delta / 2);
470 }
471 }
472
473 static __inline void
nvme_single_map(void * arg,bus_dma_segment_t * seg,int nseg,int error)474 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
475 {
476 uint64_t *bus_addr = (uint64_t *)arg;
477
478 KASSERT(nseg == 1, ("number of segments (%d) is not 1", nseg));
479 if (error != 0)
480 printf("nvme_single_map err %d\n", error);
481 *bus_addr = seg[0].ds_addr;
482 }
483
484 static __inline struct nvme_request *
_nvme_allocate_request(const int how,nvme_cb_fn_t cb_fn,void * cb_arg)485 _nvme_allocate_request(const int how, nvme_cb_fn_t cb_fn, void *cb_arg)
486 {
487 struct nvme_request *req;
488
489 KASSERT(how == M_WAITOK || how == M_NOWAIT,
490 ("nvme_allocate_request: invalid how %d", how));
491
492 req = malloc(sizeof(*req), M_NVME, how | M_ZERO);
493 if (req != NULL) {
494 req->cb_fn = cb_fn;
495 req->cb_arg = cb_arg;
496 req->timeout = true;
497 }
498 return (req);
499 }
500
501 static __inline struct nvme_request *
nvme_allocate_request_vaddr(void * payload,uint32_t payload_size,const int how,nvme_cb_fn_t cb_fn,void * cb_arg)502 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size,
503 const int how, nvme_cb_fn_t cb_fn, void *cb_arg)
504 {
505 struct nvme_request *req;
506
507 req = _nvme_allocate_request(how, cb_fn, cb_arg);
508 if (req != NULL) {
509 req->payload = memdesc_vaddr(payload, payload_size);
510 req->payload_valid = true;
511 }
512 return (req);
513 }
514
515 static __inline struct nvme_request *
nvme_allocate_request_null(const int how,nvme_cb_fn_t cb_fn,void * cb_arg)516 nvme_allocate_request_null(const int how, nvme_cb_fn_t cb_fn, void *cb_arg)
517 {
518 struct nvme_request *req;
519
520 req = _nvme_allocate_request(how, cb_fn, cb_arg);
521 return (req);
522 }
523
524 static __inline struct nvme_request *
nvme_allocate_request_bio(struct bio * bio,const int how,nvme_cb_fn_t cb_fn,void * cb_arg)525 nvme_allocate_request_bio(struct bio *bio, const int how, nvme_cb_fn_t cb_fn,
526 void *cb_arg)
527 {
528 struct nvme_request *req;
529
530 req = _nvme_allocate_request(how, cb_fn, cb_arg);
531 if (req != NULL) {
532 req->payload = memdesc_bio(bio);
533 req->payload_valid = true;
534 }
535 return (req);
536 }
537
538 static __inline struct nvme_request *
nvme_allocate_request_ccb(union ccb * ccb,const int how,nvme_cb_fn_t cb_fn,void * cb_arg)539 nvme_allocate_request_ccb(union ccb *ccb, const int how, nvme_cb_fn_t cb_fn,
540 void *cb_arg)
541 {
542 struct nvme_request *req;
543
544 req = _nvme_allocate_request(how, cb_fn, cb_arg);
545 if (req != NULL) {
546 req->payload = memdesc_ccb(ccb);
547 req->payload_valid = true;
548 }
549 return (req);
550 }
551
552 #define nvme_free_request(req) free(req, M_NVME)
553
554 void nvme_notify_async(struct nvme_controller *ctrlr,
555 const struct nvme_completion *async_cpl,
556 uint32_t log_page_id, void *log_page_buffer,
557 uint32_t log_page_size);
558 void nvme_notify_fail(struct nvme_controller *ctrlr);
559
560 void nvme_ctrlr_shared_handler(void *arg);
561 void nvme_ctrlr_poll(struct nvme_controller *ctrlr);
562
563 int nvme_ctrlr_suspend(struct nvme_controller *ctrlr);
564 int nvme_ctrlr_resume(struct nvme_controller *ctrlr);
565
566 #endif /* __NVME_PRIVATE_H__ */
567