xref: /titanic_41/usr/src/uts/sun4v/sys/niagararegs.h (revision 4df55fde49134f9735f84011f23a767c75e393c7)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _SYS_NIAGARAREGS_H
28 #define	_SYS_NIAGARAREGS_H
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
34 /*
35  * Niagara SPARC Performance Instrumentation Counter
36  */
37 #define	PIC0_MASK (((uint64_t)1 << 32) - 1)	/* pic0 in bits 31:0 */
38 #define	PIC1_SHIFT 32				/* pic1 in bits 64:32 */
39 
40 /*
41  * Niagara SPARC Performance Control Register
42  */
43 
44 #define	CPC_PCR_PRIVPIC		0
45 #define	CPC_PCR_SYS		1
46 #define	CPC_PCR_USR		2
47 
48 #define	CPC_PCR_PIC0_SHIFT	4
49 #define	CPC_PCR_PIC1_SHIFT	0
50 #define	CPC_PCR_PIC0_MASK	UINT64_C(0x7)
51 #define	CPC_PCR_PIC1_MASK	UINT64_C(0)
52 
53 #define	CPC_PCR_OVF_MASK	UINT64_C(0x300)
54 #define	CPC_PCR_OVF_SHIFT	8
55 
56 /*
57  * Niagara DRAM performance counters
58  */
59 #define	DRAM_BANKS		0x4
60 
61 #define	DRAM_PIC0_SEL_SHIFT	0x4
62 #define	DRAM_PIC1_SEL_SHIFT	0x0
63 
64 #define	DRAM_PIC0_SHIFT		0x20
65 #define	DRAM_PIC0_MASK		0x7fffffff
66 #define	DRAM_PIC1_SHIFT		0x0
67 #define	DRAM_PIC1_MASK		0x7fffffff
68 
69 /*
70  * Niagara JBUS performance counters
71  */
72 #define	NIAGARA_JBUS_PIC0_SEL_SHIFT	0x4
73 #define	NIAGARA_JBUS_PIC1_SEL_SHIFT	0x0
74 
75 #define	NIAGARA_JBUS_PIC0_SHIFT		0x20
76 #define	NIAGARA_JBUS_PIC0_MASK		0x7fffffff
77 #define	NIAGARA_JBUS_PIC1_SHIFT		0x0
78 #define	NIAGARA_JBUS_PIC1_MASK		0x7fffffff
79 
80 
81 /*
82  * Hypervisor FAST_TRAP API function numbers to get/set DRAM and
83  * JBUS performance counters
84  */
85 #define	HV_NIAGARA_GETPERF	0x100
86 #define	HV_NIAGARA_SETPERF	0x101
87 
88 /*
89  * Hypervisor FAST_TRAP API function numbers for Niagara MMU statistics
90  */
91 #define	HV_NIAGARA_MMUSTAT_CONF	0x102
92 #define	HV_NIAGARA_MMUSTAT_INFO	0x103
93 
94 /*
95  * DRAM/JBUS performance counter register numbers for HV_NIAGARA_GETPERF
96  * and HV_NIAGARA_SETPERF
97  */
98 #define	HV_NIAGARA_JBUS_CTL		0x0
99 #define	HV_NIAGARA_JBUS_COUNT		0x1
100 #define	HV_DRAM_CTL0		0x2
101 #define	HV_DRAM_COUNT0		0x3
102 #define	HV_DRAM_CTL1		0x4
103 #define	HV_DRAM_COUNT1		0x5
104 #define	HV_DRAM_CTL2		0x6
105 #define	HV_DRAM_COUNT2		0x7
106 #define	HV_DRAM_CTL3		0x8
107 #define	HV_DRAM_COUNT3		0x9
108 
109 #ifndef _ASM
110 
111 /*
112  * Niagara MMU statistics data structure
113  */
114 
115 #define	NIAGARA_MMUSTAT_PGSZS	8
116 
117 typedef struct niagara_tsbinfo {
118 	uint64_t	tsbhit_count;
119 	uint64_t	tsbhit_time;
120 } niagara_tsbinfo_t;
121 
122 typedef struct niagara_mmustat {
123 	niagara_tsbinfo_t	kitsb[NIAGARA_MMUSTAT_PGSZS];
124 	niagara_tsbinfo_t	uitsb[NIAGARA_MMUSTAT_PGSZS];
125 	niagara_tsbinfo_t	kdtsb[NIAGARA_MMUSTAT_PGSZS];
126 	niagara_tsbinfo_t	udtsb[NIAGARA_MMUSTAT_PGSZS];
127 } niagara_mmustat_t;
128 
129 
130 /*
131  * prototypes for hypervisor interface to get/set DRAM and JBUS
132  * performance counters
133  */
134 extern uint64_t hv_niagara_setperf(uint64_t regnum, uint64_t val);
135 extern uint64_t hv_niagara_getperf(uint64_t regnum, uint64_t *val);
136 extern uint64_t hv_niagara_mmustat_conf(uint64_t buf, uint64_t *prev_buf);
137 extern uint64_t hv_niagara_mmustat_info(uint64_t *buf);
138 
139 #endif /* _ASM */
140 
141 /*
142  * Bits defined in L2 Error Status Register
143  *
144  *	(Niagara 1)
145  * +---+---+---+---+----+----+----+----+----+----+----+----+----+----+
146  * |MEU|MEC|RW |RSV|MODA|VCID|LDAC|LDAU|LDWC|LDWU|LDRC|LDRU|LDSC|LDSU|
147  * +---+---+---+---+----+----+----+----+----+----+----+----+----+----+
148  *  63  62  61  60   59 58-54  53   52   51   50   49   48   47   46
149  *
150  *	(Niagara 2)
151  * +---+---+---+----+--------+----+----+----+----+----+----+----+----+
152  * |MEU|MEC|RW |MODA|  VCID  |LDAC|LDAU|LDWC|LDWU|LDRC|LDRU|LDSC|LDSU|
153  * +---+---+---+----+--------+----+----+----+----+----+----+----+----+
154  *  63  62  61  60     59-54   53   52   51   50   49   48   47   46
155  *
156  *      (Niagara 1)
157  * +---+---+---+---+---+---+---+---+---+---+---+-------+------+
158  * |LTC|LRU|LVU|DAC|DAU|DRC|DRU|DSC|DSU|VEC|VEU| RSVD1 | SYND |
159  * +---+---+---+---+---+---+---+---+---+---+---+-------+------+
160  *  45  44  43  42  41  40  39  38  37  36  35   34-32   31-0
161  *
162  *      (Niagara 2)
163  * +---+---+---+---+---+---+---+---+---+---+---+---+----+-----+
164  * |LTC|LRU|LVU|DAC|DAU|DRC|DRU|DSC|DSU|VEC|VEU|LVC|RSVD| SYND|
165  * +---+---+---+---+---+---+---+---+---+---+---+---+----+-----+
166  *  45  44  43  42  41  40  39  38  37  36  35  34  33-28 27-0
167  *
168  * Note that relative to error status bits, Niagara-1 is a strict subset of
169  * Niagara-2.
170  */
171 
172 #define	NI_L2AFSR_MEU 	0x8000000000000000ULL
173 #define	NI_L2AFSR_MEC	0x4000000000000000ULL
174 #define	NI_L2AFSR_RW 	0x2000000000000000ULL
175 #define	NI2_L2AFSR_MODA	0x1000000000000000ULL
176 #define	NI1_L2AFSR_MODA	0x0800000000000000ULL
177 #define	NI_L2AFSR_VCID	0x07C0000000000000ULL
178 #define	NI_L2AFSR_LDAC	0x0020000000000000ULL
179 #define	NI_L2AFSR_LDAU	0x0010000000000000ULL
180 #define	NI_L2AFSR_LDWC	0x0008000000000000ULL
181 #define	NI_L2AFSR_LDWU	0x0004000000000000ULL
182 #define	NI_L2AFSR_LDRC	0x0002000000000000ULL
183 #define	NI_L2AFSR_LDRU	0x0001000000000000ULL
184 #define	NI_L2AFSR_LDSC	0x0000800000000000ULL
185 #define	NI_L2AFSR_LDSU	0x0000400000000000ULL
186 #define	NI_L2AFSR_LTC	0x0000200000000000ULL
187 #define	NI_L2AFSR_LRU	0x0000100000000000ULL
188 #define	NI_L2AFSR_LVU	0x0000080000000000ULL
189 #define	NI_L2AFSR_DAC	0x0000040000000000ULL
190 #define	NI_L2AFSR_DAU	0x0000020000000000ULL
191 #define	NI_L2AFSR_DRC	0x0000010000000000ULL
192 #define	NI_L2AFSR_DRU	0x0000008000000000ULL
193 #define	NI_L2AFSR_DSC	0x0000004000000000ULL
194 #define	NI_L2AFSR_DSU	0x0000002000000000ULL
195 #define	NI_L2AFSR_VEC	0x0000001000000000ULL
196 #define	NI_L2AFSR_VEU	0x0000000800000000ULL
197 #define	NI_L2AFSR_LVC	0x0000000400000000ULL
198 #define	NI1_L2AFSR_SYND	0x00000000FFFFFFFFULL
199 #define	NI2_L2AFSR_SYND	0x000000000FFFFFFFULL
200 
201 /*
202  * These L2 bit masks are used to determine if another bit of higher priority
203  * is set.  This tells us whether the reported syndrome and address are valid
204  * for this ereport. If the error in hand is Pn, use Pn-1 to bitwise & with
205  * the l2-afsr value.  If result is 0, then this ereport's afsr is valid.
206  */
207 #define	NI_L2AFSR_P01	(NI_L2AFSR_LVU)
208 #define	NI_L2AFSR_P02	(NI_L2AFSR_P01 | NI_L2AFSR_LRU)
209 #define	NI_L2AFSR_P03	(NI_L2AFSR_P02 | NI_L2AFSR_LDAU | NI_L2AFSR_LDSU)
210 #define	NI_L2AFSR_P04	(NI_L2AFSR_P03 | NI_L2AFSR_LDWU)
211 #define	NI_L2AFSR_P05	(NI_L2AFSR_P04 | NI_L2AFSR_LDRU)
212 #define	NI_L2AFSR_P06	(NI_L2AFSR_P05 | NI_L2AFSR_DAU | NI_L2AFSR_DRU)
213 #define	NI_L2AFSR_P07   (NI_L2AFSR_P06 | NI_L2AFSR_LVC)
214 #define	NI_L2AFSR_P08	(NI_L2AFSR_P07 | NI_L2AFSR_LTC)
215 #define	NI_L2AFSR_P09	(NI_L2AFSR_P08 | NI_L2AFSR_LDAC | NI_L2AFSR_LDSC)
216 #define	NI_L2AFSR_P10	(NI_L2AFSR_P09 | NI_L2AFSR_LDWC)
217 #define	NI_L2AFSR_P11	(NI_L2AFSR_P10 | NI_L2AFSR_LDRC)
218 #define	NI_L2AFSR_P12	(NI_L2AFSR_P11 | NI_L2AFSR_DAC | NI_L2AFSR_DRC)
219 
220 /*
221  * Bits defined in DRAM Error Status Register (Niagara-2)
222  * Niagara-1 is strict subset
223  *
224  * +---+---+---+---+---+---+---+---+---+---+----------+------+
225  * |MEU|MEC|DAC|DAU|DSC|DSU|DBU|MEB|FBU|FBR| RESERVED | SYND |
226  * +---+---+---+---+---+---+---+---+---+---+----------+------+
227  *  63  62  61  60  59  58  57  56  55  54    53-16     15-0
228  *
229  */
230 #define	NI_DMAFSR_MEU 	0x8000000000000000ULL
231 #define	NI_DMAFSR_MEC	0x4000000000000000ULL
232 #define	NI_DMAFSR_DAC 	0x2000000000000000ULL
233 #define	NI_DMAFSR_DAU	0x1000000000000000ULL
234 #define	NI_DMAFSR_DSC	0x0800000000000000ULL
235 #define	NI_DMAFSR_DSU	0x0400000000000000ULL
236 #define	NI_DMAFSR_DBU	0x0200000000000000ULL
237 #define	NI_DMAFSR_MEB	0x0100000000000000ULL
238 #define	NI_DMAFSR_FBU	0x0080000000000000ULL
239 #define	NI_DMAFSR_FBR	0x0040000000000000ULL
240 #define	NI_DMAFSR_SYND	0x000000000000FFFFULL
241 
242 /* Bit mask for DRAM priority determination */
243 #define	NI_DMAFSR_P01	(NI_DMAFSR_DSU | NI_DMAFSR_DAU | NI_DMAFSR_FBU)
244 
245 /*
246  * The following is the syndrome value placed in memory
247  * when an uncorrectable error is written back from L2 cache.
248  */
249 #define	NI_DRAM_POISON_SYND_FROM_LDWU		0x1118
250 #define	N2_DRAM_POISON_SYND_FROM_LDWU		0x8221
251 
252 /*
253  * This L2 poison syndrome is placed on 4 byte checkwords of L2
254  * when a UE is loaded or DMA'ed into L2
255  */
256 #define	NI_L2_POISON_SYND_FROM_DAU		0x3
257 #define	NI_L2_POISON_SYND_MASK			0x7F
258 #define	NI_L2_POISON_SYND_SIZE			7
259 
260 #ifdef __cplusplus
261 }
262 #endif
263 
264 #endif /* _SYS_NIAGARAREGS_H */
265