1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NIUMX_VAR_H 27 #define _SYS_NIUMX_VAR_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 typedef enum { /* same sequence as niumx_debug_sym[] */ 34 /* 0 */ NIUMX_DBG_ATTACH, 35 /* 1 */ NIUMX_DBG_MAP, 36 /* 2 */ NIUMX_DBG_CTLOPS, 37 /* 3 */ NIUMX_DBG_INTROPS, 38 /* 4 */ NIUMX_DBG_A_INTX, 39 /* 5 */ NIUMX_DBG_R_INTX, 40 /* 6 */ NIUMX_DBG_INTR, 41 /* 7 */ NIUMX_DBG_DMA_ALLOCH, 42 /* 8 */ NIUMX_DBG_DMA_BINDH, 43 /* 9 */ NIUMX_DBG_DMA_UNBINDH, 44 /* 10 */ NIUMX_DBG_CHK_MOD 45 } niumx_debug_bit_t; 46 47 #if defined(DEBUG) 48 #define DBG niumx_dbg 49 extern void niumx_dbg(niumx_debug_bit_t bit, dev_info_t *dip, char *fmt, ...); 50 #else 51 #define DBG 0 && 52 #endif /* DEBUG */ 53 54 typedef uint64_t niudevhandle_t; 55 #define NIUMX_DEVHDLE_MASK 0xFFFFFFF 56 typedef uint32_t niucpuid_t; 57 typedef uint32_t niudevino_t; 58 typedef uint64_t niusysino_t; 59 60 /* 61 * The following structure represents an interrupt handler control block for 62 * each interrupt added via ddi_intr_add_handler(). 63 */ 64 typedef struct niumx_ih { 65 dev_info_t *ih_dip; /* devinfo structure */ 66 uint32_t ih_inum; /* interrupt index, from leaf */ 67 niusysino_t ih_sysino; /* System virtual inumber, from HV */ 68 niucpuid_t ih_cpuid; /* cpu that ino is targeting */ 69 int ih_state; /* interrupt valid state */ 70 int ih_pri; /* interrupt priority */ 71 uint_t (*ih_hdlr)(); /* interrupt handler */ 72 caddr_t ih_arg1; /* interrupt handler argument #1 */ 73 caddr_t ih_arg2; /* interrupt handler argument #2 */ 74 struct niumx_ih *ih_next; /* next in the chain */ 75 } niumx_ih_t; 76 77 #define NIUMX_MAX_INTRS 64 78 79 #define NIUMX_SOFT_STATE_OPEN 1 80 #define NIUMX_SOFT_STATE_OPEN_EXCL 2 81 #define NIUMX_SOFT_STATE_CLOSED 4 82 83 84 typedef struct niumx_devstate { 85 dev_info_t *dip; 86 int niumx_soft_state; 87 int niumx_open_count; 88 niudevhandle_t niumx_dev_hdl; /* device handle */ 89 kmutex_t niumx_mutex; 90 int niumx_fm_cap; 91 ddi_iblock_cookie_t niumx_fm_ibc; 92 niumx_ih_t niumx_ihtable[NIUMX_MAX_INTRS]; 93 } niumx_devstate_t; 94 95 /* 96 * flags for overloading dmai_inuse field of the dma request structure: 97 */ 98 #define dmai_pfnlst dmai_iopte 99 #define dmai_pfn0 dmai_sbi 100 #define dmai_roffset dmai_pool 101 102 #define NIUMX_PAGE_SHIFT 13 103 #define NIUMX_PAGE_SIZE (1 << NIUMX_PAGE_SHIFT) 104 #define NIUMX_PAGE_MASK ~(NIUMX_PAGE_SIZE - 1) 105 #define NIUMX_PAGE_OFFSET (NIUMX_PAGE_SIZE - 1) 106 #define NIUMX_PTOB(x) (((uint64_t)(x)) << NIUMX_PAGE_SHIFT) 107 108 /* for "ranges" property */ 109 typedef struct niumx_ranges { 110 uint32_t child_hi; 111 uint32_t child_lo; 112 uint32_t parent_hi; 113 uint32_t parent_lo; 114 uint32_t size_hi; 115 uint32_t size_lo; 116 } niumx_ranges_t; 117 118 /* IPL of 6 for networking devices */ 119 #define NIUMX_DEFAULT_PIL 6 120 121 typedef struct { 122 uint32_t addr_high; 123 uint32_t addr_low; 124 uint32_t size_high; 125 uint32_t size_low; 126 } niu_regspec_t; 127 128 /* 129 * HV INTR API versioning. 130 * 131 * Currently NIU nexus driver supports version 1.0 132 */ 133 #define NIUMX_INTR_MAJOR_VER_1 0x1ull 134 #define NIUMX_INTR_MAJOR_VER NIUMX_INTR_MAJOR_VER_1 135 136 #define NIUMX_INTR_MINOR_VER_0 0x0ull 137 #define NIUMX_INTR_MINOR_VER NIUMX_INTR_MINOR_VER_0 138 139 #define NIUMX_NAMEINST(dip) ddi_driver_name(dip), ddi_get_instance(dip) 140 #define NIUMX_DIP_TO_HANDLE(dip) \ 141 ((niumx_devstate_t *)NIUMX_DIP_TO_STATE(dip))->niumx_dev_hdl 142 #define NIUMX_DIP_TO_INST(dip) ddi_get_instance(dip) 143 #define NIUMX_INST_TO_STATE(inst) ddi_get_soft_state(niumx_state, inst) 144 #define NIUMX_DIP_TO_STATE(dip) NIUMX_INST_TO_STATE(NIUMX_DIP_TO_INST(dip)) 145 #define NIUMX_DEV_TO_SOFTSTATE(dev) \ 146 ((pci_t *)ddi_get_soft_state(niumx_state, \ 147 PCI_MINOR_NUM_TO_INSTANCE(getminor(dev)))) 148 149 #ifdef __cplusplus 150 } 151 #endif 152 153 #endif /* _SYS_NIUMX_VAR_H */ 154