1 /* $OpenBSD: if_nfereg.h,v 1.16 2006/02/22 19:23:44 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2005 Jonathan Gray <jsg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #define NFE_RX_RING_COUNT 256 20 #define NFE_JUMBO_RX_RING_COUNT NFE_RX_RING_COUNT 21 #define NFE_TX_RING_COUNT 256 22 23 #define NFE_PROC_DEFAULT ((NFE_RX_RING_COUNT * 3) / 4) 24 #define NFE_PROC_MIN 50 25 #define NFE_PROC_MAX (NFE_RX_RING_COUNT - 1) 26 27 #define NFE_INC(x, y) (x) = ((x) + 1) % y 28 29 /* RX/TX MAC addr + type + VLAN + align + slack */ 30 #define NFE_RX_HEADERS 64 31 32 /* Maximum MTU size. */ 33 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* Hard limit not known. */ 34 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia:9202 */ 35 36 #define NFE_JUMBO_FRAMELEN NV_PKTLIMIT_2 37 #define NFE_JUMBO_MTU \ 38 (NFE_JUMBO_FRAMELEN - NFE_RX_HEADERS) 39 #define NFE_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 40 41 #define NFE_MAX_SCATTER 35 42 #define NFE_TSO_MAXSGSIZE 4096 43 #define NFE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 44 45 #define NFE_IRQ_STATUS 0x000 46 #define NFE_IRQ_MASK 0x004 47 #define NFE_SETUP_R6 0x008 48 #define NFE_IMTIMER 0x00c 49 #define NFE_MSI_MAP0 0x020 50 #define NFE_MSI_MAP1 0x024 51 #define NFE_MSI_IRQ_MASK 0x030 52 #define NFE_MAC_RESET 0x03c 53 #define NFE_MISC1 0x080 54 #define NFE_TX_CTL 0x084 55 #define NFE_TX_STATUS 0x088 56 #define NFE_RXFILTER 0x08c 57 #define NFE_RXBUFSZ 0x090 58 #define NFE_RX_CTL 0x094 59 #define NFE_RX_STATUS 0x098 60 #define NFE_RNDSEED 0x09c 61 #define NFE_SETUP_R1 0x0a0 62 #define NFE_SETUP_R2 0x0a4 63 #define NFE_MACADDR_HI 0x0a8 64 #define NFE_MACADDR_LO 0x0ac 65 #define NFE_MULTIADDR_HI 0x0b0 66 #define NFE_MULTIADDR_LO 0x0b4 67 #define NFE_MULTIMASK_HI 0x0b8 68 #define NFE_MULTIMASK_LO 0x0bc 69 #define NFE_PHY_IFACE 0x0c0 70 #define NFE_TX_RING_ADDR_LO 0x100 71 #define NFE_RX_RING_ADDR_LO 0x104 72 #define NFE_RING_SIZE 0x108 73 #define NFE_TX_UNK 0x10c 74 #define NFE_LINKSPEED 0x110 75 #define NFE_SETUP_R5 0x130 76 #define NFE_SETUP_R3 0x13C 77 #define NFE_SETUP_R7 0x140 78 #define NFE_RXTX_CTL 0x144 79 #define NFE_TX_RING_ADDR_HI 0x148 80 #define NFE_RX_RING_ADDR_HI 0x14c 81 #define NFE_TX_PAUSE_FRAME 0x170 82 #define NFE_PHY_STATUS 0x180 83 #define NFE_SETUP_R4 0x184 84 #define NFE_STATUS 0x188 85 #define NFE_PHY_SPEED 0x18c 86 #define NFE_PHY_CTL 0x190 87 #define NFE_PHY_DATA 0x194 88 #define NFE_TX_UNICAST 0x1a0 89 #define NFE_TX_MULTICAST 0x1a4 90 #define NFE_TX_BROADCAST 0x1a8 91 #define NFE_WOL_CTL 0x200 92 #define NFE_PATTERN_CRC 0x204 93 #define NFE_PATTERN_MASK 0x208 94 #define NFE_PWR_CAP 0x268 95 #define NFE_PWR_STATE 0x26c 96 #define NFE_TX_OCTET 0x280 97 #define NFE_TX_ZERO_REXMIT 0x284 98 #define NFE_TX_ONE_REXMIT 0x288 99 #define NFE_TX_MULTI_REXMIT 0x28c 100 #define NFE_TX_LATE_COL 0x290 101 #define NFE_TX_FIFO_UNDERUN 0x294 102 #define NFE_TX_CARRIER_LOST 0x298 103 #define NFE_TX_EXCESS_DEFERRAL 0x29c 104 #define NFE_TX_RETRY_ERROR 0x2a0 105 #define NFE_RX_FRAME_ERROR 0x2a4 106 #define NFE_RX_EXTRA_BYTES 0x2a8 107 #define NFE_RX_LATE_COL 0x2ac 108 #define NFE_RX_RUNT 0x2b0 109 #define NFE_RX_JUMBO 0x2b4 110 #define NFE_RX_FIFO_OVERUN 0x2b8 111 #define NFE_RX_CRC_ERROR 0x2bc 112 #define NFE_RX_FAE 0x2c0 113 #define NFE_RX_LEN_ERROR 0x2c4 114 #define NFE_RX_UNICAST 0x2c8 115 #define NFE_RX_MULTICAST 0x2cc 116 #define NFE_RX_BROADCAST 0x2d0 117 #define NFE_TX_DEFERAL 0x2d4 118 #define NFE_TX_FRAME 0x2d8 119 #define NFE_RX_OCTET 0x2dc 120 #define NFE_TX_PAUSE 0x2e0 121 #define NFE_RX_PAUSE 0x2e4 122 #define NFE_RX_DROP 0x2e8 123 #define NFE_VTAG_CTL 0x300 124 #define NFE_MSIX_MAP0 0x3e0 125 #define NFE_MSIX_MAP1 0x3e4 126 #define NFE_MSIX_IRQ_STATUS 0x3f0 127 #define NFE_PWR2_CTL 0x600 128 129 #define NFE_MAC_RESET_MAGIC 0x00f3 130 131 #define NFE_MAC_ADDR_INORDER 0x8000 132 133 #define NFE_PHY_ERROR 0x00001 134 #define NFE_PHY_WRITE 0x00400 135 #define NFE_PHY_BUSY 0x08000 136 #define NFE_PHYADD_SHIFT 5 137 138 #define NFE_STATUS_MAGIC 0x140000 139 140 #define NFE_R1_MAGIC_1000 0x14050f 141 #define NFE_R1_MAGIC_10_100 0x16070f 142 #define NFE_R1_MAGIC_DEFAULT 0x15050f 143 #define NFE_R2_MAGIC 0x16 144 #define NFE_R4_MAGIC 0x08 145 #define NFE_R6_MAGIC 0x03 146 #define NFE_WOL_MAGIC 0x1111 147 #define NFE_RX_START 0x01 148 #define NFE_TX_START 0x01 149 150 #define NFE_IRQ_RXERR 0x0001 151 #define NFE_IRQ_RX 0x0002 152 #define NFE_IRQ_RX_NOBUF 0x0004 153 #define NFE_IRQ_TXERR 0x0008 154 #define NFE_IRQ_TX_DONE 0x0010 155 #define NFE_IRQ_TIMER 0x0020 156 #define NFE_IRQ_LINK 0x0040 157 #define NFE_IRQ_TXERR2 0x0080 158 #define NFE_IRQ_TX1 0x0100 159 160 #define NFE_IRQ_WANTED \ 161 (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX | \ 162 NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE | \ 163 NFE_IRQ_LINK) 164 165 #define NFE_RXTX_KICKTX 0x0001 166 #define NFE_RXTX_BIT1 0x0002 167 #define NFE_RXTX_BIT2 0x0004 168 #define NFE_RXTX_RESET 0x0010 169 #define NFE_RXTX_VTAG_STRIP 0x0040 170 #define NFE_RXTX_VTAG_INSERT 0x0080 171 #define NFE_RXTX_RXCSUM 0x0400 172 #define NFE_RXTX_V2MAGIC 0x2100 173 #define NFE_RXTX_V3MAGIC 0x2200 174 #define NFE_RXFILTER_MAGIC 0x007f0000 175 #define NFE_PFF_RX_PAUSE (1 << 3) 176 #define NFE_PFF_LOOPBACK (1 << 4) 177 #define NFE_PFF_U2M (1 << 5) 178 #define NFE_PFF_PROMISC (1 << 7) 179 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 180 181 /* default interrupt moderation timer of 128us */ 182 #define NFE_IM_DEFAULT ((128 * 100) / 1024) 183 184 #define NFE_VTAG_ENABLE (1 << 13) 185 186 #define NFE_PWR_VALID (1 << 8) 187 #define NFE_PWR_WAKEUP (1 << 15) 188 189 #define NFE_PWR2_WAKEUP_MASK 0x0f11 190 #define NFE_PWR2_REVA3 (1 << 0) 191 #define NFE_PWR2_GATE_CLOCKS 0x0f00 192 193 #define NFE_MEDIA_SET 0x10000 194 #define NFE_MEDIA_1000T 0x00032 195 #define NFE_MEDIA_100TX 0x00064 196 #define NFE_MEDIA_10T 0x003e8 197 198 #define NFE_PHY_100TX (1 << 0) 199 #define NFE_PHY_1000T (1 << 1) 200 #define NFE_PHY_HDX (1 << 8) 201 202 #define NFE_MISC1_MAGIC 0x003b0f3c 203 #define NFE_MISC1_TX_PAUSE (1 << 0) 204 #define NFE_MISC1_HDX (1 << 1) 205 206 #define NFE_TX_PAUSE_FRAME_DISABLE 0x1ff0080 207 #define NFE_TX_PAUSE_FRAME_ENABLE 0x0c00030 208 209 #define NFE_SEED_MASK 0x0003ff00 210 #define NFE_SEED_10T 0x00007f00 211 #define NFE_SEED_100TX 0x00002d00 212 #define NFE_SEED_1000T 0x00007400 213 214 #define NFE_NUM_MIB_STATV1 21 215 #define NFE_NUM_MIB_STATV2 27 216 #define NFE_NUM_MIB_STATV3 30 217 218 #define NFE_MSI_MESSAGES 8 219 #define NFE_MSI_VECTOR_0_ENABLED 0x01 220 221 /* 222 * It seems that nForce supports only the lower 40 bits of a DMA address. 223 */ 224 #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 225 #define NFE_DMA_MAXADDR BUS_SPACE_MAXADDR 226 #else 227 #define NFE_DMA_MAXADDR 0xFFFFFFFFFF 228 #endif 229 230 #define NFE_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) 231 #define NFE_ADDR_HI(x) ((u_int64_t) (x) >> 32) 232 233 /* Rx/Tx descriptor */ 234 struct nfe_desc32 { 235 uint32_t physaddr; 236 uint16_t length; 237 uint16_t flags; 238 #define NFE_RX_FIXME_V1 0x6004 239 #define NFE_RX_VALID_V1 (1 << 0) 240 #define NFE_TX_ERROR_V1 0x7808 241 #define NFE_TX_LASTFRAG_V1 (1 << 0) 242 #define NFE_RX_ERROR1_V1 (1<<7) 243 #define NFE_RX_ERROR2_V1 (1<<8) 244 #define NFE_RX_ERROR3_V1 (1<<9) 245 #define NFE_RX_ERROR4_V1 (1<<10) 246 } __packed; 247 248 #define NFE_V1_TXERR "\020" \ 249 "\14TXERROR\13UNDERFLOW\12LATECOLLISION\11LOSTCARRIER\10DEFERRED" \ 250 "\08FORCEDINT\03RETRY\00LASTPACKET" 251 252 /* V2 Rx/Tx descriptor */ 253 struct nfe_desc64 { 254 uint32_t physaddr[2]; 255 uint32_t vtag; 256 #define NFE_RX_VTAG (1 << 16) 257 #define NFE_TX_VTAG (1 << 18) 258 uint16_t length; 259 uint16_t flags; 260 #define NFE_RX_FIXME_V2 0x4300 261 #define NFE_RX_VALID_V2 (1 << 13) 262 #define NFE_TX_ERROR_V2 0x5c04 263 #define NFE_TX_LASTFRAG_V2 (1 << 13) 264 #define NFE_RX_ERROR1_V2 (1<<2) 265 #define NFE_RX_ERROR2_V2 (1<<3) 266 #define NFE_RX_ERROR3_V2 (1<<4) 267 #define NFE_RX_ERROR4_V2 (1<<5) 268 } __packed; 269 270 #define NFE_V2_TXERR "\020" \ 271 "\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY" 272 273 #define NFE_RING_ALIGN (sizeof(struct nfe_desc64)) 274 275 /* flags common to V1/V2 descriptors */ 276 #define NFE_RX_UDP_CSUMOK (1 << 10) 277 #define NFE_RX_TCP_CSUMOK (1 << 11) 278 #define NFE_RX_IP_CSUMOK (1 << 12) 279 #define NFE_RX_ERROR (1 << 14) 280 #define NFE_RX_READY (1 << 15) 281 #define NFE_RX_LEN_MASK 0x3fff 282 #define NFE_TX_TCP_UDP_CSUM (1 << 10) 283 #define NFE_TX_IP_CSUM (1 << 11) 284 #define NFE_TX_TSO (1 << 12) 285 #define NFE_TX_TSO_SHIFT 14 286 #define NFE_TX_VALID (1 << 15) 287 288 #define NFE_READ(sc, reg) \ 289 bus_read_4((sc)->nfe_res[0], (reg)) 290 291 #define NFE_WRITE(sc, reg, val) \ 292 bus_write_4((sc)->nfe_res[0], (reg), (val)) 293 294 #define NFE_TIMEOUT 1000 295 296 #ifndef PCI_VENDOR_NVIDIA 297 #define PCI_VENDOR_NVIDIA 0x10DE 298 #endif 299 300 #define PCI_PRODUCT_NVIDIA_NFORCE_LAN 0x01C3 301 #define PCI_PRODUCT_NVIDIA_NFORCE2_LAN 0x0066 302 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 0x00D6 303 #define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 0x0086 304 #define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 0x008C 305 #define PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 0x00E6 306 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 0x00DF 307 #define PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 0x0056 308 #define PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 0x0057 309 #define PCI_PRODUCT_NVIDIA_MCP04_LAN1 0x0037 310 #define PCI_PRODUCT_NVIDIA_MCP04_LAN2 0x0038 311 #define PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 0x0268 312 #define PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 0x0269 313 #define PCI_PRODUCT_NVIDIA_MCP55_LAN1 0x0372 314 #define PCI_PRODUCT_NVIDIA_MCP55_LAN2 0x0373 315 #define PCI_PRODUCT_NVIDIA_MCP61_LAN1 0x03e5 316 #define PCI_PRODUCT_NVIDIA_MCP61_LAN2 0x03e6 317 #define PCI_PRODUCT_NVIDIA_MCP61_LAN3 0x03ee 318 #define PCI_PRODUCT_NVIDIA_MCP61_LAN4 0x03ef 319 #define PCI_PRODUCT_NVIDIA_MCP65_LAN1 0x0450 320 #define PCI_PRODUCT_NVIDIA_MCP65_LAN2 0x0451 321 #define PCI_PRODUCT_NVIDIA_MCP65_LAN3 0x0452 322 #define PCI_PRODUCT_NVIDIA_MCP65_LAN4 0x0453 323 #define PCI_PRODUCT_NVIDIA_MCP67_LAN1 0x054c 324 #define PCI_PRODUCT_NVIDIA_MCP67_LAN2 0x054d 325 #define PCI_PRODUCT_NVIDIA_MCP67_LAN3 0x054e 326 #define PCI_PRODUCT_NVIDIA_MCP67_LAN4 0x054f 327 #define PCI_PRODUCT_NVIDIA_MCP73_LAN1 0x07dc 328 #define PCI_PRODUCT_NVIDIA_MCP73_LAN2 0x07dd 329 #define PCI_PRODUCT_NVIDIA_MCP73_LAN3 0x07de 330 #define PCI_PRODUCT_NVIDIA_MCP73_LAN4 0x07df 331 #define PCI_PRODUCT_NVIDIA_MCP77_LAN1 0x0760 332 #define PCI_PRODUCT_NVIDIA_MCP77_LAN2 0x0761 333 #define PCI_PRODUCT_NVIDIA_MCP77_LAN3 0x0762 334 #define PCI_PRODUCT_NVIDIA_MCP77_LAN4 0x0763 335 #define PCI_PRODUCT_NVIDIA_MCP79_LAN1 0x0ab0 336 #define PCI_PRODUCT_NVIDIA_MCP79_LAN2 0x0ab1 337 #define PCI_PRODUCT_NVIDIA_MCP79_LAN3 0x0ab2 338 #define PCI_PRODUCT_NVIDIA_MCP79_LAN4 0x0ab3 339 #define PCI_PRODUCT_NVIDIA_MCP89_LAN 0x0d7d 340 341 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 342 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 343 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 344 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 345 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 346 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 347 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 348 349 #define NFE_DEBUG 0x0000 350 #define NFE_DEBUG_INIT 0x0001 351 #define NFE_DEBUG_RUNNING 0x0002 352 #define NFE_DEBUG_DEINIT 0x0004 353 #define NFE_DEBUG_IOCTL 0x0008 354 #define NFE_DEBUG_INTERRUPT 0x0010 355 #define NFE_DEBUG_API 0x0020 356 #define NFE_DEBUG_LOCK 0x0040 357 #define NFE_DEBUG_BROKEN 0x0080 358 #define NFE_DEBUG_MII 0x0100 359 #define NFE_DEBUG_ALL 0xFFFF 360