1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2019 MediaTek Inc.
3 *
4 * Author: Roy Luo <royluo@google.com>
5 * Ryder Lee <ryder.lee@mediatek.com>
6 */
7
8 #include <linux/firmware.h>
9 #include "mt7615.h"
10 #include "mcu.h"
11 #include "mac.h"
12 #include "eeprom.h"
13
14 static bool prefer_offload_fw = true;
15 module_param(prefer_offload_fw, bool, 0644);
16 MODULE_PARM_DESC(prefer_offload_fw,
17 "Prefer client mode offload firmware (MT7663)");
18
19 struct mt7615_patch_hdr {
20 char build_date[16];
21 char platform[4];
22 __be32 hw_sw_ver;
23 __be32 patch_ver;
24 __be16 checksum;
25 } __packed;
26
27 struct mt7615_fw_trailer {
28 __le32 addr;
29 u8 chip_id;
30 u8 feature_set;
31 u8 eco_code;
32 char fw_ver[10];
33 char build_date[15];
34 __le32 len;
35 } __packed;
36
37 #define FW_V3_COMMON_TAILER_SIZE 36
38 #define FW_V3_REGION_TAILER_SIZE 40
39 #define FW_START_OVERRIDE BIT(0)
40 #define FW_START_DLYCAL BIT(1)
41 #define FW_START_WORKING_PDA_CR4 BIT(2)
42
43 struct mt7663_fw_buf {
44 __le32 crc;
45 __le32 d_img_size;
46 __le32 block_size;
47 u8 rsv[4];
48 __le32 img_dest_addr;
49 __le32 img_size;
50 u8 feature_set;
51 };
52
53 #define MT7615_PATCH_ADDRESS 0x80000
54 #define MT7622_PATCH_ADDRESS 0x9c000
55 #define MT7663_PATCH_ADDRESS 0xdc000
56
57 #define N9_REGION_NUM 2
58 #define CR4_REGION_NUM 1
59
60 #define IMG_CRC_LEN 4
61
mt7615_mcu_fill_msg(struct mt7615_dev * dev,struct sk_buff * skb,int cmd,int * wait_seq)62 void mt7615_mcu_fill_msg(struct mt7615_dev *dev, struct sk_buff *skb,
63 int cmd, int *wait_seq)
64 {
65 int txd_len, mcu_cmd = FIELD_GET(__MCU_CMD_FIELD_ID, cmd);
66 struct mt7615_uni_txd *uni_txd;
67 struct mt7615_mcu_txd *mcu_txd;
68 u8 seq, q_idx, pkt_fmt;
69 __le32 *txd;
70 u32 val;
71
72 /* TODO: make dynamic based on msg type */
73 dev->mt76.mcu.timeout = 20 * HZ;
74
75 seq = ++dev->mt76.mcu.msg_seq & 0xf;
76 if (!seq)
77 seq = ++dev->mt76.mcu.msg_seq & 0xf;
78 if (wait_seq)
79 *wait_seq = seq;
80
81 txd_len = cmd & __MCU_CMD_FIELD_UNI ? sizeof(*uni_txd) : sizeof(*mcu_txd);
82 txd = (__le32 *)skb_push(skb, txd_len);
83
84 if (cmd != MCU_CMD(FW_SCATTER)) {
85 q_idx = MT_TX_MCU_PORT_RX_Q0;
86 pkt_fmt = MT_TX_TYPE_CMD;
87 } else {
88 q_idx = MT_TX_MCU_PORT_RX_FWDL;
89 pkt_fmt = MT_TX_TYPE_FW;
90 }
91
92 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len) |
93 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_MCU) |
94 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
95 txd[0] = cpu_to_le32(val);
96
97 val = MT_TXD1_LONG_FORMAT |
98 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_CMD) |
99 FIELD_PREP(MT_TXD1_PKT_FMT, pkt_fmt);
100 txd[1] = cpu_to_le32(val);
101
102 if (cmd & __MCU_CMD_FIELD_UNI) {
103 uni_txd = (struct mt7615_uni_txd *)txd;
104 uni_txd->len = cpu_to_le16(skb->len - sizeof(uni_txd->txd));
105 uni_txd->option = MCU_CMD_UNI_EXT_ACK;
106 uni_txd->cid = cpu_to_le16(mcu_cmd);
107 uni_txd->s2d_index = MCU_S2D_H2N;
108 uni_txd->pkt_type = MCU_PKT_ID;
109 uni_txd->seq = seq;
110
111 return;
112 }
113
114 mcu_txd = (struct mt7615_mcu_txd *)txd;
115 mcu_txd->len = cpu_to_le16(skb->len - sizeof(mcu_txd->txd));
116 mcu_txd->pq_id = cpu_to_le16(MCU_PQ_ID(MT_TX_PORT_IDX_MCU, q_idx));
117 mcu_txd->s2d_index = MCU_S2D_H2N;
118 mcu_txd->pkt_type = MCU_PKT_ID;
119 mcu_txd->seq = seq;
120 mcu_txd->cid = mcu_cmd;
121 mcu_txd->ext_cid = FIELD_GET(__MCU_CMD_FIELD_EXT_ID, cmd);
122
123 if (mcu_txd->ext_cid || (cmd & __MCU_CMD_FIELD_CE)) {
124 if (cmd & __MCU_CMD_FIELD_QUERY)
125 mcu_txd->set_query = MCU_Q_QUERY;
126 else
127 mcu_txd->set_query = MCU_Q_SET;
128 mcu_txd->ext_cid_ack = !!mcu_txd->ext_cid;
129 } else {
130 mcu_txd->set_query = MCU_Q_NA;
131 }
132 }
133 EXPORT_SYMBOL_GPL(mt7615_mcu_fill_msg);
134
mt7615_mcu_parse_response(struct mt76_dev * mdev,int cmd,struct sk_buff * skb,int seq)135 int mt7615_mcu_parse_response(struct mt76_dev *mdev, int cmd,
136 struct sk_buff *skb, int seq)
137 {
138 struct mt7615_mcu_rxd *rxd;
139 int ret = 0;
140
141 if (!skb) {
142 dev_err(mdev->dev, "Message %08x (seq %d) timeout\n",
143 cmd, seq);
144 return -ETIMEDOUT;
145 }
146
147 rxd = (struct mt7615_mcu_rxd *)skb->data;
148 if (seq != rxd->seq)
149 return -EAGAIN;
150
151 if (cmd == MCU_CMD(PATCH_SEM_CONTROL)) {
152 skb_pull(skb, sizeof(*rxd) - 4);
153 ret = *skb->data;
154 } else if (cmd == MCU_EXT_CMD(THERMAL_CTRL)) {
155 skb_pull(skb, sizeof(*rxd));
156 ret = le32_to_cpu(*(__le32 *)skb->data);
157 } else if (cmd == MCU_EXT_QUERY(RF_REG_ACCESS)) {
158 skb_pull(skb, sizeof(*rxd));
159 ret = le32_to_cpu(*(__le32 *)&skb->data[8]);
160 } else if (cmd == MCU_UNI_CMD(DEV_INFO_UPDATE) ||
161 cmd == MCU_UNI_CMD(BSS_INFO_UPDATE) ||
162 cmd == MCU_UNI_CMD(STA_REC_UPDATE) ||
163 cmd == MCU_UNI_CMD(HIF_CTRL) ||
164 cmd == MCU_UNI_CMD(OFFLOAD) ||
165 cmd == MCU_UNI_CMD(SUSPEND)) {
166 struct mt76_connac_mcu_uni_event *event;
167
168 skb_pull(skb, sizeof(*rxd));
169 event = (struct mt76_connac_mcu_uni_event *)skb->data;
170 ret = le32_to_cpu(event->status);
171 } else if (cmd == MCU_CE_QUERY(REG_READ)) {
172 struct mt76_connac_mcu_reg_event *event;
173
174 skb_pull(skb, sizeof(*rxd));
175 event = (struct mt76_connac_mcu_reg_event *)skb->data;
176 ret = (int)le32_to_cpu(event->val);
177 }
178
179 return ret;
180 }
181 EXPORT_SYMBOL_GPL(mt7615_mcu_parse_response);
182
183 static int
mt7615_mcu_send_message(struct mt76_dev * mdev,struct sk_buff * skb,int cmd,int * seq)184 mt7615_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
185 int cmd, int *seq)
186 {
187 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
188 enum mt76_mcuq_id qid;
189
190 mt7615_mcu_fill_msg(dev, skb, cmd, seq);
191 if (test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state))
192 qid = MT_MCUQ_WM;
193 else
194 qid = MT_MCUQ_FWDL;
195
196 return mt76_tx_queue_skb_raw(dev, dev->mt76.q_mcu[qid], skb, 0);
197 }
198
mt7615_rf_rr(struct mt7615_dev * dev,u32 wf,u32 reg)199 u32 mt7615_rf_rr(struct mt7615_dev *dev, u32 wf, u32 reg)
200 {
201 struct {
202 __le32 wifi_stream;
203 __le32 address;
204 __le32 data;
205 } req = {
206 .wifi_stream = cpu_to_le32(wf),
207 .address = cpu_to_le32(reg),
208 };
209
210 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_QUERY(RF_REG_ACCESS),
211 &req, sizeof(req), true);
212 }
213
mt7615_rf_wr(struct mt7615_dev * dev,u32 wf,u32 reg,u32 val)214 int mt7615_rf_wr(struct mt7615_dev *dev, u32 wf, u32 reg, u32 val)
215 {
216 struct {
217 __le32 wifi_stream;
218 __le32 address;
219 __le32 data;
220 } req = {
221 .wifi_stream = cpu_to_le32(wf),
222 .address = cpu_to_le32(reg),
223 .data = cpu_to_le32(val),
224 };
225
226 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_REG_ACCESS),
227 &req, sizeof(req), false);
228 }
229
mt7622_trigger_hif_int(struct mt7615_dev * dev,bool en)230 void mt7622_trigger_hif_int(struct mt7615_dev *dev, bool en)
231 {
232 if (!is_mt7622(&dev->mt76))
233 return;
234
235 #if defined(__linux__)
236 regmap_update_bits(dev->infracfg, MT_INFRACFG_MISC,
237 MT_INFRACFG_MISC_AP2CONN_WAKE,
238 !en * MT_INFRACFG_MISC_AP2CONN_WAKE);
239 #elif defined(__FreeBSD__)
240 panic("%s: LinuxKPI needs regmap\n", __func__);
241 #endif
242 }
243 EXPORT_SYMBOL_GPL(mt7622_trigger_hif_int);
244
mt7615_mcu_drv_pmctrl(struct mt7615_dev * dev)245 static int mt7615_mcu_drv_pmctrl(struct mt7615_dev *dev)
246 {
247 struct mt76_phy *mphy = &dev->mt76.phy;
248 struct mt76_connac_pm *pm = &dev->pm;
249 struct mt76_dev *mdev = &dev->mt76;
250 u32 addr;
251 int err;
252
253 if (is_mt7663(mdev)) {
254 /* Clear firmware own via N9 eint */
255 mt76_wr(dev, MT_PCIE_DOORBELL_PUSH, MT_CFG_LPCR_HOST_DRV_OWN);
256 mt76_poll(dev, MT_CONN_ON_MISC, MT_CFG_LPCR_HOST_FW_OWN, 0, 3000);
257
258 addr = MT_CONN_HIF_ON_LPCTL;
259 } else {
260 addr = MT_CFG_LPCR_HOST;
261 }
262
263 mt76_wr(dev, addr, MT_CFG_LPCR_HOST_DRV_OWN);
264
265 mt7622_trigger_hif_int(dev, true);
266
267 err = !mt76_poll_msec(dev, addr, MT_CFG_LPCR_HOST_FW_OWN, 0, 3000);
268
269 mt7622_trigger_hif_int(dev, false);
270
271 if (err) {
272 dev_err(mdev->dev, "driver own failed\n");
273 return -ETIMEDOUT;
274 }
275
276 clear_bit(MT76_STATE_PM, &mphy->state);
277
278 pm->stats.last_wake_event = jiffies;
279 pm->stats.doze_time += pm->stats.last_wake_event -
280 pm->stats.last_doze_event;
281
282 return 0;
283 }
284
mt7615_mcu_lp_drv_pmctrl(struct mt7615_dev * dev)285 static int mt7615_mcu_lp_drv_pmctrl(struct mt7615_dev *dev)
286 {
287 struct mt76_phy *mphy = &dev->mt76.phy;
288 struct mt76_connac_pm *pm = &dev->pm;
289 int i, err = 0;
290
291 mutex_lock(&pm->mutex);
292
293 if (!test_bit(MT76_STATE_PM, &mphy->state))
294 goto out;
295
296 for (i = 0; i < MT7615_DRV_OWN_RETRY_COUNT; i++) {
297 mt76_wr(dev, MT_PCIE_DOORBELL_PUSH, MT_CFG_LPCR_HOST_DRV_OWN);
298 if (mt76_poll_msec(dev, MT_CONN_HIF_ON_LPCTL,
299 MT_CFG_LPCR_HOST_FW_OWN, 0, 50))
300 break;
301 }
302
303 if (i == MT7615_DRV_OWN_RETRY_COUNT) {
304 dev_err(dev->mt76.dev, "driver own failed\n");
305 err = -EIO;
306 goto out;
307 }
308 clear_bit(MT76_STATE_PM, &mphy->state);
309
310 pm->stats.last_wake_event = jiffies;
311 pm->stats.doze_time += pm->stats.last_wake_event -
312 pm->stats.last_doze_event;
313 out:
314 mutex_unlock(&pm->mutex);
315
316 return err;
317 }
318
mt7615_mcu_fw_pmctrl(struct mt7615_dev * dev)319 static int mt7615_mcu_fw_pmctrl(struct mt7615_dev *dev)
320 {
321 struct mt76_phy *mphy = &dev->mt76.phy;
322 struct mt76_connac_pm *pm = &dev->pm;
323 int err = 0;
324 u32 addr;
325
326 mutex_lock(&pm->mutex);
327
328 if (mt76_connac_skip_fw_pmctrl(mphy, pm))
329 goto out;
330
331 mt7622_trigger_hif_int(dev, true);
332
333 addr = is_mt7663(&dev->mt76) ? MT_CONN_HIF_ON_LPCTL : MT_CFG_LPCR_HOST;
334 mt76_wr(dev, addr, MT_CFG_LPCR_HOST_FW_OWN);
335
336 if (is_mt7622(&dev->mt76) &&
337 !mt76_poll_msec(dev, addr, MT_CFG_LPCR_HOST_FW_OWN,
338 MT_CFG_LPCR_HOST_FW_OWN, 3000)) {
339 dev_err(dev->mt76.dev, "Timeout for firmware own\n");
340 clear_bit(MT76_STATE_PM, &mphy->state);
341 err = -EIO;
342 }
343
344 mt7622_trigger_hif_int(dev, false);
345 if (!err) {
346 pm->stats.last_doze_event = jiffies;
347 pm->stats.awake_time += pm->stats.last_doze_event -
348 pm->stats.last_wake_event;
349 }
350 out:
351 mutex_unlock(&pm->mutex);
352
353 return err;
354 }
355
356 static void
mt7615_mcu_csa_finish(void * priv,u8 * mac,struct ieee80211_vif * vif)357 mt7615_mcu_csa_finish(void *priv, u8 *mac, struct ieee80211_vif *vif)
358 {
359 if (vif->bss_conf.csa_active)
360 ieee80211_csa_finish(vif);
361 }
362
363 static void
mt7615_mcu_rx_csa_notify(struct mt7615_dev * dev,struct sk_buff * skb)364 mt7615_mcu_rx_csa_notify(struct mt7615_dev *dev, struct sk_buff *skb)
365 {
366 struct mt7615_phy *ext_phy = mt7615_ext_phy(dev);
367 struct mt76_phy *mphy = &dev->mt76.phy;
368 struct mt7615_mcu_csa_notify *c;
369
370 c = (struct mt7615_mcu_csa_notify *)skb->data;
371
372 if (c->omac_idx > EXT_BSSID_MAX)
373 return;
374
375 if (ext_phy && ext_phy->omac_mask & BIT_ULL(c->omac_idx))
376 mphy = dev->mt76.phys[MT_BAND1];
377
378 ieee80211_iterate_active_interfaces_atomic(mphy->hw,
379 IEEE80211_IFACE_ITER_RESUME_ALL,
380 mt7615_mcu_csa_finish, mphy->hw);
381 }
382
383 static void
mt7615_mcu_rx_radar_detected(struct mt7615_dev * dev,struct sk_buff * skb)384 mt7615_mcu_rx_radar_detected(struct mt7615_dev *dev, struct sk_buff *skb)
385 {
386 struct mt76_phy *mphy = &dev->mt76.phy;
387 struct mt7615_mcu_rdd_report *r;
388
389 r = (struct mt7615_mcu_rdd_report *)skb->data;
390
391 if (!dev->radar_pattern.n_pulses && !r->long_detected &&
392 !r->constant_prf_detected && !r->staggered_prf_detected)
393 return;
394
395 if (r->band_idx && dev->mt76.phys[MT_BAND1])
396 mphy = dev->mt76.phys[MT_BAND1];
397
398 if (mt76_phy_dfs_state(mphy) < MT_DFS_STATE_CAC)
399 return;
400
401 ieee80211_radar_detected(mphy->hw);
402 dev->hw_pattern++;
403 }
404
405 static void
mt7615_mcu_rx_log_message(struct mt7615_dev * dev,struct sk_buff * skb)406 mt7615_mcu_rx_log_message(struct mt7615_dev *dev, struct sk_buff *skb)
407 {
408 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data;
409 const char *data = (char *)&rxd[1];
410 const char *type;
411
412 switch (rxd->s2d_index) {
413 case 0:
414 type = "N9";
415 break;
416 case 2:
417 type = "CR4";
418 break;
419 default:
420 type = "unknown";
421 break;
422 }
423
424 wiphy_info(mt76_hw(dev)->wiphy, "%s: %.*s", type,
425 (int)(skb->len - sizeof(*rxd)), data);
426 }
427
428 static void
mt7615_mcu_rx_ext_event(struct mt7615_dev * dev,struct sk_buff * skb)429 mt7615_mcu_rx_ext_event(struct mt7615_dev *dev, struct sk_buff *skb)
430 {
431 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data;
432
433 switch (rxd->ext_eid) {
434 case MCU_EXT_EVENT_RDD_REPORT:
435 mt7615_mcu_rx_radar_detected(dev, skb);
436 break;
437 case MCU_EXT_EVENT_CSA_NOTIFY:
438 mt7615_mcu_rx_csa_notify(dev, skb);
439 break;
440 case MCU_EXT_EVENT_FW_LOG_2_HOST:
441 mt7615_mcu_rx_log_message(dev, skb);
442 break;
443 default:
444 break;
445 }
446 }
447
448 static void
mt7615_mcu_scan_event(struct mt7615_dev * dev,struct sk_buff * skb)449 mt7615_mcu_scan_event(struct mt7615_dev *dev, struct sk_buff *skb)
450 {
451 u8 *seq_num = skb->data + sizeof(struct mt7615_mcu_rxd);
452 struct mt7615_phy *phy;
453 struct mt76_phy *mphy;
454
455 if (*seq_num & BIT(7) && dev->mt76.phys[MT_BAND1])
456 mphy = dev->mt76.phys[MT_BAND1];
457 else
458 mphy = &dev->mt76.phy;
459
460 phy = (struct mt7615_phy *)mphy->priv;
461
462 spin_lock_bh(&dev->mt76.lock);
463 __skb_queue_tail(&phy->scan_event_list, skb);
464 spin_unlock_bh(&dev->mt76.lock);
465
466 ieee80211_queue_delayed_work(mphy->hw, &phy->scan_work,
467 MT7615_HW_SCAN_TIMEOUT);
468 }
469
470 static void
mt7615_mcu_roc_event(struct mt7615_dev * dev,struct sk_buff * skb)471 mt7615_mcu_roc_event(struct mt7615_dev *dev, struct sk_buff *skb)
472 {
473 struct mt7615_roc_tlv *event;
474 struct mt7615_phy *phy;
475 struct mt76_phy *mphy;
476 int duration;
477
478 skb_pull(skb, sizeof(struct mt7615_mcu_rxd));
479 event = (struct mt7615_roc_tlv *)skb->data;
480
481 if (event->dbdc_band && dev->mt76.phys[MT_BAND1])
482 mphy = dev->mt76.phys[MT_BAND1];
483 else
484 mphy = &dev->mt76.phy;
485
486 ieee80211_ready_on_channel(mphy->hw);
487
488 phy = (struct mt7615_phy *)mphy->priv;
489 phy->roc_grant = true;
490 wake_up(&phy->roc_wait);
491
492 duration = le32_to_cpu(event->max_interval);
493 mod_timer(&phy->roc_timer,
494 round_jiffies_up(jiffies + msecs_to_jiffies(duration)));
495 }
496
497 static void
mt7615_mcu_beacon_loss_event(struct mt7615_dev * dev,struct sk_buff * skb)498 mt7615_mcu_beacon_loss_event(struct mt7615_dev *dev, struct sk_buff *skb)
499 {
500 struct mt76_connac_beacon_loss_event *event;
501 struct mt76_phy *mphy;
502 u8 band_idx = 0; /* DBDC support */
503
504 skb_pull(skb, sizeof(struct mt7615_mcu_rxd));
505 event = (struct mt76_connac_beacon_loss_event *)skb->data;
506 if (band_idx && dev->mt76.phys[MT_BAND1])
507 mphy = dev->mt76.phys[MT_BAND1];
508 else
509 mphy = &dev->mt76.phy;
510
511 ieee80211_iterate_active_interfaces_atomic(mphy->hw,
512 IEEE80211_IFACE_ITER_RESUME_ALL,
513 mt76_connac_mcu_beacon_loss_iter,
514 event);
515 }
516
517 static void
mt7615_mcu_bss_event(struct mt7615_dev * dev,struct sk_buff * skb)518 mt7615_mcu_bss_event(struct mt7615_dev *dev, struct sk_buff *skb)
519 {
520 struct mt76_connac_mcu_bss_event *event;
521 struct mt76_phy *mphy;
522 u8 band_idx = 0; /* DBDC support */
523
524 skb_pull(skb, sizeof(struct mt7615_mcu_rxd));
525 event = (struct mt76_connac_mcu_bss_event *)skb->data;
526
527 if (band_idx && dev->mt76.phys[MT_BAND1])
528 mphy = dev->mt76.phys[MT_BAND1];
529 else
530 mphy = &dev->mt76.phy;
531
532 if (event->is_absent)
533 ieee80211_stop_queues(mphy->hw);
534 else
535 ieee80211_wake_queues(mphy->hw);
536 }
537
538 static void
mt7615_mcu_rx_unsolicited_event(struct mt7615_dev * dev,struct sk_buff * skb)539 mt7615_mcu_rx_unsolicited_event(struct mt7615_dev *dev, struct sk_buff *skb)
540 {
541 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data;
542
543 switch (rxd->eid) {
544 case MCU_EVENT_EXT:
545 mt7615_mcu_rx_ext_event(dev, skb);
546 break;
547 case MCU_EVENT_BSS_BEACON_LOSS:
548 mt7615_mcu_beacon_loss_event(dev, skb);
549 break;
550 case MCU_EVENT_ROC:
551 mt7615_mcu_roc_event(dev, skb);
552 break;
553 case MCU_EVENT_SCHED_SCAN_DONE:
554 case MCU_EVENT_SCAN_DONE:
555 mt7615_mcu_scan_event(dev, skb);
556 return;
557 case MCU_EVENT_BSS_ABSENCE:
558 mt7615_mcu_bss_event(dev, skb);
559 break;
560 case MCU_EVENT_COREDUMP:
561 mt76_connac_mcu_coredump_event(&dev->mt76, skb,
562 &dev->coredump);
563 return;
564 default:
565 break;
566 }
567 dev_kfree_skb(skb);
568 }
569
mt7615_mcu_rx_event(struct mt7615_dev * dev,struct sk_buff * skb)570 void mt7615_mcu_rx_event(struct mt7615_dev *dev, struct sk_buff *skb)
571 {
572 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data;
573
574 if (rxd->ext_eid == MCU_EXT_EVENT_THERMAL_PROTECT ||
575 rxd->ext_eid == MCU_EXT_EVENT_FW_LOG_2_HOST ||
576 rxd->ext_eid == MCU_EXT_EVENT_ASSERT_DUMP ||
577 rxd->ext_eid == MCU_EXT_EVENT_PS_SYNC ||
578 rxd->eid == MCU_EVENT_BSS_BEACON_LOSS ||
579 rxd->eid == MCU_EVENT_SCHED_SCAN_DONE ||
580 rxd->eid == MCU_EVENT_BSS_ABSENCE ||
581 rxd->eid == MCU_EVENT_SCAN_DONE ||
582 rxd->eid == MCU_EVENT_COREDUMP ||
583 rxd->eid == MCU_EVENT_ROC ||
584 !rxd->seq)
585 mt7615_mcu_rx_unsolicited_event(dev, skb);
586 else
587 mt76_mcu_rx_event(&dev->mt76, skb);
588 }
589
590 static int
mt7615_mcu_muar_config(struct mt7615_dev * dev,struct ieee80211_vif * vif,bool bssid,bool enable)591 mt7615_mcu_muar_config(struct mt7615_dev *dev, struct ieee80211_vif *vif,
592 bool bssid, bool enable)
593 {
594 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
595 u32 idx = mvif->mt76.omac_idx - REPEATER_BSSID_START;
596 u32 mask = dev->omac_mask >> 32 & ~BIT(idx);
597 const u8 *addr = vif->addr;
598 struct {
599 u8 mode;
600 u8 force_clear;
601 u8 clear_bitmap[8];
602 u8 entry_count;
603 u8 write;
604
605 u8 index;
606 u8 bssid;
607 u8 addr[ETH_ALEN];
608 } __packed req = {
609 .mode = !!mask || enable,
610 .entry_count = 1,
611 .write = 1,
612
613 .index = idx * 2 + bssid,
614 };
615
616 if (bssid)
617 addr = vif->bss_conf.bssid;
618
619 if (enable)
620 ether_addr_copy(req.addr, addr);
621
622 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MUAR_UPDATE),
623 &req, sizeof(req), true);
624 }
625
626 static int
mt7615_mcu_add_dev(struct mt7615_phy * phy,struct ieee80211_vif * vif,bool enable)627 mt7615_mcu_add_dev(struct mt7615_phy *phy, struct ieee80211_vif *vif,
628 bool enable)
629 {
630 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
631 struct mt7615_dev *dev = phy->dev;
632 struct {
633 struct req_hdr {
634 u8 omac_idx;
635 u8 band_idx;
636 __le16 tlv_num;
637 u8 is_tlv_append;
638 u8 rsv[3];
639 } __packed hdr;
640 struct req_tlv {
641 __le16 tag;
642 __le16 len;
643 u8 active;
644 u8 band_idx;
645 u8 omac_addr[ETH_ALEN];
646 } __packed tlv;
647 } data = {
648 .hdr = {
649 .omac_idx = mvif->mt76.omac_idx,
650 .band_idx = mvif->mt76.band_idx,
651 .tlv_num = cpu_to_le16(1),
652 .is_tlv_append = 1,
653 },
654 .tlv = {
655 .tag = cpu_to_le16(DEV_INFO_ACTIVE),
656 .len = cpu_to_le16(sizeof(struct req_tlv)),
657 .active = enable,
658 .band_idx = mvif->mt76.band_idx,
659 },
660 };
661
662 if (mvif->mt76.omac_idx >= REPEATER_BSSID_START)
663 return mt7615_mcu_muar_config(dev, vif, false, enable);
664
665 memcpy(data.tlv.omac_addr, vif->addr, ETH_ALEN);
666 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(DEV_INFO_UPDATE),
667 &data, sizeof(data), true);
668 }
669
670 static int
mt7615_mcu_add_beacon_offload(struct mt7615_dev * dev,struct ieee80211_hw * hw,struct ieee80211_vif * vif,bool enable)671 mt7615_mcu_add_beacon_offload(struct mt7615_dev *dev,
672 struct ieee80211_hw *hw,
673 struct ieee80211_vif *vif, bool enable)
674 {
675 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
676 struct mt76_wcid *wcid = &dev->mt76.global_wcid;
677 struct ieee80211_mutable_offsets offs;
678 struct ieee80211_tx_info *info;
679 struct req {
680 u8 omac_idx;
681 u8 enable;
682 u8 wlan_idx;
683 u8 band_idx;
684 u8 pkt_type;
685 u8 need_pre_tbtt_int;
686 __le16 csa_ie_pos;
687 __le16 pkt_len;
688 __le16 tim_ie_pos;
689 u8 pkt[512];
690 u8 csa_cnt;
691 /* bss color change */
692 u8 bcc_cnt;
693 __le16 bcc_ie_pos;
694 } __packed req = {
695 .omac_idx = mvif->mt76.omac_idx,
696 .enable = enable,
697 .wlan_idx = wcid->idx,
698 .band_idx = mvif->mt76.band_idx,
699 };
700 struct sk_buff *skb;
701
702 if (!enable)
703 goto out;
704
705 skb = ieee80211_beacon_get_template(hw, vif, &offs, 0);
706 if (!skb)
707 return -EINVAL;
708
709 if (skb->len > 512 - MT_TXD_SIZE) {
710 dev_err(dev->mt76.dev, "Bcn size limit exceed\n");
711 dev_kfree_skb(skb);
712 return -EINVAL;
713 }
714
715 info = IEEE80211_SKB_CB(skb);
716 info->hw_queue |= FIELD_PREP(MT_TX_HW_QUEUE_PHY, mvif->mt76.band_idx);
717
718 mt7615_mac_write_txwi(dev, (__le32 *)(req.pkt), skb, wcid, NULL,
719 0, NULL, 0, true);
720 memcpy(req.pkt + MT_TXD_SIZE, skb->data, skb->len);
721 req.pkt_len = cpu_to_le16(MT_TXD_SIZE + skb->len);
722 req.tim_ie_pos = cpu_to_le16(MT_TXD_SIZE + offs.tim_offset);
723 if (offs.cntdwn_counter_offs[0]) {
724 u16 csa_offs;
725
726 csa_offs = MT_TXD_SIZE + offs.cntdwn_counter_offs[0] - 4;
727 req.csa_ie_pos = cpu_to_le16(csa_offs);
728 req.csa_cnt = skb->data[offs.cntdwn_counter_offs[0]];
729 }
730 dev_kfree_skb(skb);
731
732 out:
733 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(BCN_OFFLOAD), &req,
734 sizeof(req), true);
735 }
736
737 static int
mt7615_mcu_ctrl_pm_state(struct mt7615_dev * dev,int band,int state)738 mt7615_mcu_ctrl_pm_state(struct mt7615_dev *dev, int band, int state)
739 {
740 return mt76_connac_mcu_set_pm(&dev->mt76, band, state);
741 }
742
743 static int
mt7615_mcu_add_bss(struct mt7615_phy * phy,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable)744 mt7615_mcu_add_bss(struct mt7615_phy *phy, struct ieee80211_vif *vif,
745 struct ieee80211_sta *sta, bool enable)
746 {
747 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
748 struct mt7615_dev *dev = phy->dev;
749 struct sk_buff *skb;
750
751 if (mvif->mt76.omac_idx >= REPEATER_BSSID_START)
752 mt7615_mcu_muar_config(dev, vif, true, enable);
753
754 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, NULL);
755 if (IS_ERR(skb))
756 return PTR_ERR(skb);
757
758 if (enable)
759 mt76_connac_mcu_bss_omac_tlv(skb, vif);
760
761 mt76_connac_mcu_bss_basic_tlv(skb, vif, sta, phy->mt76,
762 mvif->sta.wcid.idx, enable);
763
764 if (enable && mvif->mt76.omac_idx >= EXT_BSSID_START &&
765 mvif->mt76.omac_idx < REPEATER_BSSID_START)
766 mt76_connac_mcu_bss_ext_tlv(skb, &mvif->mt76);
767
768 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
769 MCU_EXT_CMD(BSS_INFO_UPDATE), true);
770 }
771
772 static int
mt7615_mcu_wtbl_tx_ba(struct mt7615_dev * dev,struct ieee80211_ampdu_params * params,bool enable)773 mt7615_mcu_wtbl_tx_ba(struct mt7615_dev *dev,
774 struct ieee80211_ampdu_params *params,
775 bool enable)
776 {
777 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv;
778 struct mt7615_vif *mvif = msta->vif;
779 struct wtbl_req_hdr *wtbl_hdr;
780 struct sk_buff *skb = NULL;
781 int err;
782
783 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid,
784 WTBL_SET, NULL, &skb);
785 if (IS_ERR(wtbl_hdr))
786 return PTR_ERR(wtbl_hdr);
787
788 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, true,
789 NULL, wtbl_hdr);
790
791 err = mt76_mcu_skb_send_msg(&dev->mt76, skb,
792 MCU_EXT_CMD(WTBL_UPDATE), true);
793 if (err < 0)
794 return err;
795
796 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
797 &msta->wcid);
798 if (IS_ERR(skb))
799 return PTR_ERR(skb);
800
801 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, true);
802
803 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
804 MCU_EXT_CMD(STA_REC_UPDATE), true);
805 }
806
807 static int
mt7615_mcu_wtbl_rx_ba(struct mt7615_dev * dev,struct ieee80211_ampdu_params * params,bool enable)808 mt7615_mcu_wtbl_rx_ba(struct mt7615_dev *dev,
809 struct ieee80211_ampdu_params *params,
810 bool enable)
811 {
812 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv;
813 struct mt7615_vif *mvif = msta->vif;
814 struct wtbl_req_hdr *wtbl_hdr;
815 struct sk_buff *skb;
816 int err;
817
818 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
819 &msta->wcid);
820 if (IS_ERR(skb))
821 return PTR_ERR(skb);
822
823 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, false);
824
825 err = mt76_mcu_skb_send_msg(&dev->mt76, skb,
826 MCU_EXT_CMD(STA_REC_UPDATE), true);
827 if (err < 0 || !enable)
828 return err;
829
830 skb = NULL;
831 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid,
832 WTBL_SET, NULL, &skb);
833 if (IS_ERR(wtbl_hdr))
834 return PTR_ERR(wtbl_hdr);
835
836 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, false,
837 NULL, wtbl_hdr);
838
839 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
840 MCU_EXT_CMD(WTBL_UPDATE), true);
841 }
842
843 static int
mt7615_mcu_wtbl_sta_add(struct mt7615_phy * phy,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable)844 mt7615_mcu_wtbl_sta_add(struct mt7615_phy *phy, struct ieee80211_vif *vif,
845 struct ieee80211_sta *sta, bool enable)
846 {
847 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
848 struct sk_buff *skb, *sskb, *wskb = NULL;
849 struct mt7615_dev *dev = phy->dev;
850 struct wtbl_req_hdr *wtbl_hdr;
851 struct mt7615_sta *msta;
852 bool new_entry = true;
853 int cmd, err;
854
855 msta = sta ? (struct mt7615_sta *)sta->drv_priv : &mvif->sta;
856
857 sskb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
858 &msta->wcid);
859 if (IS_ERR(sskb))
860 return PTR_ERR(sskb);
861
862 if (!sta) {
863 if (mvif->sta_added)
864 new_entry = false;
865 else
866 mvif->sta_added = true;
867 }
868 mt76_connac_mcu_sta_basic_tlv(&dev->mt76, sskb, vif, sta, enable,
869 new_entry);
870 if (enable && sta)
871 mt76_connac_mcu_sta_tlv(phy->mt76, sskb, sta, vif, 0,
872 MT76_STA_INFO_STATE_ASSOC);
873
874 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid,
875 WTBL_RESET_AND_SET, NULL,
876 &wskb);
877 if (IS_ERR(wtbl_hdr))
878 return PTR_ERR(wtbl_hdr);
879
880 if (enable) {
881 mt76_connac_mcu_wtbl_generic_tlv(&dev->mt76, wskb, vif, sta,
882 NULL, wtbl_hdr);
883 if (sta)
884 mt76_connac_mcu_wtbl_ht_tlv(&dev->mt76, wskb, sta,
885 NULL, wtbl_hdr, true, true);
886 mt76_connac_mcu_wtbl_hdr_trans_tlv(wskb, vif, &msta->wcid,
887 NULL, wtbl_hdr);
888 }
889
890 cmd = enable ? MCU_EXT_CMD(WTBL_UPDATE) : MCU_EXT_CMD(STA_REC_UPDATE);
891 skb = enable ? wskb : sskb;
892
893 err = mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true);
894 if (err < 0) {
895 skb = enable ? sskb : wskb;
896 dev_kfree_skb(skb);
897
898 return err;
899 }
900
901 cmd = enable ? MCU_EXT_CMD(STA_REC_UPDATE) : MCU_EXT_CMD(WTBL_UPDATE);
902 skb = enable ? sskb : wskb;
903
904 return mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true);
905 }
906
907 static int
mt7615_mcu_wtbl_update_hdr_trans(struct mt7615_dev * dev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)908 mt7615_mcu_wtbl_update_hdr_trans(struct mt7615_dev *dev,
909 struct ieee80211_vif *vif,
910 struct ieee80211_sta *sta)
911 {
912 return mt76_connac_mcu_wtbl_update_hdr_trans(&dev->mt76, vif, sta);
913 }
914
915 static const struct mt7615_mcu_ops wtbl_update_ops = {
916 .add_beacon_offload = mt7615_mcu_add_beacon_offload,
917 .set_pm_state = mt7615_mcu_ctrl_pm_state,
918 .add_dev_info = mt7615_mcu_add_dev,
919 .add_bss_info = mt7615_mcu_add_bss,
920 .add_tx_ba = mt7615_mcu_wtbl_tx_ba,
921 .add_rx_ba = mt7615_mcu_wtbl_rx_ba,
922 .sta_add = mt7615_mcu_wtbl_sta_add,
923 .set_drv_ctrl = mt7615_mcu_drv_pmctrl,
924 .set_fw_ctrl = mt7615_mcu_fw_pmctrl,
925 .set_sta_decap_offload = mt7615_mcu_wtbl_update_hdr_trans,
926 };
927
928 static int
mt7615_mcu_sta_ba(struct mt7615_dev * dev,struct ieee80211_ampdu_params * params,bool enable,bool tx)929 mt7615_mcu_sta_ba(struct mt7615_dev *dev,
930 struct ieee80211_ampdu_params *params,
931 bool enable, bool tx)
932 {
933 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv;
934 struct mt7615_vif *mvif = msta->vif;
935 struct wtbl_req_hdr *wtbl_hdr;
936 struct tlv *sta_wtbl;
937 struct sk_buff *skb;
938
939 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
940 &msta->wcid);
941 if (IS_ERR(skb))
942 return PTR_ERR(skb);
943
944 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, tx);
945
946 sta_wtbl = mt76_connac_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv));
947
948 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid,
949 WTBL_SET, sta_wtbl, &skb);
950 if (IS_ERR(wtbl_hdr))
951 return PTR_ERR(wtbl_hdr);
952
953 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, tx,
954 sta_wtbl, wtbl_hdr);
955
956 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
957 MCU_EXT_CMD(STA_REC_UPDATE), true);
958 }
959
960 static int
mt7615_mcu_sta_tx_ba(struct mt7615_dev * dev,struct ieee80211_ampdu_params * params,bool enable)961 mt7615_mcu_sta_tx_ba(struct mt7615_dev *dev,
962 struct ieee80211_ampdu_params *params,
963 bool enable)
964 {
965 return mt7615_mcu_sta_ba(dev, params, enable, true);
966 }
967
968 static int
mt7615_mcu_sta_rx_ba(struct mt7615_dev * dev,struct ieee80211_ampdu_params * params,bool enable)969 mt7615_mcu_sta_rx_ba(struct mt7615_dev *dev,
970 struct ieee80211_ampdu_params *params,
971 bool enable)
972 {
973 return mt7615_mcu_sta_ba(dev, params, enable, false);
974 }
975
976 static int
__mt7615_mcu_add_sta(struct mt76_phy * phy,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable,int cmd,bool offload_fw)977 __mt7615_mcu_add_sta(struct mt76_phy *phy, struct ieee80211_vif *vif,
978 struct ieee80211_sta *sta, bool enable, int cmd,
979 bool offload_fw)
980 {
981 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
982 struct mt76_sta_cmd_info info = {
983 .sta = sta,
984 .vif = vif,
985 .offload_fw = offload_fw,
986 .enable = enable,
987 .newly = true,
988 .cmd = cmd,
989 };
990
991 info.wcid = sta ? (struct mt76_wcid *)sta->drv_priv : &mvif->sta.wcid;
992 return mt76_connac_mcu_sta_cmd(phy, &info);
993 }
994
995 static int
mt7615_mcu_add_sta(struct mt7615_phy * phy,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable)996 mt7615_mcu_add_sta(struct mt7615_phy *phy, struct ieee80211_vif *vif,
997 struct ieee80211_sta *sta, bool enable)
998 {
999 return __mt7615_mcu_add_sta(phy->mt76, vif, sta, enable,
1000 MCU_EXT_CMD(STA_REC_UPDATE), false);
1001 }
1002
1003 static int
mt7615_mcu_sta_update_hdr_trans(struct mt7615_dev * dev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1004 mt7615_mcu_sta_update_hdr_trans(struct mt7615_dev *dev,
1005 struct ieee80211_vif *vif,
1006 struct ieee80211_sta *sta)
1007 {
1008 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
1009
1010 return mt76_connac_mcu_sta_update_hdr_trans(&dev->mt76,
1011 vif, &msta->wcid,
1012 MCU_EXT_CMD(STA_REC_UPDATE));
1013 }
1014
1015 static const struct mt7615_mcu_ops sta_update_ops = {
1016 .add_beacon_offload = mt7615_mcu_add_beacon_offload,
1017 .set_pm_state = mt7615_mcu_ctrl_pm_state,
1018 .add_dev_info = mt7615_mcu_add_dev,
1019 .add_bss_info = mt7615_mcu_add_bss,
1020 .add_tx_ba = mt7615_mcu_sta_tx_ba,
1021 .add_rx_ba = mt7615_mcu_sta_rx_ba,
1022 .sta_add = mt7615_mcu_add_sta,
1023 .set_drv_ctrl = mt7615_mcu_drv_pmctrl,
1024 .set_fw_ctrl = mt7615_mcu_fw_pmctrl,
1025 .set_sta_decap_offload = mt7615_mcu_sta_update_hdr_trans,
1026 };
1027
1028 static int
mt7615_mcu_uni_ctrl_pm_state(struct mt7615_dev * dev,int band,int state)1029 mt7615_mcu_uni_ctrl_pm_state(struct mt7615_dev *dev, int band, int state)
1030 {
1031 return 0;
1032 }
1033
1034 static int
mt7615_mcu_uni_add_beacon_offload(struct mt7615_dev * dev,struct ieee80211_hw * hw,struct ieee80211_vif * vif,bool enable)1035 mt7615_mcu_uni_add_beacon_offload(struct mt7615_dev *dev,
1036 struct ieee80211_hw *hw,
1037 struct ieee80211_vif *vif,
1038 bool enable)
1039 {
1040 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
1041 struct mt76_wcid *wcid = &dev->mt76.global_wcid;
1042 struct ieee80211_mutable_offsets offs;
1043 struct {
1044 struct req_hdr {
1045 u8 bss_idx;
1046 u8 pad[3];
1047 } __packed hdr;
1048 struct bcn_content_tlv {
1049 __le16 tag;
1050 __le16 len;
1051 __le16 tim_ie_pos;
1052 __le16 csa_ie_pos;
1053 __le16 bcc_ie_pos;
1054 /* 0: disable beacon offload
1055 * 1: enable beacon offload
1056 * 2: update probe respond offload
1057 */
1058 u8 enable;
1059 /* 0: legacy format (TXD + payload)
1060 * 1: only cap field IE
1061 */
1062 u8 type;
1063 __le16 pkt_len;
1064 u8 pkt[512];
1065 } __packed beacon_tlv;
1066 } req = {
1067 .hdr = {
1068 .bss_idx = mvif->mt76.idx,
1069 },
1070 .beacon_tlv = {
1071 .tag = cpu_to_le16(UNI_BSS_INFO_BCN_CONTENT),
1072 .len = cpu_to_le16(sizeof(struct bcn_content_tlv)),
1073 .enable = enable,
1074 },
1075 };
1076 struct sk_buff *skb;
1077
1078 if (!enable)
1079 goto out;
1080
1081 skb = ieee80211_beacon_get_template(mt76_hw(dev), vif, &offs, 0);
1082 if (!skb)
1083 return -EINVAL;
1084
1085 if (skb->len > 512 - MT_TXD_SIZE) {
1086 dev_err(dev->mt76.dev, "beacon size limit exceed\n");
1087 dev_kfree_skb(skb);
1088 return -EINVAL;
1089 }
1090
1091 mt7615_mac_write_txwi(dev, (__le32 *)(req.beacon_tlv.pkt), skb,
1092 wcid, NULL, 0, NULL, 0, true);
1093 memcpy(req.beacon_tlv.pkt + MT_TXD_SIZE, skb->data, skb->len);
1094 req.beacon_tlv.pkt_len = cpu_to_le16(MT_TXD_SIZE + skb->len);
1095 req.beacon_tlv.tim_ie_pos = cpu_to_le16(MT_TXD_SIZE + offs.tim_offset);
1096
1097 if (offs.cntdwn_counter_offs[0]) {
1098 u16 csa_offs;
1099
1100 csa_offs = MT_TXD_SIZE + offs.cntdwn_counter_offs[0] - 4;
1101 req.beacon_tlv.csa_ie_pos = cpu_to_le16(csa_offs);
1102 }
1103 dev_kfree_skb(skb);
1104
1105 out:
1106 return mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD(BSS_INFO_UPDATE),
1107 &req, sizeof(req), true);
1108 }
1109
1110 static int
mt7615_mcu_uni_add_dev(struct mt7615_phy * phy,struct ieee80211_vif * vif,bool enable)1111 mt7615_mcu_uni_add_dev(struct mt7615_phy *phy, struct ieee80211_vif *vif,
1112 bool enable)
1113 {
1114 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
1115
1116 return mt76_connac_mcu_uni_add_dev(phy->mt76, vif, &mvif->sta.wcid,
1117 enable);
1118 }
1119
1120 static int
mt7615_mcu_uni_add_bss(struct mt7615_phy * phy,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable)1121 mt7615_mcu_uni_add_bss(struct mt7615_phy *phy, struct ieee80211_vif *vif,
1122 struct ieee80211_sta *sta, bool enable)
1123 {
1124 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
1125
1126 return mt76_connac_mcu_uni_add_bss(phy->mt76, vif, &mvif->sta.wcid,
1127 enable, NULL);
1128 }
1129
1130 static inline int
mt7615_mcu_uni_add_sta(struct mt7615_phy * phy,struct ieee80211_vif * vif,struct ieee80211_sta * sta,bool enable)1131 mt7615_mcu_uni_add_sta(struct mt7615_phy *phy, struct ieee80211_vif *vif,
1132 struct ieee80211_sta *sta, bool enable)
1133 {
1134 return __mt7615_mcu_add_sta(phy->mt76, vif, sta, enable,
1135 MCU_UNI_CMD(STA_REC_UPDATE), true);
1136 }
1137
1138 static int
mt7615_mcu_uni_tx_ba(struct mt7615_dev * dev,struct ieee80211_ampdu_params * params,bool enable)1139 mt7615_mcu_uni_tx_ba(struct mt7615_dev *dev,
1140 struct ieee80211_ampdu_params *params,
1141 bool enable)
1142 {
1143 struct mt7615_sta *sta = (struct mt7615_sta *)params->sta->drv_priv;
1144
1145 return mt76_connac_mcu_sta_ba(&dev->mt76, &sta->vif->mt76, params,
1146 MCU_UNI_CMD(STA_REC_UPDATE), enable,
1147 true);
1148 }
1149
1150 static int
mt7615_mcu_uni_rx_ba(struct mt7615_dev * dev,struct ieee80211_ampdu_params * params,bool enable)1151 mt7615_mcu_uni_rx_ba(struct mt7615_dev *dev,
1152 struct ieee80211_ampdu_params *params,
1153 bool enable)
1154 {
1155 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv;
1156 struct mt7615_vif *mvif = msta->vif;
1157 struct wtbl_req_hdr *wtbl_hdr;
1158 struct tlv *sta_wtbl;
1159 struct sk_buff *skb;
1160 int err;
1161
1162 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
1163 &msta->wcid);
1164 if (IS_ERR(skb))
1165 return PTR_ERR(skb);
1166
1167 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, false);
1168
1169 err = mt76_mcu_skb_send_msg(&dev->mt76, skb,
1170 MCU_UNI_CMD(STA_REC_UPDATE), true);
1171 if (err < 0 || !enable)
1172 return err;
1173
1174 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
1175 &msta->wcid);
1176 if (IS_ERR(skb))
1177 return PTR_ERR(skb);
1178
1179 sta_wtbl = mt76_connac_mcu_add_tlv(skb, STA_REC_WTBL,
1180 sizeof(struct tlv));
1181
1182 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid,
1183 WTBL_SET, sta_wtbl, &skb);
1184 if (IS_ERR(wtbl_hdr))
1185 return PTR_ERR(wtbl_hdr);
1186
1187 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, false,
1188 sta_wtbl, wtbl_hdr);
1189
1190 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
1191 MCU_UNI_CMD(STA_REC_UPDATE), true);
1192 }
1193
1194 static int
mt7615_mcu_sta_uni_update_hdr_trans(struct mt7615_dev * dev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1195 mt7615_mcu_sta_uni_update_hdr_trans(struct mt7615_dev *dev,
1196 struct ieee80211_vif *vif,
1197 struct ieee80211_sta *sta)
1198 {
1199 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
1200
1201 return mt76_connac_mcu_sta_update_hdr_trans(&dev->mt76,
1202 vif, &msta->wcid,
1203 MCU_UNI_CMD(STA_REC_UPDATE));
1204 }
1205
1206 static const struct mt7615_mcu_ops uni_update_ops = {
1207 .add_beacon_offload = mt7615_mcu_uni_add_beacon_offload,
1208 .set_pm_state = mt7615_mcu_uni_ctrl_pm_state,
1209 .add_dev_info = mt7615_mcu_uni_add_dev,
1210 .add_bss_info = mt7615_mcu_uni_add_bss,
1211 .add_tx_ba = mt7615_mcu_uni_tx_ba,
1212 .add_rx_ba = mt7615_mcu_uni_rx_ba,
1213 .sta_add = mt7615_mcu_uni_add_sta,
1214 .set_drv_ctrl = mt7615_mcu_lp_drv_pmctrl,
1215 .set_fw_ctrl = mt7615_mcu_fw_pmctrl,
1216 .set_sta_decap_offload = mt7615_mcu_sta_uni_update_hdr_trans,
1217 };
1218
mt7615_mcu_restart(struct mt76_dev * dev)1219 int mt7615_mcu_restart(struct mt76_dev *dev)
1220 {
1221 return mt76_mcu_send_msg(dev, MCU_CMD(RESTART_DL_REQ), NULL, 0, true);
1222 }
1223 EXPORT_SYMBOL_GPL(mt7615_mcu_restart);
1224
mt7615_load_patch(struct mt7615_dev * dev,u32 addr,const char * name)1225 static int mt7615_load_patch(struct mt7615_dev *dev, u32 addr, const char *name)
1226 {
1227 const struct mt7615_patch_hdr *hdr;
1228 const struct firmware *fw = NULL;
1229 int len, ret, sem;
1230
1231 ret = firmware_request_nowarn(&fw, name, dev->mt76.dev);
1232 if (ret)
1233 return ret;
1234
1235 if (!fw || !fw->data || fw->size < sizeof(*hdr)) {
1236 dev_err(dev->mt76.dev, "Invalid firmware\n");
1237 ret = -EINVAL;
1238 goto release_fw;
1239 }
1240
1241 sem = mt76_connac_mcu_patch_sem_ctrl(&dev->mt76, true);
1242 switch (sem) {
1243 case PATCH_IS_DL:
1244 goto release_fw;
1245 case PATCH_NOT_DL_SEM_SUCCESS:
1246 break;
1247 default:
1248 dev_err(dev->mt76.dev, "Failed to get patch semaphore\n");
1249 ret = -EAGAIN;
1250 goto release_fw;
1251 }
1252
1253 hdr = (const struct mt7615_patch_hdr *)(fw->data);
1254
1255 dev_info(dev->mt76.dev, "HW/SW Version: 0x%x, Build Time: %.16s\n",
1256 be32_to_cpu(hdr->hw_sw_ver), hdr->build_date);
1257
1258 len = fw->size - sizeof(*hdr);
1259
1260 ret = mt76_connac_mcu_init_download(&dev->mt76, addr, len,
1261 DL_MODE_NEED_RSP);
1262 if (ret) {
1263 dev_err(dev->mt76.dev, "Download request failed\n");
1264 goto out;
1265 }
1266
1267 ret = mt76_mcu_send_firmware(&dev->mt76, MCU_CMD(FW_SCATTER),
1268 fw->data + sizeof(*hdr), len);
1269 if (ret) {
1270 dev_err(dev->mt76.dev, "Failed to send firmware to device\n");
1271 goto out;
1272 }
1273
1274 ret = mt76_connac_mcu_start_patch(&dev->mt76);
1275 if (ret)
1276 dev_err(dev->mt76.dev, "Failed to start patch\n");
1277
1278 out:
1279 sem = mt76_connac_mcu_patch_sem_ctrl(&dev->mt76, false);
1280 switch (sem) {
1281 case PATCH_REL_SEM_SUCCESS:
1282 break;
1283 default:
1284 ret = -EAGAIN;
1285 dev_err(dev->mt76.dev, "Failed to release patch semaphore\n");
1286 break;
1287 }
1288
1289 release_fw:
1290 release_firmware(fw);
1291
1292 return ret;
1293 }
1294
1295 static int
mt7615_mcu_send_ram_firmware(struct mt7615_dev * dev,const struct mt7615_fw_trailer * hdr,const u8 * data,bool is_cr4)1296 mt7615_mcu_send_ram_firmware(struct mt7615_dev *dev,
1297 const struct mt7615_fw_trailer *hdr,
1298 const u8 *data, bool is_cr4)
1299 {
1300 int n_region = is_cr4 ? CR4_REGION_NUM : N9_REGION_NUM;
1301 int err, i, offset = 0;
1302 u32 len, addr, mode;
1303
1304 for (i = 0; i < n_region; i++) {
1305 mode = mt76_connac_mcu_gen_dl_mode(&dev->mt76,
1306 hdr[i].feature_set, is_cr4);
1307 len = le32_to_cpu(hdr[i].len) + IMG_CRC_LEN;
1308 addr = le32_to_cpu(hdr[i].addr);
1309
1310 err = mt76_connac_mcu_init_download(&dev->mt76, addr, len,
1311 mode);
1312 if (err) {
1313 dev_err(dev->mt76.dev, "Download request failed\n");
1314 return err;
1315 }
1316
1317 err = mt76_mcu_send_firmware(&dev->mt76, MCU_CMD(FW_SCATTER),
1318 data + offset, len);
1319 if (err) {
1320 dev_err(dev->mt76.dev, "Failed to send firmware to device\n");
1321 return err;
1322 }
1323
1324 offset += len;
1325 }
1326
1327 return 0;
1328 }
1329
mt7615_load_n9(struct mt7615_dev * dev,const char * name)1330 static int mt7615_load_n9(struct mt7615_dev *dev, const char *name)
1331 {
1332 const struct mt7615_fw_trailer *hdr;
1333 const struct firmware *fw;
1334 int ret;
1335
1336 ret = request_firmware(&fw, name, dev->mt76.dev);
1337 if (ret)
1338 return ret;
1339
1340 if (!fw || !fw->data || fw->size < N9_REGION_NUM * sizeof(*hdr)) {
1341 dev_err(dev->mt76.dev, "Invalid firmware\n");
1342 ret = -EINVAL;
1343 goto out;
1344 }
1345
1346 hdr = (const struct mt7615_fw_trailer *)(fw->data + fw->size -
1347 N9_REGION_NUM * sizeof(*hdr));
1348
1349 dev_info(dev->mt76.dev, "N9 Firmware Version: %.10s, Build Time: %.15s\n",
1350 hdr->fw_ver, hdr->build_date);
1351
1352 ret = mt7615_mcu_send_ram_firmware(dev, hdr, fw->data, false);
1353 if (ret)
1354 goto out;
1355
1356 ret = mt76_connac_mcu_start_firmware(&dev->mt76,
1357 le32_to_cpu(hdr->addr),
1358 FW_START_OVERRIDE);
1359 if (ret) {
1360 dev_err(dev->mt76.dev, "Failed to start N9 firmware\n");
1361 goto out;
1362 }
1363
1364 snprintf(dev->mt76.hw->wiphy->fw_version,
1365 sizeof(dev->mt76.hw->wiphy->fw_version),
1366 "%.10s-%.15s", hdr->fw_ver, hdr->build_date);
1367
1368 if (!is_mt7615(&dev->mt76)) {
1369 dev->fw_ver = MT7615_FIRMWARE_V2;
1370 dev->mcu_ops = &sta_update_ops;
1371 } else {
1372 dev->fw_ver = MT7615_FIRMWARE_V1;
1373 dev->mcu_ops = &wtbl_update_ops;
1374 }
1375
1376 out:
1377 release_firmware(fw);
1378 return ret;
1379 }
1380
mt7615_load_cr4(struct mt7615_dev * dev,const char * name)1381 static int mt7615_load_cr4(struct mt7615_dev *dev, const char *name)
1382 {
1383 const struct mt7615_fw_trailer *hdr;
1384 const struct firmware *fw;
1385 int ret;
1386
1387 ret = request_firmware(&fw, name, dev->mt76.dev);
1388 if (ret)
1389 return ret;
1390
1391 if (!fw || !fw->data || fw->size < CR4_REGION_NUM * sizeof(*hdr)) {
1392 dev_err(dev->mt76.dev, "Invalid firmware\n");
1393 ret = -EINVAL;
1394 goto out;
1395 }
1396
1397 hdr = (const struct mt7615_fw_trailer *)(fw->data + fw->size -
1398 CR4_REGION_NUM * sizeof(*hdr));
1399
1400 dev_info(dev->mt76.dev, "CR4 Firmware Version: %.10s, Build Time: %.15s\n",
1401 hdr->fw_ver, hdr->build_date);
1402
1403 ret = mt7615_mcu_send_ram_firmware(dev, hdr, fw->data, true);
1404 if (ret)
1405 goto out;
1406
1407 ret = mt76_connac_mcu_start_firmware(&dev->mt76, 0,
1408 FW_START_WORKING_PDA_CR4);
1409 if (ret) {
1410 dev_err(dev->mt76.dev, "Failed to start CR4 firmware\n");
1411 goto out;
1412 }
1413
1414 out:
1415 release_firmware(fw);
1416
1417 return ret;
1418 }
1419
mt7615_load_ram(struct mt7615_dev * dev)1420 static int mt7615_load_ram(struct mt7615_dev *dev)
1421 {
1422 int ret;
1423
1424 ret = mt7615_load_n9(dev, MT7615_FIRMWARE_N9);
1425 if (ret)
1426 return ret;
1427
1428 return mt7615_load_cr4(dev, MT7615_FIRMWARE_CR4);
1429 }
1430
mt7615_load_firmware(struct mt7615_dev * dev)1431 static int mt7615_load_firmware(struct mt7615_dev *dev)
1432 {
1433 int ret;
1434 u32 val;
1435
1436 val = mt76_get_field(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE);
1437
1438 if (val != FW_STATE_FW_DOWNLOAD) {
1439 dev_err(dev->mt76.dev, "Firmware is not ready for download\n");
1440 return -EIO;
1441 }
1442
1443 ret = mt7615_load_patch(dev, MT7615_PATCH_ADDRESS, MT7615_ROM_PATCH);
1444 if (ret)
1445 return ret;
1446
1447 ret = mt7615_load_ram(dev);
1448 if (ret)
1449 return ret;
1450
1451 if (!mt76_poll_msec(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE,
1452 FIELD_PREP(MT_TOP_MISC2_FW_STATE,
1453 FW_STATE_RDY), 500)) {
1454 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n");
1455 return -EIO;
1456 }
1457
1458 return 0;
1459 }
1460
mt7622_load_firmware(struct mt7615_dev * dev)1461 static int mt7622_load_firmware(struct mt7615_dev *dev)
1462 {
1463 int ret;
1464 u32 val;
1465
1466 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH);
1467
1468 val = mt76_get_field(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE);
1469 if (val != FW_STATE_FW_DOWNLOAD) {
1470 dev_err(dev->mt76.dev, "Firmware is not ready for download\n");
1471 return -EIO;
1472 }
1473
1474 ret = mt7615_load_patch(dev, MT7622_PATCH_ADDRESS, MT7622_ROM_PATCH);
1475 if (ret)
1476 return ret;
1477
1478 ret = mt7615_load_n9(dev, MT7622_FIRMWARE_N9);
1479 if (ret)
1480 return ret;
1481
1482 if (!mt76_poll_msec(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE,
1483 FIELD_PREP(MT_TOP_OFF_RSV_FW_STATE,
1484 FW_STATE_NORMAL_TRX), 1500)) {
1485 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n");
1486 return -EIO;
1487 }
1488
1489 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH);
1490
1491 return 0;
1492 }
1493
mt7615_mcu_fw_log_2_host(struct mt7615_dev * dev,u8 ctrl)1494 int mt7615_mcu_fw_log_2_host(struct mt7615_dev *dev, u8 ctrl)
1495 {
1496 struct {
1497 u8 ctrl_val;
1498 u8 pad[3];
1499 } data = {
1500 .ctrl_val = ctrl
1501 };
1502
1503 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(FW_LOG_2_HOST),
1504 &data, sizeof(data), true);
1505 }
1506
mt7615_mcu_cal_cache_apply(struct mt7615_dev * dev)1507 static int mt7615_mcu_cal_cache_apply(struct mt7615_dev *dev)
1508 {
1509 struct {
1510 bool cache_enable;
1511 u8 pad[3];
1512 } data = {
1513 .cache_enable = true
1514 };
1515
1516 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(CAL_CACHE), &data,
1517 sizeof(data), false);
1518 }
1519
mt7663_load_n9(struct mt7615_dev * dev,const char * name)1520 static int mt7663_load_n9(struct mt7615_dev *dev, const char *name)
1521 {
1522 u32 offset = 0, override_addr = 0, flag = FW_START_DLYCAL;
1523 const struct mt76_connac2_fw_trailer *hdr;
1524 const struct mt7663_fw_buf *buf;
1525 const struct firmware *fw;
1526 const u8 *base_addr;
1527 int i, ret;
1528
1529 ret = request_firmware(&fw, name, dev->mt76.dev);
1530 if (ret)
1531 return ret;
1532
1533 if (!fw || !fw->data || fw->size < FW_V3_COMMON_TAILER_SIZE) {
1534 dev_err(dev->mt76.dev, "Invalid firmware\n");
1535 ret = -EINVAL;
1536 goto out;
1537 }
1538
1539 hdr = (const void *)(fw->data + fw->size - FW_V3_COMMON_TAILER_SIZE);
1540 dev_info(dev->mt76.dev, "N9 Firmware Version: %.10s, Build Time: %.15s\n",
1541 hdr->fw_ver, hdr->build_date);
1542 dev_info(dev->mt76.dev, "Region number: 0x%x\n", hdr->n_region);
1543
1544 base_addr = fw->data + fw->size - FW_V3_COMMON_TAILER_SIZE;
1545 for (i = 0; i < hdr->n_region; i++) {
1546 u32 shift = (hdr->n_region - i) * FW_V3_REGION_TAILER_SIZE;
1547 u32 len, addr, mode;
1548
1549 dev_info(dev->mt76.dev, "Parsing tailer Region: %d\n", i);
1550
1551 buf = (const struct mt7663_fw_buf *)(base_addr - shift);
1552 mode = mt76_connac_mcu_gen_dl_mode(&dev->mt76,
1553 buf->feature_set, false);
1554 addr = le32_to_cpu(buf->img_dest_addr);
1555 len = le32_to_cpu(buf->img_size);
1556
1557 ret = mt76_connac_mcu_init_download(&dev->mt76, addr, len,
1558 mode);
1559 if (ret) {
1560 dev_err(dev->mt76.dev, "Download request failed\n");
1561 goto out;
1562 }
1563
1564 ret = mt76_mcu_send_firmware(&dev->mt76, MCU_CMD(FW_SCATTER),
1565 fw->data + offset, len);
1566 if (ret) {
1567 dev_err(dev->mt76.dev, "Failed to send firmware\n");
1568 goto out;
1569 }
1570
1571 offset += le32_to_cpu(buf->img_size);
1572 if (buf->feature_set & DL_MODE_VALID_RAM_ENTRY) {
1573 override_addr = le32_to_cpu(buf->img_dest_addr);
1574 dev_info(dev->mt76.dev, "Region %d, override_addr = 0x%08x\n",
1575 i, override_addr);
1576 }
1577 }
1578
1579 if (override_addr)
1580 flag |= FW_START_OVERRIDE;
1581
1582 dev_info(dev->mt76.dev, "override_addr = 0x%08x, option = %d\n",
1583 override_addr, flag);
1584
1585 ret = mt76_connac_mcu_start_firmware(&dev->mt76, override_addr, flag);
1586 if (ret) {
1587 dev_err(dev->mt76.dev, "Failed to start N9 firmware\n");
1588 goto out;
1589 }
1590
1591 snprintf(dev->mt76.hw->wiphy->fw_version,
1592 sizeof(dev->mt76.hw->wiphy->fw_version),
1593 "%.10s-%.15s", hdr->fw_ver, hdr->build_date);
1594
1595 out:
1596 release_firmware(fw);
1597
1598 return ret;
1599 }
1600
1601 static int
mt7663_load_rom_patch(struct mt7615_dev * dev,const char ** n9_firmware)1602 mt7663_load_rom_patch(struct mt7615_dev *dev, const char **n9_firmware)
1603 {
1604 const char *selected_rom, *secondary_rom = MT7663_ROM_PATCH;
1605 const char *primary_rom = MT7663_OFFLOAD_ROM_PATCH;
1606 int ret;
1607
1608 if (!prefer_offload_fw) {
1609 secondary_rom = MT7663_OFFLOAD_ROM_PATCH;
1610 primary_rom = MT7663_ROM_PATCH;
1611 }
1612 selected_rom = primary_rom;
1613
1614 ret = mt7615_load_patch(dev, MT7663_PATCH_ADDRESS, primary_rom);
1615 if (ret) {
1616 dev_info(dev->mt76.dev, "%s not found, switching to %s",
1617 primary_rom, secondary_rom);
1618 ret = mt7615_load_patch(dev, MT7663_PATCH_ADDRESS,
1619 secondary_rom);
1620 if (ret) {
1621 dev_err(dev->mt76.dev, "failed to load %s",
1622 secondary_rom);
1623 return ret;
1624 }
1625 selected_rom = secondary_rom;
1626 }
1627
1628 if (!strcmp(selected_rom, MT7663_OFFLOAD_ROM_PATCH)) {
1629 *n9_firmware = MT7663_OFFLOAD_FIRMWARE_N9;
1630 dev->fw_ver = MT7615_FIRMWARE_V3;
1631 dev->mcu_ops = &uni_update_ops;
1632 } else {
1633 *n9_firmware = MT7663_FIRMWARE_N9;
1634 dev->fw_ver = MT7615_FIRMWARE_V2;
1635 dev->mcu_ops = &sta_update_ops;
1636 }
1637
1638 return 0;
1639 }
1640
__mt7663_load_firmware(struct mt7615_dev * dev)1641 int __mt7663_load_firmware(struct mt7615_dev *dev)
1642 {
1643 const char *n9_firmware;
1644 int ret;
1645
1646 ret = mt76_get_field(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY);
1647 if (ret) {
1648 dev_dbg(dev->mt76.dev, "Firmware is already download\n");
1649 return -EIO;
1650 }
1651
1652 ret = mt7663_load_rom_patch(dev, &n9_firmware);
1653 if (ret)
1654 return ret;
1655
1656 ret = mt7663_load_n9(dev, n9_firmware);
1657 if (ret)
1658 return ret;
1659
1660 if (!mt76_poll_msec(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY,
1661 MT_TOP_MISC2_FW_N9_RDY, 1500)) {
1662 ret = mt76_get_field(dev, MT_CONN_ON_MISC,
1663 MT7663_TOP_MISC2_FW_STATE);
1664 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n");
1665 return -EIO;
1666 }
1667
1668 #ifdef CONFIG_PM
1669 if (mt7615_firmware_offload(dev))
1670 dev->mt76.hw->wiphy->wowlan = &mt76_connac_wowlan_support;
1671 #endif /* CONFIG_PM */
1672
1673 dev_dbg(dev->mt76.dev, "Firmware init done\n");
1674
1675 return 0;
1676 }
1677 EXPORT_SYMBOL_GPL(__mt7663_load_firmware);
1678
mt7663_load_firmware(struct mt7615_dev * dev)1679 static int mt7663_load_firmware(struct mt7615_dev *dev)
1680 {
1681 int ret;
1682
1683 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH);
1684
1685 ret = __mt7663_load_firmware(dev);
1686 if (ret)
1687 return ret;
1688
1689 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH);
1690
1691 return 0;
1692 }
1693
mt7615_mcu_init(struct mt7615_dev * dev)1694 int mt7615_mcu_init(struct mt7615_dev *dev)
1695 {
1696 static const struct mt76_mcu_ops mt7615_mcu_ops = {
1697 .headroom = sizeof(struct mt7615_mcu_txd),
1698 .mcu_skb_send_msg = mt7615_mcu_send_message,
1699 .mcu_parse_response = mt7615_mcu_parse_response,
1700 };
1701 int ret;
1702
1703 dev->mt76.mcu_ops = &mt7615_mcu_ops,
1704
1705 ret = mt7615_mcu_drv_pmctrl(dev);
1706 if (ret)
1707 return ret;
1708
1709 switch (mt76_chip(&dev->mt76)) {
1710 case 0x7622:
1711 ret = mt7622_load_firmware(dev);
1712 break;
1713 case 0x7663:
1714 ret = mt7663_load_firmware(dev);
1715 break;
1716 default:
1717 ret = mt7615_load_firmware(dev);
1718 break;
1719 }
1720 if (ret)
1721 return ret;
1722
1723 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_FWDL], false);
1724 dev_dbg(dev->mt76.dev, "Firmware init done\n");
1725 set_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state);
1726
1727 if (dev->dbdc_support) {
1728 ret = mt7615_mcu_cal_cache_apply(dev);
1729 if (ret)
1730 return ret;
1731 }
1732
1733 return mt7615_mcu_fw_log_2_host(dev, 0);
1734 }
1735 EXPORT_SYMBOL_GPL(mt7615_mcu_init);
1736
mt7615_mcu_exit(struct mt7615_dev * dev)1737 void mt7615_mcu_exit(struct mt7615_dev *dev)
1738 {
1739 mt7615_mcu_restart(&dev->mt76);
1740 mt7615_mcu_set_fw_ctrl(dev);
1741 skb_queue_purge(&dev->mt76.mcu.res_q);
1742 }
1743 EXPORT_SYMBOL_GPL(mt7615_mcu_exit);
1744
mt7615_mcu_set_eeprom(struct mt7615_dev * dev)1745 int mt7615_mcu_set_eeprom(struct mt7615_dev *dev)
1746 {
1747 struct {
1748 u8 buffer_mode;
1749 u8 content_format;
1750 __le16 len;
1751 } __packed req_hdr = {
1752 .buffer_mode = 1,
1753 };
1754 u8 *eep = (u8 *)dev->mt76.eeprom.data;
1755 struct sk_buff *skb;
1756 int eep_len, offset;
1757
1758 switch (mt76_chip(&dev->mt76)) {
1759 case 0x7622:
1760 eep_len = MT7622_EE_MAX - MT_EE_NIC_CONF_0;
1761 offset = MT_EE_NIC_CONF_0;
1762 break;
1763 case 0x7663:
1764 eep_len = MT7663_EE_MAX - MT_EE_CHIP_ID;
1765 req_hdr.content_format = 1;
1766 offset = MT_EE_CHIP_ID;
1767 break;
1768 default:
1769 eep_len = MT7615_EE_MAX - MT_EE_NIC_CONF_0;
1770 offset = MT_EE_NIC_CONF_0;
1771 break;
1772 }
1773
1774 req_hdr.len = cpu_to_le16(eep_len);
1775
1776 skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, sizeof(req_hdr) + eep_len);
1777 if (!skb)
1778 return -ENOMEM;
1779
1780 skb_put_data(skb, &req_hdr, sizeof(req_hdr));
1781 skb_put_data(skb, eep + offset, eep_len);
1782
1783 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
1784 MCU_EXT_CMD(EFUSE_BUFFER_MODE), true);
1785 }
1786
mt7615_mcu_set_wmm(struct mt7615_dev * dev,u8 queue,const struct ieee80211_tx_queue_params * params)1787 int mt7615_mcu_set_wmm(struct mt7615_dev *dev, u8 queue,
1788 const struct ieee80211_tx_queue_params *params)
1789 {
1790 #define WMM_AIFS_SET BIT(0)
1791 #define WMM_CW_MIN_SET BIT(1)
1792 #define WMM_CW_MAX_SET BIT(2)
1793 #define WMM_TXOP_SET BIT(3)
1794 #define WMM_PARAM_SET (WMM_AIFS_SET | WMM_CW_MIN_SET | \
1795 WMM_CW_MAX_SET | WMM_TXOP_SET)
1796 struct req_data {
1797 u8 number;
1798 u8 rsv[3];
1799 u8 queue;
1800 u8 valid;
1801 u8 aifs;
1802 u8 cw_min;
1803 __le16 cw_max;
1804 __le16 txop;
1805 } __packed req = {
1806 .number = 1,
1807 .queue = queue,
1808 .valid = WMM_PARAM_SET,
1809 .aifs = params->aifs,
1810 .cw_min = 5,
1811 .cw_max = cpu_to_le16(10),
1812 .txop = cpu_to_le16(params->txop),
1813 };
1814
1815 if (params->cw_min)
1816 req.cw_min = fls(params->cw_min);
1817 if (params->cw_max)
1818 req.cw_max = cpu_to_le16(fls(params->cw_max));
1819
1820 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(EDCA_UPDATE),
1821 &req, sizeof(req), true);
1822 }
1823
mt7615_mcu_set_dbdc(struct mt7615_dev * dev)1824 int mt7615_mcu_set_dbdc(struct mt7615_dev *dev)
1825 {
1826 struct mt7615_phy *ext_phy = mt7615_ext_phy(dev);
1827 struct dbdc_entry {
1828 u8 type;
1829 u8 index;
1830 u8 band;
1831 u8 _rsv;
1832 };
1833 struct {
1834 u8 enable;
1835 u8 num;
1836 u8 _rsv[2];
1837 struct dbdc_entry entry[64];
1838 } req = {
1839 .enable = !!ext_phy,
1840 };
1841 int i;
1842
1843 if (!ext_phy)
1844 goto out;
1845
1846 #define ADD_DBDC_ENTRY(_type, _idx, _band) \
1847 do { \
1848 req.entry[req.num].type = _type; \
1849 req.entry[req.num].index = _idx; \
1850 req.entry[req.num++].band = _band; \
1851 } while (0)
1852
1853 for (i = 0; i < 4; i++) {
1854 bool band = !!(ext_phy->omac_mask & BIT_ULL(i));
1855
1856 ADD_DBDC_ENTRY(DBDC_TYPE_BSS, i, band);
1857 }
1858
1859 for (i = 0; i < 14; i++) {
1860 bool band = !!(ext_phy->omac_mask & BIT_ULL(0x11 + i));
1861
1862 ADD_DBDC_ENTRY(DBDC_TYPE_MBSS, i, band);
1863 }
1864
1865 ADD_DBDC_ENTRY(DBDC_TYPE_MU, 0, 1);
1866
1867 for (i = 0; i < 3; i++)
1868 ADD_DBDC_ENTRY(DBDC_TYPE_BF, i, 1);
1869
1870 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 0, 0);
1871 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 1, 0);
1872 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 2, 1);
1873 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 3, 1);
1874
1875 ADD_DBDC_ENTRY(DBDC_TYPE_MGMT, 0, 0);
1876 ADD_DBDC_ENTRY(DBDC_TYPE_MGMT, 1, 1);
1877
1878 out:
1879 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(DBDC_CTRL), &req,
1880 sizeof(req), true);
1881 }
1882
mt7615_mcu_del_wtbl_all(struct mt7615_dev * dev)1883 int mt7615_mcu_del_wtbl_all(struct mt7615_dev *dev)
1884 {
1885 struct wtbl_req_hdr req = {
1886 .operation = WTBL_RESET_ALL,
1887 };
1888
1889 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(WTBL_UPDATE),
1890 &req, sizeof(req), true);
1891 }
1892
mt7615_mcu_set_fcc5_lpn(struct mt7615_dev * dev,int val)1893 int mt7615_mcu_set_fcc5_lpn(struct mt7615_dev *dev, int val)
1894 {
1895 struct {
1896 __le16 tag;
1897 __le16 min_lpn;
1898 } req = {
1899 .tag = cpu_to_le16(0x1),
1900 .min_lpn = cpu_to_le16(val),
1901 };
1902
1903 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RADAR_TH),
1904 &req, sizeof(req), true);
1905 }
1906
mt7615_mcu_set_pulse_th(struct mt7615_dev * dev,const struct mt7615_dfs_pulse * pulse)1907 int mt7615_mcu_set_pulse_th(struct mt7615_dev *dev,
1908 const struct mt7615_dfs_pulse *pulse)
1909 {
1910 struct {
1911 __le16 tag;
1912 __le32 max_width; /* us */
1913 __le32 max_pwr; /* dbm */
1914 __le32 min_pwr; /* dbm */
1915 __le32 min_stgr_pri; /* us */
1916 __le32 max_stgr_pri; /* us */
1917 __le32 min_cr_pri; /* us */
1918 __le32 max_cr_pri; /* us */
1919 } req = {
1920 .tag = cpu_to_le16(0x3),
1921 #define __req_field(field) .field = cpu_to_le32(pulse->field)
1922 __req_field(max_width),
1923 __req_field(max_pwr),
1924 __req_field(min_pwr),
1925 __req_field(min_stgr_pri),
1926 __req_field(max_stgr_pri),
1927 __req_field(min_cr_pri),
1928 __req_field(max_cr_pri),
1929 #undef __req_field
1930 };
1931
1932 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RADAR_TH),
1933 &req, sizeof(req), true);
1934 }
1935
mt7615_mcu_set_radar_th(struct mt7615_dev * dev,int index,const struct mt7615_dfs_pattern * pattern)1936 int mt7615_mcu_set_radar_th(struct mt7615_dev *dev, int index,
1937 const struct mt7615_dfs_pattern *pattern)
1938 {
1939 struct {
1940 __le16 tag;
1941 __le16 radar_type;
1942 u8 enb;
1943 u8 stgr;
1944 u8 min_crpn;
1945 u8 max_crpn;
1946 u8 min_crpr;
1947 u8 min_pw;
1948 u8 max_pw;
1949 __le32 min_pri;
1950 __le32 max_pri;
1951 u8 min_crbn;
1952 u8 max_crbn;
1953 u8 min_stgpn;
1954 u8 max_stgpn;
1955 u8 min_stgpr;
1956 } req = {
1957 .tag = cpu_to_le16(0x2),
1958 .radar_type = cpu_to_le16(index),
1959 #define __req_field_u8(field) .field = pattern->field
1960 #define __req_field_u32(field) .field = cpu_to_le32(pattern->field)
1961 __req_field_u8(enb),
1962 __req_field_u8(stgr),
1963 __req_field_u8(min_crpn),
1964 __req_field_u8(max_crpn),
1965 __req_field_u8(min_crpr),
1966 __req_field_u8(min_pw),
1967 __req_field_u8(max_pw),
1968 __req_field_u32(min_pri),
1969 __req_field_u32(max_pri),
1970 __req_field_u8(min_crbn),
1971 __req_field_u8(max_crbn),
1972 __req_field_u8(min_stgpn),
1973 __req_field_u8(max_stgpn),
1974 __req_field_u8(min_stgpr),
1975 #undef __req_field_u8
1976 #undef __req_field_u32
1977 };
1978
1979 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RADAR_TH),
1980 &req, sizeof(req), true);
1981 }
1982
mt7615_mcu_rdd_send_pattern(struct mt7615_dev * dev)1983 int mt7615_mcu_rdd_send_pattern(struct mt7615_dev *dev)
1984 {
1985 struct {
1986 u8 pulse_num;
1987 u8 rsv[3];
1988 struct {
1989 __le32 start_time;
1990 __le16 width;
1991 __le16 power;
1992 } pattern[32];
1993 } req = {
1994 .pulse_num = dev->radar_pattern.n_pulses,
1995 };
1996 u32 start_time = ktime_to_ms(ktime_get_boottime());
1997 int i;
1998
1999 if (dev->radar_pattern.n_pulses > ARRAY_SIZE(req.pattern))
2000 return -EINVAL;
2001
2002 /* TODO: add some noise here */
2003 for (i = 0; i < dev->radar_pattern.n_pulses; i++) {
2004 u32 ts = start_time + i * dev->radar_pattern.period;
2005
2006 req.pattern[i].width = cpu_to_le16(dev->radar_pattern.width);
2007 req.pattern[i].power = cpu_to_le16(dev->radar_pattern.power);
2008 req.pattern[i].start_time = cpu_to_le32(ts);
2009 }
2010
2011 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RDD_PATTERN),
2012 &req, sizeof(req), false);
2013 }
2014
mt7615_mcu_set_txpower_sku(struct mt7615_phy * phy,u8 * sku)2015 static void mt7615_mcu_set_txpower_sku(struct mt7615_phy *phy, u8 *sku)
2016 {
2017 struct mt76_phy *mphy = phy->mt76;
2018 struct ieee80211_hw *hw = mphy->hw;
2019 struct mt76_power_limits limits;
2020 s8 *limits_array = (s8 *)&limits;
2021 int n_chains = hweight8(mphy->antenna_mask);
2022 int tx_power = hw->conf.power_level * 2;
2023 int i;
2024 static const u8 sku_mapping[] = {
2025 #define SKU_FIELD(_type, _field) \
2026 [MT_SKU_##_type] = offsetof(struct mt76_power_limits, _field)
2027 SKU_FIELD(CCK_1_2, cck[0]),
2028 SKU_FIELD(CCK_55_11, cck[2]),
2029 SKU_FIELD(OFDM_6_9, ofdm[0]),
2030 SKU_FIELD(OFDM_12_18, ofdm[2]),
2031 SKU_FIELD(OFDM_24_36, ofdm[4]),
2032 SKU_FIELD(OFDM_48, ofdm[6]),
2033 SKU_FIELD(OFDM_54, ofdm[7]),
2034 SKU_FIELD(HT20_0_8, mcs[0][0]),
2035 SKU_FIELD(HT20_32, ofdm[0]),
2036 SKU_FIELD(HT20_1_2_9_10, mcs[0][1]),
2037 SKU_FIELD(HT20_3_4_11_12, mcs[0][3]),
2038 SKU_FIELD(HT20_5_13, mcs[0][5]),
2039 SKU_FIELD(HT20_6_14, mcs[0][6]),
2040 SKU_FIELD(HT20_7_15, mcs[0][7]),
2041 SKU_FIELD(HT40_0_8, mcs[1][0]),
2042 SKU_FIELD(HT40_32, ofdm[0]),
2043 SKU_FIELD(HT40_1_2_9_10, mcs[1][1]),
2044 SKU_FIELD(HT40_3_4_11_12, mcs[1][3]),
2045 SKU_FIELD(HT40_5_13, mcs[1][5]),
2046 SKU_FIELD(HT40_6_14, mcs[1][6]),
2047 SKU_FIELD(HT40_7_15, mcs[1][7]),
2048 SKU_FIELD(VHT20_0, mcs[0][0]),
2049 SKU_FIELD(VHT20_1_2, mcs[0][1]),
2050 SKU_FIELD(VHT20_3_4, mcs[0][3]),
2051 SKU_FIELD(VHT20_5_6, mcs[0][5]),
2052 SKU_FIELD(VHT20_7, mcs[0][7]),
2053 SKU_FIELD(VHT20_8, mcs[0][8]),
2054 SKU_FIELD(VHT20_9, mcs[0][9]),
2055 SKU_FIELD(VHT40_0, mcs[1][0]),
2056 SKU_FIELD(VHT40_1_2, mcs[1][1]),
2057 SKU_FIELD(VHT40_3_4, mcs[1][3]),
2058 SKU_FIELD(VHT40_5_6, mcs[1][5]),
2059 SKU_FIELD(VHT40_7, mcs[1][7]),
2060 SKU_FIELD(VHT40_8, mcs[1][8]),
2061 SKU_FIELD(VHT40_9, mcs[1][9]),
2062 SKU_FIELD(VHT80_0, mcs[2][0]),
2063 SKU_FIELD(VHT80_1_2, mcs[2][1]),
2064 SKU_FIELD(VHT80_3_4, mcs[2][3]),
2065 SKU_FIELD(VHT80_5_6, mcs[2][5]),
2066 SKU_FIELD(VHT80_7, mcs[2][7]),
2067 SKU_FIELD(VHT80_8, mcs[2][8]),
2068 SKU_FIELD(VHT80_9, mcs[2][9]),
2069 SKU_FIELD(VHT160_0, mcs[3][0]),
2070 SKU_FIELD(VHT160_1_2, mcs[3][1]),
2071 SKU_FIELD(VHT160_3_4, mcs[3][3]),
2072 SKU_FIELD(VHT160_5_6, mcs[3][5]),
2073 SKU_FIELD(VHT160_7, mcs[3][7]),
2074 SKU_FIELD(VHT160_8, mcs[3][8]),
2075 SKU_FIELD(VHT160_9, mcs[3][9]),
2076 #undef SKU_FIELD
2077 };
2078
2079 tx_power = mt76_get_sar_power(mphy, mphy->chandef.chan, tx_power);
2080 tx_power -= mt76_tx_power_nss_delta(n_chains);
2081 tx_power = mt76_get_rate_power_limits(mphy, mphy->chandef.chan,
2082 &limits, tx_power);
2083 mphy->txpower_cur = tx_power;
2084
2085 if (is_mt7663(mphy->dev)) {
2086 memset(sku, tx_power, MT_SKU_4SS_DELTA + 1);
2087 return;
2088 }
2089
2090 for (i = 0; i < MT_SKU_1SS_DELTA; i++)
2091 sku[i] = limits_array[sku_mapping[i]];
2092
2093 for (i = 0; i < 4; i++) {
2094 int delta = 0;
2095
2096 if (i < n_chains - 1)
2097 delta = mt76_tx_power_nss_delta(n_chains) -
2098 mt76_tx_power_nss_delta(i + 1);
2099 sku[MT_SKU_1SS_DELTA + i] = delta;
2100 }
2101 }
2102
mt7615_mcu_chan_bw(struct cfg80211_chan_def * chandef)2103 static u8 mt7615_mcu_chan_bw(struct cfg80211_chan_def *chandef)
2104 {
2105 static const u8 width_to_bw[] = {
2106 [NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ,
2107 [NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ,
2108 [NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ,
2109 [NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ,
2110 [NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ,
2111 [NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ,
2112 [NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ,
2113 [NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ,
2114 };
2115
2116 if (chandef->width >= ARRAY_SIZE(width_to_bw))
2117 return 0;
2118
2119 return width_to_bw[chandef->width];
2120 }
2121
mt7615_mcu_set_chan_info(struct mt7615_phy * phy,int cmd)2122 int mt7615_mcu_set_chan_info(struct mt7615_phy *phy, int cmd)
2123 {
2124 struct mt7615_dev *dev = phy->dev;
2125 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2126 int freq1 = chandef->center_freq1, freq2 = chandef->center_freq2;
2127 struct {
2128 u8 control_chan;
2129 u8 center_chan;
2130 u8 bw;
2131 u8 tx_streams;
2132 u8 rx_streams_mask;
2133 u8 switch_reason;
2134 u8 band_idx;
2135 /* for 80+80 only */
2136 u8 center_chan2;
2137 __le16 cac_case;
2138 u8 channel_band;
2139 u8 rsv0;
2140 __le32 outband_freq;
2141 u8 txpower_drop;
2142 u8 rsv1[3];
2143 u8 txpower_sku[53];
2144 u8 rsv2[3];
2145 } req = {
2146 .control_chan = chandef->chan->hw_value,
2147 .center_chan = ieee80211_frequency_to_channel(freq1),
2148 .tx_streams = hweight8(phy->mt76->antenna_mask),
2149 .rx_streams_mask = phy->mt76->chainmask,
2150 .center_chan2 = ieee80211_frequency_to_channel(freq2),
2151 };
2152
2153 if (cmd == MCU_EXT_CMD(SET_RX_PATH) ||
2154 dev->mt76.hw->conf.flags & IEEE80211_CONF_MONITOR)
2155 req.switch_reason = CH_SWITCH_NORMAL;
2156 else if (phy->mt76->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
2157 req.switch_reason = CH_SWITCH_SCAN_BYPASS_DPD;
2158 else if (!cfg80211_reg_can_beacon(phy->mt76->hw->wiphy, chandef,
2159 NL80211_IFTYPE_AP))
2160 req.switch_reason = CH_SWITCH_DFS;
2161 else
2162 req.switch_reason = CH_SWITCH_NORMAL;
2163
2164 req.band_idx = phy != &dev->phy;
2165 req.bw = mt7615_mcu_chan_bw(chandef);
2166
2167 if (mt76_testmode_enabled(phy->mt76))
2168 memset(req.txpower_sku, 0x3f, 49);
2169 else
2170 mt7615_mcu_set_txpower_sku(phy, req.txpower_sku);
2171
2172 return mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), true);
2173 }
2174
mt7615_mcu_get_temperature(struct mt7615_dev * dev)2175 int mt7615_mcu_get_temperature(struct mt7615_dev *dev)
2176 {
2177 struct {
2178 u8 action;
2179 u8 rsv[3];
2180 } req = {};
2181
2182 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(THERMAL_CTRL),
2183 &req, sizeof(req), true);
2184 }
2185
mt7615_mcu_set_test_param(struct mt7615_dev * dev,u8 param,bool test_mode,u32 val)2186 int mt7615_mcu_set_test_param(struct mt7615_dev *dev, u8 param, bool test_mode,
2187 u32 val)
2188 {
2189 struct {
2190 u8 test_mode_en;
2191 u8 param_idx;
2192 u8 _rsv[2];
2193
2194 __le32 value;
2195
2196 u8 pad[8];
2197 } req = {
2198 .test_mode_en = test_mode,
2199 .param_idx = param,
2200 .value = cpu_to_le32(val),
2201 };
2202
2203 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL),
2204 &req, sizeof(req), false);
2205 }
2206
mt7615_mcu_set_sku_en(struct mt7615_phy * phy,bool enable)2207 int mt7615_mcu_set_sku_en(struct mt7615_phy *phy, bool enable)
2208 {
2209 struct mt7615_dev *dev = phy->dev;
2210 struct {
2211 u8 format_id;
2212 u8 sku_enable;
2213 u8 band_idx;
2214 u8 rsv;
2215 } req = {
2216 .format_id = 0,
2217 .band_idx = phy != &dev->phy,
2218 .sku_enable = enable,
2219 };
2220
2221 return mt76_mcu_send_msg(&dev->mt76,
2222 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL),
2223 &req, sizeof(req), true);
2224 }
2225
mt7615_find_freq_idx(const u16 * freqs,int n_freqs,u16 cur)2226 static int mt7615_find_freq_idx(const u16 *freqs, int n_freqs, u16 cur)
2227 {
2228 int i;
2229
2230 for (i = 0; i < n_freqs; i++)
2231 if (cur == freqs[i])
2232 return i;
2233
2234 return -1;
2235 }
2236
mt7615_dcoc_freq_idx(u16 freq,u8 bw)2237 static int mt7615_dcoc_freq_idx(u16 freq, u8 bw)
2238 {
2239 static const u16 freq_list[] = {
2240 4980, 5805, 5905, 5190,
2241 5230, 5270, 5310, 5350,
2242 5390, 5430, 5470, 5510,
2243 5550, 5590, 5630, 5670,
2244 5710, 5755, 5795, 5835,
2245 5875, 5210, 5290, 5370,
2246 5450, 5530, 5610, 5690,
2247 5775, 5855
2248 };
2249 static const u16 freq_bw40[] = {
2250 5190, 5230, 5270, 5310,
2251 5350, 5390, 5430, 5470,
2252 5510, 5550, 5590, 5630,
2253 5670, 5710, 5755, 5795,
2254 5835, 5875
2255 };
2256 int offset_2g = ARRAY_SIZE(freq_list);
2257 int idx;
2258
2259 if (freq < 4000) {
2260 if (freq < 2427)
2261 return offset_2g;
2262 if (freq < 2442)
2263 return offset_2g + 1;
2264 if (freq < 2457)
2265 return offset_2g + 2;
2266
2267 return offset_2g + 3;
2268 }
2269
2270 switch (bw) {
2271 case NL80211_CHAN_WIDTH_80:
2272 case NL80211_CHAN_WIDTH_80P80:
2273 case NL80211_CHAN_WIDTH_160:
2274 break;
2275 default:
2276 idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40),
2277 freq + 10);
2278 if (idx >= 0) {
2279 freq = freq_bw40[idx];
2280 break;
2281 }
2282
2283 idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40),
2284 freq - 10);
2285 if (idx >= 0) {
2286 freq = freq_bw40[idx];
2287 break;
2288 }
2289 fallthrough;
2290 case NL80211_CHAN_WIDTH_40:
2291 idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40),
2292 freq);
2293 if (idx >= 0)
2294 break;
2295
2296 return -1;
2297
2298 }
2299
2300 return mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), freq);
2301 }
2302
mt7615_mcu_apply_rx_dcoc(struct mt7615_phy * phy)2303 int mt7615_mcu_apply_rx_dcoc(struct mt7615_phy *phy)
2304 {
2305 struct mt7615_dev *dev = phy->dev;
2306 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2307 int freq2 = chandef->center_freq2;
2308 int ret;
2309 struct {
2310 u8 direction;
2311 u8 runtime_calibration;
2312 u8 _rsv[2];
2313
2314 __le16 center_freq;
2315 u8 bw;
2316 u8 band;
2317 u8 is_freq2;
2318 u8 success;
2319 u8 dbdc_en;
2320
2321 u8 _rsv2;
2322
2323 struct {
2324 __le32 sx0_i_lna[4];
2325 __le32 sx0_q_lna[4];
2326
2327 __le32 sx2_i_lna[4];
2328 __le32 sx2_q_lna[4];
2329 } dcoc_data[4];
2330 } req = {
2331 .direction = 1,
2332
2333 .bw = mt7615_mcu_chan_bw(chandef),
2334 .band = chandef->center_freq1 > 4000,
2335 .dbdc_en = !!dev->mt76.phys[MT_BAND1],
2336 };
2337 u16 center_freq = chandef->center_freq1;
2338 int freq_idx;
2339 u8 *eep = dev->mt76.eeprom.data;
2340
2341 if (!(eep[MT_EE_CALDATA_FLASH] & MT_EE_CALDATA_FLASH_RX_CAL))
2342 return 0;
2343
2344 if (chandef->width == NL80211_CHAN_WIDTH_160) {
2345 freq2 = center_freq + 40;
2346 center_freq -= 40;
2347 }
2348
2349 again:
2350 req.runtime_calibration = 1;
2351 freq_idx = mt7615_dcoc_freq_idx(center_freq, chandef->width);
2352 if (freq_idx < 0)
2353 goto out;
2354
2355 memcpy(req.dcoc_data, eep + MT7615_EEPROM_DCOC_OFFSET +
2356 freq_idx * MT7615_EEPROM_DCOC_SIZE,
2357 sizeof(req.dcoc_data));
2358 req.runtime_calibration = 0;
2359
2360 out:
2361 req.center_freq = cpu_to_le16(center_freq);
2362 ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RXDCOC_CAL), &req,
2363 sizeof(req), true);
2364
2365 if ((chandef->width == NL80211_CHAN_WIDTH_80P80 ||
2366 chandef->width == NL80211_CHAN_WIDTH_160) && !req.is_freq2) {
2367 req.is_freq2 = true;
2368 center_freq = freq2;
2369 goto again;
2370 }
2371
2372 return ret;
2373 }
2374
mt7615_dpd_freq_idx(u16 freq,u8 bw)2375 static int mt7615_dpd_freq_idx(u16 freq, u8 bw)
2376 {
2377 static const u16 freq_list[] = {
2378 4920, 4940, 4960, 4980,
2379 5040, 5060, 5080, 5180,
2380 5200, 5220, 5240, 5260,
2381 5280, 5300, 5320, 5340,
2382 5360, 5380, 5400, 5420,
2383 5440, 5460, 5480, 5500,
2384 5520, 5540, 5560, 5580,
2385 5600, 5620, 5640, 5660,
2386 5680, 5700, 5720, 5745,
2387 5765, 5785, 5805, 5825,
2388 5845, 5865, 5885, 5905
2389 };
2390 int offset_2g = ARRAY_SIZE(freq_list);
2391 int idx;
2392
2393 if (freq < 4000) {
2394 if (freq < 2432)
2395 return offset_2g;
2396 if (freq < 2457)
2397 return offset_2g + 1;
2398
2399 return offset_2g + 2;
2400 }
2401
2402 if (bw != NL80211_CHAN_WIDTH_20) {
2403 idx = mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list),
2404 freq + 10);
2405 if (idx >= 0)
2406 return idx;
2407
2408 idx = mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list),
2409 freq - 10);
2410 if (idx >= 0)
2411 return idx;
2412 }
2413
2414 return mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), freq);
2415 }
2416
2417
mt7615_mcu_apply_tx_dpd(struct mt7615_phy * phy)2418 int mt7615_mcu_apply_tx_dpd(struct mt7615_phy *phy)
2419 {
2420 struct mt7615_dev *dev = phy->dev;
2421 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2422 int freq2 = chandef->center_freq2;
2423 int ret;
2424 struct {
2425 u8 direction;
2426 u8 runtime_calibration;
2427 u8 _rsv[2];
2428
2429 __le16 center_freq;
2430 u8 bw;
2431 u8 band;
2432 u8 is_freq2;
2433 u8 success;
2434 u8 dbdc_en;
2435
2436 u8 _rsv2;
2437
2438 struct {
2439 struct {
2440 u32 dpd_g0;
2441 u8 data[32];
2442 } wf0, wf1;
2443
2444 struct {
2445 u32 dpd_g0_prim;
2446 u32 dpd_g0_sec;
2447 u8 data_prim[32];
2448 u8 data_sec[32];
2449 } wf2, wf3;
2450 } dpd_data;
2451 } req = {
2452 .direction = 1,
2453
2454 .bw = mt7615_mcu_chan_bw(chandef),
2455 .band = chandef->center_freq1 > 4000,
2456 .dbdc_en = !!dev->mt76.phys[MT_BAND1],
2457 };
2458 u16 center_freq = chandef->center_freq1;
2459 int freq_idx;
2460 u8 *eep = dev->mt76.eeprom.data;
2461
2462 if (!(eep[MT_EE_CALDATA_FLASH] & MT_EE_CALDATA_FLASH_TX_DPD))
2463 return 0;
2464
2465 if (chandef->width == NL80211_CHAN_WIDTH_160) {
2466 freq2 = center_freq + 40;
2467 center_freq -= 40;
2468 }
2469
2470 again:
2471 req.runtime_calibration = 1;
2472 freq_idx = mt7615_dpd_freq_idx(center_freq, chandef->width);
2473 if (freq_idx < 0)
2474 goto out;
2475
2476 memcpy(&req.dpd_data, eep + MT7615_EEPROM_TXDPD_OFFSET +
2477 freq_idx * MT7615_EEPROM_TXDPD_SIZE,
2478 sizeof(req.dpd_data));
2479 req.runtime_calibration = 0;
2480
2481 out:
2482 req.center_freq = cpu_to_le16(center_freq);
2483 ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXDPD_CAL),
2484 &req, sizeof(req), true);
2485
2486 if ((chandef->width == NL80211_CHAN_WIDTH_80P80 ||
2487 chandef->width == NL80211_CHAN_WIDTH_160) && !req.is_freq2) {
2488 req.is_freq2 = true;
2489 center_freq = freq2;
2490 goto again;
2491 }
2492
2493 return ret;
2494 }
2495
mt7615_mcu_set_rx_hdr_trans_blacklist(struct mt7615_dev * dev)2496 int mt7615_mcu_set_rx_hdr_trans_blacklist(struct mt7615_dev *dev)
2497 {
2498 struct {
2499 u8 operation;
2500 u8 count;
2501 u8 _rsv[2];
2502 u8 index;
2503 u8 enable;
2504 __le16 etype;
2505 } req = {
2506 .operation = 1,
2507 .count = 1,
2508 .enable = 1,
2509 .etype = cpu_to_le16(ETH_P_PAE),
2510 };
2511
2512 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RX_HDR_TRANS),
2513 &req, sizeof(req), false);
2514 }
2515
mt7615_mcu_set_bss_pm(struct mt7615_dev * dev,struct ieee80211_vif * vif,bool enable)2516 int mt7615_mcu_set_bss_pm(struct mt7615_dev *dev, struct ieee80211_vif *vif,
2517 bool enable)
2518 {
2519 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
2520 struct {
2521 u8 bss_idx;
2522 u8 dtim_period;
2523 __le16 aid;
2524 __le16 bcn_interval;
2525 __le16 atim_window;
2526 u8 uapsd;
2527 u8 bmc_delivered_ac;
2528 u8 bmc_triggered_ac;
2529 u8 pad;
2530 } req = {
2531 .bss_idx = mvif->mt76.idx,
2532 .aid = cpu_to_le16(vif->cfg.aid),
2533 .dtim_period = vif->bss_conf.dtim_period,
2534 .bcn_interval = cpu_to_le16(vif->bss_conf.beacon_int),
2535 };
2536 struct {
2537 u8 bss_idx;
2538 u8 pad[3];
2539 } req_hdr = {
2540 .bss_idx = mvif->mt76.idx,
2541 };
2542 int err;
2543
2544 if (vif->type != NL80211_IFTYPE_STATION)
2545 return 0;
2546
2547 err = mt76_mcu_send_msg(&dev->mt76, MCU_CE_CMD(SET_BSS_ABORT),
2548 &req_hdr, sizeof(req_hdr), false);
2549 if (err < 0 || !enable)
2550 return err;
2551
2552 return mt76_mcu_send_msg(&dev->mt76, MCU_CE_CMD(SET_BSS_CONNECTED),
2553 &req, sizeof(req), false);
2554 }
2555
mt7615_mcu_set_roc(struct mt7615_phy * phy,struct ieee80211_vif * vif,struct ieee80211_channel * chan,int duration)2556 int mt7615_mcu_set_roc(struct mt7615_phy *phy, struct ieee80211_vif *vif,
2557 struct ieee80211_channel *chan, int duration)
2558 {
2559 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
2560 struct mt7615_dev *dev = phy->dev;
2561 struct mt7615_roc_tlv req = {
2562 .bss_idx = mvif->mt76.idx,
2563 .active = !chan,
2564 .max_interval = cpu_to_le32(duration),
2565 .primary_chan = chan ? chan->hw_value : 0,
2566 .band = chan ? chan->band : 0,
2567 .req_type = 2,
2568 };
2569
2570 phy->roc_grant = false;
2571
2572 return mt76_mcu_send_msg(&dev->mt76, MCU_CE_CMD(SET_ROC),
2573 &req, sizeof(req), false);
2574 }
2575