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Searched defs:N0 (Results 1 – 25 of 33) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1003 SDValue N0, N1, N2; in isOneUseSetCC() local
1075 SDValue N0, in reassociationCanBreakAddressingModePattern()
1194 SDValue N0, SDValue N1, in reassociateOpsCommutative()
1293 SDValue DAGCombiner::reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0, in reassociateOps()
1314 const SDLoc &DL, EVT VT, SDValue N0, in reassociateReduction()
1522 SDValue N0 = Op.getOperand(0); in PromoteIntBinOp() local
1590 SDValue N0 = Op.getOperand(0); in PromoteIntShiftOp() local
2054 SDValue N0 = N->getOperand(0); in combine() local
2387 SDValue N0 = N->getOperand(0); in foldSelectWithIdentityConstant() local
2565 SDValue N0 = N->getOperand(0); in foldSubToAvg() local
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H A DTargetLowering.cpp752 SDValue N0 = Op.getOperand(0); in SimplifyMultipleUseDemandedBits() local
3229 SDValue N0 = Op.getOperand(0); in SimplifyDemandedVectorElts() local
3818 TargetLowering::buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0, in buildLegalVectorShuffle()
3976 SDValue TargetLowering::foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, in foldSetCCWithAnd()
4080 EVT SCCVT, SDValue N0, SDValue N1, ISD::CondCode Cond, DAGCombinerInfo &DCI, in optimizeSetCCOfSignedTruncationCheck()
4164 EVT SCCVT, SDValue N0, SDValue N1C, ISD::CondCode Cond, in optimizeSetCCByHoistingAndByConstFromLogicalShift()
4235 SDValue TargetLowering::foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, in foldSetCCWithBinOp()
4274 SDValue N0, const APInt &C1, in simplifySetCCWithCTPOP()
4347 static SDValue foldSetCCWithRotate(EVT VT, SDValue N0, SDValue N1, in foldSetCCWithRotate()
4390 static SDValue foldSetCCWithFunnelShift(EVT VT, SDValue N0, SDValue N1, in foldSetCCWithFunnelShift()
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H A DSelectionDAG.cpp3349 SDValue N0 = Op.getOperand(0); in computeKnownBits() local
3360 SDValue N0 = Op.getOperand(0); in computeKnownBits() local
4235 SelectionDAG::computeOverflowForSignedAdd(SDValue N0, SDValue N1) const { in computeOverflowForSignedAdd()
4250 SelectionDAG::computeOverflowForUnsignedAdd(SDValue N0, SDValue N1) const { in computeOverflowForUnsignedAdd()
4273 SelectionDAG::computeOverflowForSignedSub(SDValue N0, SDValue N1) const { in computeOverflowForSignedSub()
4291 SelectionDAG::computeOverflowForUnsignedSub(SDValue N0, SDValue N1) const { in computeOverflowForUnsignedSub()
4304 SelectionDAG::computeOverflowForUnsignedMul(SDValue N0, SDValue N1) const { in computeOverflowForUnsignedMul()
4317 SelectionDAG::computeOverflowForSignedMul(SDValue N0, SDValue N1) const { in computeOverflowForSignedMul()
4546 SDValue N0 = Op.getOperand(0); in ComputeNumSignBits() local
11173 SDValue N0 = N.getOperand(0); in salvageDebugInfo() local
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H A DInstrEmitter.cpp578 SDValue N0 = Node->getOperand(0); in EmitSubregNode() local
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp613 SDValue N0 = Node->getOperand(0); in tryShrinkShlLogicImm() local
691 SDValue N0 = Node->getOperand(0); in trySignedBitfieldExtract() local
696 MVT VT) { in trySignedBitfieldExtract()
1076 SDValue N0 = Node->getOperand(0); in Select() local
1106 SDValue N0 = Node->getOperand(0); in Select() local
1190 SDValue N0 = Node->getOperand(0); in Select() local
1223 SDValue N0 = Node->getOperand(0); in Select() local
1469 SDValue N0 = Node->getOperand(0); in Select() local
2893 SDValue N0 = N.getOperand(0); in selectSExtBits() local
2935 SDValue N0 = N.getOperand(0); in selectSHXADDOp() local
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H A DRISCVISelLowering.cpp13158 SDValue N0 = N->getOperand(0); transformAddShlImm() local
13269 SDValue N0 = N->getOperand(0); combineSelectAndUseCommutative() local
13303 SDValue N0 = N->getOperand(0); transformAddImmMulImm() local
13362 SDValue N0 = N->getOperand(0); combineBinOpOfZExt() local
13399 SDValue N0 = N->getOperand(0); combineAddOfBooleanXor() local
13447 SDValue N0 = N->getOperand(0); combineSubOfBoolean() local
13498 SDValue N0 = N->getOperand(0); combineSubShiftToOrcB() local
13521 SDValue N0 = N->getOperand(0); performSUBCombine() local
13549 SDValue N0 = N->getOperand(0); combineDeMorganOfBoolean() local
13600 SDValue N0 = N->getOperand(0); combineTruncSelectToSMaxUSat() local
13664 SDValue N0 = N->getOperand(0); performTRUNCATECombine() local
13693 SDValue N0 = N->getOperand(0); performANDCombine() local
13728 combineOrOfCZERO(SDNode * N,SDValue N0,SDValue N1,SelectionDAG & DAG) combineOrOfCZERO() argument
13777 SDValue N0 = N->getOperand(0); performORCombine() local
13791 SDValue N0 = N->getOperand(0); performXORCombine() local
14059 SDValue N0 = N->getOperand(0); performMULCombine() local
14135 SDValue N0 = N.getOperand(0); narrowIndex() local
14173 SDValue N0 = N->getOperand(0); performSETCCCombine() local
15614 SDValue N0 = N->getOperand(0); performSRACombine() local
16499 SDValue N0 = Op.getOperand(0); combineTruncOfSraSext() local
16788 SDValue N0 = N->getOperand(0); PerformDAGCombine() local
17608 SDValue N0 = N->getOperand(0); PerformDAGCombine() local
17661 SDValue N0 = N->getOperand(0); isDesirableToCommuteWithShift() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.h288 Register N0, N2, N3; member
H A DAMDGPUISelDAGToDAG.cpp732 SDValue &N0, SDValue &N1) { in getBaseWithOffsetUsingSplitOR()
1085 SDValue N0 = Addr.getOperand(0); in SelectDS1Addr1Offset() local
1264 SDValue N0 = Addr.getOperand(0); in SelectDSReadWrite2() local
1357 SDValue N0 = Addr; in SelectMUBUF() local
1500 SDValue N0 = Addr.getOperand(0); in SelectMUBUFScratchOffen() local
1651 SDValue N0, N1; in SelectFlatOffsetImpl() local
2145 SDValue N0, N1; in SelectSMRDBaseOffset() local
2237 SDValue N0 = Index.getOperand(0); in SelectMOVRELOffset() local
H A DAMDGPUISelLowering.cpp3523 SDValue N0 = Op.getOperand(0); in LowerFP_TO_FP16() local
3910 SDValue N0 = N->getOperand(0); in performAssertSZExtCombine() local
4235 SDValue N0, SDValue N1, unsigned Size, bool Signed) { in getMul24()
4278 SDValue N0 = N->getOperand(0); in performMulCombine() local
4353 SDValue N0 = N->getOperand(0); in performMulLoHiCombine() local
4412 SDValue N0 = N->getOperand(0); in performMulhsCombine() local
4445 SDValue N0 = N->getOperand(0); in performMulhuCombine() local
4726 bool AMDGPUTargetLowering::shouldFoldFNegIntoSrc(SDNode *N, SDValue N0) { in shouldFoldFNegIntoSrc()
4748 SDValue N0 = N->getOperand(0); in performFNegCombine() local
5010 SDValue N0 = N->getOperand(0); in performFAbsCombine() local
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H A DSIISelLowering.cpp9964 SDValue N0 = Offset; in splitBufferOffsets() local
10027 SDValue N0 = CombinedOffset.getOperand(0); in setBufferOffsets() local
11306 SDValue N0 = N->getOperand(0); in performSHLPtrCombine() local
12573 SDValue N0 = N->getOperand(0); in performRcpCombine() local
12957 SDValue N0 = N->getOperand(0); in performFCanonicalizeCombine() local
13584 const SDNode *N0, in getFusedOpcode()
13647 SDValue N0, SDValue N1, SDValue N2, in getMad64_32()
16449 bool SITargetLowering::isReassocProfitable(SelectionDAG &DAG, SDValue N0, in isReassocProfitable()
16463 Register N0, Register N1) const { in isReassocProfitable()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1512 SDValue N0 = N->getOperand(0); in tryOptimizeRem8Extend() local
1896 SDValue N0 = N.getOperand(0); in matchWrapper() local
3934 SDValue N0 = Node->getOperand(0); in matchBitExtract() local
4095 SDValue N0 = Node->getOperand(0); in matchBEXTRFromAndImm() local
4220 SDValue N0 = Node->getOperand(0); in emitPCMPISTR() local
4253 SDValue N0 = Node->getOperand(0); in emitPCMPESTR() local
4658 SDValue N0 = N->getOperand(0); in tryVPTERNLOG() local
4881 SDValue N0 = SetccOp0; in tryVPTESTM() local
5040 SDValue N0 = N->getOperand(0); in tryMatchBitSelect() local
5334 SDValue N0 = Node->getOperand(0); in Select() local
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H A DX86ISelLowering.cpp5841 SDValue N0 = N.getOperand(0); in getFauxShuffleMask() local
5864 SDValue N0 = peekThroughBitcasts(N.getOperand(0)); in getFauxShuffleMask() local
6085 SDValue N0 = N.getOperand(0); in getFauxShuffleMask() local
12431 static SDValue lowerShuffleOfExtractsAsVperm(const SDLoc &DL, SDValue N0, in lowerShuffleOfExtractsAsVperm()
18213 SDValue N0 = Op.getOperand(0); in LowerINSERT_VECTOR_ELT() local
19614 SDValue N0 = Op.getOperand(IsStrict ? 1 : 0); in lowerUINT_TO_FP_v2i32() local
19820 SDValue N0 = Op.getOperand(OpNo); in lowerUINT_TO_FP_vec() local
21810 SDValue N0 = Op.getOperand(0); in LowerFROUND() local
21962 SDValue N0 = Op.getOperand(0); in LowerFGETSIGN() local
28097 SDValue N0 = Op.getOperand(0); in LowerCTTZ() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp151 SDValue N0 = N.getOperand(0); in MatchWrapper() local
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp575 SDValue N0 = Op.getOperand(0); in isADDADDMUL() local
1537 SDValue N0 = N->getOperand(0); in PerformDAGCombine() local
1573 SDValue N0 = N->getOperand(0); in PerformDAGCombine() local
1610 SDValue N0 = N->getOperand(0); in PerformDAGCombine() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp9607 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubSExt() local
9618 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubZExt() local
9632 SDNode *N0 = Op.getOperand(0).getNode(); in LowerMUL() local
9732 static SDValue LowerSDIV_v4i16(SDValue N0, SDValue N1, const SDLoc &dl, in LowerSDIV_v4i16()
9778 SDValue N0 = Op.getOperand(0); in LowerSDIV() local
9815 SDValue N0 = Op.getOperand(0); in LowerUDIV() local
12619 SDValue N0 = N->getOperand(0); in combineSelectAndUseCommutative() local
12642 static SDValue AddCombineToVPADD(SDNode *N, SDValue N0, SDValue N1, in AddCombineToVPADD()
12670 static SDValue AddCombineVUZPToVPADDL(SDNode *N, SDValue N0, SDValue N1, in AddCombineVUZPToVPADDL()
12723 AddCombineBUILD_VECTORToVPADDL(SDNode *N, SDValue N0, SDValue N1, in AddCombineBUILD_VECTORToVPADDL()
[all …]
H A DARMISelDAGToDAG.cpp442 SDValue N0 = N.getOperand(0); in PreprocessISelDAG() local
3901 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); in Select() local
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp5298 PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, in PerformADDCombineWithOperands()
5342 PerformFADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, in PerformFADDCombineWithOperands()
5448 SDValue N0 = N->getOperand(0); in PerformADDCombine() local
5469 SDValue N0 = N->getOperand(0); in PerformFADDCombine() local
5809 PerformMULCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, in PerformMULCombineWithOperands()
5846 SDValue N0 = N->getOperand(0); in PerformMULCombine() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp1445 SDValue N0 = N->getOperand(0); in combineSelectAndUseCommutative() local
1459 SDValue N0 = N->getOperand(0); in PerformSUBCombine() local
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelDAGToDAG.cpp579 SDValue N0 = N.getOperand(0); in matchWrapper() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp5070 SDValue N0 = N.getOperand(0); in isAddSubSExt() local
5081 SDValue N0 = N.getOperand(0); in isAddSubZExt() local
5215 static unsigned selectUmullSmull(SDValue &N0, SDValue &N1, SelectionDAG &DAG, in selectUmullSmull()
5289 SDValue N0 = Op.getOperand(0); in LowerMUL() local
7159 bool AArch64TargetLowering::isReassocProfitable(SelectionDAG &DAG, SDValue N0, in isReassocProfitable()
14090 SDValue N0 = N->getOperand(0); in LowerBUILD_VECTOR() local
17991 SDValue N0 = N->getOperand(0); in BuildSREMPow2() local
18221 SDValue N0 = N->getOperand(0).getOperand(0); in performVectorExtCombine() local
18262 SDValue N0 = N->getOperand(0); in performMulCombine() local
18335 auto Shl = [&](SDValue N0, unsigned N1) { in performMulCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1135 SDValue N0 = I->getOperand(0), N1 = I->getOperand(1); in ppSimplifyOrSelect0() local
1545 SDValue N0 = N.getOperand(0); in SelectGlobalAddress() local
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp10121 SDValue N0 = peekThroughBitcasts(Op.getOperand(0)); in LowerROTL() local
16584 SDValue N0 = N->getOperand(0); in BuildSDIVPow2() local
17657 SDValue N0 = Op.getOperand(0); in getNegatedExpression() local
17765 SDValue N0 = N->getOperand(0); in stripModuloOnShift() local
17799 SDValue N0 = N->getOperand(0); in combineSHL() local
18122 SDValue N0 = N->getOperand(0); in combineFMALike() local
H A DPPCISelDAGToDAG.cpp5196 SDValue N0 = N->getOperand(0); in tryAsSingleRLDIMI() local
5516 SDValue N0 = N->getOperand(0); in Select() local
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp6672 SDValue N0 = N->getOperand(0); in combineZERO_EXTEND() local
6723 SDValue N0 = N->getOperand(0); in combineSIGN_EXTEND_INREG() local
6744 SDValue N0 = N->getOperand(0); in combineSIGN_EXTEND() local
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3792 virtual bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, in isReassocProfitable()
3803 virtual bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0, in isReassocProfitable()

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