| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.h | 209 uint16_t Masked : 1; member
219 uint16_t Masked : 1; member
229 uint16_t Masked : 1; member
238 uint16_t Masked : 1; member
247 uint16_t Masked : 1; member
256 uint16_t Masked :1; member
264 uint16_t Masked : 1; member
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| H A D | RISCVISelLowering.cpp | 12083 SDValue Masked = DAG.getNode(ISD::AND, DL, XLenVT, Shifted, in lowerGET_ROUNDING() local
18545 const RISCV::RISCVMaskedPseudoInfo *Masked = in lookupMaskedIntrinsic() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Vectorize/ |
| H A D | LoopIdiomVectorize.h | 16 enum class LoopIdiomVectorizeStyle { Masked, Predicated }; enumerator
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | TargetLibraryInfo.h | 47 bool Masked; variable
53 ElementCount VectorizationFactor, bool Masked, StringRef VABIPrefix) in VecDesc()
400 bool Masked) const { in getVectorMappingInfo()
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| H A D | TargetTransformInfo.h | 1341 Masked, ///< The cast is used with a masked load/store. enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Support/ |
| H A D | APFixedPoint.cpp | 47 APInt Masked(NewVal & Mask); in convert() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TypePromotion.cpp | 645 Value *Masked = Builder.CreateAnd(Trunc->getOperand(0), Mask); in ConvertTruncs() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 2222 Value *Masked = IC.Builder.CreateAnd(Input, II.getArgOperand(1)); in instCombineIntrinsic() local
2268 Value *Masked = IC.Builder.CreateAnd(Shifted, II.getArgOperand(1)); in instCombineIntrinsic() local
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| H A D | X86ISelDAGToDAG.cpp | 4810 bool FoldedBCast, bool Masked) { in getVPTESTMOpc()
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| H A D | X86ISelLowering.cpp | 10718 if (SDValue Masked = lowerShuffleAsBitMask(DL, VT, V1, V2, Mask, Zeroable, in lowerShuffleAsBlend() local
10785 if (SDValue Masked = lowerShuffleAsBitMask(DL, VT, V1, V2, Mask, Zeroable, in lowerShuffleAsBlend() local
13247 if (SDValue Masked = lowerShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, in lowerV4I32Shuffle() local
13956 if (SDValue Masked = lowerShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, in lowerV8I16Shuffle() local
14304 if (SDValue Masked = lowerShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, in lowerV16I8Shuffle() local
17145 if (SDValue Masked = lowerShuffleAsBitMask(DL, MVT::v64i8, V1, V2, Mask, in lowerV64I8Shuffle() local
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
| H A D | MemProfiler.cpp | 433 if (auto *Masked = dyn_cast<ConstantInt>(Vector->getOperand(Idx))) { in instrumentMaskedLoadOrStore() local
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| H A D | InstrProfiling.cpp | 1153 auto *Masked = Builder.CreateAnd(Bitmap, ArgVal); in createRMWOrFunc() local
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineShifts.cpp | 195 Value *Masked, *ShiftShAmt; in dropRedundantMaskingOfLeftShiftInput() local
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| H A D | InstCombineSelect.cpp | 3526 Value *Masked = in foldBitCeil() local
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| H A D | InstCombineAndOrXor.cpp | 774 Value *Masked = Builder.CreateAnd(L1, Mask); in foldAndOrOfICmpsOfAndWithPow2() local
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| H A D | InstCombineCompares.cpp | 1165 Value *Masked = Builder.CreateAnd(X, Mask); in foldIRemByPowerOfTwoToBitTest() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 5578 auto Masked = B.buildAnd(S32, HighHalf, AndMask); in legalizePointerAsRsrcIntrin() local
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| H A D | SIISelLowering.cpp | 10073 SDValue Masked = DAG.getNode(ISD::AND, Loc, MVT::i32, HighHalf, Mask); in lowerPointerAsRsrcIntrin() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 7183 SDValue Masked = DAG.getNode(ISD::AND, DL, VT, N, IntMax); in prepareSREMEqFold() local
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| H A D | DAGCombiner.cpp | 3061 bool Masked = false; in getAsCarry() local
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGOpenMPRuntime.cpp | 10664 llvm::SmallVector<char, 2> Masked; in emitX86DeclareSimdFunction() local
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