1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Marvell 10G 88x3310 PHY driver
4 *
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
6 * from two different companies.
7 *
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
11 *
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
15 *
16 * With XAUI, observation shows:
17 *
18 * XAUI PHYXS -- <appropriate PCS as above>
19 *
20 * and no switching of the host interface mode occurs.
21 *
22 * If both the fiber and copper ports are connected, the first to gain
23 * link takes priority and the other port is completely locked out.
24 */
25 #include <linux/bitfield.h>
26 #include <linux/ctype.h>
27 #include <linux/delay.h>
28 #include <linux/hwmon.h>
29 #include <linux/marvell_phy.h>
30 #include <linux/phy.h>
31 #include <linux/sfp.h>
32 #include <linux/netdevice.h>
33
34 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
35 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
36
37 #define MV_VERSION(a,b,c,d) ((a) << 24 | (b) << 16 | (c) << 8 | (d))
38
39 enum {
40 MV_PMA_FW_VER0 = 0xc011,
41 MV_PMA_FW_VER1 = 0xc012,
42 MV_PMA_21X0_PORT_CTRL = 0xc04a,
43 MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15),
44 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7,
45 MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0,
46 MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1,
47 MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2,
48 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4,
49 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5,
50 MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
51 MV_PMA_BOOT = 0xc050,
52 MV_PMA_BOOT_FATAL = BIT(0),
53
54 MV_PCS_BASE_T = 0x0000,
55 MV_PCS_BASE_R = 0x1000,
56 MV_PCS_1000BASEX = 0x2000,
57
58 MV_PCS_CSCR1 = 0x8000,
59 MV_PCS_CSCR1_ED_MASK = 0x0300,
60 MV_PCS_CSCR1_ED_OFF = 0x0000,
61 MV_PCS_CSCR1_ED_RX = 0x0200,
62 MV_PCS_CSCR1_ED_NLP = 0x0300,
63 MV_PCS_CSCR1_MDIX_MASK = 0x0060,
64 MV_PCS_CSCR1_MDIX_MDI = 0x0000,
65 MV_PCS_CSCR1_MDIX_MDIX = 0x0020,
66 MV_PCS_CSCR1_MDIX_AUTO = 0x0060,
67
68 MV_PCS_DSC1 = 0x8003,
69 MV_PCS_DSC1_ENABLE = BIT(9),
70 MV_PCS_DSC1_10GBT = 0x01c0,
71 MV_PCS_DSC1_1GBR = 0x0038,
72 MV_PCS_DSC1_100BTX = 0x0007,
73 MV_PCS_DSC2 = 0x8004,
74 MV_PCS_DSC2_2P5G = 0xf000,
75 MV_PCS_DSC2_5G = 0x0f00,
76
77 MV_PCS_CSSR1 = 0x8008,
78 MV_PCS_CSSR1_SPD1_MASK = 0xc000,
79 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000,
80 MV_PCS_CSSR1_SPD1_1000 = 0x8000,
81 MV_PCS_CSSR1_SPD1_100 = 0x4000,
82 MV_PCS_CSSR1_SPD1_10 = 0x0000,
83 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13),
84 MV_PCS_CSSR1_RESOLVED = BIT(11),
85 MV_PCS_CSSR1_MDIX = BIT(6),
86 MV_PCS_CSSR1_SPD2_MASK = 0x000c,
87 MV_PCS_CSSR1_SPD2_5000 = 0x0008,
88 MV_PCS_CSSR1_SPD2_2500 = 0x0004,
89 MV_PCS_CSSR1_SPD2_10000 = 0x0000,
90
91 /* Temperature read register (88E2110 only) */
92 MV_PCS_TEMP = 0x8042,
93
94 /* Number of ports on the device */
95 MV_PCS_PORT_INFO = 0xd00d,
96 MV_PCS_PORT_INFO_NPORTS_MASK = 0x0380,
97 MV_PCS_PORT_INFO_NPORTS_SHIFT = 7,
98
99 /* SerDes reinitialization 88E21X0 */
100 MV_AN_21X0_SERDES_CTRL2 = 0x800f,
101 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS = BIT(13),
102 MV_AN_21X0_SERDES_CTRL2_RUN_INIT = BIT(15),
103
104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
105 * registers appear to set themselves to the 0x800X when AN is
106 * restarted, but status registers appear readable from either.
107 */
108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
110
111 /* Vendor2 MMD registers */
112 MV_V2_PORT_CTRL = 0xf001,
113 MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
114 MV_V2_33X0_PORT_CTRL_SWRST = BIT(15),
115 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7,
116 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0,
117 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1,
118 MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1,
119 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2,
120 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 0x3,
121 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 0x4,
122 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5,
123 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
124 MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 0x7,
125 MV_V2_PORT_INTR_STS = 0xf040,
126 MV_V2_PORT_INTR_MASK = 0xf043,
127 MV_V2_PORT_INTR_STS_WOL_EN = BIT(8),
128 MV_V2_MAGIC_PKT_WORD0 = 0xf06b,
129 MV_V2_MAGIC_PKT_WORD1 = 0xf06c,
130 MV_V2_MAGIC_PKT_WORD2 = 0xf06d,
131 /* Wake on LAN registers */
132 MV_V2_WOL_CTRL = 0xf06e,
133 MV_V2_WOL_CTRL_CLEAR_STS = BIT(15),
134 MV_V2_WOL_CTRL_MAGIC_PKT_EN = BIT(0),
135 /* Temperature control/read registers (88X3310 only) */
136 MV_V2_TEMP_CTRL = 0xf08a,
137 MV_V2_TEMP_CTRL_MASK = 0xc000,
138 MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
139 MV_V2_TEMP_CTRL_DISABLE = 0xc000,
140 MV_V2_TEMP = 0xf08c,
141 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
142 };
143
144 struct mv3310_mactype {
145 bool valid;
146 bool fixed_interface;
147 phy_interface_t interface_10g;
148 };
149
150 struct mv3310_chip {
151 bool (*has_downshift)(struct phy_device *phydev);
152 void (*init_supported_interfaces)(unsigned long *mask);
153 int (*get_mactype)(struct phy_device *phydev);
154 int (*set_mactype)(struct phy_device *phydev, int mactype);
155 int (*select_mactype)(unsigned long *interfaces);
156
157 const struct mv3310_mactype *mactypes;
158 size_t n_mactypes;
159
160 #ifdef CONFIG_HWMON
161 int (*hwmon_read_temp_reg)(struct phy_device *phydev);
162 #endif
163 };
164
165 struct mv3310_priv {
166 DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX);
167 const struct mv3310_mactype *mactype;
168
169 u32 firmware_ver;
170 bool has_downshift;
171
172 struct device *hwmon_dev;
173 char *hwmon_name;
174 };
175
to_mv3310_chip(struct phy_device * phydev)176 static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev)
177 {
178 return phydev->drv->driver_data;
179 }
180
181 #ifdef CONFIG_HWMON
mv3310_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)182 static umode_t mv3310_hwmon_is_visible(const void *data,
183 enum hwmon_sensor_types type,
184 u32 attr, int channel)
185 {
186 if (type == hwmon_chip && attr == hwmon_chip_update_interval)
187 return 0444;
188 if (type == hwmon_temp && attr == hwmon_temp_input)
189 return 0444;
190 return 0;
191 }
192
mv3310_hwmon_read_temp_reg(struct phy_device * phydev)193 static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev)
194 {
195 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
196 }
197
mv2110_hwmon_read_temp_reg(struct phy_device * phydev)198 static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev)
199 {
200 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP);
201 }
202
mv3310_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * value)203 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
204 u32 attr, int channel, long *value)
205 {
206 struct phy_device *phydev = dev_get_drvdata(dev);
207 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
208 int temp;
209
210 if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
211 *value = MSEC_PER_SEC;
212 return 0;
213 }
214
215 if (type == hwmon_temp && attr == hwmon_temp_input) {
216 temp = chip->hwmon_read_temp_reg(phydev);
217 if (temp < 0)
218 return temp;
219
220 *value = ((temp & 0xff) - 75) * 1000;
221
222 return 0;
223 }
224
225 return -EOPNOTSUPP;
226 }
227
228 static const struct hwmon_ops mv3310_hwmon_ops = {
229 .is_visible = mv3310_hwmon_is_visible,
230 .read = mv3310_hwmon_read,
231 };
232
233 static const struct hwmon_channel_info * const mv3310_hwmon_info[] = {
234 HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL),
235 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
236 NULL,
237 };
238
239 static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
240 .ops = &mv3310_hwmon_ops,
241 .info = mv3310_hwmon_info,
242 };
243
mv3310_hwmon_config(struct phy_device * phydev,bool enable)244 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
245 {
246 u16 val;
247 int ret;
248
249 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310)
250 return 0;
251
252 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
253 MV_V2_TEMP_UNKNOWN);
254 if (ret < 0)
255 return ret;
256
257 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
258
259 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
260 MV_V2_TEMP_CTRL_MASK, val);
261 }
262
mv3310_hwmon_probe(struct phy_device * phydev)263 static int mv3310_hwmon_probe(struct phy_device *phydev)
264 {
265 struct device *dev = &phydev->mdio.dev;
266 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
267 int i, j, ret;
268
269 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
270 if (!priv->hwmon_name)
271 return -ENODEV;
272
273 for (i = j = 0; priv->hwmon_name[i]; i++) {
274 if (isalnum(priv->hwmon_name[i])) {
275 if (i != j)
276 priv->hwmon_name[j] = priv->hwmon_name[i];
277 j++;
278 }
279 }
280 priv->hwmon_name[j] = '\0';
281
282 ret = mv3310_hwmon_config(phydev, true);
283 if (ret)
284 return ret;
285
286 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
287 priv->hwmon_name, phydev,
288 &mv3310_hwmon_chip_info, NULL);
289
290 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
291 }
292 #else
mv3310_hwmon_config(struct phy_device * phydev,bool enable)293 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
294 {
295 return 0;
296 }
297
mv3310_hwmon_probe(struct phy_device * phydev)298 static int mv3310_hwmon_probe(struct phy_device *phydev)
299 {
300 return 0;
301 }
302 #endif
303
mv3310_power_down(struct phy_device * phydev)304 static int mv3310_power_down(struct phy_device *phydev)
305 {
306 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
307 MV_V2_PORT_CTRL_PWRDOWN);
308 }
309
mv3310_power_up(struct phy_device * phydev)310 static int mv3310_power_up(struct phy_device *phydev)
311 {
312 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
313 int ret;
314
315 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
316 MV_V2_PORT_CTRL_PWRDOWN);
317
318 /* Sometimes, the power down bit doesn't clear immediately, and
319 * a read of this register causes the bit not to clear. Delay
320 * 100us to allow the PHY to come out of power down mode before
321 * the next access.
322 */
323 udelay(100);
324
325 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
326 priv->firmware_ver < 0x00030000)
327 return ret;
328
329 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
330 MV_V2_33X0_PORT_CTRL_SWRST);
331 }
332
mv3310_reset(struct phy_device * phydev,u32 unit)333 static int mv3310_reset(struct phy_device *phydev, u32 unit)
334 {
335 int val, err;
336
337 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
338 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
339 if (err < 0)
340 return err;
341
342 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
343 unit + MDIO_CTRL1, val,
344 !(val & MDIO_CTRL1_RESET),
345 5000, 100000, true);
346 }
347
mv3310_get_downshift(struct phy_device * phydev,u8 * ds)348 static int mv3310_get_downshift(struct phy_device *phydev, u8 *ds)
349 {
350 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
351 int val;
352
353 if (!priv->has_downshift)
354 return -EOPNOTSUPP;
355
356 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1);
357 if (val < 0)
358 return val;
359
360 if (val & MV_PCS_DSC1_ENABLE)
361 /* assume that all fields are the same */
362 *ds = 1 + FIELD_GET(MV_PCS_DSC1_10GBT, (u16)val);
363 else
364 *ds = DOWNSHIFT_DEV_DISABLE;
365
366 return 0;
367 }
368
mv3310_set_downshift(struct phy_device * phydev,u8 ds)369 static int mv3310_set_downshift(struct phy_device *phydev, u8 ds)
370 {
371 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
372 u16 val;
373 int err;
374
375 if (!priv->has_downshift)
376 return -EOPNOTSUPP;
377
378 if (ds == DOWNSHIFT_DEV_DISABLE)
379 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
380 MV_PCS_DSC1_ENABLE);
381
382 /* DOWNSHIFT_DEV_DEFAULT_COUNT is confusing. It looks like it should
383 * set the default settings for the PHY. However, it is used for
384 * "ethtool --set-phy-tunable ethN downshift on". The intention is
385 * to enable downshift at a default number of retries. The default
386 * settings for 88x3310 are for two retries with downshift disabled.
387 * So let's use two retries with downshift enabled.
388 */
389 if (ds == DOWNSHIFT_DEV_DEFAULT_COUNT)
390 ds = 2;
391
392 if (ds > 8)
393 return -E2BIG;
394
395 ds -= 1;
396 val = FIELD_PREP(MV_PCS_DSC2_2P5G, ds);
397 val |= FIELD_PREP(MV_PCS_DSC2_5G, ds);
398 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2,
399 MV_PCS_DSC2_2P5G | MV_PCS_DSC2_5G, val);
400 if (err < 0)
401 return err;
402
403 val = MV_PCS_DSC1_ENABLE;
404 val |= FIELD_PREP(MV_PCS_DSC1_10GBT, ds);
405 val |= FIELD_PREP(MV_PCS_DSC1_1GBR, ds);
406 val |= FIELD_PREP(MV_PCS_DSC1_100BTX, ds);
407
408 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
409 MV_PCS_DSC1_ENABLE | MV_PCS_DSC1_10GBT |
410 MV_PCS_DSC1_1GBR | MV_PCS_DSC1_100BTX, val);
411 }
412
mv3310_get_edpd(struct phy_device * phydev,u16 * edpd)413 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd)
414 {
415 int val;
416
417 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1);
418 if (val < 0)
419 return val;
420
421 switch (val & MV_PCS_CSCR1_ED_MASK) {
422 case MV_PCS_CSCR1_ED_NLP:
423 *edpd = 1000;
424 break;
425 case MV_PCS_CSCR1_ED_RX:
426 *edpd = ETHTOOL_PHY_EDPD_NO_TX;
427 break;
428 default:
429 *edpd = ETHTOOL_PHY_EDPD_DISABLE;
430 break;
431 }
432 return 0;
433 }
434
mv3310_set_edpd(struct phy_device * phydev,u16 edpd)435 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd)
436 {
437 u16 val;
438 int err;
439
440 switch (edpd) {
441 case 1000:
442 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
443 val = MV_PCS_CSCR1_ED_NLP;
444 break;
445
446 case ETHTOOL_PHY_EDPD_NO_TX:
447 val = MV_PCS_CSCR1_ED_RX;
448 break;
449
450 case ETHTOOL_PHY_EDPD_DISABLE:
451 val = MV_PCS_CSCR1_ED_OFF;
452 break;
453
454 default:
455 return -EINVAL;
456 }
457
458 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
459 MV_PCS_CSCR1_ED_MASK, val);
460 if (err > 0)
461 err = mv3310_reset(phydev, MV_PCS_BASE_T);
462
463 return err;
464 }
465
mv3310_sfp_insert(void * upstream,const struct sfp_eeprom_id * id)466 static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
467 {
468 struct phy_device *phydev = upstream;
469 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
470 DECLARE_PHY_INTERFACE_MASK(interfaces);
471 phy_interface_t iface;
472
473 sfp_parse_support(phydev->sfp_bus, id, support, interfaces);
474 iface = sfp_select_interface(phydev->sfp_bus, support);
475
476 if (iface != PHY_INTERFACE_MODE_10GBASER) {
477 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
478 return -EINVAL;
479 }
480 return 0;
481 }
482
483 static const struct sfp_upstream_ops mv3310_sfp_ops = {
484 .attach = phy_sfp_attach,
485 .detach = phy_sfp_detach,
486 .connect_phy = phy_sfp_connect_phy,
487 .disconnect_phy = phy_sfp_disconnect_phy,
488 .module_insert = mv3310_sfp_insert,
489 };
490
mv3310_probe(struct phy_device * phydev)491 static int mv3310_probe(struct phy_device *phydev)
492 {
493 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
494 struct mv3310_priv *priv;
495 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
496 int ret;
497
498 if (!phydev->is_c45 ||
499 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
500 return -ENODEV;
501
502 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
503 if (ret < 0)
504 return ret;
505
506 if (ret & MV_PMA_BOOT_FATAL) {
507 dev_warn(&phydev->mdio.dev,
508 "PHY failed to boot firmware, status=%04x\n", ret);
509 return -ENODEV;
510 }
511
512 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
513 if (!priv)
514 return -ENOMEM;
515
516 dev_set_drvdata(&phydev->mdio.dev, priv);
517
518 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
519 if (ret < 0)
520 return ret;
521
522 priv->firmware_ver = ret << 16;
523
524 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
525 if (ret < 0)
526 return ret;
527
528 priv->firmware_ver |= ret;
529
530 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n",
531 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
532 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);
533
534 if (chip->has_downshift)
535 priv->has_downshift = chip->has_downshift(phydev);
536
537 /* Powering down the port when not in use saves about 600mW */
538 ret = mv3310_power_down(phydev);
539 if (ret)
540 return ret;
541
542 ret = mv3310_hwmon_probe(phydev);
543 if (ret)
544 return ret;
545
546 chip->init_supported_interfaces(priv->supported_interfaces);
547
548 return phy_sfp_probe(phydev, &mv3310_sfp_ops);
549 }
550
mv3310_remove(struct phy_device * phydev)551 static void mv3310_remove(struct phy_device *phydev)
552 {
553 mv3310_hwmon_config(phydev, false);
554 }
555
mv3310_suspend(struct phy_device * phydev)556 static int mv3310_suspend(struct phy_device *phydev)
557 {
558 return mv3310_power_down(phydev);
559 }
560
mv3310_resume(struct phy_device * phydev)561 static int mv3310_resume(struct phy_device *phydev)
562 {
563 int ret;
564
565 ret = mv3310_power_up(phydev);
566 if (ret)
567 return ret;
568
569 return mv3310_hwmon_config(phydev, true);
570 }
571
572 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
573 * don't set bit 14 in PMA Extended Abilities (1.11), although they do
574 * support 2.5GBASET and 5GBASET. For these models, we can still read their
575 * 2.5G/5G extended abilities register (1.21). We detect these models based on
576 * the PMA device identifier, with a mask matching models known to have this
577 * issue
578 */
mv3310_has_pma_ngbaset_quirk(struct phy_device * phydev)579 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
580 {
581 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
582 return false;
583
584 /* Only some revisions of the 88X3310 family PMA seem to be impacted */
585 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
586 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
587 }
588
mv2110_get_mactype(struct phy_device * phydev)589 static int mv2110_get_mactype(struct phy_device *phydev)
590 {
591 int mactype;
592
593 mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL);
594 if (mactype < 0)
595 return mactype;
596
597 return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
598 }
599
mv2110_set_mactype(struct phy_device * phydev,int mactype)600 static int mv2110_set_mactype(struct phy_device *phydev, int mactype)
601 {
602 int err, val;
603
604 mactype &= MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
605 err = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL,
606 MV_PMA_21X0_PORT_CTRL_SWRST |
607 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK,
608 MV_PMA_21X0_PORT_CTRL_SWRST | mactype);
609 if (err)
610 return err;
611
612 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
613 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS |
614 MV_AN_21X0_SERDES_CTRL2_RUN_INIT);
615 if (err)
616 return err;
617
618 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN,
619 MV_AN_21X0_SERDES_CTRL2, val,
620 !(val &
621 MV_AN_21X0_SERDES_CTRL2_RUN_INIT),
622 5000, 100000, true);
623 if (err)
624 return err;
625
626 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
627 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS);
628 }
629
mv2110_select_mactype(unsigned long * interfaces)630 static int mv2110_select_mactype(unsigned long *interfaces)
631 {
632 if (test_bit(PHY_INTERFACE_MODE_USXGMII, interfaces))
633 return MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII;
634 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
635 !test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
636 return MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER;
637 else if (test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
638 return MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
639 else
640 return -1;
641 }
642
mv3310_get_mactype(struct phy_device * phydev)643 static int mv3310_get_mactype(struct phy_device *phydev)
644 {
645 int mactype;
646
647 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
648 if (mactype < 0)
649 return mactype;
650
651 return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
652 }
653
mv3310_set_mactype(struct phy_device * phydev,int mactype)654 static int mv3310_set_mactype(struct phy_device *phydev, int mactype)
655 {
656 int ret;
657
658 mactype &= MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
659 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
660 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK,
661 mactype);
662 if (ret <= 0)
663 return ret;
664
665 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
666 MV_V2_33X0_PORT_CTRL_SWRST);
667 }
668
mv3310_select_mactype(unsigned long * interfaces)669 static int mv3310_select_mactype(unsigned long *interfaces)
670 {
671 if (test_bit(PHY_INTERFACE_MODE_USXGMII, interfaces))
672 return MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII;
673 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
674 test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
675 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
676 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
677 test_bit(PHY_INTERFACE_MODE_RXAUI, interfaces))
678 return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI;
679 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
680 test_bit(PHY_INTERFACE_MODE_XAUI, interfaces))
681 return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI;
682 else if (test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
683 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
684 else if (test_bit(PHY_INTERFACE_MODE_RXAUI, interfaces))
685 return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH;
686 else if (test_bit(PHY_INTERFACE_MODE_XAUI, interfaces))
687 return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH;
688 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces))
689 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
690 else
691 return -1;
692 }
693
694 static const struct mv3310_mactype mv2110_mactypes[] = {
695 [MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII] = {
696 .valid = true,
697 .fixed_interface = true,
698 .interface_10g = PHY_INTERFACE_MODE_USXGMII,
699 },
700 [MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER] = {
701 .valid = true,
702 .interface_10g = PHY_INTERFACE_MODE_NA,
703 },
704 [MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN] = {
705 .valid = true,
706 .interface_10g = PHY_INTERFACE_MODE_NA,
707 },
708 [MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH] = {
709 .valid = true,
710 .fixed_interface = true,
711 .interface_10g = PHY_INTERFACE_MODE_10GBASER,
712 },
713 };
714
715 static const struct mv3310_mactype mv3310_mactypes[] = {
716 [MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI] = {
717 .valid = true,
718 .interface_10g = PHY_INTERFACE_MODE_RXAUI,
719 },
720 [MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH] = {
721 .valid = true,
722 .fixed_interface = true,
723 .interface_10g = PHY_INTERFACE_MODE_XAUI,
724 },
725 [MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH] = {
726 .valid = true,
727 .fixed_interface = true,
728 .interface_10g = PHY_INTERFACE_MODE_RXAUI,
729 },
730 [MV_V2_3310_PORT_CTRL_MACTYPE_XAUI] = {
731 .valid = true,
732 .interface_10g = PHY_INTERFACE_MODE_XAUI,
733 },
734 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER] = {
735 .valid = true,
736 .interface_10g = PHY_INTERFACE_MODE_10GBASER,
737 },
738 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN] = {
739 .valid = true,
740 .interface_10g = PHY_INTERFACE_MODE_10GBASER,
741 },
742 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH] = {
743 .valid = true,
744 .fixed_interface = true,
745 .interface_10g = PHY_INTERFACE_MODE_10GBASER,
746 },
747 [MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII] = {
748 .valid = true,
749 .fixed_interface = true,
750 .interface_10g = PHY_INTERFACE_MODE_USXGMII,
751 },
752 };
753
754 static const struct mv3310_mactype mv3340_mactypes[] = {
755 [MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI] = {
756 .valid = true,
757 .interface_10g = PHY_INTERFACE_MODE_RXAUI,
758 },
759 [MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN] = {
760 .valid = true,
761 .interface_10g = PHY_INTERFACE_MODE_RXAUI,
762 },
763 [MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH] = {
764 .valid = true,
765 .fixed_interface = true,
766 .interface_10g = PHY_INTERFACE_MODE_RXAUI,
767 },
768 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER] = {
769 .valid = true,
770 .interface_10g = PHY_INTERFACE_MODE_10GBASER,
771 },
772 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN] = {
773 .valid = true,
774 .interface_10g = PHY_INTERFACE_MODE_10GBASER,
775 },
776 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH] = {
777 .valid = true,
778 .fixed_interface = true,
779 .interface_10g = PHY_INTERFACE_MODE_10GBASER,
780 },
781 [MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII] = {
782 .valid = true,
783 .fixed_interface = true,
784 .interface_10g = PHY_INTERFACE_MODE_USXGMII,
785 },
786 };
787
mv3310_fill_possible_interfaces(struct phy_device * phydev)788 static void mv3310_fill_possible_interfaces(struct phy_device *phydev)
789 {
790 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
791 unsigned long *possible = phydev->possible_interfaces;
792 const struct mv3310_mactype *mactype = priv->mactype;
793
794 if (mactype->interface_10g != PHY_INTERFACE_MODE_NA)
795 __set_bit(priv->mactype->interface_10g, possible);
796
797 if (!mactype->fixed_interface) {
798 __set_bit(PHY_INTERFACE_MODE_5GBASER, possible);
799 __set_bit(PHY_INTERFACE_MODE_2500BASEX, possible);
800 __set_bit(PHY_INTERFACE_MODE_SGMII, possible);
801 }
802 }
803
mv3310_config_init(struct phy_device * phydev)804 static int mv3310_config_init(struct phy_device *phydev)
805 {
806 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
807 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
808 int err, mactype;
809
810 /* Check that the PHY interface type is compatible */
811 if (!test_bit(phydev->interface, priv->supported_interfaces))
812 return -ENODEV;
813
814 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
815
816 /* Power up so reset works */
817 err = mv3310_power_up(phydev);
818 if (err)
819 return err;
820
821 /* If host provided host supported interface modes, try to select the
822 * best one
823 */
824 if (!phy_interface_empty(phydev->host_interfaces)) {
825 mactype = chip->select_mactype(phydev->host_interfaces);
826 if (mactype >= 0) {
827 phydev_info(phydev, "Changing MACTYPE to %i\n",
828 mactype);
829 err = chip->set_mactype(phydev, mactype);
830 if (err)
831 return err;
832 }
833 }
834
835 mactype = chip->get_mactype(phydev);
836 if (mactype < 0)
837 return mactype;
838
839 if (mactype >= chip->n_mactypes || !chip->mactypes[mactype].valid) {
840 phydev_err(phydev, "MACTYPE configuration invalid\n");
841 return -EINVAL;
842 }
843
844 priv->mactype = &chip->mactypes[mactype];
845
846 mv3310_fill_possible_interfaces(phydev);
847
848 /* Enable EDPD mode - saving 600mW */
849 err = mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
850 if (err)
851 return err;
852
853 /* Allow downshift */
854 err = mv3310_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);
855 if (err && err != -EOPNOTSUPP)
856 return err;
857
858 return 0;
859 }
860
mv3310_get_features(struct phy_device * phydev)861 static int mv3310_get_features(struct phy_device *phydev)
862 {
863 int ret, val;
864
865 ret = genphy_c45_pma_read_abilities(phydev);
866 if (ret)
867 return ret;
868
869 if (mv3310_has_pma_ngbaset_quirk(phydev)) {
870 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
871 MDIO_PMA_NG_EXTABLE);
872 if (val < 0)
873 return val;
874
875 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
876 phydev->supported,
877 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
878
879 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
880 phydev->supported,
881 val & MDIO_PMA_NG_EXTABLE_5GBT);
882 }
883
884 return 0;
885 }
886
mv3310_config_mdix(struct phy_device * phydev)887 static int mv3310_config_mdix(struct phy_device *phydev)
888 {
889 u16 val;
890 int err;
891
892 switch (phydev->mdix_ctrl) {
893 case ETH_TP_MDI_AUTO:
894 val = MV_PCS_CSCR1_MDIX_AUTO;
895 break;
896 case ETH_TP_MDI_X:
897 val = MV_PCS_CSCR1_MDIX_MDIX;
898 break;
899 case ETH_TP_MDI:
900 val = MV_PCS_CSCR1_MDIX_MDI;
901 break;
902 default:
903 return -EINVAL;
904 }
905
906 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
907 MV_PCS_CSCR1_MDIX_MASK, val);
908 if (err > 0)
909 err = mv3310_reset(phydev, MV_PCS_BASE_T);
910
911 return err;
912 }
913
mv3310_config_aneg(struct phy_device * phydev)914 static int mv3310_config_aneg(struct phy_device *phydev)
915 {
916 bool changed = false;
917 u16 reg;
918 int ret;
919
920 ret = mv3310_config_mdix(phydev);
921 if (ret < 0)
922 return ret;
923
924 if (phydev->autoneg == AUTONEG_DISABLE)
925 return genphy_c45_pma_setup_forced(phydev);
926
927 ret = genphy_c45_an_config_aneg(phydev);
928 if (ret < 0)
929 return ret;
930 if (ret > 0)
931 changed = true;
932
933 /* Clause 45 has no standardized support for 1000BaseT, therefore
934 * use vendor registers for this mode.
935 */
936 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
937 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
938 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
939 if (ret < 0)
940 return ret;
941 if (ret > 0)
942 changed = true;
943
944 return genphy_c45_check_and_restart_aneg(phydev, changed);
945 }
946
mv3310_aneg_done(struct phy_device * phydev)947 static int mv3310_aneg_done(struct phy_device *phydev)
948 {
949 int val;
950
951 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
952 if (val < 0)
953 return val;
954
955 if (val & MDIO_STAT1_LSTATUS)
956 return 1;
957
958 return genphy_c45_aneg_done(phydev);
959 }
960
mv3310_update_interface(struct phy_device * phydev)961 static void mv3310_update_interface(struct phy_device *phydev)
962 {
963 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
964
965 if (!phydev->link)
966 return;
967
968 /* In all of the "* with Rate Matching" modes the PHY interface is fixed
969 * at 10Gb. The PHY adapts the rate to actual wire speed with help of
970 * internal 16KB buffer.
971 *
972 * In USXGMII mode the PHY interface mode is also fixed.
973 */
974 if (priv->mactype->fixed_interface) {
975 phydev->interface = priv->mactype->interface_10g;
976 return;
977 }
978
979 /* The PHY automatically switches its serdes interface (and active PHYXS
980 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R /
981 * xaui / rxaui modes according to the speed.
982 * Florian suggests setting phydev->interface to communicate this to the
983 * MAC. Only do this if we are already in one of the above modes.
984 */
985 switch (phydev->speed) {
986 case SPEED_10000:
987 phydev->interface = priv->mactype->interface_10g;
988 break;
989 case SPEED_5000:
990 phydev->interface = PHY_INTERFACE_MODE_5GBASER;
991 break;
992 case SPEED_2500:
993 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
994 break;
995 case SPEED_1000:
996 case SPEED_100:
997 case SPEED_10:
998 phydev->interface = PHY_INTERFACE_MODE_SGMII;
999 break;
1000 default:
1001 break;
1002 }
1003 }
1004
1005 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
mv3310_read_status_10gbaser(struct phy_device * phydev)1006 static int mv3310_read_status_10gbaser(struct phy_device *phydev)
1007 {
1008 phydev->link = 1;
1009 phydev->speed = SPEED_10000;
1010 phydev->duplex = DUPLEX_FULL;
1011 phydev->port = PORT_FIBRE;
1012
1013 return 0;
1014 }
1015
mv3310_read_status_copper(struct phy_device * phydev)1016 static int mv3310_read_status_copper(struct phy_device *phydev)
1017 {
1018 int cssr1, speed, val;
1019
1020 val = genphy_c45_read_link(phydev);
1021 if (val < 0)
1022 return val;
1023
1024 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
1025 if (val < 0)
1026 return val;
1027
1028 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);
1029 if (cssr1 < 0)
1030 return cssr1;
1031
1032 /* If the link settings are not resolved, mark the link down */
1033 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) {
1034 phydev->link = 0;
1035 return 0;
1036 }
1037
1038 /* Read the copper link settings */
1039 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK;
1040 if (speed == MV_PCS_CSSR1_SPD1_SPD2)
1041 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK;
1042
1043 switch (speed) {
1044 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000:
1045 phydev->speed = SPEED_10000;
1046 break;
1047
1048 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000:
1049 phydev->speed = SPEED_5000;
1050 break;
1051
1052 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500:
1053 phydev->speed = SPEED_2500;
1054 break;
1055
1056 case MV_PCS_CSSR1_SPD1_1000:
1057 phydev->speed = SPEED_1000;
1058 break;
1059
1060 case MV_PCS_CSSR1_SPD1_100:
1061 phydev->speed = SPEED_100;
1062 break;
1063
1064 case MV_PCS_CSSR1_SPD1_10:
1065 phydev->speed = SPEED_10;
1066 break;
1067 }
1068
1069 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ?
1070 DUPLEX_FULL : DUPLEX_HALF;
1071 phydev->port = PORT_TP;
1072 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ?
1073 ETH_TP_MDI_X : ETH_TP_MDI;
1074
1075 if (val & MDIO_AN_STAT1_COMPLETE) {
1076 val = genphy_c45_read_lpa(phydev);
1077 if (val < 0)
1078 return val;
1079
1080 /* Read the link partner's 1G advertisement */
1081 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
1082 if (val < 0)
1083 return val;
1084
1085 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
1086
1087 /* Update the pause status */
1088 phy_resolve_aneg_pause(phydev);
1089 }
1090
1091 return 0;
1092 }
1093
mv3310_read_status(struct phy_device * phydev)1094 static int mv3310_read_status(struct phy_device *phydev)
1095 {
1096 int err, val;
1097
1098 phydev->speed = SPEED_UNKNOWN;
1099 phydev->duplex = DUPLEX_UNKNOWN;
1100 linkmode_zero(phydev->lp_advertising);
1101 phydev->link = 0;
1102 phydev->pause = 0;
1103 phydev->asym_pause = 0;
1104 phydev->mdix = ETH_TP_MDI_INVALID;
1105
1106 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
1107 if (val < 0)
1108 return val;
1109
1110 if (val & MDIO_STAT1_LSTATUS)
1111 err = mv3310_read_status_10gbaser(phydev);
1112 else
1113 err = mv3310_read_status_copper(phydev);
1114 if (err < 0)
1115 return err;
1116
1117 if (phydev->link)
1118 mv3310_update_interface(phydev);
1119
1120 return 0;
1121 }
1122
mv3310_get_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,void * data)1123 static int mv3310_get_tunable(struct phy_device *phydev,
1124 struct ethtool_tunable *tuna, void *data)
1125 {
1126 switch (tuna->id) {
1127 case ETHTOOL_PHY_DOWNSHIFT:
1128 return mv3310_get_downshift(phydev, data);
1129 case ETHTOOL_PHY_EDPD:
1130 return mv3310_get_edpd(phydev, data);
1131 default:
1132 return -EOPNOTSUPP;
1133 }
1134 }
1135
mv3310_set_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,const void * data)1136 static int mv3310_set_tunable(struct phy_device *phydev,
1137 struct ethtool_tunable *tuna, const void *data)
1138 {
1139 switch (tuna->id) {
1140 case ETHTOOL_PHY_DOWNSHIFT:
1141 return mv3310_set_downshift(phydev, *(u8 *)data);
1142 case ETHTOOL_PHY_EDPD:
1143 return mv3310_set_edpd(phydev, *(u16 *)data);
1144 default:
1145 return -EOPNOTSUPP;
1146 }
1147 }
1148
mv3310_has_downshift(struct phy_device * phydev)1149 static bool mv3310_has_downshift(struct phy_device *phydev)
1150 {
1151 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
1152
1153 /* Fails to downshift with firmware older than v0.3.5.0 */
1154 return priv->firmware_ver >= MV_VERSION(0,3,5,0);
1155 }
1156
mv3310_init_supported_interfaces(unsigned long * mask)1157 static void mv3310_init_supported_interfaces(unsigned long *mask)
1158 {
1159 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1160 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1161 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
1162 __set_bit(PHY_INTERFACE_MODE_XAUI, mask);
1163 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
1164 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1165 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1166 }
1167
mv3340_init_supported_interfaces(unsigned long * mask)1168 static void mv3340_init_supported_interfaces(unsigned long *mask)
1169 {
1170 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1171 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1172 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
1173 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
1174 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1175 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1176 }
1177
mv2110_init_supported_interfaces(unsigned long * mask)1178 static void mv2110_init_supported_interfaces(unsigned long *mask)
1179 {
1180 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1181 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1182 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
1183 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1184 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1185 }
1186
mv2111_init_supported_interfaces(unsigned long * mask)1187 static void mv2111_init_supported_interfaces(unsigned long *mask)
1188 {
1189 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1190 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1191 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1192 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1193 }
1194
1195 static const struct mv3310_chip mv3310_type = {
1196 .has_downshift = mv3310_has_downshift,
1197 .init_supported_interfaces = mv3310_init_supported_interfaces,
1198 .get_mactype = mv3310_get_mactype,
1199 .set_mactype = mv3310_set_mactype,
1200 .select_mactype = mv3310_select_mactype,
1201
1202 .mactypes = mv3310_mactypes,
1203 .n_mactypes = ARRAY_SIZE(mv3310_mactypes),
1204
1205 #ifdef CONFIG_HWMON
1206 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
1207 #endif
1208 };
1209
1210 static const struct mv3310_chip mv3340_type = {
1211 .has_downshift = mv3310_has_downshift,
1212 .init_supported_interfaces = mv3340_init_supported_interfaces,
1213 .get_mactype = mv3310_get_mactype,
1214 .set_mactype = mv3310_set_mactype,
1215 .select_mactype = mv3310_select_mactype,
1216
1217 .mactypes = mv3340_mactypes,
1218 .n_mactypes = ARRAY_SIZE(mv3340_mactypes),
1219
1220 #ifdef CONFIG_HWMON
1221 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
1222 #endif
1223 };
1224
1225 static const struct mv3310_chip mv2110_type = {
1226 .init_supported_interfaces = mv2110_init_supported_interfaces,
1227 .get_mactype = mv2110_get_mactype,
1228 .set_mactype = mv2110_set_mactype,
1229 .select_mactype = mv2110_select_mactype,
1230
1231 .mactypes = mv2110_mactypes,
1232 .n_mactypes = ARRAY_SIZE(mv2110_mactypes),
1233
1234 #ifdef CONFIG_HWMON
1235 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
1236 #endif
1237 };
1238
1239 static const struct mv3310_chip mv2111_type = {
1240 .init_supported_interfaces = mv2111_init_supported_interfaces,
1241 .get_mactype = mv2110_get_mactype,
1242 .set_mactype = mv2110_set_mactype,
1243 .select_mactype = mv2110_select_mactype,
1244
1245 .mactypes = mv2110_mactypes,
1246 .n_mactypes = ARRAY_SIZE(mv2110_mactypes),
1247
1248 #ifdef CONFIG_HWMON
1249 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
1250 #endif
1251 };
1252
mv3310_get_number_of_ports(struct phy_device * phydev)1253 static int mv3310_get_number_of_ports(struct phy_device *phydev)
1254 {
1255 int ret;
1256
1257 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO);
1258 if (ret < 0)
1259 return ret;
1260
1261 ret &= MV_PCS_PORT_INFO_NPORTS_MASK;
1262 ret >>= MV_PCS_PORT_INFO_NPORTS_SHIFT;
1263
1264 return ret + 1;
1265 }
1266
mv3310_match_phy_device(struct phy_device * phydev)1267 static int mv3310_match_phy_device(struct phy_device *phydev)
1268 {
1269 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1270 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
1271 return 0;
1272
1273 return mv3310_get_number_of_ports(phydev) == 1;
1274 }
1275
mv3340_match_phy_device(struct phy_device * phydev)1276 static int mv3340_match_phy_device(struct phy_device *phydev)
1277 {
1278 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1279 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
1280 return 0;
1281
1282 return mv3310_get_number_of_ports(phydev) == 4;
1283 }
1284
mv211x_match_phy_device(struct phy_device * phydev,bool has_5g)1285 static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g)
1286 {
1287 int val;
1288
1289 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1290 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110)
1291 return 0;
1292
1293 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED);
1294 if (val < 0)
1295 return val;
1296
1297 return !!(val & MDIO_PCS_SPEED_5G) == has_5g;
1298 }
1299
mv2110_match_phy_device(struct phy_device * phydev)1300 static int mv2110_match_phy_device(struct phy_device *phydev)
1301 {
1302 return mv211x_match_phy_device(phydev, true);
1303 }
1304
mv2111_match_phy_device(struct phy_device * phydev)1305 static int mv2111_match_phy_device(struct phy_device *phydev)
1306 {
1307 return mv211x_match_phy_device(phydev, false);
1308 }
1309
mv3110_get_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)1310 static void mv3110_get_wol(struct phy_device *phydev,
1311 struct ethtool_wolinfo *wol)
1312 {
1313 int ret;
1314
1315 wol->supported = WAKE_MAGIC;
1316 wol->wolopts = 0;
1317
1318 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL);
1319 if (ret < 0)
1320 return;
1321
1322 if (ret & MV_V2_WOL_CTRL_MAGIC_PKT_EN)
1323 wol->wolopts |= WAKE_MAGIC;
1324 }
1325
mv3110_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)1326 static int mv3110_set_wol(struct phy_device *phydev,
1327 struct ethtool_wolinfo *wol)
1328 {
1329 int ret;
1330
1331 if (wol->wolopts & WAKE_MAGIC) {
1332 /* Enable the WOL interrupt */
1333 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1334 MV_V2_PORT_INTR_MASK,
1335 MV_V2_PORT_INTR_STS_WOL_EN);
1336 if (ret < 0)
1337 return ret;
1338
1339 /* Store the device address for the magic packet */
1340 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1341 MV_V2_MAGIC_PKT_WORD2,
1342 ((phydev->attached_dev->dev_addr[5] << 8) |
1343 phydev->attached_dev->dev_addr[4]));
1344 if (ret < 0)
1345 return ret;
1346
1347 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1348 MV_V2_MAGIC_PKT_WORD1,
1349 ((phydev->attached_dev->dev_addr[3] << 8) |
1350 phydev->attached_dev->dev_addr[2]));
1351 if (ret < 0)
1352 return ret;
1353
1354 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1355 MV_V2_MAGIC_PKT_WORD0,
1356 ((phydev->attached_dev->dev_addr[1] << 8) |
1357 phydev->attached_dev->dev_addr[0]));
1358 if (ret < 0)
1359 return ret;
1360
1361 /* Clear WOL status and enable magic packet matching */
1362 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1363 MV_V2_WOL_CTRL,
1364 MV_V2_WOL_CTRL_MAGIC_PKT_EN |
1365 MV_V2_WOL_CTRL_CLEAR_STS);
1366 if (ret < 0)
1367 return ret;
1368 } else {
1369 /* Disable magic packet matching & reset WOL status bit */
1370 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1371 MV_V2_WOL_CTRL,
1372 MV_V2_WOL_CTRL_MAGIC_PKT_EN,
1373 MV_V2_WOL_CTRL_CLEAR_STS);
1374 if (ret < 0)
1375 return ret;
1376 }
1377
1378 /* Reset the clear WOL status bit as it does not self-clear */
1379 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
1380 MV_V2_WOL_CTRL,
1381 MV_V2_WOL_CTRL_CLEAR_STS);
1382 }
1383
1384 static struct phy_driver mv3310_drivers[] = {
1385 {
1386 .phy_id = MARVELL_PHY_ID_88X3310,
1387 .phy_id_mask = MARVELL_PHY_ID_MASK,
1388 .match_phy_device = mv3310_match_phy_device,
1389 .name = "mv88x3310",
1390 .driver_data = &mv3310_type,
1391 .get_features = mv3310_get_features,
1392 .config_init = mv3310_config_init,
1393 .probe = mv3310_probe,
1394 .suspend = mv3310_suspend,
1395 .resume = mv3310_resume,
1396 .config_aneg = mv3310_config_aneg,
1397 .aneg_done = mv3310_aneg_done,
1398 .read_status = mv3310_read_status,
1399 .get_tunable = mv3310_get_tunable,
1400 .set_tunable = mv3310_set_tunable,
1401 .remove = mv3310_remove,
1402 .set_loopback = genphy_c45_loopback,
1403 .get_wol = mv3110_get_wol,
1404 .set_wol = mv3110_set_wol,
1405 },
1406 {
1407 .phy_id = MARVELL_PHY_ID_88X3310,
1408 .phy_id_mask = MARVELL_PHY_ID_MASK,
1409 .match_phy_device = mv3340_match_phy_device,
1410 .name = "mv88x3340",
1411 .driver_data = &mv3340_type,
1412 .get_features = mv3310_get_features,
1413 .config_init = mv3310_config_init,
1414 .probe = mv3310_probe,
1415 .suspend = mv3310_suspend,
1416 .resume = mv3310_resume,
1417 .config_aneg = mv3310_config_aneg,
1418 .aneg_done = mv3310_aneg_done,
1419 .read_status = mv3310_read_status,
1420 .get_tunable = mv3310_get_tunable,
1421 .set_tunable = mv3310_set_tunable,
1422 .remove = mv3310_remove,
1423 .set_loopback = genphy_c45_loopback,
1424 },
1425 {
1426 .phy_id = MARVELL_PHY_ID_88E2110,
1427 .phy_id_mask = MARVELL_PHY_ID_MASK,
1428 .match_phy_device = mv2110_match_phy_device,
1429 .name = "mv88e2110",
1430 .driver_data = &mv2110_type,
1431 .probe = mv3310_probe,
1432 .suspend = mv3310_suspend,
1433 .resume = mv3310_resume,
1434 .config_init = mv3310_config_init,
1435 .config_aneg = mv3310_config_aneg,
1436 .aneg_done = mv3310_aneg_done,
1437 .read_status = mv3310_read_status,
1438 .get_tunable = mv3310_get_tunable,
1439 .set_tunable = mv3310_set_tunable,
1440 .remove = mv3310_remove,
1441 .set_loopback = genphy_c45_loopback,
1442 .get_wol = mv3110_get_wol,
1443 .set_wol = mv3110_set_wol,
1444 },
1445 {
1446 .phy_id = MARVELL_PHY_ID_88E2110,
1447 .phy_id_mask = MARVELL_PHY_ID_MASK,
1448 .match_phy_device = mv2111_match_phy_device,
1449 .name = "mv88e2111",
1450 .driver_data = &mv2111_type,
1451 .probe = mv3310_probe,
1452 .suspend = mv3310_suspend,
1453 .resume = mv3310_resume,
1454 .config_init = mv3310_config_init,
1455 .config_aneg = mv3310_config_aneg,
1456 .aneg_done = mv3310_aneg_done,
1457 .read_status = mv3310_read_status,
1458 .get_tunable = mv3310_get_tunable,
1459 .set_tunable = mv3310_set_tunable,
1460 .remove = mv3310_remove,
1461 .set_loopback = genphy_c45_loopback,
1462 },
1463 };
1464
1465 module_phy_driver(mv3310_drivers);
1466
1467 static const struct mdio_device_id __maybe_unused mv3310_tbl[] = {
1468 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
1469 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
1470 { },
1471 };
1472 MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
1473 MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver");
1474 MODULE_LICENSE("GPL");
1475