1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 5 * All rights reserved. 6 * 7 * Developed by Semihalf. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of MARVELL nor the names of contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 #ifndef _MVWIN_H_ 35 #define _MVWIN_H_ 36 37 /* 38 * Decode windows addresses. 39 * 40 * All decoding windows must be aligned to their size, which has to be 41 * a power of 2. 42 */ 43 44 /* 45 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA) 46 */ 47 48 /* SoC Regs */ 49 #define MV_PHYS_BASE 0xF1000000 50 #define MV_SIZE (1024 * 1024) /* 1 MB */ 51 52 /* SRAM */ 53 #define MV_CESA_SRAM_BASE 0xF1100000 54 55 /* 56 * External devices: 0x80000000, 1 GB (VA == PA) 57 * Includes Device Bus, PCI and PCIE. 58 */ 59 #define MV_PCI_PORTS 1 /* 1x PCIE -> worst case */ 60 61 /* PCI/PCIE Memory */ 62 #define MV_PCI_MEM_PHYS_BASE 0x80000000 63 #define MV_PCI_MEM_SIZE (512 * 1024 * 1024) /* 512 MB */ 64 #define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 65 #define MV_PCI_MEM_SLICE_SIZE (MV_PCI_MEM_SIZE / MV_PCI_PORTS) 66 /* PCI/PCIE I/O */ 67 #define MV_PCI_IO_PHYS_BASE 0xBF000000 68 #define MV_PCI_IO_SIZE (16 * 1024 * 1024) /* 16 MB */ 69 #define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 70 #define MV_PCI_IO_SLICE_SIZE (MV_PCI_IO_SIZE / MV_PCI_PORTS) 71 #define MV_PCI_VA_MEM_BASE 0 72 #define MV_PCI_VA_IO_BASE 0 73 74 /* 75 * Device Bus (VA == PA) 76 */ 77 #define MV_DEV_BOOT_BASE 0xF9300000 78 #define MV_DEV_BOOT_SIZE (1024 * 1024) /* 1 MB */ 79 80 #define MV_DEV_CS0_BASE 0xF9400000 81 #define MV_DEV_CS0_SIZE (1024 * 1024) /* 1 MB */ 82 83 #define MV_DEV_CS1_BASE 0xF9500000 84 #define MV_DEV_CS1_SIZE (32 * 1024 * 1024) /* 32 MB */ 85 86 #define MV_DEV_CS2_BASE 0xFB500000 87 #define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */ 88 89 /* 90 * Integrated SoC peripherals addresses 91 */ 92 #define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 93 #define MV_DDR_CADR_BASE_ARMV7 (MV_BASE + 0x20180) 94 #define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 95 #define MV_MPP_BASE (MV_BASE + 0x10000) 96 97 #define MV_MISC_BASE (MV_BASE + 0x18200) 98 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 99 #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 100 #define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700) 101 102 #define MV_CPU_CONTROL_BASE_ARMV7 (MV_MBUS_BRIDGE_BASE + 0x1800) 103 #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 104 105 #define MV_PCI_BASE (MV_BASE + 0x30000) 106 #define MV_PCI_SIZE 0x2000 107 108 #define MV_PCIE_BASE_ARMADA38X (MV_BASE + 0x80000) 109 #define MV_PCIE_BASE (MV_BASE + 0x40000) 110 #define MV_PCIE_SIZE 0x2000 111 #define MV_SDIO_BASE (MV_BASE + 0x90000) 112 #define MV_SDIO_SIZE 0x10000 113 114 /* 115 * Decode windows definitions and macros 116 */ 117 #define MV_WIN_CPU_CTRL_ARMV7(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) 118 #define MV_WIN_CPU_BASE_ARMV7(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4) 119 #define MV_WIN_CPU_REMAP_LO_ARMV7(n) (0x10 * (n) + 0x008) 120 #define MV_WIN_CPU_REMAP_HI_ARMV7(n) (0x10 * (n) + 0x00C) 121 122 #define MV_WIN_CPU_CTRL_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 123 #define MV_WIN_CPU_BASE_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 124 #define MV_WIN_CPU_REMAP_LO_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 125 #define MV_WIN_CPU_REMAP_HI_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 126 127 #define MV_WIN_CPU_MAX 8 128 #define MV_WIN_CPU_MAX_ARMV7 20 129 130 #define MV_WIN_CPU_ATTR_SHIFT 8 131 #define MV_WIN_CPU_TARGET_SHIFT 4 132 #define MV_WIN_CPU_ENABLE_BIT 1 133 134 #define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 135 #define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 136 #define MV_WIN_DDR_MAX 4 137 138 /* 139 * These values are valid only for peripherals decoding windows 140 * Bit in ATTR is zeroed according to CS bank number 141 */ 142 #define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs))) 143 #define MV_WIN_DDR_TARGET 0x0 144 145 #define MV_WIN_CESA_TARGET 3 146 #define MV_WIN_CESA_ATTR(eng_sel) 0 147 148 #define MV_WIN_CESA_TARGET_ARMADAXP 9 149 /* 150 * Bits [2:3] of cesa attribute select engine: 151 * eng_sel: 152 * 1: engine1 153 * 2: engine0 154 */ 155 #define MV_WIN_CESA_ATTR_ARMADAXP(eng_sel) (1 | ((eng_sel) << 2)) 156 #define MV_WIN_CESA_TARGET_ARMADA38X 9 157 /* 158 * Bits [1:0] = Data swapping 159 * 0x0 = Byte swap 160 * 0x1 = No swap 161 * 0x2 = Byte and word swap 162 * 0x3 = Word swap 163 * Bits [4:2] = CESA select: 164 * 0x6 = CESA0 165 * 0x5 = CESA1 166 */ 167 #define MV_WIN_CESA_ATTR_ARMADA38X(eng_sel) (0x11 | (1 << (3 - (eng_sel)))) 168 /* CESA TDMA address decoding registers */ 169 #define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xA04) 170 #define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xA00) 171 #define MV_WIN_CESA_MAX 4 172 173 #define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320) 174 #define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324) 175 #define MV_WIN_USB_MAX 4 176 177 #define MV_WIN_USB3_CTRL(n) (0x8 * (n) + 0x4000) 178 #define MV_WIN_USB3_BASE(n) (0x8 * (n) + 0x4004) 179 #define MV_WIN_USB3_MAX 8 180 181 #define MV_WIN_NETA_OFFSET 0x2000 182 #define MV_WIN_NETA_BASE(n) MV_WIN_ETH_BASE(n) + MV_WIN_NETA_OFFSET 183 184 #define MV_WIN_CESA_OFFSET 0x2000 185 186 #define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 187 #define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 188 #define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 189 #define MV_WIN_ETH_MAX 6 190 191 #define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 192 #define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 193 #define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 194 #define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 195 #define MV_WIN_IDMA_MAX 8 196 #define MV_IDMA_CHAN_MAX 4 197 198 #define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100) 199 #define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100) 200 #define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100) 201 #define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100) 202 #define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) 203 #define MV_WIN_XOR_MAX 8 204 #define MV_XOR_CHAN_MAX 2 205 #define MV_XOR_NON_REMAP 4 206 207 #define MV_WIN_PCIE_TARGET_ARMADAXP(n) (4 + (4 * ((n) % 2))) 208 #define MV_WIN_PCIE_MEM_ATTR_ARMADAXP(n) (0xE8 + (0x10 * ((n) / 2))) 209 #define MV_WIN_PCIE_IO_ATTR_ARMADAXP(n) (0xE0 + (0x10 * ((n) / 2))) 210 #define MV_WIN_PCIE_TARGET_ARMADA38X(n) ((n) == 0 ? 8 : 4) 211 #define MV_WIN_PCIE_MEM_ATTR_ARMADA38X(n) ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20))) 212 #define MV_WIN_PCIE_IO_ATTR_ARMADA38X(n) ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20))) 213 #define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2))) 214 #define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2))) 215 #define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2))) 216 217 #define MV_WIN_PCI_TARGET 3 218 #define MV_WIN_PCI_MEM_ATTR 0x59 219 #define MV_WIN_PCI_IO_ATTR 0x51 220 221 #define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 222 (n) + 1) + 0x1820) 223 #define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 224 (n) + 1) + 0x1824) 225 #define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 226 (n) + 1) + 0x182C) 227 #define MV_WIN_PCIE_MAX 6 228 229 #define MV_PCIE_BAR_CTRL(n) (0x04 * (n) + 0x1800) 230 #define MV_PCIE_BAR_BASE(n) (0x08 * ((n) < 3 ? (n) : 4) + 0x0010) 231 #define MV_PCIE_BAR_BASE_H(n) (0x08 * (n) + 0x0014) 232 #define MV_PCIE_BAR_MAX 4 233 #define MV_PCIE_BAR_64BIT (0x4) 234 #define MV_PCIE_BAR_PREFETCH_EN (0x8) 235 236 #define MV_PCIE_CONTROL (0x1a00) 237 #define MV_PCIE_ROOT_CMPLX (1 << 1) 238 239 #define MV_WIN_SATA_CTRL_ARMADA38X(n) (0x10 * (n) + 0x60) 240 #define MV_WIN_SATA_BASE_ARMADA38X(n) (0x10 * (n) + 0x64) 241 #define MV_WIN_SATA_SIZE_ARMADA38X(n) (0x10 * (n) + 0x68) 242 #define MV_WIN_SATA_MAX_ARMADA38X 4 243 #define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) 244 #define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) 245 #define MV_WIN_SATA_MAX 4 246 247 #define MV_WIN_SDHCI_CTRL(n) (0x8 * (n) + 0x4080) 248 #define MV_WIN_SDHCI_BASE(n) (0x8 * (n) + 0x4084) 249 #define MV_WIN_SDHCI_MAX 8 250 251 #define MV_BOOTROM_MEM_ADDR 0xFFF00000 252 #define MV_BOOTROM_WIN_SIZE 0xF 253 #define MV_CPU_SUBSYS_REGS_LEN 0x100 254 255 #define IO_WIN_9_CTRL_OFFSET 0x98 256 #define IO_WIN_9_BASE_OFFSET 0x9C 257 258 /* Mbus decoding unit IDs and attributes */ 259 #define MBUS_BOOTROM_TGT_ID 0x1 260 #define MBUS_BOOTROM_ATTR 0x1D 261 262 /* Internal Units Sync Barrier Control Register */ 263 #define MV_SYNC_BARRIER_CTRL 0x84 264 #define MV_SYNC_BARRIER_CTRL_ALL 0xFFFF 265 266 /* IO Window Control Register fields */ 267 #define IO_WIN_SIZE_SHIFT 16 268 #define IO_WIN_SIZE_MASK 0xFFFF 269 #define IO_WIN_COH_ATTR_MASK (0xF << 12) 270 #define IO_WIN_ATTR_SHIFT 8 271 #define IO_WIN_ATTR_MASK 0xFF 272 #define IO_WIN_TGT_SHIFT 4 273 #define IO_WIN_TGT_MASK 0xF 274 #define IO_WIN_SYNC_SHIFT 1 275 #define IO_WIN_SYNC_MASK 0x1 276 #define IO_WIN_ENA_SHIFT 0 277 #define IO_WIN_ENA_MASK 0x1 278 279 #define WIN_REG_IDX_RD(pre,reg,off,base) \ 280 static __inline uint32_t \ 281 pre ## _ ## reg ## _read(int i) \ 282 { \ 283 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 284 } 285 286 #define WIN_REG_IDX_RD2(pre,reg,off,base) \ 287 static __inline uint32_t \ 288 pre ## _ ## reg ## _read(int i, int j) \ 289 { \ 290 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 291 } \ 292 293 #define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 294 static __inline uint32_t \ 295 pre ## _ ## reg ## _read(uint32_t base, int i) \ 296 { \ 297 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 298 } 299 300 #define WIN_REG_BASE_IDX_RD2(pre,reg,off) \ 301 static __inline uint32_t \ 302 pre ## _ ## reg ## _read(uint32_t base, int i, int j) \ 303 { \ 304 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 305 } 306 307 #define WIN_REG_IDX_WR(pre,reg,off,base) \ 308 static __inline void \ 309 pre ## _ ## reg ## _write(int i, uint32_t val) \ 310 { \ 311 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 312 } 313 314 #define WIN_REG_IDX_WR2(pre,reg,off,base) \ 315 static __inline void \ 316 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \ 317 { \ 318 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 319 } 320 321 #define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 322 static __inline void \ 323 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 324 { \ 325 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 326 } 327 328 #define WIN_REG_BASE_IDX_WR2(pre,reg,off) \ 329 static __inline void \ 330 pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \ 331 { \ 332 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 333 } 334 335 #define WIN_REG_RD(pre,reg,off,base) \ 336 static __inline uint32_t \ 337 pre ## _ ## reg ## _read(void) \ 338 { \ 339 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 340 } 341 342 #define WIN_REG_BASE_RD(pre,reg,off) \ 343 static __inline uint32_t \ 344 pre ## _ ## reg ## _read(uint32_t base) \ 345 { \ 346 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 347 } 348 349 #define WIN_REG_WR(pre,reg,off,base) \ 350 static __inline void \ 351 pre ## _ ## reg ## _write(uint32_t val) \ 352 { \ 353 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 354 } 355 356 #define WIN_REG_BASE_WR(pre,reg,off) \ 357 static __inline void \ 358 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 359 { \ 360 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 361 } 362 363 #endif /* _MVWIN_H_ */ 364