1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 /*
27 * MII overrides for Marvell PHYs.
28 */
29
30 #include <sys/types.h>
31 #include <sys/ddi.h>
32 #include <sys/sunddi.h>
33 #include <sys/mii.h>
34 #include <sys/miiregs.h>
35 #include "miipriv.h"
36
37 #define MVPHY_PSC MII_VENDOR(0) /* PHY specific control */
38
39 #define MV_PSC_TXFIFO_DEPTH 0xc000
40 #define MV_PSC_RXFIFO_DEPTH 0x3000
41 #define MV_PSC_ASSERT_CRS_TX 0x0800 /* older PHYs */
42 #define MV_PSC_DOWNSHIFT_EN 0x0800 /* newer PHYs */
43 #define MV_PSC_FORCE_GOOD_LINK 0x0400
44 #define MV_PSC_DIS_SCRAMBLER 0x0200
45 #define MV_PSC_MII_5BIT_EN 0x0100
46 #define MV_PSC_EN_DETECT_MASK 0x0300
47 #define MV_PSC_EN_EXT_DISTANCE 0x0080
48 #define MV_PSC_AUTO_X_MODE 0x0060
49 #define MV_PSC_AUTO_X_1000T 0x0040
50 #define MV_PSC_MDIX_MANUAL 0x0010
51 #define MV_PSC_MDI_MANUAL 0x0000
52 #define MV_PSC_RGMII_POWER_UP 0x0008 /* 88E1116, 88E1149 page 2 */
53 #define MV_PSC_POWER_DOWN 0x0004 /* 88E1116 page 0 */
54
55 #define MV_PSC_MODE_MASK 0x0380 /* 88E1112 page 2 */
56 #define MV_PSC_MODE_AUTO 0x0180
57 #define MV_PSC_MODE_COPPER 0x0280
58 #define MV_PSC_MODE_1000BASEX 0x0380
59
60 #define MV_PSC_DIS_125CLK 0x0010
61 #define MV_PSC_MAC_PDOWN 0x0008
62 #define MV_PSC_SQE_TEST 0x0004
63 #define MV_PSC_POL_REVERSE 0x0002
64 #define MV_PSC_JABBER_DIS 0x0001
65
66 /* 88E3016 */
67 #define MV_PSC_AUTO_MDIX 0x0030
68 #define MV_PSC_SIGDET_POLARITY 0x0040
69 #define MV_PSC_EXT_DIST 0x0080
70 #define MV_PSC_FEFI_DIS 0x0100
71 #define MV_PSC_NLP_GEN_DIS 0x0800
72 #define MV_PSC_LPNP 0x1000
73 #define MV_PSC_NLP_CHK_DIS 0x2000
74 #define MV_PSC_EN_DETECT 0x4000
75
76 /* LED control page 3, 88E1116, 88E1149 */
77 #define MV_PSC_LED_LOS_MASK 0xf000
78 #define MV_PSC_LED_INIT_MASK 0x0f00
79 #define MV_PSC_LED_STA1_MASK 0x00f0
80 #define MV_PSC_LED_STA0_MASK 0x000f
81
82 #define MV_PSC_LED_LOS_CTRL(x) (((x) << 12) & MV_PSC_LED_LOS_MASK)
83 #define MV_PSC_LED_INIT_CTRL(x) (((x) << 8) & MV_PSC_LED_INIT_MASK)
84 #define MV_PSC_LED_STA1_CTRL(x) (((x) << 4) & MV_PSC_LED_STA1_MASK)
85 #define MV_PSC_LED_STA0_CTRL(x) (((x)) & MV_PSC_LED_STA0_MASK)
86
87
88 #define MVPHY_INTEN MII_VENDOR(2) /* Interrupt enable */
89
90 #define MV_INTEN_PULSE_MASK 0x7000
91 #define MV_INTEN_PULSE_NOSTR 0x0000
92 #define MV_INTEN_PULSE_21MS 0x1000
93 #define MV_INTEN_PULSE_42MS 0x2000
94 #define MV_INTEN_PULSE_84MS 0x3000
95 #define MV_INTEN_PULSE_170MS 0x4000
96 #define MV_INTEN_PULSE_340MS 0x5000
97 #define MV_INTEN_PULSE_670MS 0x6000
98 #define MV_INTEN_PULSE_1300MS 0x7000
99
100 #define MV_INTEN_BLINK_MASK 0x0700
101 #define MV_INTEN_BLINK_42MS 0x0000
102 #define MV_INTEN_BLINK_84MS 0x0100
103 #define MV_INTEN_BLINK_170MS 0x0200
104 #define MV_INTEN_BLINK_340MS 0x0300
105 #define MV_INTEN_BLINK_670MS 0x0400
106
107 #define MVPHY_INTST MII_VENDOR(3) /* Interrupt status */
108
109 #define MVPHY_EPSC MII_VENDOR(4) /* Ext. phy specific control */
110 #define MV_EPSC_DOWN_NO_IDLE 0x8000
111 #define MV_EPSC_FIBER_LOOPBACK 0x4000
112 #define MV_EPSC_TX_CLK_2_5 0x0060
113 #define MV_EPSC_TX_CLK_25 0x0070
114 #define MV_EPSC_TX_CLK_0 0x0000
115
116 #define MVPHY_EADR MII_VENDOR(6) /* Extended address */
117
118 #define MVPHY_LED_PSEL MII_VENDOR(6) /* 88E3016 */
119 #define MV_LED_PSEL_COLX 0x00
120 #define MV_LED_PSEL_ERROR 0x01
121 #define MV_LED_PSEL_DUPLEX 0x02
122 #define MV_LED_PSEL_DP_COL 0x03
123 #define MV_LED_PSEL_SPEED 0x04
124 #define MV_LED_PSEL_LINK 0x05
125 #define MV_LED_PSEL_TX 0x06
126 #define MV_LED_PSEL_RX 0x07
127 #define MV_LED_PSEL_ACT 0x08
128 #define MV_LED_PSEL_LNK_RX 0x09
129 #define MV_LED_PSEL_LNK_ACT 0x0a
130 #define MV_LED_PSEL_ACT_BL 0x0b
131 #define MV_LED_PSEL_TX_BL 0x0c
132 #define MV_LED_PSEL_RX_BL 0x0d
133 #define MV_LED_PSEL_COLX_BL 0x0e
134 #define MV_LED_PSEL_INACT 0x0f
135 #define MV_LED_PSEL_LED2(x) (x << 8)
136 #define MV_LED_PSEL_LED1(x) (x << 4)
137 #define MV_LED_PSEL_LED0(x) (x << 0)
138
139 #define MVPHY_PAGE_ADDR MII_VENDOR(13)
140 #define MVPHY_PAGE_DATA MII_VENDOR(14)
141
142
143 #define MVPHY_EPSS MII_VENDOR(11) /* Ext. phy specific status */
144
145 #define MV_EPSS_FCAUTOSEL 0x8000 /* fiber/copper autosel */
146 #define MV_EPSS_FCRESOL 0x1000 /* fiber/copper resol */
147
148 static int
mvphy_reset_88e3016(phy_handle_t * ph)149 mvphy_reset_88e3016(phy_handle_t *ph)
150 {
151 uint16_t reg;
152 int rv;
153
154 rv = phy_reset(ph);
155
156 reg = phy_read(ph, MVPHY_PSC);
157
158 reg |= MV_PSC_AUTO_MDIX;
159 reg &= ~(MV_PSC_EN_DETECT | MV_PSC_DIS_SCRAMBLER);
160 reg |= MV_PSC_LPNP;
161
162 /* enable class A driver for Yukon FE+ A0. */
163 PHY_SET(ph, MII_VENDOR(12), 0x0001);
164
165 phy_write(ph, MVPHY_PSC, reg);
166
167 /* LED2 = ACT blink, LED1 = LINK), LED0 = SPEED */
168 phy_write(ph, MVPHY_LED_PSEL,
169 MV_LED_PSEL_LED2(MV_LED_PSEL_ACT_BL) |
170 MV_LED_PSEL_LED1(MV_LED_PSEL_LINK) |
171 MV_LED_PSEL_LED0(MV_LED_PSEL_SPEED));
172
173 /* calibration, values not documented */
174 phy_write(ph, MVPHY_PAGE_ADDR, 17);
175 phy_write(ph, MVPHY_PAGE_DATA, 0x3f60);
176
177 /* Normal BMCR reset now */
178 return (rv);
179 }
180
181 static int
mvphy_loop_88e3016(phy_handle_t * ph)182 mvphy_loop_88e3016(phy_handle_t *ph)
183 {
184 uint16_t reg;
185 int rv;
186
187 rv = phy_loop(ph);
188
189 /*
190 * The PHY apparently needs a soft reset, but supposedly
191 * retains most of the other critical state.
192 */
193 reg = phy_read(ph, MII_CONTROL);
194 reg |= MII_CONTROL_RESET;
195 phy_write(ph, MII_CONTROL, reg);
196
197 reg = phy_read(ph, MVPHY_PSC);
198 reg &= ~(MV_PSC_AUTO_MDIX);
199 reg &= ~(MV_PSC_EN_DETECT | MV_PSC_DIS_SCRAMBLER);
200 reg |= MV_PSC_LPNP;
201
202 phy_write(ph, MVPHY_PSC, reg);
203
204 return (rv);
205 }
206
207 static int
mvphy_reset_88e3082(phy_handle_t * ph)208 mvphy_reset_88e3082(phy_handle_t *ph)
209 {
210 uint16_t reg;
211 int rv;
212
213 rv = phy_reset(ph);
214
215 reg = phy_read(ph, MVPHY_PSC);
216 reg |= (MV_PSC_AUTO_X_MODE >> 1);
217 reg |= MV_PSC_ASSERT_CRS_TX;
218 reg &= ~MV_PSC_POL_REVERSE;
219 phy_write(ph, MVPHY_PSC, reg);
220
221 return (rv);
222 }
223
224 static int
mvphy_reset_88e1149(phy_handle_t * ph)225 mvphy_reset_88e1149(phy_handle_t *ph)
226 {
227 uint16_t reg;
228 int rv;
229
230 /* make sure that this PHY uses page 0 (copper) */
231 phy_write(ph, MVPHY_EADR, 0);
232
233 reg = phy_read(ph, MVPHY_PSC);
234 /* Disable energy detect mode */
235 reg &= ~MV_PSC_EN_DETECT_MASK;
236 reg |= MV_PSC_AUTO_X_MODE;
237 reg |= MV_PSC_DOWNSHIFT_EN;
238 reg &= ~MV_PSC_POL_REVERSE;
239 phy_write(ph, MVPHY_PSC, reg);
240
241 rv = phy_reset(ph);
242
243 phy_write(ph, MVPHY_EADR, 2);
244 PHY_SET(ph, MVPHY_PSC, MV_PSC_RGMII_POWER_UP);
245
246 /*
247 * Fix for signal amplitude in 10BASE-T, undocumented.
248 * This is from the Marvell reference source code.
249 */
250 phy_write(ph, MVPHY_EADR, 255);
251 phy_write(ph, 0x18, 0xaa99);
252 phy_write(ph, 0x17, 0x2011);
253
254 if (MII_PHY_REV(ph->phy_id) == 0) {
255 /*
256 * EC_U: IEEE A/B 1000BASE-T symmetry failure
257 *
258 * EC_U is rev 0, Ultra 2 is rev 1 (at least the
259 * unit I have), so we trigger on revid.
260 */
261 phy_write(ph, 0x18, 0xa204);
262 phy_write(ph, 0x17, 0x2002);
263 }
264
265 /* page 3 is led control */
266 phy_write(ph, MVPHY_EADR, 3);
267 phy_write(ph, MVPHY_PSC,
268 MV_PSC_LED_LOS_CTRL(1) | /* link/act */
269 MV_PSC_LED_INIT_CTRL(8) | /* 10 Mbps */
270 MV_PSC_LED_STA1_CTRL(7) | /* 100 Mbps */
271 MV_PSC_LED_STA0_CTRL(7)); /* 1000 Mbps */
272 phy_write(ph, MVPHY_INTEN, 0);
273
274 phy_write(ph, MVPHY_EADR, 0);
275
276 /*
277 * Weird... undocumented logic in the Intel e1000g driver.
278 * I'm not sure what these values really do.
279 */
280 phy_write(ph, MVPHY_PAGE_ADDR, 3);
281 phy_write(ph, MVPHY_PAGE_DATA, 0);
282
283 return (rv);
284 }
285
286 static int
mvphy_reset_88e1116(phy_handle_t * ph)287 mvphy_reset_88e1116(phy_handle_t *ph)
288 {
289 uint16_t reg;
290
291 /* make sure that this PHY uses page 0 (copper) */
292 phy_write(ph, MVPHY_EADR, 0);
293
294 reg = phy_read(ph, MVPHY_PSC);
295
296 reg &= ~MV_PSC_POWER_DOWN;
297 /* Disable energy detect mode */
298 reg &= ~MV_PSC_EN_DETECT_MASK;
299 reg |= MV_PSC_AUTO_X_MODE;
300 reg |= MV_PSC_ASSERT_CRS_TX;
301 reg &= ~MV_PSC_POL_REVERSE;
302 phy_write(ph, MVPHY_PSC, reg);
303
304 phy_write(ph, MVPHY_EADR, 2);
305 PHY_SET(ph, MVPHY_PSC, MV_PSC_RGMII_POWER_UP);
306
307 /* page 3 is led control */
308 phy_write(ph, MVPHY_EADR, 3);
309 phy_write(ph, MVPHY_PSC,
310 MV_PSC_LED_LOS_CTRL(1) | /* link/act */
311 MV_PSC_LED_INIT_CTRL(8) | /* 10 Mbps */
312 MV_PSC_LED_STA1_CTRL(7) | /* 100 Mbps */
313 MV_PSC_LED_STA0_CTRL(7)); /* 1000 Mbps */
314 phy_write(ph, MVPHY_INTEN, 0);
315
316 phy_write(ph, MVPHY_EADR, 0);
317
318 return (phy_reset(ph));
319 }
320
321 static int
mvphy_reset_88e1118(phy_handle_t * ph)322 mvphy_reset_88e1118(phy_handle_t *ph)
323 {
324 uint16_t reg;
325 reg = phy_read(ph, MVPHY_PSC);
326
327 /* Disable energy detect mode */
328 reg &= ~MV_PSC_EN_DETECT_MASK;
329 reg |= MV_PSC_AUTO_X_MODE;
330 reg |= MV_PSC_ASSERT_CRS_TX;
331 reg &= ~MV_PSC_POL_REVERSE;
332 phy_write(ph, MVPHY_PSC, reg);
333
334 return (phy_reset(ph));
335 }
336
337 static int
mvphy_reset_88e1111(phy_handle_t * ph)338 mvphy_reset_88e1111(phy_handle_t *ph)
339 {
340 uint16_t reg;
341
342 reg = phy_read(ph, MVPHY_PSC);
343
344 /* Disable energy detect mode */
345 reg &= ~MV_PSC_EN_DETECT_MASK;
346 reg |= MV_PSC_AUTO_X_MODE;
347 reg |= MV_PSC_ASSERT_CRS_TX;
348 reg &= ~MV_PSC_POL_REVERSE;
349
350 phy_write(ph, MVPHY_PSC, reg);
351
352 /* force TX CLOCK to 25 MHz */
353 PHY_SET(ph, MVPHY_EPSC, MV_EPSC_TX_CLK_25);
354
355 return (phy_reset(ph));
356
357 }
358
359 static int
mvphy_reset_88e1112(phy_handle_t * ph)360 mvphy_reset_88e1112(phy_handle_t *ph)
361 {
362 uint16_t reg, page;
363
364 if (phy_read(ph, MVPHY_EPSS) & MV_EPSS_FCRESOL) {
365
366 /* interface indicates fiber */
367 PHY_CLR(ph, MVPHY_PSC, MV_PSC_AUTO_X_MODE);
368
369 page = phy_read(ph, MVPHY_EADR);
370
371 /* Go into locked 1000BASE-X mode */
372 page = phy_read(ph, MVPHY_EADR);
373 phy_write(ph, MVPHY_EADR, 2);
374 reg = phy_read(ph, MVPHY_PSC);
375 reg &= ~MV_PSC_MODE_MASK;
376 reg |= MV_PSC_MODE_1000BASEX;
377 phy_write(ph, MVPHY_PSC, reg);
378 phy_write(ph, MVPHY_EADR, page);
379
380 } else {
381 reg = phy_read(ph, MVPHY_PSC);
382
383 /* Disable energy detect mode */
384 reg &= ~MV_PSC_EN_DETECT_MASK;
385 reg |= MV_PSC_AUTO_X_MODE;
386 reg |= MV_PSC_ASSERT_CRS_TX;
387 reg &= ~MV_PSC_POL_REVERSE;
388 phy_write(ph, MVPHY_PSC, reg);
389 }
390
391 return (phy_reset(ph));
392 }
393
394 static int
mvphy_reset_88e1011(phy_handle_t * ph)395 mvphy_reset_88e1011(phy_handle_t *ph)
396 {
397 uint16_t reg;
398
399 if (phy_read(ph, MVPHY_EPSS) & MV_EPSS_FCRESOL) {
400
401 /* interface indicates fiber */
402 PHY_CLR(ph, MVPHY_PSC, MV_PSC_AUTO_X_MODE);
403
404 } else {
405 reg = phy_read(ph, MVPHY_PSC);
406 reg &= ~MV_PSC_AUTO_X_MODE;
407 reg |= MV_PSC_ASSERT_CRS_TX;
408 reg &= ~MV_PSC_POL_REVERSE;
409 phy_write(ph, MVPHY_PSC, reg);
410 }
411 /* force TX CLOCK to 25 MHz */
412 PHY_SET(ph, MVPHY_EPSC, MV_EPSC_TX_CLK_25);
413
414 return (phy_reset(ph));
415 }
416
417 static int
mvphy_reset(phy_handle_t * ph)418 mvphy_reset(phy_handle_t *ph)
419 {
420 uint16_t reg;
421
422 reg = phy_read(ph, MVPHY_PSC);
423
424 reg &= ~MV_PSC_AUTO_X_MODE;
425 reg |= MV_PSC_ASSERT_CRS_TX;
426 reg &= ~MV_PSC_POL_REVERSE;
427 phy_write(ph, MVPHY_PSC, reg);
428
429 PHY_SET(ph, MVPHY_EPSC, MV_EPSC_TX_CLK_25);
430
431 /* Normal BMCR reset now */
432 return (phy_reset(ph));
433 }
434
435 static int
mvphy_start(phy_handle_t * ph)436 mvphy_start(phy_handle_t *ph)
437 {
438 int rv;
439
440 rv = phy_start(ph);
441 /*
442 * If not autonegotiating, then we need to reset the PHY according to
443 * Marvell. I don't think this is according to the spec. Apparently
444 * the register states are not lost during this.
445 */
446 if ((rv == 0) && (!ph->phy_adv_aneg)) {
447 rv = ph->phy_reset(ph);
448 }
449 return (rv);
450 }
451
452 boolean_t
phy_marvell_probe(phy_handle_t * ph)453 phy_marvell_probe(phy_handle_t *ph)
454 {
455 switch (MII_PHY_MFG(ph->phy_id)) {
456 case MII_OUI_MARVELL:
457 ph->phy_vendor = "Marvell";
458 switch (MII_PHY_MODEL(ph->phy_id)) {
459 case MII_MODEL_MARVELL_88E1000:
460 case MII_MODEL_MARVELL_88E1000_2:
461 case MII_MODEL_MARVELL_88E1000_3:
462 ph->phy_model = "88E1000";
463 ph->phy_reset = mvphy_reset;
464 break;
465 case MII_MODEL_MARVELL_88E1011:
466 ph->phy_model = "88E1011";
467 ph->phy_reset = mvphy_reset_88e1011;
468 break;
469 case MII_MODEL_MARVELL_88E1111:
470 ph->phy_model = "88E1111";
471 ph->phy_reset = mvphy_reset_88e1111;
472 break;
473 case MII_MODEL_MARVELL_88E1112:
474 ph->phy_model = "88E1112";
475 ph->phy_reset = mvphy_reset_88e1112;
476 break;
477 case MII_MODEL_MARVELL_88E1116:
478 ph->phy_model = "88E1116";
479 ph->phy_reset = mvphy_reset_88e1116;
480 break;
481 case MII_MODEL_MARVELL_88E1116R:
482 ph->phy_model = "88E1116R";
483 ph->phy_reset = mvphy_reset;
484 break;
485 case MII_MODEL_MARVELL_88E1118:
486 ph->phy_model = "88E1118";
487 ph->phy_reset = mvphy_reset_88e1118;
488 break;
489 case MII_MODEL_MARVELL_88E1149:
490 ph->phy_model = "88E1149";
491 ph->phy_reset = mvphy_reset;
492 ph->phy_reset = mvphy_reset_88e1149;
493 break;
494 case MII_MODEL_MARVELL_88E3016:
495 ph->phy_model = "88E3016";
496 ph->phy_reset = mvphy_reset_88e3016;
497 ph->phy_loop = mvphy_loop_88e3016;
498 break;
499 case MII_MODEL_MARVELL_88E3082:
500 ph->phy_model = "88E3082";
501 ph->phy_reset = mvphy_reset_88e3082;
502 break;
503 default:
504 /* Unknown PHY model */
505 return (B_FALSE);
506 }
507 break;
508
509 default:
510 return (B_FALSE);
511 }
512
513 ph->phy_start = mvphy_start;
514
515 return (B_TRUE);
516 }
517