1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Marvell 88E6xxx Ethernet switch single-chip definition
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 */
7
8 #ifndef _MV88E6XXX_CHIP_H
9 #define _MV88E6XXX_CHIP_H
10
11 #include <linux/idr.h>
12 #include <linux/if_vlan.h>
13 #include <linux/irq.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/kthread.h>
16 #include <linux/phy.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/timecounter.h>
19 #include <net/dsa.h>
20
21 #define EDSA_HLEN 8
22 #define MV88E6XXX_N_FID 4096
23 #define MV88E6XXX_N_SID 64
24
25 #define MV88E6XXX_FID_STANDALONE 0
26 #define MV88E6XXX_FID_BRIDGED 1
27
28 /* PVT limits for 4-bit port and 5-bit switch */
29 #define MV88E6XXX_MAX_PVT_SWITCHES 32
30 #define MV88E6XXX_MAX_PVT_PORTS 16
31 #define MV88E6XXX_MAX_PVT_ENTRIES \
32 (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS)
33
34 #define MV88E6XXX_MAX_GPIO 16
35
36 enum mv88e6xxx_egress_mode {
37 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
38 MV88E6XXX_EGRESS_MODE_UNTAGGED,
39 MV88E6XXX_EGRESS_MODE_TAGGED,
40 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
41 };
42
43 enum mv88e6xxx_egress_direction {
44 MV88E6XXX_EGRESS_DIR_INGRESS,
45 MV88E6XXX_EGRESS_DIR_EGRESS,
46 };
47
48 enum mv88e6xxx_frame_mode {
49 MV88E6XXX_FRAME_MODE_NORMAL,
50 MV88E6XXX_FRAME_MODE_DSA,
51 MV88E6XXX_FRAME_MODE_PROVIDER,
52 MV88E6XXX_FRAME_MODE_ETHERTYPE,
53 };
54
55 /* List of supported models */
56 enum mv88e6xxx_model {
57 MV88E6020,
58 MV88E6071,
59 MV88E6085,
60 MV88E6095,
61 MV88E6097,
62 MV88E6123,
63 MV88E6131,
64 MV88E6141,
65 MV88E6161,
66 MV88E6165,
67 MV88E6171,
68 MV88E6172,
69 MV88E6175,
70 MV88E6176,
71 MV88E6185,
72 MV88E6190,
73 MV88E6190X,
74 MV88E6191,
75 MV88E6191X,
76 MV88E6193X,
77 MV88E6220,
78 MV88E6240,
79 MV88E6250,
80 MV88E6290,
81 MV88E6320,
82 MV88E6321,
83 MV88E6341,
84 MV88E6350,
85 MV88E6351,
86 MV88E6352,
87 MV88E6361,
88 MV88E6390,
89 MV88E6390X,
90 MV88E6393X,
91 };
92
93 enum mv88e6xxx_family {
94 MV88E6XXX_FAMILY_NONE,
95 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
96 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
97 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
98 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
99 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
100 MV88E6XXX_FAMILY_6250, /* 6220 6250 6020 6071 */
101 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
102 MV88E6XXX_FAMILY_6341, /* 6141 6341 */
103 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
104 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
105 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
106 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6361 6393X */
107 };
108
109 /**
110 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
111 * @MV88E6XXX_EDSA_UNSUPPORTED: Device has no support for EDSA tags
112 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that
113 * egressing FORWARD frames with an EDSA
114 * tag is reserved for future use, but
115 * empirical data shows that this mode
116 * is supported.
117 * @MV88E6XXX_EDSA_SUPPORTED: EDSA tags are fully supported.
118 */
119 enum mv88e6xxx_edsa_support {
120 MV88E6XXX_EDSA_UNSUPPORTED = 0,
121 MV88E6XXX_EDSA_UNDOCUMENTED,
122 MV88E6XXX_EDSA_SUPPORTED,
123 };
124
125 struct mv88e6xxx_ops;
126
127 struct mv88e6xxx_info {
128 enum mv88e6xxx_family family;
129 u16 prod_num;
130 const char *name;
131 unsigned int num_databases;
132 unsigned int num_macs;
133 unsigned int num_ports;
134 unsigned int num_internal_phys;
135 unsigned int num_gpio;
136 unsigned int max_vid;
137 unsigned int max_sid;
138 unsigned int port_base_addr;
139 unsigned int phy_base_addr;
140 unsigned int global1_addr;
141 unsigned int global2_addr;
142 unsigned int age_time_coeff;
143 unsigned int g1_irqs;
144 unsigned int g2_irqs;
145 bool pvt;
146
147 /* Mark certain ports as invalid. This is required for example for the
148 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
149 * ports 2-4 are not routet to pins.
150 */
151 unsigned int invalid_port_mask;
152 /* Multi-chip Addressing Mode.
153 * Some chips respond to only 2 registers of its own SMI device address
154 * when it is non-zero, and use indirect access to internal registers.
155 */
156 bool multi_chip;
157 /* Dual-chip Addressing Mode
158 * Some chips respond to only half of the 32 SMI addresses,
159 * allowing two to coexist on the same SMI interface.
160 */
161 bool dual_chip;
162
163 enum mv88e6xxx_edsa_support edsa_support;
164
165 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
166 * operation. 0 means that the ATU Move operation is not supported.
167 */
168 u8 atu_move_port_mask;
169 const struct mv88e6xxx_ops *ops;
170
171 /* Supports PTP */
172 bool ptp_support;
173
174 /* Internal PHY start index. 0 means that internal PHYs range starts at
175 * port 0, 1 means internal PHYs range starts at port 1, etc
176 */
177 unsigned int internal_phys_offset;
178 };
179
180 struct mv88e6xxx_atu_entry {
181 u8 state;
182 bool trunk;
183 u16 portvec;
184 u8 mac[ETH_ALEN];
185 };
186
187 struct mv88e6xxx_vtu_entry {
188 u16 vid;
189 u16 fid;
190 u8 sid;
191 bool valid;
192 bool policy;
193 u8 member[DSA_MAX_PORTS];
194 u8 state[DSA_MAX_PORTS]; /* Older silicon has no STU */
195 };
196
197 struct mv88e6xxx_stu_entry {
198 u8 sid;
199 bool valid;
200 u8 state[DSA_MAX_PORTS];
201 };
202
203 struct mv88e6xxx_bus_ops;
204 struct mv88e6xxx_irq_ops;
205 struct mv88e6xxx_gpio_ops;
206 struct mv88e6xxx_avb_ops;
207 struct mv88e6xxx_ptp_ops;
208 struct mv88e6xxx_pcs_ops;
209
210 struct mv88e6xxx_irq {
211 u16 masked;
212 struct irq_chip chip;
213 struct irq_domain *domain;
214 int nirqs;
215 };
216
217 /* state flags for mv88e6xxx_port_hwtstamp::state */
218 enum {
219 MV88E6XXX_HWTSTAMP_ENABLED,
220 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
221 };
222
223 struct mv88e6xxx_port_hwtstamp {
224 /* Port index */
225 int port_id;
226
227 /* Timestamping state */
228 unsigned long state;
229
230 /* Resources for receive timestamping */
231 struct sk_buff_head rx_queue;
232 struct sk_buff_head rx_queue2;
233
234 /* Resources for transmit timestamping */
235 unsigned long tx_tstamp_start;
236 struct sk_buff *tx_skb;
237 u16 tx_seq_id;
238
239 /* Current timestamp configuration */
240 struct hwtstamp_config tstamp_config;
241 };
242
243 enum mv88e6xxx_policy_mapping {
244 MV88E6XXX_POLICY_MAPPING_DA,
245 MV88E6XXX_POLICY_MAPPING_SA,
246 MV88E6XXX_POLICY_MAPPING_VTU,
247 MV88E6XXX_POLICY_MAPPING_ETYPE,
248 MV88E6XXX_POLICY_MAPPING_PPPOE,
249 MV88E6XXX_POLICY_MAPPING_VBAS,
250 MV88E6XXX_POLICY_MAPPING_OPT82,
251 MV88E6XXX_POLICY_MAPPING_UDP,
252 };
253
254 enum mv88e6xxx_policy_action {
255 MV88E6XXX_POLICY_ACTION_NORMAL,
256 MV88E6XXX_POLICY_ACTION_MIRROR,
257 MV88E6XXX_POLICY_ACTION_TRAP,
258 MV88E6XXX_POLICY_ACTION_DISCARD,
259 };
260
261 struct mv88e6xxx_policy {
262 enum mv88e6xxx_policy_mapping mapping;
263 enum mv88e6xxx_policy_action action;
264 struct ethtool_rx_flow_spec fs;
265 u8 addr[ETH_ALEN];
266 int port;
267 u16 vid;
268 };
269
270 struct mv88e6xxx_vlan {
271 u16 vid;
272 bool valid;
273 };
274
275 struct mv88e6xxx_port {
276 struct mv88e6xxx_chip *chip;
277 int port;
278 struct mv88e6xxx_vlan bridge_pvid;
279 u64 serdes_stats[2];
280 u64 atu_member_violation;
281 u64 atu_miss_violation;
282 u64 atu_full_violation;
283 u64 vtu_member_violation;
284 u64 vtu_miss_violation;
285 phy_interface_t interface;
286 u8 cmode;
287 bool mirror_ingress;
288 bool mirror_egress;
289 struct devlink_region *region;
290 void *pcs_private;
291
292 /* MacAuth Bypass control flag */
293 bool mab;
294 };
295
296 enum mv88e6xxx_region_id {
297 MV88E6XXX_REGION_GLOBAL1 = 0,
298 MV88E6XXX_REGION_GLOBAL2,
299 MV88E6XXX_REGION_ATU,
300 MV88E6XXX_REGION_VTU,
301 MV88E6XXX_REGION_STU,
302 MV88E6XXX_REGION_PVT,
303
304 _MV88E6XXX_REGION_MAX,
305 };
306
307 struct mv88e6xxx_region_priv {
308 enum mv88e6xxx_region_id id;
309 };
310
311 struct mv88e6xxx_mst {
312 struct list_head node;
313
314 refcount_t refcnt;
315 struct net_device *br;
316 u16 msti;
317
318 struct mv88e6xxx_stu_entry stu;
319 };
320
321 #define STATS_TYPE_PORT BIT(0)
322 #define STATS_TYPE_BANK0 BIT(1)
323 #define STATS_TYPE_BANK1 BIT(2)
324
325 struct mv88e6xxx_hw_stat {
326 char string[ETH_GSTRING_LEN];
327 size_t size;
328 int reg;
329 int type;
330 };
331
332 struct mv88e6xxx_chip {
333 const struct mv88e6xxx_info *info;
334
335 /* Currently configured tagging protocol */
336 enum dsa_tag_protocol tag_protocol;
337
338 /* The dsa_switch this private structure is related to */
339 struct dsa_switch *ds;
340
341 /* The device this structure is associated to */
342 struct device *dev;
343
344 /* This mutex protects the access to the switch registers */
345 struct mutex reg_lock;
346
347 /* The MII bus and the address on the bus that is used to
348 * communication with the switch
349 */
350 const struct mv88e6xxx_bus_ops *smi_ops;
351 struct mii_bus *bus;
352 int sw_addr;
353
354 /* Handles automatic disabling and re-enabling of the PHY
355 * polling unit.
356 */
357 const struct mv88e6xxx_bus_ops *phy_ops;
358 struct mutex ppu_mutex;
359 int ppu_disabled;
360 struct work_struct ppu_work;
361 struct timer_list ppu_timer;
362
363 /* This mutex serialises access to the statistics unit.
364 * Hold this mutex over snapshot + dump sequences.
365 */
366 struct mutex stats_mutex;
367
368 /* A switch may have a GPIO line tied to its reset pin. Parse
369 * this from the device tree, and use it before performing
370 * switch soft reset.
371 */
372 struct gpio_desc *reset;
373
374 /* set to size of eeprom if supported by the switch */
375 u32 eeprom_len;
376
377 /* List of mdio busses */
378 struct list_head mdios;
379
380 /* Policy Control List IDs and rules */
381 struct idr policies;
382
383 /* There can be two interrupt controllers, which are chained
384 * off a GPIO as interrupt source
385 */
386 struct mv88e6xxx_irq g1_irq;
387 struct mv88e6xxx_irq g2_irq;
388 int irq;
389 char irq_name[64];
390 int device_irq;
391 char device_irq_name[64];
392 int watchdog_irq;
393 char watchdog_irq_name[64];
394
395 int atu_prob_irq;
396 char atu_prob_irq_name[64];
397 int vtu_prob_irq;
398 char vtu_prob_irq_name[64];
399 struct kthread_worker *kworker;
400 struct kthread_delayed_work irq_poll_work;
401
402 /* GPIO resources */
403 u8 gpio_data[2];
404
405 /* This cyclecounter abstracts the switch PTP time.
406 * reg_lock must be held for any operation that read()s.
407 */
408 struct cyclecounter tstamp_cc;
409 struct timecounter tstamp_tc;
410 struct delayed_work overflow_work;
411
412 struct ptp_clock *ptp_clock;
413 struct ptp_clock_info ptp_clock_info;
414 struct delayed_work tai_event_work;
415 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
416 u16 trig_config;
417 u16 evcap_config;
418 u16 enable_count;
419
420 /* Current ingress and egress monitor ports */
421 int egress_dest_port;
422 int ingress_dest_port;
423
424 /* Per-port timestamping resources. */
425 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
426
427 /* Array of port structures. */
428 struct mv88e6xxx_port ports[DSA_MAX_PORTS];
429
430 /* devlink regions */
431 struct devlink_region *regions[_MV88E6XXX_REGION_MAX];
432
433 /* Bridge MST to SID mappings */
434 struct list_head msts;
435 };
436
437 struct mv88e6xxx_bus_ops {
438 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
439 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
440 int (*init)(struct mv88e6xxx_chip *chip);
441 };
442
443 struct mv88e6xxx_mdio_bus {
444 struct mii_bus *bus;
445 struct mv88e6xxx_chip *chip;
446 struct list_head list;
447 bool external;
448 };
449
450 struct mv88e6xxx_ops {
451 /* Switch Setup Errata, called early in the switch setup to
452 * allow any errata actions to be performed
453 */
454 int (*setup_errata)(struct mv88e6xxx_chip *chip);
455
456 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
457 int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
458
459 /* Ingress Rate Limit unit (IRL) operations */
460 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
461
462 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
463 struct ethtool_eeprom *eeprom, u8 *data);
464 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
465 struct ethtool_eeprom *eeprom, u8 *data);
466
467 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
468
469 int (*phy_read)(struct mv88e6xxx_chip *chip,
470 struct mii_bus *bus,
471 int addr, int reg, u16 *val);
472 int (*phy_write)(struct mv88e6xxx_chip *chip,
473 struct mii_bus *bus,
474 int addr, int reg, u16 val);
475
476 int (*phy_read_c45)(struct mv88e6xxx_chip *chip,
477 struct mii_bus *bus,
478 int addr, int devad, int reg, u16 *val);
479 int (*phy_write_c45)(struct mv88e6xxx_chip *chip,
480 struct mii_bus *bus,
481 int addr, int devad, int reg, u16 val);
482
483 /* Priority Override Table operations */
484 int (*pot_clear)(struct mv88e6xxx_chip *chip);
485
486 /* PHY Polling Unit (PPU) operations */
487 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
488 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
489
490 /* Additional handlers to run before and after hard reset, to make sure
491 * that the switch and EEPROM are in a good state.
492 */
493 int (*hardware_reset_pre)(struct mv88e6xxx_chip *chip);
494 int (*hardware_reset_post)(struct mv88e6xxx_chip *chip);
495
496 /* Switch Software Reset */
497 int (*reset)(struct mv88e6xxx_chip *chip);
498
499 /* RGMII Receive/Transmit Timing Control
500 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
501 */
502 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
503 phy_interface_t mode);
504
505 #define LINK_FORCED_DOWN 0
506 #define LINK_FORCED_UP 1
507 #define LINK_UNFORCED -2
508
509 /* Port's MAC link state
510 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
511 * or LINK_UNFORCED for normal link detection.
512 */
513 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
514
515 /* Synchronise the port link state with that of the SERDES
516 */
517 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
518
519 #define PAUSE_ON 1
520 #define PAUSE_OFF 0
521
522 /* Enable/disable sending Pause */
523 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
524 int pause);
525
526 #define SPEED_UNFORCED -2
527 #define DUPLEX_UNFORCED -2
528
529 /* Port's MAC speed (in Mbps) and MAC duplex mode
530 *
531 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
532 * Use SPEED_UNFORCED for normal detection.
533 *
534 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
535 * or DUPLEX_UNFORCED for normal duplex detection.
536 */
537 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
538 int speed, int duplex);
539
540 /* What interface mode should be used for maximum speed? */
541 phy_interface_t (*port_max_speed_mode)(struct mv88e6xxx_chip *chip,
542 int port);
543
544 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
545
546 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
547 enum mv88e6xxx_policy_mapping mapping,
548 enum mv88e6xxx_policy_action action);
549
550 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
551 enum mv88e6xxx_frame_mode mode);
552 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port,
553 bool unicast);
554 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port,
555 bool multicast);
556 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
557 u16 etype);
558 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
559 size_t size);
560
561 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
562 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
563 u8 out);
564 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
565 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
566 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
567
568 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
569 * Some chips allow this to be configured on specific ports.
570 */
571 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
572 phy_interface_t mode);
573 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
574
575 /* Some devices have a per port register indicating what is
576 * the upstream port this port should forward to.
577 */
578 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
579 int upstream_port);
580
581 /* Snapshot the statistics for a port. The statistics can then
582 * be read back a leisure but still with a consistent view.
583 */
584 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
585
586 /* Set the histogram mode for statistics, when the control registers
587 * are separated out of the STATS_OP register.
588 */
589 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
590
591 /* Return the number of strings describing statistics */
592 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
593 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
594 size_t (*stats_get_stat)(struct mv88e6xxx_chip *chip, int port,
595 const struct mv88e6xxx_hw_stat *stat,
596 uint64_t *data);
597 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
598 int (*set_egress_port)(struct mv88e6xxx_chip *chip,
599 enum mv88e6xxx_egress_direction direction,
600 int port);
601
602 #define MV88E6XXX_CASCADE_PORT_NONE 0xe
603 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
604
605 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
606
607 const struct mv88e6xxx_irq_ops *watchdog_ops;
608
609 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
610
611 /* SERDES lane mapping */
612 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
613
614 /* SERDES interrupt handling */
615 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
616 int port);
617
618 /* Statistics from the SERDES interface */
619 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
620 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
621 uint8_t *data);
622 size_t (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
623 uint64_t *data);
624
625 /* SERDES registers for ethtool */
626 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port);
627 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
628 void *_p);
629
630 /* SERDES SGMII/Fiber Output Amplitude */
631 int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port,
632 int val);
633
634 /* Address Translation Unit operations */
635 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
636 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
637
638 /* VLAN Translation Unit operations */
639 int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
640 struct mv88e6xxx_vtu_entry *entry);
641 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
642 struct mv88e6xxx_vtu_entry *entry);
643
644 /* Spanning Tree Unit operations */
645 int (*stu_getnext)(struct mv88e6xxx_chip *chip,
646 struct mv88e6xxx_stu_entry *entry);
647 int (*stu_loadpurge)(struct mv88e6xxx_chip *chip,
648 struct mv88e6xxx_stu_entry *entry);
649
650 /* GPIO operations */
651 const struct mv88e6xxx_gpio_ops *gpio_ops;
652
653 /* Interface to the AVB/PTP registers */
654 const struct mv88e6xxx_avb_ops *avb_ops;
655
656 /* Remote Management Unit operations */
657 int (*rmu_disable)(struct mv88e6xxx_chip *chip);
658
659 /* Precision Time Protocol operations */
660 const struct mv88e6xxx_ptp_ops *ptp_ops;
661
662 /* Phylink */
663 void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port,
664 struct phylink_config *config);
665
666 const struct mv88e6xxx_pcs_ops *pcs_ops;
667
668 /* Max Frame Size */
669 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
670 };
671
672 struct mv88e6xxx_irq_ops {
673 /* Action to be performed when the interrupt happens */
674 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
675 /* Setup the hardware to generate the interrupt */
676 int (*irq_setup)(struct mv88e6xxx_chip *chip);
677 /* Reset the hardware to stop generating the interrupt */
678 void (*irq_free)(struct mv88e6xxx_chip *chip);
679 };
680
681 struct mv88e6xxx_gpio_ops {
682 /* Get/set data on GPIO pin */
683 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
684 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
685 int value);
686
687 /* get/set GPIO direction */
688 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
689 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
690 bool input);
691
692 /* get/set GPIO pin control */
693 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
694 int *func);
695 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
696 int func);
697 };
698
699 struct mv88e6xxx_avb_ops {
700 /* Access port-scoped Precision Time Protocol registers */
701 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
702 u16 *data, int len);
703 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
704 u16 data);
705
706 /* Access global Precision Time Protocol registers */
707 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
708 int len);
709 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
710
711 /* Access global Time Application Interface registers */
712 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
713 int len);
714 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
715 };
716
717 struct mv88e6xxx_ptp_ops {
718 u64 (*clock_read)(const struct cyclecounter *cc);
719 int (*ptp_enable)(struct ptp_clock_info *ptp,
720 struct ptp_clock_request *rq, int on);
721 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
722 enum ptp_pin_function func, unsigned int chan);
723 void (*event_work)(struct work_struct *ugly);
724 int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
725 int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
726 int (*global_enable)(struct mv88e6xxx_chip *chip);
727 int (*global_disable)(struct mv88e6xxx_chip *chip);
728 int (*set_ptp_cpu_port)(struct mv88e6xxx_chip *chip, int port);
729 int n_ext_ts;
730 int arr0_sts_reg;
731 int arr1_sts_reg;
732 int dep_sts_reg;
733 u32 rx_filters;
734 u32 cc_shift;
735 u32 cc_mult;
736 u32 cc_mult_num;
737 u32 cc_mult_dem;
738 };
739
740 struct mv88e6xxx_pcs_ops {
741 int (*pcs_init)(struct mv88e6xxx_chip *chip, int port);
742 void (*pcs_teardown)(struct mv88e6xxx_chip *chip, int port);
743 struct phylink_pcs *(*pcs_select)(struct mv88e6xxx_chip *chip, int port,
744 phy_interface_t mode);
745
746 };
747
mv88e6xxx_has_stu(struct mv88e6xxx_chip * chip)748 static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip)
749 {
750 return chip->info->max_sid > 0 &&
751 chip->info->ops->stu_loadpurge &&
752 chip->info->ops->stu_getnext;
753 }
754
mv88e6xxx_has_pvt(struct mv88e6xxx_chip * chip)755 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
756 {
757 return chip->info->pvt;
758 }
759
mv88e6xxx_has_lag(struct mv88e6xxx_chip * chip)760 static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip)
761 {
762 return !!chip->info->global2_addr;
763 }
764
mv88e6xxx_num_databases(struct mv88e6xxx_chip * chip)765 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
766 {
767 return chip->info->num_databases;
768 }
769
mv88e6xxx_num_macs(struct mv88e6xxx_chip * chip)770 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip)
771 {
772 return chip->info->num_macs;
773 }
774
mv88e6xxx_num_ports(struct mv88e6xxx_chip * chip)775 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
776 {
777 return chip->info->num_ports;
778 }
779
mv88e6xxx_max_vid(struct mv88e6xxx_chip * chip)780 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip)
781 {
782 return chip->info->max_vid;
783 }
784
mv88e6xxx_max_sid(struct mv88e6xxx_chip * chip)785 static inline unsigned int mv88e6xxx_max_sid(struct mv88e6xxx_chip *chip)
786 {
787 return chip->info->max_sid;
788 }
789
mv88e6xxx_port_mask(struct mv88e6xxx_chip * chip)790 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
791 {
792 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);
793 }
794
mv88e6xxx_num_gpio(struct mv88e6xxx_chip * chip)795 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
796 {
797 return chip->info->num_gpio;
798 }
799
mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip * chip,int port)800 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
801 {
802 return (chip->info->invalid_port_mask & BIT(port)) != 0;
803 }
804
mv88e6xxx_port_set_mab(struct mv88e6xxx_chip * chip,int port,bool mab)805 static inline void mv88e6xxx_port_set_mab(struct mv88e6xxx_chip *chip,
806 int port, bool mab)
807 {
808 chip->ports[port].mab = mab;
809 }
810
811 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
812 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
813 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
814 u16 mask, u16 val);
815 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
816 int bit, int val);
817 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
818
mv88e6xxx_reg_lock(struct mv88e6xxx_chip * chip)819 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
820 {
821 mutex_lock(&chip->reg_lock);
822 }
823
mv88e6xxx_reg_unlock(struct mv88e6xxx_chip * chip)824 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
825 {
826 mutex_unlock(&chip->reg_lock);
827 }
828
829 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
830 int (*cb)(struct mv88e6xxx_chip *chip,
831 const struct mv88e6xxx_vtu_entry *entry,
832 void *priv),
833 void *priv);
834
835 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap);
836
837 #endif /* _MV88E6XXX_CHIP_H */
838