xref: /linux/drivers/net/dsa/mv88e6xxx/serdes.h (revision 06d07429858317ded2db7986113a9e0129cd599b)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Marvell 88E6xxx SERDES manipulation, via SMI bus
4  *
5  * Copyright (c) 2008 Marvell Semiconductor
6  *
7  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8  */
9 
10 #ifndef _MV88E6XXX_SERDES_H
11 #define _MV88E6XXX_SERDES_H
12 
13 #include "chip.h"
14 
15 struct phylink_link_state;
16 
17 #define MV88E6352_ADDR_SERDES		0x0f
18 #define MV88E6352_SERDES_PAGE_FIBER	0x01
19 #define MV88E6352_SERDES_IRQ		0x0b
20 #define MV88E6352_SERDES_INT_ENABLE	0x12
21 #define MV88E6352_SERDES_INT_SPEED_CHANGE	BIT(14)
22 #define MV88E6352_SERDES_INT_DUPLEX_CHANGE	BIT(13)
23 #define MV88E6352_SERDES_INT_PAGE_RX		BIT(12)
24 #define MV88E6352_SERDES_INT_AN_COMPLETE	BIT(11)
25 #define MV88E6352_SERDES_INT_LINK_CHANGE	BIT(10)
26 #define MV88E6352_SERDES_INT_SYMBOL_ERROR	BIT(9)
27 #define MV88E6352_SERDES_INT_FALSE_CARRIER	BIT(8)
28 #define MV88E6352_SERDES_INT_FIFO_OVER_UNDER	BIT(7)
29 #define MV88E6352_SERDES_INT_FIBRE_ENERGY	BIT(4)
30 #define MV88E6352_SERDES_INT_STATUS	0x13
31 
32 #define MV88E6352_SERDES_SPEC_CTRL2	0x1a
33 #define MV88E6352_SERDES_OUT_AMP_MASK		0x0007
34 
35 #define MV88E6341_PORT5_LANE		0x15
36 
37 #define MV88E6390_PORT9_LANE0		0x09
38 #define MV88E6390_PORT9_LANE1		0x12
39 #define MV88E6390_PORT9_LANE2		0x13
40 #define MV88E6390_PORT9_LANE3		0x14
41 #define MV88E6390_PORT10_LANE0		0x0a
42 #define MV88E6390_PORT10_LANE1		0x15
43 #define MV88E6390_PORT10_LANE2		0x16
44 #define MV88E6390_PORT10_LANE3		0x17
45 
46 /* 10GBASE-R and 10GBASE-X4/X2 */
47 #define MV88E6390_10G_CTRL1		(0x1000 + MDIO_CTRL1)
48 #define MV88E6390_10G_STAT1		(0x1000 + MDIO_STAT1)
49 #define MV88E6390_10G_INT_ENABLE	0x9001
50 #define MV88E6390_10G_INT_LINK_DOWN	BIT(3)
51 #define MV88E6390_10G_INT_LINK_UP	BIT(2)
52 #define MV88E6390_10G_INT_STATUS	0x9003
53 #define MV88E6393X_10G_INT_ENABLE	0x9000
54 #define MV88E6393X_10G_INT_LINK_CHANGE	BIT(2)
55 #define MV88E6393X_10G_INT_STATUS	0x9001
56 
57 /* USXGMII */
58 #define MV88E6390_USXGMII_LP_STATUS       0xf0a2
59 #define MV88E6390_USXGMII_PHY_STATUS      0xf0a6
60 
61 /* 1000BASE-X and SGMII */
62 #define MV88E6390_SGMII_BMCR		(0x2000 + MII_BMCR)
63 #define MV88E6390_SGMII_BMSR		(0x2000 + MII_BMSR)
64 #define MV88E6390_SGMII_ADVERTISE	(0x2000 + MII_ADVERTISE)
65 #define MV88E6390_SGMII_LPA		(0x2000 + MII_LPA)
66 #define MV88E6390_SGMII_INT_ENABLE	0xa001
67 #define MV88E6390_SGMII_INT_SPEED_CHANGE	BIT(14)
68 #define MV88E6390_SGMII_INT_DUPLEX_CHANGE	BIT(13)
69 #define MV88E6390_SGMII_INT_PAGE_RX		BIT(12)
70 #define MV88E6390_SGMII_INT_AN_COMPLETE		BIT(11)
71 #define MV88E6390_SGMII_INT_LINK_DOWN		BIT(10)
72 #define MV88E6390_SGMII_INT_LINK_UP		BIT(9)
73 #define MV88E6390_SGMII_INT_SYMBOL_ERROR	BIT(8)
74 #define MV88E6390_SGMII_INT_FALSE_CARRIER	BIT(7)
75 #define MV88E6390_SGMII_INT_STATUS	0xa002
76 #define MV88E6390_SGMII_PHY_STATUS	0xa003
77 #define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK	GENMASK(15, 14)
78 #define MV88E6390_SGMII_PHY_STATUS_SPEED_1000	0x8000
79 #define MV88E6390_SGMII_PHY_STATUS_SPEED_100	0x4000
80 #define MV88E6390_SGMII_PHY_STATUS_SPEED_10	0x0000
81 #define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL	BIT(13)
82 #define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11)
83 #define MV88E6390_SGMII_PHY_STATUS_LINK		BIT(10)
84 #define MV88E6390_SGMII_PHY_STATUS_TX_PAUSE	BIT(3)
85 #define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE	BIT(2)
86 
87 /* Packet generator pad packet checker */
88 #define MV88E6390_PG_CONTROL		0xf010
89 #define MV88E6390_PG_CONTROL_ENABLE_PC		BIT(0)
90 
91 #define MV88E6393X_PORT0_LANE			0x00
92 #define MV88E6393X_PORT9_LANE			0x09
93 #define MV88E6393X_PORT10_LANE			0x0a
94 
95 /* Port Operational Configuration */
96 #define MV88E6393X_SERDES_POC			0xf002
97 #define MV88E6393X_SERDES_POC_PCS_1000BASEX	0x0000
98 #define MV88E6393X_SERDES_POC_PCS_2500BASEX	0x0001
99 #define MV88E6393X_SERDES_POC_PCS_SGMII_PHY	0x0002
100 #define MV88E6393X_SERDES_POC_PCS_SGMII_MAC	0x0003
101 #define MV88E6393X_SERDES_POC_PCS_5GBASER	0x0004
102 #define MV88E6393X_SERDES_POC_PCS_10GBASER	0x0005
103 #define MV88E6393X_SERDES_POC_PCS_USXGMII_PHY	0x0006
104 #define MV88E6393X_SERDES_POC_PCS_USXGMII_MAC	0x0007
105 #define MV88E6393X_SERDES_POC_PCS_MASK		0x0007
106 #define MV88E6393X_SERDES_POC_RESET		BIT(15)
107 #define MV88E6393X_SERDES_POC_PDOWN		BIT(5)
108 #define MV88E6393X_SERDES_POC_AN		BIT(3)
109 #define MV88E6393X_SERDES_CTRL1			0xf003
110 #define MV88E6393X_SERDES_CTRL1_TX_PDOWN	BIT(9)
111 #define MV88E6393X_SERDES_CTRL1_RX_PDOWN	BIT(8)
112 
113 #define MV88E6393X_ERRATA_4_8_REG		0xF074
114 #define MV88E6393X_ERRATA_4_8_BIT		BIT(14)
115 
116 int mv88e6xxx_pcs_decode_state(struct device *dev, u16 bmsr, u16 lpa,
117 			       u16 status, struct phylink_link_state *state);
118 
119 int mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
120 int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
121 int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
122 int mv88e6393x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
123 unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
124 					  int port);
125 unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
126 					  int port);
127 int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
128 int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip,
129 				 int port, uint8_t *data);
130 size_t mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
131 				  uint64_t *data);
132 int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
133 int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip,
134 				 int port, uint8_t *data);
135 size_t mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
136 				  uint64_t *data);
137 
138 int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
139 void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
140 int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
141 void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
142 
143 int mv88e6352_serdes_set_tx_amplitude(struct mv88e6xxx_chip *chip, int port,
144 				      int val);
145 
146 /* Return the (first) SERDES lane address a port is using, -errno otherwise. */
mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip * chip,int port)147 static inline int mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip,
148 					    int port)
149 {
150 	if (!chip->info->ops->serdes_get_lane)
151 		return -EOPNOTSUPP;
152 
153 	return chip->info->ops->serdes_get_lane(chip, port);
154 }
155 
156 static inline unsigned int
mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip * chip,int port)157 mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
158 {
159 	if (!chip->info->ops->serdes_irq_mapping)
160 		return 0;
161 
162 	return chip->info->ops->serdes_irq_mapping(chip, port);
163 }
164 
165 extern const struct mv88e6xxx_pcs_ops mv88e6185_pcs_ops;
166 extern const struct mv88e6xxx_pcs_ops mv88e6352_pcs_ops;
167 extern const struct mv88e6xxx_pcs_ops mv88e6390_pcs_ops;
168 extern const struct mv88e6xxx_pcs_ops mv88e6393x_pcs_ops;
169 
170 #endif
171