1 /*- 2 * Copyright (c) 1995 Bruce D. Evans. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the author nor the names of contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _X86_X86_VAR_H_ 31 #define _X86_X86_VAR_H_ 32 33 /* 34 * Miscellaneous machine-dependent declarations. 35 */ 36 37 extern long Maxmem; 38 extern u_int basemem; 39 extern u_int cpu_exthigh; 40 extern u_int cpu_feature; 41 extern u_int cpu_feature2; 42 extern u_int amd_feature; 43 extern u_int amd_feature2; 44 extern u_int amd_rascap; 45 extern u_int amd_pminfo; 46 extern u_int amd_extended_feature_extensions; 47 extern u_int via_feature_rng; 48 extern u_int via_feature_xcrypt; 49 extern u_int cpu_clflush_line_size; 50 extern u_int cpu_stdext_feature; 51 extern u_int cpu_stdext_feature2; 52 extern u_int cpu_stdext_feature3; 53 extern uint64_t cpu_ia32_arch_caps; 54 extern u_int cpu_high; 55 extern u_int cpu_id; 56 extern u_int cpu_max_ext_state_size; 57 extern u_int cpu_mxcsr_mask; 58 extern u_int cpu_procinfo; 59 extern u_int cpu_procinfo2; 60 extern u_int cpu_procinfo3; 61 extern char cpu_vendor[]; 62 extern char cpu_model[]; 63 extern u_int cpu_vendor_id; 64 extern u_int cpu_mon_mwait_flags; 65 extern u_int cpu_mon_mwait_edx; 66 extern u_int cpu_mon_min_size; 67 extern u_int cpu_mon_max_size; 68 extern u_int cpu_maxphyaddr; 69 extern u_int cpu_power_eax; 70 extern u_int cpu_power_ebx; 71 extern u_int cpu_power_ecx; 72 extern u_int cpu_power_edx; 73 extern u_int hv_base; 74 extern u_int hv_high; 75 extern char hv_vendor[]; 76 extern char kstack[]; 77 extern char sigcode[]; 78 extern int szsigcode; 79 extern int workaround_erratum383; 80 extern int _udatasel; 81 extern int _ucodesel; 82 extern int _ucode32sel; 83 extern int _ufssel; 84 extern int _ugssel; 85 extern int use_xsave; 86 extern uint64_t xsave_mask; 87 extern u_int max_apic_id; 88 extern int i386_read_exec; 89 extern int pti; 90 extern int hw_ibrs_ibpb_active; 91 extern int hw_mds_disable; 92 extern int hw_ssb_active; 93 extern int x86_taa_enable; 94 extern int cpu_flush_rsb_ctxsw; 95 extern int x86_rngds_mitg_enable; 96 extern int zenbleed_enable; 97 extern int cpu_amdc1e_bug; 98 extern char bootmethod[16]; 99 100 struct pcb; 101 struct thread; 102 struct reg; 103 struct fpreg; 104 struct dbreg; 105 struct dumperinfo; 106 struct trapframe; 107 struct minidumpstate; 108 109 /* 110 * The interface type of the interrupt handler entry point cannot be 111 * expressed in C. Use simplest non-variadic function type as an 112 * approximation. 113 */ 114 typedef void alias_for_inthand_t(void); 115 116 bool acpi_get_fadt_bootflags(uint16_t *flagsp); 117 void *alloc_fpusave(int flags); 118 u_int cpu_auxmsr(void); 119 vm_paddr_t cpu_getmaxphyaddr(void); 120 bool cpu_mwait_usable(void); 121 void cpu_probe_amdc1e(void); 122 void cpu_setregs(void); 123 int dbreg_set_watchpoint(vm_offset_t addr, vm_size_t size, int access); 124 int dbreg_clr_watchpoint(vm_offset_t addr, vm_size_t size); 125 void dbreg_list_watchpoints(void); 126 void x86_clear_dbregs(struct pcb *pcb); 127 bool disable_wp(void); 128 void restore_wp(bool old_wp); 129 void finishidentcpu(void); 130 void identify_cpu1(void); 131 void identify_cpu2(void); 132 void identify_cpu_ext_features(void); 133 void identify_cpu_fixup_bsp(void); 134 void identify_hypervisor(void); 135 void initializecpu(void); 136 void initializecpucache(void); 137 bool fix_cpuid(void); 138 void fillw(int /*u_short*/ pat, void *base, size_t cnt); 139 int isa_nmi(int cd); 140 void handle_ibrs_entry(void); 141 void handle_ibrs_exit(void); 142 void hw_ibrs_recalculate(bool all_cpus); 143 void hw_mds_recalculate(void); 144 void hw_ssb_recalculate(bool all_cpus); 145 void x86_taa_recalculate(void); 146 void x86_rngds_mitg_recalculate(bool all_cpus); 147 void zenbleed_sanitize_enable(void); 148 void zenbleed_check_and_apply(bool all_cpus); 149 void nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame); 150 void nmi_call_kdb_smp(u_int type, struct trapframe *frame); 151 void nmi_handle_intr(u_int type, struct trapframe *frame); 152 void pagecopy(void *from, void *to); 153 void printcpuinfo(void); 154 int pti_get_default(void); 155 int user_dbreg_trap(register_t dr6); 156 int cpu_minidumpsys(struct dumperinfo *, const struct minidumpstate *); 157 struct pcb *get_pcb_td(struct thread *td); 158 void x86_set_fork_retval(struct thread *td); 159 uint64_t rdtsc_ordered(void); 160 161 /* 162 * MSR ops for x86_msr_op() 163 */ 164 #define MSR_OP_ANDNOT 0x00000001 165 #define MSR_OP_OR 0x00000002 166 #define MSR_OP_WRITE 0x00000003 167 #define MSR_OP_READ 0x00000004 168 169 /* 170 * Where and which execution mode 171 */ 172 #define MSR_OP_LOCAL 0x10000000 173 #define MSR_OP_SCHED_ALL 0x20000000 174 #define MSR_OP_SCHED_ONE 0x30000000 175 #define MSR_OP_RENDEZVOUS_ALL 0x40000000 176 #define MSR_OP_RENDEZVOUS_ONE 0x50000000 177 #define MSR_OP_CPUID(id) ((id) << 8) 178 179 void x86_msr_op(u_int msr, u_int op, uint64_t arg1, uint64_t *res); 180 181 #if defined(__i386__) && defined(INVARIANTS) 182 void trap_check_kstack(void); 183 #else 184 #define trap_check_kstack() 185 #endif 186 187 #endif 188