xref: /titanic_41/usr/src/uts/intel/sys/mc_intel.h (revision 491f61a1e1c1fc54a47bbcf53dbbbe1293b93b27)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _MC_INTEL_H
28 #define	_MC_INTEL_H
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
34 #define	FM_EREPORT_CPU_INTEL	"intel"
35 
36 #define	MCINTEL_NVLIST_VERSTR	"mcintel-nvlist-version"
37 #define	MCINTEL_NVLIST_VERS0	0
38 
39 #define	MCINTEL_NVLIST_VERS	MCINTEL_NVLIST_VERS0
40 
41 #define	MCINTEL_NVLIST_MEM	"memory-controller"
42 #define	MCINTEL_NVLIST_NMEM	"memory-controllers"
43 #define	MCINTEL_NVLIST_MC	"memory-channels"
44 #define	MCINTEL_NVLIST_DIMMS	"memory-dimms"
45 #define	MCINTEL_NVLIST_DIMMSZ	"memory-dimm-size"
46 #define	MCINTEL_NVLIST_NRANKS	"dimm-max-ranks"
47 #define	MCINTEL_NVLIST_NDIMMS	"dimm-max-dimms"
48 #define	MCINTEL_NVLIST_RANKS	"dimm-ranks"
49 #define	MCINTEL_NVLIST_1ST_RANK	"dimm-start-rank"
50 #define	MCINTEL_NVLIST_DIMM_NUM	"dimm-number"
51 #define	MCINTEL_NVLIST_ROWS	"dimm-rows"
52 #define	MCINTEL_NVLIST_COL	"dimm-column"
53 #define	MCINTEL_NVLIST_BANK	"dimm-banks"
54 #define	MCINTEL_NVLIST_WIDTH	"dimm-width"
55 #define	MCINTEL_NVLIST_MID	"dimm-manufacture-id"
56 #define	MCINTEL_NVLIST_MLOC	"dimm-manufacture-location"
57 #define	MCINTEL_NVLIST_MWEEK	"dimm-manufacture-week"
58 #define	MCINTEL_NVLIST_MYEAR	"dimm-manufacture-year"
59 #define	MCINTEL_NVLIST_SERIALNO	"dimm-serial-number"
60 #define	MCINTEL_NVLIST_PARTNO	"dimm-part-number"
61 #define	MCINTEL_NVLIST_REV	"dimm-part-rev"
62 
63 #define	FM_EREPORT_PAYLOAD_NAME_FERR_GLOBAL		"ferr_global"
64 #define	FM_EREPORT_PAYLOAD_NAME_NERR_GLOBAL		"nerr_global"
65 #define	FM_EREPORT_PAYLOAD_NAME_FSB			"fsb"
66 #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_FSB		"ferr_fat_fsb"
67 #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_FSB		"nerr_fat_fsb"
68 #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_FSB		"ferr_nf_fsb"
69 #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_FSB		"nerr_nf_fsb"
70 #define	FM_EREPORT_PAYLOAD_NAME_NRECFSB			"nrecfsb"
71 #define	FM_EREPORT_PAYLOAD_NAME_NRECFSB_ADDR		"nrecfsb_addr"
72 #define	FM_EREPORT_PAYLOAD_NAME_RECFSB			"recfsb"
73 #define	FM_EREPORT_PAYLOAD_NAME_PEX			"pex"
74 #define	FM_EREPORT_PAYLOAD_NAME_PEX_FAT_FERR		"pex_fat_ferr"
75 #define	FM_EREPORT_PAYLOAD_NAME_PEX_FAT_NERR		"pex_fat_nerr"
76 #define	FM_EREPORT_PAYLOAD_NAME_PEX_NF_CORR_FERR	"pex_nf_corr_ferr"
77 #define	FM_EREPORT_PAYLOAD_NAME_PEX_NF_CORR_NERR	"pex_nf_corr_nerr"
78 #define	FM_EREPORT_PAYLOAD_NAME_UNCERRSEV		"uncerrsev"
79 #define	FM_EREPORT_PAYLOAD_NAME_RPERRSTS		"rperrsts"
80 #define	FM_EREPORT_PAYLOAD_NAME_RPERRSID		"rperrsid"
81 #define	FM_EREPORT_PAYLOAD_NAME_UNCERRSTS		"uncerrsts"
82 #define	FM_EREPORT_PAYLOAD_NAME_AERRCAPCTRL		"aerrcapctrl"
83 #define	FM_EREPORT_PAYLOAD_NAME_CORERRSTS		"corerrsts"
84 #define	FM_EREPORT_PAYLOAD_NAME_PEXDEVSTS		"pexdevsts"
85 #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_INT		"ferr_fat_int"
86 #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_INT		"ferr_nf_int"
87 #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_INT		"nerr_fat_int"
88 #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_INT		"nerr_nf_int"
89 #define	FM_EREPORT_PAYLOAD_NAME_NRECINT			"nrecint"
90 #define	FM_EREPORT_PAYLOAD_NAME_RECINT			"recint"
91 #define	FM_EREPORT_PAYLOAD_NAME_NRECSF			"nrecsf"
92 #define	FM_EREPORT_PAYLOAD_NAME_RECSF			"recsf"
93 #define	FM_EREPORT_PAYLOAD_NAME_RANK			"rank"
94 #define	FM_EREPORT_PAYLOAD_NAME_BANK			"bank"
95 #define	FM_EREPORT_PAYLOAD_NAME_CAS			"cas"
96 #define	FM_EREPORT_PAYLOAD_NAME_RAS			"ras"
97 #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_FBD		"ferr_fat_fbd"
98 #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_FBD		"nerr_fat_fbd"
99 #define	FM_EREPORT_PAYLOAD_NAME_VALIDLOG		"validlog"
100 #define	FM_EREPORT_PAYLOAD_NAME_NRECMEMA		"nrecmema"
101 #define	FM_EREPORT_PAYLOAD_NAME_NRECMEMB		"nrecmemb"
102 #define	FM_EREPORT_PAYLOAD_NAME_NRECFGLOG		"nrecfglog"
103 #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDA		"nrecfbda"
104 #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDB		"nrecfbdb"
105 #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDC		"nrecfbdc"
106 #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDD		"nrecfbdd"
107 #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDE		"nrecfbde"
108 #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDF		"nrecfbdf"
109 #define	FM_EREPORT_PAYLOAD_NAME_SPCPC			"spcpc"
110 #define	FM_EREPORT_PAYLOAD_NAME_SPCPS			"spcps"
111 #define	FM_EREPORT_PAYLOAD_NAME_UERRCNT			"uerrcnt"
112 #define	FM_EREPORT_PAYLOAD_NAME_UERRCNT_LAST		"uerrcnt_last"
113 #define	FM_EREPORT_PAYLOAD_NAME_BADRAM			"badram"
114 #define	FM_EREPORT_PAYLOAD_NAME_BADRAMA			"badrama"
115 #define	FM_EREPORT_PAYLOAD_NAME_BADRAMB			"badramb"
116 #define	FM_EREPORT_PAYLOAD_NAME_BADCNT			"badcnt"
117 #define	FM_EREPORT_PAYLOAD_NAME_MC			"mc"
118 #define	FM_EREPORT_PAYLOAD_NAME_MCA			"mca"
119 #define	FM_EREPORT_PAYLOAD_NAME_TOLM			"tolm"
120 #define	FM_EREPORT_PAYLOAD_NAME_MIR			"mir"
121 #define	FM_EREPORT_PAYLOAD_NAME_MTR			"mtr"
122 #define	FM_EREPORT_PAYLOAD_NAME_DMIR			"dmir"
123 #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_FBD		"ferr_nf_fbd"
124 #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_FBD		"nerr_nf_fbd"
125 #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_MEM		"ferr_nf_mem"
126 #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_MEM		"nerr_nf_mem"
127 #define	FM_EREPORT_PAYLOAD_NAME_RECMEMA			"recmema"
128 #define	FM_EREPORT_PAYLOAD_NAME_RECMEMB			"recmemb"
129 #define	FM_EREPORT_PAYLOAD_NAME_REDMEMA			"redmema"
130 #define	FM_EREPORT_PAYLOAD_NAME_REDMEMB			"redmemb"
131 #define	FM_EREPORT_PAYLOAD_NAME_RECFGLOG		"recfglog"
132 #define	FM_EREPORT_PAYLOAD_NAME_RECFBDA			"recfbda"
133 #define	FM_EREPORT_PAYLOAD_NAME_RECFBDB			"recfbdb"
134 #define	FM_EREPORT_PAYLOAD_NAME_RECFBDC			"recfbdc"
135 #define	FM_EREPORT_PAYLOAD_NAME_RECFBDD			"recfbdd"
136 #define	FM_EREPORT_PAYLOAD_NAME_RECFBDE			"recfbde"
137 #define	FM_EREPORT_PAYLOAD_NAME_RECFBDF			"recfbdf"
138 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT			"cerrcnt"
139 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT_LAST		"cerrcnt_last"
140 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT_EXT		"cerrcnt_ext"
141 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT_EXT_LAST	"cerrcnt_ext_last"
142 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTA		"cerrcnta"
143 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTB		"cerrcntb"
144 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTC		"cerrcntc"
145 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTD		"cerrcntd"
146 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTA_LAST		"cerrcnta_last"
147 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTB_LAST		"cerrcntb_last"
148 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTC_LAST		"cerrcntc_last"
149 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTD_LAST		"cerrcntd_last"
150 #define	FM_EREPORT_PAYLOAD_NAME_PCISTS			"pcists"
151 #define	FM_EREPORT_PAYLOAD_NAME_PEXDEVSTS		"pexdevsts"
152 #define	FM_EREPORT_PAYLOAD_NAME_ERROR_NO		"intel-error-list"
153 
154 #define	FM_EREPORT_PAYLOAD_NAME_CTSTS			"ctsts"
155 #define	FM_EREPORT_PAYLOAD_NAME_THRTSTS			"thrtsts"
156 #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_THR		"ferr_fat_thr"
157 #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_THR		"nerr_fat_thr"
158 #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_THR		"ferr_nf_thr"
159 #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_THR		"nerr_nf_thr"
160 
161 #define	FM_EREPORT_PAYLOAD_NAME_ADDR			"addr"
162 #define	FM_EREPORT_PAYLOAD_NAME_BANK_NUM		"bank-number"
163 #define	FM_EREPORT_PAYLOAD_NAME_BANK_MISC		"bank-misc"
164 #define	FM_EREPORT_PAYLOAD_NAME_BANK_STAT		"bank-status"
165 #define	FM_EREPORT_PAYLOAD_NAME_BANK_OFFSET		"bank-offset"
166 #define	FM_EREPORT_PAYLOAD_NAME_MC_TYPE			"mc-type"
167 #define	FM_EREPORT_PAYLOAD_CPUID			"cpuid"
168 
169 #define	FM_EREPORT_PAYLOAD_BQR				"Bus-queue-request"
170 #define	FM_EREPORT_PAYLOAD_BQET				"Bus-queue-error-type"
171 #define	FM_EREPORT_PAYLOAD_FRC				"FRC-error"
172 #define	FM_EREPORT_PAYLOAD_BERR				"BERR"
173 #define	FM_EREPORT_PAYLOAD_INT_BINT			"Internal-BINT"
174 #define	FM_EREPORT_PAYLOAD_EXT_BINT			"External-BINT"
175 #define	FM_EREPORT_PAYLOAD_BUS_BINT			"Bus-BINT"
176 #define	FM_EREPORT_PAYLOAD_TO_BINT			"Timeout-BINT"
177 #define	FM_EREPORT_PAYLOAD_HARD				"Hard-error"
178 #define	FM_EREPORT_PAYLOAD_IERR				"IERR"
179 #define	FM_EREPORT_PAYLOAD_AERR				"AERR"
180 #define	FM_EREPORT_PAYLOAD_UERR				"UERR"
181 #define	FM_EREPORT_PAYLOAD_CECC				"CECC"
182 #define	FM_EREPORT_PAYLOAD_UECC				"UECC"
183 #define	FM_EREPORT_PAYLOAD_ECC_SYND			"ECC-syndrome"
184 
185 #define	FM_EREPORT_PAYLOAD_FSB_PARITY			"fsb-address-parity"
186 #define	FM_EREPORT_PAYLOAD_RESP_HF			"response-hard-fail"
187 #define	FM_EREPORT_PAYLOAD_RESP_PARITY			"response-parity"
188 #define	FM_EREPORT_PAYLOAD_DATA_PARITY			"bus-data-parity"
189 #define	FM_EREPORT_PAYLOAD_INV_PIC			"invalid-pic-request"
190 #define	FM_EREPORT_PAYLOAD_PAD_SM			"pad-state-machine"
191 #define	FM_EREPORT_PAYLOAD_PAD_SG			"pad-strobe-glitch"
192 
193 #define	FM_EREPORT_PAYLOAD_TAG				"tag-error"
194 #define	FM_EREPORT_PAYLOAD_TAG_CLEAN			"clean"
195 #define	FM_EREPORT_PAYLOAD_TAG_HIT			"hit"
196 #define	FM_EREPORT_PAYLOAD_TAG_MISS			"miss"
197 #define	FM_EREPORT_PAYLOAD_DATA				"data-error"
198 #define	FM_EREPORT_PAYLOAD_DATA_SINGLE			"single-bit"
199 #define	FM_EREPORT_PAYLOAD_DATA_DBL_CLEAN		"double-bit-clean"
200 #define	FM_EREPORT_PAYLOAD_DATA_DBL_MOD			"double-bit-modified"
201 #define	FM_EREPORT_PAYLOAD_L3				"l3-cache"
202 #define	FM_EREPORT_PAYLOAD_INV_PIC			"invalid-pic-request"
203 #define	FM_EREPORT_PAYLOAD_CACHE_NERRORS		"cache-error-count"
204 
205 #define	FM_EREPORT_PAYLOAD_NAME_RESOURCE		"resource"
206 #define	FM_EREPORT_PAYLOAD_MEM_ECC_COUNTER_THIS	"mem_cor_ecc_counter"
207 #define	FM_EREPORT_PAYLOAD_MEM_ECC_COUNTER_LAST	"mem_cor_ecc_counter_last"
208 
209 #define	INTEL_NB_5000P	0x25d88086
210 #define	INTEL_NB_5000V	0x25d48086
211 #define	INTEL_NB_5000X	0x25c08086
212 #define	INTEL_NB_5000Z	0x25d08086
213 #define	INTEL_NB_5100	0x65c08086
214 #define	INTEL_NB_5400	0x40008086
215 #define	INTEL_NB_5400A	0x40018086
216 #define	INTEL_NB_5400B	0x40038086
217 #define	INTEL_NB_7300	0x36008086
218 
219 #define	INTEL_NHM	0x2c408086
220 #define	INTEL_QP_IO	0x34008086
221 #define	INTEL_QP_36D	0x34068086
222 #define	INTEL_QP_24D	0x34038086
223 #define	INTEL_QP_WP	0x34058086
224 #define	INTEL_QP_U1	0x34018086
225 #define	INTEL_QP_U2	0x34028086
226 #define	INTEL_QP_U3	0x34048086
227 #define	INTEL_QP_U4	0x34078086
228 #define	INTEL_QP_JF	0x37208086
229 #define	INTEL_QP_JF0	0x37008086
230 #define	INTEL_QP_JF1	0x37018086
231 #define	INTEL_QP_JF2	0x37028086
232 #define	INTEL_QP_JF3	0x37038086
233 #define	INTEL_QP_JF4	0x37048086
234 #define	INTEL_QP_JF5	0x37058086
235 #define	INTEL_QP_JF6	0x37068086
236 #define	INTEL_QP_JF7	0x37078086
237 #define	INTEL_QP_JF8	0x37088086
238 #define	INTEL_QP_JF9	0x37098086
239 #define	INTEL_QP_JFa	0x370a8086
240 #define	INTEL_QP_JFb	0x370b8086
241 #define	INTEL_QP_JFc	0x370c8086
242 #define	INTEL_QP_JFd	0x370d8086
243 #define	INTEL_QP_JFe	0x370e8086
244 #define	INTEL_QP_JFf	0x370f8086
245 
246 /* Intel QuickPath Bus Interconnect Errors */
247 
248 #define	MSR_MC_STATUS_QP_HEADER_PARITY		(1 << 16)
249 #define	MSR_MC_STATUS_QP_DATA_PARITY		(1 << 17)
250 #define	MSR_MC_STATUS_QP_RETRIES_EXCEEDED	(1 << 18)
251 #define	MSR_MC_STATUS_QP_POISON		(1 << 19)
252 
253 #define	MSR_MC_STATUS_QP_UNSUPPORTED_MSG	(1 << 22)
254 #define	MSR_MC_STATUS_QP_UNSUPPORTED_CREDIT	(1 << 23)
255 #define	MSR_MC_STATUS_QP_FLIT_BUF_OVER		(1 << 24)
256 #define	MSR_MC_STATUS_QP_FAILED_RESPONSE	(1 << 25)
257 #define	MSR_MC_STATUS_QP_CLOCK_JITTER		(1 << 26)
258 
259 #define	MSR_MC_MISC_QP_CLASS		0x000000ff
260 #define	MSR_MC_MISC_QP_RTID		0x00003f00
261 #define	MSR_MC_MISC_QP_RHNID		0x00070000
262 #define	MSR_MC_MISC_QP_IIB		0x01000000
263 
264 /* Intel QuickPath Memory Errors */
265 
266 #define	MCAX86_COMPOUND_BUS_MEMORY		0x0080
267 #define	MCAX86_COMPOUND_BUS_MEMORY_MASK		0xff80
268 #define	MCAX86_COMPOUND_BUS_MEMORY_TRANSACTION	0x0070
269 #define	MCAX86_COMPOUND_BUS_MEMORY_READ		0x0010
270 #define	MCAX86_COMPOUND_BUS_MEMORY_WRITE	0x0020
271 #define	MCAX86_COMPOUND_BUS_MEMORY_CMD		0x0030
272 #define	MCAX86_COMPOUND_BUS_MEMORY_CHANNEL	0x000f
273 
274 #define	MSR_MC_STATUS_MEM_ECC_READ	(1 << 16)
275 #define	MSR_MC_STATUS_MEM_ECC_SCRUB	(1 << 17)
276 #define	MSR_MC_STATUS_MEM_PARITY	(1 << 18)
277 #define	MSR_MC_STATUS_MEM_REDUNDANT_MEM	(1 << 19)
278 #define	MSR_MC_STATUS_MEM_SPARE_MEM	(1 << 20)
279 #define	MSR_MC_STATUS_MEM_ILLEGAL_ADDR	(1 << 21)
280 #define	MSR_MC_STATUS_MEM_BAD_ID	(1 << 22)
281 #define	MSR_MC_STATUS_MEM_ADDR_PARITY	(1 << 23)
282 #define	MSR_MC_STATUS_MEM_BYTE_PARITY	(1 << 24)
283 
284 #define	MSR_MC_MISC_MEM_RTID		0x00000000000000ffULL
285 #define	MSR_MC_MISC_MEM_DIMM		0x0000000000030000ULL
286 #define	MSR_MC_MISC_MEM_DIMM_SHIFT	16
287 #define	MSR_MC_MISC_MEM_CHANNEL		0x00000000000c0000ULL
288 #define	MSR_MC_MISC_MEM_CHANNEL_SHIFT	18
289 #define	MSR_MC_MISC_MEM_SYNDROME	0xffffffff00000000ULL
290 #define	MSR_MC_MISC_MEM_SYNDROME_SHIFT	32
291 
292 #define	OFFSET_ROW_BANK_COL	0x8000000000000000ULL
293 #define	OFFSET_RANK_SHIFT	52
294 #define	OFFSET_RAS_SHIFT	32
295 #define	OFFSET_BANK_SHIFT	24
296 #define	TCODE_OFFSET(rank, bank, ras, cas) (OFFSET_ROW_BANK_COL | \
297 	((uint64_t)(rank) << OFFSET_RANK_SHIFT) | \
298 	((uint64_t)(ras) << OFFSET_RAS_SHIFT) | \
299 	((uint64_t)(bank) << OFFSET_BANK_SHIFT) | (cas))
300 
301 #define	MAX_CAS_MASK	0xFFFFFF
302 #define	MAX_BANK_MASK	0xFF
303 #define	MAX_RAS_MASK	0xFFFFF
304 #define	MAX_RANK_MASK	0x7FF
305 #define	TCODE_OFFSET_RANK(tcode) \
306 	(((tcode) >> OFFSET_RANK_SHIFT) & MAX_RANK_MASK)
307 #define	TCODE_OFFSET_RAS(tcode) (((tcode) >> OFFSET_RAS_SHIFT) & MAX_RAS_MASK)
308 #define	TCODE_OFFSET_BANK(tcode) \
309 	(((tcode) >> OFFSET_BANK_SHIFT) & MAX_BANK_MASK)
310 #define	TCODE_OFFSET_CAS(tcode) ((tcode) & MAX_CAS_MASK)
311 
312 #ifdef __cplusplus
313 }
314 #endif
315 
316 #endif /* _MC_INTEL_H */
317