1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright 2020 Joyent, Inc. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34 * Copyright 2018 Nexenta Systems, Inc. 35 * Copyright 2025 Oxide Computer Company 36 * Copyright 2024 MNX Cloud, Inc. 37 */ 38 39 #ifndef _SYS_X86_ARCHEXT_H 40 #define _SYS_X86_ARCHEXT_H 41 42 #if !defined(_ASM) 43 #include <sys/bitext.h> 44 #include <sys/regset.h> 45 #include <sys/processor.h> 46 #include <vm/seg_enum.h> 47 #include <vm/page.h> 48 #endif /* _ASM */ 49 50 #ifdef __cplusplus 51 extern "C" { 52 #endif 53 54 /* 55 * cpuid instruction feature flags in %edx (standard function 1) 56 */ 57 58 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 59 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 60 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 61 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 62 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 63 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 64 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 65 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 66 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 67 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 68 /* 0x400 - reserved */ 69 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 70 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 71 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 72 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 73 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 74 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 75 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 76 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 77 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 78 /* 0x100000 - reserved */ 79 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 80 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 81 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 82 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 83 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 84 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 85 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 86 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 87 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 88 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 89 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 90 91 /* 92 * cpuid instruction feature flags in %ecx (standard function 1) 93 */ 94 95 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 96 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 97 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 98 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 99 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 100 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 101 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 102 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 103 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 104 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 105 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 106 /* 0x00000800 - reserved */ 107 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 108 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 109 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 110 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 111 /* 0x00010000 - reserved */ 112 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 113 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 114 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 115 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 116 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 117 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 118 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 119 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 120 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 121 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 122 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 123 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 124 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 125 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 126 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 127 128 /* 129 * cpuid instruction feature flags in %edx (extended function 0x80000001) 130 */ 131 132 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 133 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 134 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 135 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 136 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 137 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 138 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 139 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 140 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 141 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 142 /* 0x00000400 - sysc on K6m6 */ 143 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 144 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 145 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 146 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 147 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 148 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 149 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 150 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 151 /* 0x00040000 - reserved */ 152 /* 0x00080000 - reserved */ 153 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 154 /* 0x00200000 - reserved */ 155 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 156 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 157 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 158 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 159 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 160 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 161 /* 0x10000000 - reserved */ 162 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 163 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 164 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 165 166 /* 167 * AMD extended function 0x80000001 %ecx 168 */ 169 170 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 171 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 172 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 173 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 174 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 175 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 176 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 177 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 178 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 179 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 180 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 181 #define CPUID_AMD_ECX_XOP 0x00000800 /* AMD: Extended Operation */ 182 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 183 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 184 /* 0x00004000 - reserved */ 185 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 186 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 187 /* 0x00020000 - reserved */ 188 /* 0x00040000 - reserved */ 189 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 190 /* 0x00100000 - reserved */ 191 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 192 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 193 #define CPUID_AMD_ECX_PCEC 0x00800000 /* AMD: Core ext perf counter */ 194 #define CUPID_AMD_ECX_PCENB 0x01000000 /* AMD: NB ext perf counter */ 195 /* 0x02000000 - reserved */ 196 #define CPUID_AMD_ECX_DBKP 0x40000000 /* AMD: Data breakpoint */ 197 #define CPUID_AMD_ECX_PERFTSC 0x08000000 /* AMD: TSC Perf Counter */ 198 #define CPUID_AMD_ECX_PERFL3 0x10000000 /* AMD: L3 Perf Counter */ 199 #define CPUID_AMD_ECX_MONITORX 0x20000000 /* AMD: clzero */ 200 /* 0x40000000 - reserved */ 201 /* 0x80000000 - reserved */ 202 203 /* 204 * AMD uses %ebx for some of their features (extended function 0x80000008). 205 */ 206 #define CPUID_AMD_EBX_CLZERO 0x000000001 /* AMD: CLZERO instr */ 207 #define CPUID_AMD_EBX_IRCMSR 0x000000002 /* AMD: Ret. instrs MSR */ 208 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */ 209 #define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */ 210 #define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */ 211 #define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */ 212 #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */ 213 #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */ 214 #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */ 215 #define CPUID_AMD_EBX_PPIN 0x000800000 /* AMD: PPIN Support */ 216 #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */ 217 #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */ 218 #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */ 219 220 /* 221 * AMD SVM features (extended function 0x8000000A). 222 */ 223 #define CPUID_AMD_EDX_NESTED_PAGING (1 << 0) /* AMD: Nested paging */ 224 #define CPUID_AMD_EDX_LBR_VIRT (1 << 1) /* AMD: LBR virt. */ 225 #define CPUID_AMD_EDX_SVML (1 << 2) /* AMD: SVM lock */ 226 #define CPUID_AMD_EDX_NRIPS (1 << 3) /* AMD: NRIP save */ 227 #define CPUID_AMD_EDX_TSC_RATE_MSR (1 << 4) /* AMD: TSC ratio ctrl */ 228 #define CPUID_AMD_EDX_VMCB_CLEAN (1 << 5) /* AMD: VMCB clean bits */ 229 #define CPUID_AMD_EDX_FLUSH_ASID (1 << 6) /* AMD: flush by ASID */ 230 #define CPUID_AMD_EDX_DECODE_ASSISTS (1 << 7) /* AMD: decode assists */ 231 #define CPUID_AMD_EDX_PAUSE_INCPT (1 << 8) /* AMD: pause intercept */ 232 #define CPUID_AMD_EDX_PAUSE_TRSH (1 << 9) /* AMD: pause threshold */ 233 #define CPUID_AMD_EDX_AVIC (1 << 10) /* AMD: AVIC */ 234 235 /* 236 * AMD Encrypted Memory Capabilities -- 0x8000_001F 237 * 238 * %ecx is the number of encrypted guests. 239 * %edx is the minimum ASID value for SEV enabled, SEV-ES disabled guests 240 */ 241 #define CPUID_AMD_8X1F_EAX_NVS (1 << 29) /* VIRT_RMPUPDATE MSR */ 242 #define CPUID_AMD_8X1F_EAX_SCP (1 << 28) /* SVSM Comm Page MSR */ 243 #define CPUID_AMD_8X1F_EAX_SMT_PROT (1 << 25) /* SMT Protection */ 244 #define CPUID_AMD_8X1F_EAX_VMSAR_PROT (1 << 24) /* VMSA Reg Protection */ 245 #define CPUID_AMD_8X1F_EAX_IBSVGC (1 << 19) /* IBS Virt. for SEV-ES */ 246 #define CPUID_AMD_8X1F_EAX_VIRT_TOM (1 << 18) /* Virt TOM MSR */ 247 #define CPUID_AMD_8X1F_EAX_VMGEXIT (1 << 17) /* VMGEXIT Parameter */ 248 #define CPUID_AMD_8X1F_EAX_VTE (1 << 16) /* Virt Transparent Enc. */ 249 #define CPUID_AMD_8X1F_EAX_NO_IBS (1 << 15) /* No IBS by host */ 250 #define CPUID_AMD_8X1F_EAX_DBGSWP (1 << 14) /* Debug state for SEV-ES */ 251 #define CPUID_AMD_8X1F_EAX_ALT_INJ (1 << 13) /* Alternate Injection */ 252 #define CPUID_AMD_8X1F_EAX_RES_INJ (1 << 12) /* Restricted Injection */ 253 #define CPUID_AMD_8X1F_EAX_64B_HOST (1 << 11) /* SEV requires amd64 */ 254 #define CPUID_AMD_8X1F_EAX_HWECC (1 << 10) /* HW cache coherency req */ 255 #define CPUID_AMD_8X1F_EAX_TSC_AUX (1 << 9) /* TSC AUX Virtualization */ 256 #define CPUID_AMD_8X1F_EAX_SEC_TSC (1 << 8) /* Secure TSC */ 257 #define CPUID_AMD_8X1F_EAX_VSSS (1 << 7) /* VMPL Super. Shadow Stack */ 258 #define CPUID_AMD_8X1F_EAX_RMPQUERY (1 << 6) /* RMPQUERY Instr */ 259 #define CPUID_AMD_8X1F_EAX_VMPL (1 << 5) /* VM Permission Levels */ 260 #define CPUID_AMD_8X1F_EAX_SEV_SNP (1 << 4) /* SEV Secure Nested Paging */ 261 #define CPUID_AMD_8X1F_EAX_SEV_ES (1 << 3) /* SEV Encrypted State */ 262 #define CPUID_AMD_8X1F_EAX_PAGE_FLUSH (1 << 2) /* Page Flush MSR */ 263 #define CPUID_AMD_8X1F_EAX_SEV (1 << 1) /* Secure Encrypted Virt. */ 264 #define CPUID_AMD_8X1F_EAX_SME (1 << 0) /* Secure Memory Encrypt. */ 265 266 #define CPUID_AMD_8X1F_EBX_NVMPL(r) bitx32(r, 15, 12) /* num VM Perm lvl */ 267 #define CPUID_AMD_8X1F_EBX_PAR(r) bitx32(r, 11, 6) /* paddr bit rem */ 268 #define CPUID_AMD_8X1F_EBX_CBIT(r) bitx32(r, 5, 0) /* C-bit loc in PTE */ 269 270 /* 271 * AMD Platform QoS Extended Features -- 0x8000_0020 272 */ 273 #define CPUID_AMD_8X20_EBX_L3RR (1 << 4) /* L3 Range Reservations */ 274 275 /* 276 * AMD Extended Feature 2 -- 0x8000_0021 277 */ 278 #define CPUID_AMD_8X21_EAX_CPUID_DIS (1 << 17) /* CPUID dis for CPL > 0 */ 279 #define CPUID_AMD_8X21_EAX_PREFETCH (1 << 13) /* Prefetch control MSR */ 280 #define CPUID_AMD_8X21_EAX_NO_SMMCTL (1 << 9) /* No SMM_CTL MSR */ 281 #define CPUID_AMD_8X21_EAX_AIBRS (1 << 8) /* Automatic IBRS */ 282 #define CPUID_AMD_8X21_EAX_UAI (1 << 7) /* Upper Address Ignore */ 283 #define CPUID_AMD_8X21_EAX_SMM_PGLK (1 << 3) /* SMM Page config lock */ 284 #define CPUID_AMD_8X21_EAX_LFENCE_SER (1 << 2) /* LFENCE is dispatch serial */ 285 #define CPUID_AMD_8X21_EAX_NO_NDBP (1 << 0) /* No nested data #BP */ 286 287 #define CPUID_AMD_8X21_EBX_MPS(r) bitx32(11, 0) /* MCU Patch size x 16B */ 288 289 /* 290 * AMD Extended Performance Monitoring and Debug -- 0x8000_0022 291 */ 292 #define CPUID_AMD_8X22_LBR_FRZ (1 << 2) /* Freeze PMC / LBR on ovflw */ 293 #define CPUID_AMD_8X22_LBR_STK (1 << 1) /* Last Branch Record Stack */ 294 #define CPUID_AMD_8X22_EAX_PMV2 (1 << 0) /* Perfmon v2 */ 295 296 #define CPUID_AMD_8X22_EBX_NPMC_NB(r) bitx32(r, 15, 10) /* # NB PMC */ 297 #define CPUID_AMD_8X22_EBX_LBR_SZ(r) bitx32(r, 9, 4) /* # LBR Stack ents. */ 298 #define CPUID_AMD_8X22_EBX_NPMC_CORE(r) bitx32(r, 3, 0) /* # core PMC */ 299 300 /* 301 * AMD Secure Multi-key Encryption -- 0x8000_00023 302 */ 303 #define CPUID_AMD_8X23_EAX_MEMHMK (1 << 0) /* Secure Host Multi-Key Mem */ 304 305 #define CPUID_AMD_8X23_EBX_MAX_HMK(r) bitx32(r, 15, 0) /* Max HMK IDs */ 306 307 /* 308 * AMD Extended CPU Topology -- 0x8000_0026 309 * 310 * This is AMD's version of extended CPU topology. The topology level is placed 311 * in %ecx and also contains information about the heterogeneity of the CPUs at 312 * the core level. Note, this is similar to, but not the same as Intel's 0x1f. 313 * 314 * The %eax values other than the APIC shift are only available when the type is 315 * a core. The %ebx values other than the number of logical processors are only 316 * available when the type is a core. The core and native model ID values are 317 * processor specific. 318 * 319 * %edx is the entire extended APIC ID of the logical processor we're on. 320 */ 321 #define CPUID_AMD_8X26_EAX_ASYM_TOPO(r) bitx32(r, 31, 31) 322 #define CPUID_AMD_8x26_EAX_HET_CORES(r) bitx32(r, 30, 30) 323 #define CPUID_AMD_8X26_EAX_EFF_AVAIL(r) bitx32(r, 29, 29) 324 #define CPUID_AMD_8X26_EAX_APIC_SHIFT(r) bitx32(r, 4, 0) 325 326 #define CPUID_AMD_8X26_EBX_CORE_TYPE(r) bitx32(r, 31, 28) 327 #define CPUID_AMD_8X26_EBX_MODEL_ID(r) bitx32(r, 27, 24) 328 #define CPUID_AMD_8X26_EBX_PWR_EFF(r) bitx32(r, 23, 16) 329 #define CPUID_AMD_8X26_EBX_NLOG_PROC(r) bitx32(r, 15, 0) 330 331 #define CPUID_AMD_8X26_ECX_TYPE(r) bitx32(r, 15, 8) 332 #define CPUID_AMD_8X26_TYPE_DONE 0 /* Technically reserved */ 333 #define CUPID_AMD_8X26_TYPE_CORE 1 334 #define CUPID_AMD_8X26_TYPE_COMPLEX 2 335 #define CUPID_AMD_8X26_TYPE_DIE 3 336 #define CUPID_AMD_8X26_TYPE_SOCK 4 337 #define CPUID_AMD_8X26_ECX_INPUT(r) bitx32(r, 7, 0) 338 339 /* 340 * Intel now seems to have claimed part of the "extended" function 341 * space that we previously for non-Intel implementors to use. 342 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 343 * is available in long mode i.e. what AMD indicate using bit 0. 344 * On the other hand, everything else is labelled as reserved. 345 */ 346 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 347 348 /* 349 * Intel uses cpuid leaf 6 to cover various thermal and power control 350 * operations. 351 */ 352 #define CPUID_INTC_EAX_DTS 0x00000001 /* Digital Thermal Sensor */ 353 #define CPUID_INTC_EAX_TURBO 0x00000002 /* Turboboost */ 354 #define CPUID_INTC_EAX_ARAT 0x00000004 /* APIC-Timer-Always-Running */ 355 /* bit 3 is reserved */ 356 #define CPUID_INTC_EAX_PLN 0x00000010 /* Power limit notification */ 357 #define CPUID_INTC_EAX_ECMD 0x00000020 /* Clock mod. duty cycle */ 358 #define CPUID_INTC_EAX_PTM 0x00000040 /* Package thermal management */ 359 #define CPUID_INTC_EAX_HWP 0x00000080 /* HWP base registers */ 360 #define CPUID_INTC_EAX_HWP_NOT 0x00000100 /* HWP Notification */ 361 #define CPUID_INTC_EAX_HWP_ACT 0x00000200 /* HWP Activity Window */ 362 #define CPUID_INTC_EAX_HWP_EPR 0x00000400 /* HWP Energy Perf. Pref. */ 363 #define CPUID_INTC_EAX_HWP_PLR 0x00000800 /* HWP Package Level Request */ 364 /* bit 12 is reserved */ 365 #define CPUID_INTC_EAX_HDC 0x00002000 /* HDC */ 366 #define CPUID_INTC_EAX_TURBO3 0x00004000 /* Turbo Boost Max Tech 3.0 */ 367 #define CPUID_INTC_EAX_HWP_CAP 0x00008000 /* HWP Capabilities */ 368 #define CPUID_INTC_EAX_HWP_PECI 0x00010000 /* HWP PECI override */ 369 #define CPUID_INTC_EAX_HWP_FLEX 0x00020000 /* Flexible HWP */ 370 #define CPUID_INTC_EAX_HWP_FAST 0x00040000 /* Fast IA32_HWP_REQUEST */ 371 /* bit 19 is reserved */ 372 #define CPUID_INTC_EAX_HWP_IDLE 0x00100000 /* Ignore Idle Logical HWP */ 373 374 #define CPUID_INTC_EBX_DTS_NTRESH(x) ((x) & 0xf) 375 376 #define CPUID_INTC_ECX_MAPERF 0x00000001 /* IA32_MPERF / IA32_APERF */ 377 /* bits 1-2 are reserved */ 378 #define CPUID_INTC_ECX_PERFBIAS 0x00000008 /* IA32_ENERGY_PERF_BIAS */ 379 380 /* 381 * Intel also uses cpuid leaf 7 to have additional instructions and features. 382 * Like some other leaves, but unlike the current ones we care about, it 383 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 384 * with the potential use of additional sub-leaves in the future, we now 385 * specifically label the EBX features with their leaf and sub-leaf. 386 */ 387 #define CPUID_INTC_EBX_7_0_FSGSBASE 0x00000001 /* FSGSBASE */ 388 #define CPUID_INTC_EBX_7_0_TSC_ADJ 0x00000002 /* TSC adjust MSR */ 389 #define CPUID_INTC_EBX_7_0_SGX 0x00000004 /* SGX */ 390 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 391 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */ 392 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 393 #define CPUID_INTC_EBX_7_0_FDP_EXCPN 0x00000040 /* FDP on exception */ 394 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 395 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 396 #define CPUID_INTC_EBX_7_0_ENH_REP_MOV 0x00000200 /* Enhanced REP MOVSB */ 397 #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */ 398 #define CPUID_INTC_EBX_7_0_RTM 0x00000800 /* RTM instrs */ 399 #define CPUID_INTC_EBX_7_0_PQM 0x00001000 /* QoS Monitoring */ 400 #define CPUID_INTC_EBX_7_0_DEP_CSDS 0x00002000 /* Deprecates CS/DS */ 401 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */ 402 #define CPUID_INTC_EBX_7_0_PQE 0x00080000 /* QoS Enforcement */ 403 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */ 404 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */ 405 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 406 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 407 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */ 408 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */ 409 /* Bit 22 is reserved */ 410 #define CPUID_INTC_EBX_7_0_CLFLUSHOPT 0x00800000 /* CLFLUSOPT */ 411 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */ 412 #define CPUID_INTC_EBX_7_0_PTRACE 0x02000000 /* Processor Trace */ 413 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */ 414 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */ 415 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */ 416 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 417 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */ 418 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */ 419 420 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \ 421 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \ 422 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \ 423 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \ 424 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL) 425 426 #define CPUID_INTC_ECX_7_0_PREFETCHWT1 0x00000001 /* PREFETCHWT1 */ 427 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */ 428 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */ 429 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */ 430 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */ 431 #define CPUID_INTC_ECX_7_0_WAITPKG 0x00000020 /* WAITPKG */ 432 #define CPUID_INTC_ECX_7_0_AVX512VBMI2 0x00000040 /* AVX512 VBMI2 */ 433 #define CPUID_INTC_ECX_7_0_CET_SS 0x00000080 /* CET Shadow Stack */ 434 #define CPUID_INTC_ECX_7_0_GFNI 0x00000100 /* GFNI */ 435 #define CPUID_INTC_ECX_7_0_VAES 0x00000200 /* VAES */ 436 #define CPUID_INTC_ECX_7_0_VPCLMULQDQ 0x00000400 /* VPCLMULQDQ */ 437 #define CPUID_INTC_ECX_7_0_AVX512VNNI 0x00000800 /* AVX512 VNNI */ 438 #define CPUID_INTC_ECX_7_0_AVX512BITALG 0x00001000 /* AVX512 BITALG */ 439 #define CPUID_INTC_ECX_7_0_TME_EN 0x00002000 /* Total Memory Encr. */ 440 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */ 441 /* bit 15 is reserved */ 442 #define CPUID_INTC_ECX_7_0_LA57 0x00010000 /* 57-bit paging */ 443 /* bits 17-21 are the value of MAWAU */ 444 #define CPUID_INTC_ECX_7_0_RDPID 0x00400000 /* RPID, IA32_TSC_AUX */ 445 #define CPUID_INTC_ECX_7_0_KLSUP 0x00800000 /* Key Locker */ 446 /* bit 24 is reserved */ 447 #define CPUID_INTC_ECX_7_0_CLDEMOTE 0x02000000 /* Cache line demote */ 448 /* bit 26 is resrved */ 449 #define CPUID_INTC_ECX_7_0_MOVDIRI 0x08000000 /* MOVDIRI insn */ 450 #define CPUID_INTC_ECX_7_0_MOVDIR64B 0x10000000 /* MOVDIR64B insn */ 451 #define CPUID_INTC_ECX_7_0_ENQCMD 0x20000000 /* Enqueue Stores */ 452 #define CPUID_INTC_ECX_7_0_SGXLC 0x40000000 /* SGX Launch config */ 453 #define CPUID_INTC_ECX_7_0_PKS 0x80000000 /* protection keys */ 454 455 /* 456 * While CPUID_INTC_ECX_7_0_GFNI, CPUID_INTC_ECX_7_0_VAES, and 457 * CPUID_INTC_ECX_7_0_VPCLMULQDQ all have AVX512 components, they are still 458 * valid when AVX512 is not. However, the following flags all are only valid 459 * when AVX512 is present. 460 */ 461 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \ 462 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VNNI | \ 463 CPUID_INTC_ECX_7_0_AVX512BITALG | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ) 464 465 /* bits 0-1 are reserved */ 466 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */ 467 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ 468 #define CPUID_INTC_EDX_7_0_FSREPMOV 0x00000010 /* fast short rep mov */ 469 #define CPUID_INTC_EDX_7_0_UINTR 0x00000020 /* user interrupts */ 470 /* bits 6-7 are reserved */ 471 #define CPUID_INTC_EDX_7_0_AVX512VP2INT 0x00000100 /* VP2INTERSECT */ 472 /* bit 9 is reserved */ 473 #define CPUID_INTC_EDX_7_0_MD_CLEAR 0x00000400 /* MB VERW */ 474 /* bits 11-13 are reserved */ 475 #define CPUID_INTC_EDX_7_0_SERIALIZE 0x00004000 /* Serialize instr */ 476 #define CPUID_INTC_EDX_7_0_HYBRID 0x00008000 /* Hybrid CPU */ 477 #define CPUID_INTC_EDX_7_0_TSXLDTRK 0x00010000 /* TSX load track */ 478 /* bit 17 is reserved */ 479 #define CPUID_INTC_EDX_7_0_PCONFIG 0x00040000 /* PCONFIG */ 480 /* bit 19 is reserved */ 481 #define CPUID_INTC_EDX_7_0_CET_IBT 0x00100000 /* CET ind. branch */ 482 /* bit 21 is reserved */ 483 #define CPUID_INTC_EDX_7_0_AMX_BF16 0x00400000 /* Tile F16 */ 484 #define CPUID_INTC_EDX_7_0_AVX512FP16 0x00800000 /* AVX512 FP16 */ 485 #define CPUID_INTC_EDX_7_0_AMX_TILE 0x01000000 /* Tile arch */ 486 #define CPUID_INTC_EDX_7_0_AMX_INT8 0x02000000 /* Tile INT8 */ 487 #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */ 488 #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */ 489 #define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */ 490 #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */ 491 #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */ 492 493 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \ 494 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS | \ 495 CPUID_INTC_EDX_7_0_AVX512VP2INT | CPUID_INTC_EDX_7_0_AVX512FP16) 496 497 /* bits 0-3 are reserved */ 498 #define CPUID_INTC_EAX_7_1_AVXVNNI 0x00000010 /* VEX VNNI */ 499 #define CPUID_INTC_EAX_7_1_AVX512_BF16 0x00000020 /* AVX512 BF16 */ 500 /* bits 6-9 are reserved */ 501 #define CPUID_INTC_EAX_7_1_ZL_MOVSB 0x00000400 /* zero-length MOVSB */ 502 #define CPUID_INTC_EAX_7_1_FS_STOSB 0x00000800 /* fast short STOSB */ 503 #define CPUID_INTC_EAX_7_1_FS_CMPSB 0x00001000 /* fast CMPSB, SCASB */ 504 /* bits 13-21 are reserved */ 505 #define CPUID_INTC_EAX_7_1_HRESET 0x00400000 /* History Reset leaf */ 506 /* bits 23-25 are reserved */ 507 #define CPUID_INTC_EAX_7_1_LAM 0x02000000 /* Linear addr mask */ 508 /* bits 27-31 are reserved */ 509 510 #define CPUID_INTC_EDX_7_2_BHI_CTRL (1U << 4U) /* BHI controls */ 511 512 /* 513 * Intel also uses cpuid leaf 0xd to report additional instructions and features 514 * when the sub-leaf in %ecx == 1. We label these using the same convention as 515 * with leaf 7. 516 */ 517 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */ 518 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */ 519 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */ 520 521 #define REG_PAT 0x277 522 #define REG_TSC 0x10 /* timestamp counter */ 523 #define REG_APIC_BASE_MSR 0x1b 524 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 525 526 #if !defined(__xpv) 527 /* 528 * AMD C1E 529 */ 530 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 531 #define AMD_ACTONCMPHALT_SHIFT 27 532 #define AMD_ACTONCMPHALT_MASK 3 533 #endif 534 535 #define MSR_DEBUGCTL 0x1d9 536 537 #define DEBUGCTL_LBR 0x01 538 #define DEBUGCTL_BTF 0x02 539 540 /* Intel P6, AMD */ 541 #define MSR_LBR_FROM 0x1db 542 #define MSR_LBR_TO 0x1dc 543 #define MSR_LEX_FROM 0x1dd 544 #define MSR_LEX_TO 0x1de 545 546 /* Intel P4 (pre-Prescott, non P4 M) */ 547 #define MSR_P4_LBSTK_TOS 0x1da 548 #define MSR_P4_LBSTK_0 0x1db 549 #define MSR_P4_LBSTK_1 0x1dc 550 #define MSR_P4_LBSTK_2 0x1dd 551 #define MSR_P4_LBSTK_3 0x1de 552 553 /* Intel Pentium M */ 554 #define MSR_P6M_LBSTK_TOS 0x1c9 555 #define MSR_P6M_LBSTK_0 0x040 556 #define MSR_P6M_LBSTK_1 0x041 557 #define MSR_P6M_LBSTK_2 0x042 558 #define MSR_P6M_LBSTK_3 0x043 559 #define MSR_P6M_LBSTK_4 0x044 560 #define MSR_P6M_LBSTK_5 0x045 561 #define MSR_P6M_LBSTK_6 0x046 562 #define MSR_P6M_LBSTK_7 0x047 563 564 /* Intel P4 (Prescott) */ 565 #define MSR_PRP4_LBSTK_TOS 0x1da 566 #define MSR_PRP4_LBSTK_FROM_0 0x680 567 #define MSR_PRP4_LBSTK_FROM_1 0x681 568 #define MSR_PRP4_LBSTK_FROM_2 0x682 569 #define MSR_PRP4_LBSTK_FROM_3 0x683 570 #define MSR_PRP4_LBSTK_FROM_4 0x684 571 #define MSR_PRP4_LBSTK_FROM_5 0x685 572 #define MSR_PRP4_LBSTK_FROM_6 0x686 573 #define MSR_PRP4_LBSTK_FROM_7 0x687 574 #define MSR_PRP4_LBSTK_FROM_8 0x688 575 #define MSR_PRP4_LBSTK_FROM_9 0x689 576 #define MSR_PRP4_LBSTK_FROM_10 0x68a 577 #define MSR_PRP4_LBSTK_FROM_11 0x68b 578 #define MSR_PRP4_LBSTK_FROM_12 0x68c 579 #define MSR_PRP4_LBSTK_FROM_13 0x68d 580 #define MSR_PRP4_LBSTK_FROM_14 0x68e 581 #define MSR_PRP4_LBSTK_FROM_15 0x68f 582 #define MSR_PRP4_LBSTK_TO_0 0x6c0 583 #define MSR_PRP4_LBSTK_TO_1 0x6c1 584 #define MSR_PRP4_LBSTK_TO_2 0x6c2 585 #define MSR_PRP4_LBSTK_TO_3 0x6c3 586 #define MSR_PRP4_LBSTK_TO_4 0x6c4 587 #define MSR_PRP4_LBSTK_TO_5 0x6c5 588 #define MSR_PRP4_LBSTK_TO_6 0x6c6 589 #define MSR_PRP4_LBSTK_TO_7 0x6c7 590 #define MSR_PRP4_LBSTK_TO_8 0x6c8 591 #define MSR_PRP4_LBSTK_TO_9 0x6c9 592 #define MSR_PRP4_LBSTK_TO_10 0x6ca 593 #define MSR_PRP4_LBSTK_TO_11 0x6cb 594 #define MSR_PRP4_LBSTK_TO_12 0x6cc 595 #define MSR_PRP4_LBSTK_TO_13 0x6cd 596 #define MSR_PRP4_LBSTK_TO_14 0x6ce 597 #define MSR_PRP4_LBSTK_TO_15 0x6cf 598 599 /* 600 * PPIN definitions for Intel and AMD. Unfortunately, Intel and AMD use 601 * different MSRS for this and different MSRS to control whether or not it 602 * should be readable. 603 */ 604 #define MSR_PPIN_CTL_INTC 0x04e 605 #define MSR_PPIN_INTC 0x04f 606 #define MSR_PLATFORM_INFO 0x0ce 607 #define MSR_PLATFORM_INFO_PPIN (1 << 23) 608 609 #define MSR_PPIN_CTL_AMD 0xC00102F0 610 #define MSR_PPIN_AMD 0xC00102F1 611 612 /* 613 * These values are currently the same between Intel and AMD. 614 */ 615 #define MSR_PPIN_CTL_MASK 0x03 616 #define MSR_PPIN_CTL_DISABLED 0x00 617 #define MSR_PPIN_CTL_LOCKED 0x01 618 #define MSR_PPIN_CTL_ENABLED 0x02 619 620 /* 621 * Intel IA32_ARCH_CAPABILITIES MSR. 622 */ 623 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 624 #define IA32_ARCH_CAP_RDCL_NO (1UL << 0) 625 #define IA32_ARCH_CAP_IBRS_ALL (1UL << 1) 626 #define IA32_ARCH_CAP_RSBA (1UL << 2) 627 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY (1UL << 3) 628 #define IA32_ARCH_CAP_SSB_NO (1UL << 4) 629 #define IA32_ARCH_CAP_MDS_NO (1UL << 5) 630 #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO (1UL << 6) 631 #define IA32_ARCH_CAP_TSX_CTRL (1UL << 7) 632 #define IA32_ARCH_CAP_TAA_NO (1UL << 8) 633 #define IA32_ARCH_CAP_RESERVED_1 (1UL << 9) 634 #define IA32_ARCH_CAP_MCU_CONTROL (1UL << 10) 635 #define IA32_ARCH_CAP_ENERGY_FILTERING_CTL (1UL << 11) 636 #define IA32_ARCH_CAP_DOITM (1UL << 12) 637 #define IA32_ARCH_CAP_SBDR_SSDP_NO (1UL << 13) 638 #define IA32_ARCH_CAP_FBSDP_NO (1UL << 14) 639 #define IA32_ARCH_CAP_PSDP_NO (1UL << 15) 640 #define IA32_ARCH_CAP_RESERVED_2 (1UL << 16) 641 #define IA32_ARCH_CAP_FB_CLEAR (1UL << 17) 642 #define IA32_ARCH_CAP_FB_CLEAR_CTRL (1UL << 18) 643 #define IA32_ARCH_CAP_RRSBA (1UL << 19) 644 #define IA32_ARCH_CAP_BHI_NO (1UL << 20) 645 #define IA32_ARCH_CAP_XAPIC_DISABLE_STATUS (1UL << 21) 646 #define IA32_ARCH_CAP_RESERVED_3 (1UL << 22) 647 #define IA32_ARCH_CAP_OVERCLOCKING_STATUS (1UL << 23) 648 #define IA32_ARCH_CAP_PBRSB_NO (1UL << 24) 649 #define IA32_ARCH_CAP_GDS_CTRL (1UL << 25) 650 #define IA32_ARCH_CAP_GDS_NO (1UL << 26) 651 #define IA32_ARCH_CAP_RFDS_NO (1UL << 27) 652 #define IA32_ARCH_CAP_RFDS_CLEAR (1UL << 28) 653 654 /* 655 * Intel Speculation related MSRs 656 */ 657 #define MSR_IA32_SPEC_CTRL 0x48 658 #define IA32_SPEC_CTRL_IBRS (1UL << 0) 659 #define IA32_SPEC_CTRL_STIBP (1UL << 1) 660 #define IA32_SPEC_CTRL_SSBD (1UL << 2) 661 #define IA32_SPEC_CTRL_IPRED_DIS_U (1UL << 3) 662 #define IA32_SPEC_CTRL_IPRED_DIS_S (1UL << 4) 663 #define IA32_SPEC_CTRL_RRSBA_DIS_U (1UL << 5) 664 #define IA32_SPEC_CTRL_RRSBA_DIS_S (1UL << 6) 665 #define IA32_SPEC_CTRL_PSFD (1UL << 7) 666 #define IA32_SPEC_CTRL_DDPD_U (1UL << 8) 667 #define IA32_SPEC_CTRL_BHI_DIS_S (1UL << 10) 668 669 #define MSR_IA32_PRED_CMD 0x49 670 #define IA32_PRED_CMD_IBPB 0x01 671 672 #define MSR_IA32_FLUSH_CMD 0x10b 673 #define IA32_FLUSH_CMD_L1D 0x01 674 675 /* 676 * Intel VMX related MSRs 677 */ 678 #define MSR_IA32_FEAT_CTRL 0x03a 679 #define IA32_FEAT_CTRL_LOCK 0x1 680 #define IA32_FEAT_CTRL_SMX_EN 0x2 681 #define IA32_FEAT_CTRL_VMX_EN 0x4 682 683 #define MSR_IA32_VMX_BASIC 0x480 684 #define IA32_VMX_BASIC_INS_OUTS (1UL << 54) 685 #define IA32_VMX_BASIC_TRUE_CTRLS (1UL << 55) 686 687 #define MSR_IA32_VMX_PROCBASED_CTLS 0x482 688 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48e 689 #define IA32_VMX_PROCBASED_2ND_CTLS (1UL << 31) 690 691 #define MSR_IA32_VMX_PROCBASED2_CTLS 0x48b 692 #define IA32_VMX_PROCBASED2_EPT (1UL << 1) 693 #define IA32_VMX_PROCBASED2_VPID (1UL << 5) 694 695 #define MSR_IA32_VMX_EPT_VPID_CAP 0x48c 696 #define IA32_VMX_EPT_VPID_EXEC_ONLY (1UL << 0) 697 #define IA32_VMX_EPT_VPID_PWL4 (1UL << 6) 698 #define IA32_VMX_EPT_VPID_TYPE_UC (1UL << 8) 699 #define IA32_VMX_EPT_VPID_TYPE_WB (1UL << 14) 700 #define IA32_VMX_EPT_VPID_MAP_2M (1UL << 16) 701 #define IA32_VMX_EPT_VPID_MAP_1G (1UL << 17) 702 #define IA32_VMX_EPT_VPID_HW_AD (1UL << 21) 703 #define IA32_VMX_EPT_VPID_INVEPT (1UL << 20) 704 #define IA32_VMX_EPT_VPID_INVEPT_SINGLE (1UL << 25) 705 #define IA32_VMX_EPT_VPID_INVEPT_ALL (1UL << 26) 706 #define IA32_VMX_EPT_VPID_INVVPID (1UL << 32) 707 #define IA32_VMX_EPT_VPID_INVVPID_ADDR (1UL << 40) 708 #define IA32_VMX_EPT_VPID_INVVPID_SINGLE (1UL << 41) 709 #define IA32_VMX_EPT_VPID_INVVPID_ALL (1UL << 42) 710 #define IA32_VMX_EPT_VPID_INVVPID_RETAIN (1UL << 43) 711 712 /* 713 * Intel TSX Control MSRs 714 */ 715 #define MSR_IA32_TSX_CTRL 0x122 716 #define IA32_TSX_CTRL_RTM_DISABLE 0x01 717 #define IA32_TSX_CTRL_CPUID_CLEAR 0x02 718 719 /* 720 * Intel Thermal MSRs 721 */ 722 #define MSR_IA32_THERM_INTERRUPT 0x19b 723 #define IA32_THERM_INTERRUPT_HIGH_IE 0x00000001 724 #define IA32_THERM_INTERRUPT_LOW_IE 0x00000002 725 #define IA32_THERM_INTERRUPT_PROCHOT_IE 0x00000004 726 #define IA32_THERM_INTERRUPT_FORCEPR_IE 0x00000008 727 #define IA32_THERM_INTERRUPT_CRIT_IE 0x00000010 728 #define IA32_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) 729 #define IA32_THERM_INTTERUPT_TR1_IE 0x00008000 730 #define IA32_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) 731 #define IA32_THERM_INTERRUPT_TR2_IE 0x00800000 732 #define IA32_THERM_INTERRUPT_PL_NE 0x01000000 733 734 #define MSR_IA32_THERM_STATUS 0x19c 735 #define IA32_THERM_STATUS_STATUS 0x00000001 736 #define IA32_THERM_STATUS_STATUS_LOG 0x00000002 737 #define IA32_THERM_STATUS_PROCHOT 0x00000004 738 #define IA32_THERM_STATUS_PROCHOT_LOG 0x00000008 739 #define IA32_THERM_STATUS_CRIT_STATUS 0x00000010 740 #define IA32_THERM_STATUS_CRIT_LOG 0x00000020 741 #define IA32_THERM_STATUS_TR1_STATUS 0x00000040 742 #define IA32_THERM_STATUS_TR1_LOG 0x00000080 743 #define IA32_THERM_STATUS_TR2_STATUS 0x00000100 744 #define IA32_THERM_STATUS_TR2_LOG 0x00000200 745 #define IA32_THERM_STATUS_POWER_LIMIT_STATUS 0x00000400 746 #define IA32_THERM_STATUS_POWER_LIMIT_LOG 0x00000800 747 #define IA32_THERM_STATUS_CURRENT_STATUS 0x00001000 748 #define IA32_THERM_STATUS_CURRENT_LOG 0x00002000 749 #define IA32_THERM_STATUS_CROSS_DOMAIN_STATUS 0x00004000 750 #define IA32_THERM_STATUS_CROSS_DOMAIN_LOG 0x00008000 751 #define IA32_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) 752 #define IA32_THERM_STATUS_RESOLUTION(x) (((x) >> 27) & 0x0f) 753 #define IA32_THERM_STATUS_READ_VALID 0x80000000 754 755 #define MSR_TEMPERATURE_TARGET 0x1a2 756 #define MSR_TEMPERATURE_TARGET_TARGET(x) (((x) >> 16) & 0xff) 757 /* 758 * Not all models support the offset. Refer to the Intel SDM Volume 4 for a list 759 * of which models have support for which bits. 760 */ 761 #define MSR_TEMPERATURE_TARGET_OFFSET(x) (((x) >> 24) & 0x0f) 762 763 #define MSR_IA32_PACKAGE_THERM_STATUS 0x1b1 764 #define IA32_PKG_THERM_STATUS_STATUS 0x00000001 765 #define IA32_PKG_THERM_STATUS_STATUS_LOG 0x00000002 766 #define IA32_PKG_THERM_STATUS_PROCHOT 0x00000004 767 #define IA32_PKG_THERM_STATUS_PROCHOT_LOG 0x00000008 768 #define IA32_PKG_THERM_STATUS_CRIT_STATUS 0x00000010 769 #define IA32_PKG_THERM_STATUS_CRIT_LOG 0x00000020 770 #define IA32_PKG_THERM_STATUS_TR1_STATUS 0x00000040 771 #define IA32_PKG_THERM_STATUS_TR1_LOG 0x00000080 772 #define IA32_PKG_THERM_STATUS_TR2_STATUS 0x00000100 773 #define IA32_PKG_THERM_STATUS_TR2_LOG 0x00000200 774 #define IA32_PKG_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) 775 776 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2 777 #define IA32_PKG_THERM_INTERRUPT_HIGH_IE 0x00000001 778 #define IA32_PKG_THERM_INTERRUPT_LOW_IE 0x00000002 779 #define IA32_PKG_THERM_INTERRUPT_PROCHOT_IE 0x00000004 780 #define IA32_PKG_THERM_INTERRUPT_OVERHEAT_IE 0x00000010 781 #define IA32_PKG_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) 782 #define IA32_PKG_THERM_INTTERUPT_TR1_IE 0x00008000 783 #define IA32_PKG_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) 784 #define IA32_PKG_THERM_INTERRUPT_TR2_IE 0x00800000 785 #define IA32_PKG_THERM_INTERRUPT_PL_NE 0x01000000 786 787 /* 788 * AMD Performance counters 789 * 790 * Older (pre-F15h) CPUs exposed a set of 4 CPU performance counters, along with 791 * corresponding control registers. F15h and later CPUs added an additional 2 792 * CPU counters, exposing them all through a new range of MSRs (with the 793 * original 4 counters aliasing onto the new ones, entries 0-3) 794 * 795 * Support for those newer extended counters is denoted by CPUID_AMD_ECX_PCEC in 796 * function 0x80000001. 797 */ 798 #define MSR_AMD_K7_PERF_EVTSEL0 0xc0010000 799 #define MSR_AMD_K7_PERF_EVTSEL1 0xc0010001 800 #define MSR_AMD_K7_PERF_EVTSEL2 0xc0010002 801 #define MSR_AMD_K7_PERF_EVTSEL3 0xc0010003 802 #define MSR_AMD_K7_PERF_CTR0 0xc0010004 803 #define MSR_AMD_K7_PERF_CTR1 0xc0010005 804 #define MSR_AMD_K7_PERF_CTR2 0xc0010006 805 #define MSR_AMD_K7_PERF_CTR3 0xc0010007 806 807 #define MSR_AMD_F15H_PERF_EVTSEL0 0xc0010200 808 #define MSR_AMD_F15H_PERF_EVTSEL1 0xc0010202 809 #define MSR_AMD_F15H_PERF_EVTSEL2 0xc0010204 810 #define MSR_AMD_F15H_PERF_EVTSEL3 0xc0010206 811 #define MSR_AMD_F15H_PERF_EVTSEL4 0xc0010208 812 #define MSR_AMD_F15H_PERF_EVTSEL5 0xc001020a 813 814 #define MSR_AMD_F15H_PERF_CTR0 0xc0010201 815 #define MSR_AMD_F15H_PERF_CTR1 0xc0010203 816 #define MSR_AMD_F15H_PERF_CTR2 0xc0010205 817 #define MSR_AMD_F15H_PERF_CTR3 0xc0010207 818 #define MSR_AMD_F15H_PERF_CTR4 0xc0010209 819 #define MSR_AMD_F15H_PERF_CTR5 0xc001020b 820 821 #define AMD_PERF_EVTSEL_EVT_MASK 0xf000000ff /* Event select bits */ 822 #define AMD_PERF_EVTSEL_UNIT_MASK 0xff00 /* Unit mask */ 823 #define AMD_PERF_EVTSEL_USER_MODE (1 << 16) /* User mode */ 824 #define AMD_PERF_EVTSEL_OS_MODE (1 << 17) /* OS mode */ 825 #define AMD_PERF_EVTSEL_EDGE (1 << 18) /* Edge detect */ 826 #define AMD_PERF_EVTSEL_INT_EN (1 << 20) /* Interrupt enable */ 827 #define AMD_PERF_EVTSEL_CTR_EN (1 << 22) /* Counter enable */ 828 #define AMD_PERF_EVTSEL_INV_CMP (1 << 23) /* Invert comparison */ 829 #define AMD_PERF_EVTSEL_CNT_MASK 0xff000000 /* Counter mask */ 830 #define AMD_PERF_EVTSEL_HG_MASK 0x30000000000 /* Host/guest mask */ 831 832 #define AMD_PERF_EVTSEL_HG_GUEST 0x10000000000 /* Guest-only */ 833 #define AMD_PERF_EVTSEL_HG_HOST 0x20000000000 /* Host-only */ 834 #define AMD_PERF_EVTSEL_HG_BOTH 0x30000000000 /* Guest and host */ 835 836 /* 837 * AMD TOM and TOM2 MSRs. These control the split between DRAM and MMIO below 838 * and above 4 GiB respectively. These have existed since family 0xf. 839 * 840 * Note that these widened around the time of Zen 4, going from 48 to 52 bits. 841 * However, in a presumed nod to backwards compatibily, the AMD APM Vol 2 842 * section 7.9.4 ("Top of Memory"), states that "a given processor may implement 843 * fewer than the architecturally-defined number of physical address bits." It 844 * also states that unused bits are ignored, though system software should zero 845 * them for compatibility future extensions. These facts taken together suggest 846 * that we are safe to define these masks as the widest architecturally allowed. 847 */ 848 #define MSR_AMD_TOM 0xc001001a 849 #define MSR_AMD_TOM_MASK(x) ((x) & 0x000fffffff800000) 850 #define MSR_AMD_TOM2 0xc001001d 851 #define MSR_AMD_TOM2_MASK(x) ((x) & 0x000fffffff800000) 852 853 /* 854 * Core::X86::Msr::CPUID_7_FEATURES. AMD MSR which provides control over the 855 * features advertised in %eax and %ebx for CPUID leaf 7. 856 */ 857 #define MSR_AMD_CPUID7_FEATURES 0xc0011002 858 #define MSR_AMD_CPUID7_FEATURES_RDSEED (1 << 18) 859 860 #define MCI_CTL_VALUE 0xffffffff 861 862 #define MTRR_TYPE_UC 0 863 #define MTRR_TYPE_WC 1 864 #define MTRR_TYPE_WT 4 865 #define MTRR_TYPE_WP 5 866 #define MTRR_TYPE_WB 6 867 #define MTRR_TYPE_UC_ 7 868 869 /* 870 * For Solaris we set up the page attritubute table in the following way: 871 * PAT0 Write-Back 872 * PAT1 Write-Through 873 * PAT2 Unchacheable- 874 * PAT3 Uncacheable 875 * PAT4 Write-Back 876 * PAT5 Write-Through 877 * PAT6 Write-Combine 878 * PAT7 Uncacheable 879 * The only difference from h/w default is entry 6. 880 */ 881 #define PAT_DEFAULT_ATTRIBUTE \ 882 ((uint64_t)MTRR_TYPE_WB | \ 883 ((uint64_t)MTRR_TYPE_WT << 8) | \ 884 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 885 ((uint64_t)MTRR_TYPE_UC << 24) | \ 886 ((uint64_t)MTRR_TYPE_WB << 32) | \ 887 ((uint64_t)MTRR_TYPE_WT << 40) | \ 888 ((uint64_t)MTRR_TYPE_WC << 48) | \ 889 ((uint64_t)MTRR_TYPE_UC << 56)) 890 891 #define X86FSET_LARGEPAGE 0 892 #define X86FSET_TSC 1 893 #define X86FSET_MSR 2 894 #define X86FSET_MTRR 3 895 #define X86FSET_PGE 4 896 #define X86FSET_DE 5 897 #define X86FSET_CMOV 6 898 #define X86FSET_MMX 7 899 #define X86FSET_MCA 8 900 #define X86FSET_PAE 9 901 #define X86FSET_CX8 10 902 #define X86FSET_PAT 11 903 #define X86FSET_SEP 12 904 #define X86FSET_SSE 13 905 #define X86FSET_SSE2 14 906 #define X86FSET_HTT 15 907 #define X86FSET_ASYSC 16 908 #define X86FSET_NX 17 909 #define X86FSET_SSE3 18 910 #define X86FSET_CX16 19 911 #define X86FSET_CMP 20 912 #define X86FSET_TSCP 21 913 #define X86FSET_MWAIT 22 914 #define X86FSET_SSE4A 23 915 #define X86FSET_CPUID 24 916 #define X86FSET_SSSE3 25 917 #define X86FSET_SSE4_1 26 918 #define X86FSET_SSE4_2 27 919 #define X86FSET_1GPG 28 920 #define X86FSET_CLFSH 29 921 #define X86FSET_64 30 922 #define X86FSET_AES 31 923 #define X86FSET_PCLMULQDQ 32 924 #define X86FSET_XSAVE 33 925 #define X86FSET_AVX 34 926 #define X86FSET_VMX 35 927 #define X86FSET_SVM 36 928 #define X86FSET_TOPOEXT 37 929 #define X86FSET_F16C 38 930 #define X86FSET_RDRAND 39 931 #define X86FSET_X2APIC 40 932 #define X86FSET_AVX2 41 933 #define X86FSET_BMI1 42 934 #define X86FSET_BMI2 43 935 #define X86FSET_FMA 44 936 #define X86FSET_SMEP 45 937 #define X86FSET_SMAP 46 938 #define X86FSET_ADX 47 939 #define X86FSET_RDSEED 48 940 #define X86FSET_MPX 49 941 #define X86FSET_AVX512F 50 942 #define X86FSET_AVX512DQ 51 943 #define X86FSET_AVX512PF 52 944 #define X86FSET_AVX512ER 53 945 #define X86FSET_AVX512CD 54 946 #define X86FSET_AVX512BW 55 947 #define X86FSET_AVX512VL 56 948 #define X86FSET_AVX512FMA 57 949 #define X86FSET_AVX512VBMI 58 950 #define X86FSET_AVX512VPOPCDQ 59 951 #define X86FSET_AVX512NNIW 60 952 #define X86FSET_AVX512FMAPS 61 953 #define X86FSET_XSAVEOPT 62 954 #define X86FSET_XSAVEC 63 955 #define X86FSET_XSAVES 64 956 #define X86FSET_SHA 65 957 #define X86FSET_UMIP 66 958 #define X86FSET_PKU 67 959 #define X86FSET_OSPKE 68 960 #define X86FSET_PCID 69 961 #define X86FSET_INVPCID 70 962 #define X86FSET_IBRS 71 963 #define X86FSET_IBPB 72 964 #define X86FSET_STIBP 73 965 #define X86FSET_SSBD 74 966 #define X86FSET_SSBD_VIRT 75 967 #define X86FSET_RDCL_NO 76 968 #define X86FSET_IBRS_ALL 77 969 #define X86FSET_RSBA 78 970 #define X86FSET_SSB_NO 79 971 #define X86FSET_STIBP_ALL 80 972 #define X86FSET_FLUSH_CMD 81 973 #define X86FSET_L1D_VM_NO 82 974 #define X86FSET_FSGSBASE 83 975 #define X86FSET_CLFLUSHOPT 84 976 #define X86FSET_CLWB 85 977 #define X86FSET_MONITORX 86 978 #define X86FSET_CLZERO 87 979 #define X86FSET_XOP 88 980 #define X86FSET_FMA4 89 981 #define X86FSET_TBM 90 982 #define X86FSET_AVX512VNNI 91 983 #define X86FSET_AMD_PCEC 92 984 #define X86FSET_MD_CLEAR 93 985 #define X86FSET_MDS_NO 94 986 #define X86FSET_CORE_THERMAL 95 987 #define X86FSET_PKG_THERMAL 96 988 #define X86FSET_TSX_CTRL 97 989 #define X86FSET_TAA_NO 98 990 #define X86FSET_PPIN 99 991 #define X86FSET_VAES 100 992 #define X86FSET_VPCLMULQDQ 101 993 #define X86FSET_LFENCE_SER 102 994 #define X86FSET_GFNI 103 995 #define X86FSET_AVX512_VP2INT 104 996 #define X86FSET_AVX512_BITALG 105 997 #define X86FSET_AVX512_VBMI2 106 998 #define X86FSET_AVX512_BF16 107 999 #define X86FSET_AUTO_IBRS 108 1000 #define X86FSET_RFDS_NO 109 1001 #define X86FSET_RFDS_CLEAR 110 1002 #define X86FSET_PBRSB_NO 111 1003 #define X86FSET_BHI_NO 112 1004 #define X86FSET_BHI_CTRL 113 1005 1006 /* 1007 * Intel Deep C-State invariant TSC in leaf 0x80000007. 1008 */ 1009 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 1010 1011 /* 1012 * Intel TSC deadline timer 1013 */ 1014 #define CPUID_DEADLINE_TSC (1 << 24) 1015 1016 /* 1017 * x86_type is a legacy concept; this is supplanted 1018 * for most purposes by x86_featureset; modern CPUs 1019 * should be X86_TYPE_OTHER 1020 */ 1021 #define X86_TYPE_OTHER 0 1022 #define X86_TYPE_486 1 1023 #define X86_TYPE_P5 2 1024 #define X86_TYPE_P6 3 1025 #define X86_TYPE_CYRIX_486 4 1026 #define X86_TYPE_CYRIX_6x86L 5 1027 #define X86_TYPE_CYRIX_6x86 6 1028 #define X86_TYPE_CYRIX_GXm 7 1029 #define X86_TYPE_CYRIX_6x86MX 8 1030 #define X86_TYPE_CYRIX_MediaGX 9 1031 #define X86_TYPE_CYRIX_MII 10 1032 #define X86_TYPE_VIA_CYRIX_III 11 1033 #define X86_TYPE_P4 12 1034 1035 /* 1036 * x86_vendor allows us to select between 1037 * implementation features and helps guide 1038 * the interpretation of the cpuid instruction. 1039 */ 1040 #define X86_VENDOR_Intel 0 1041 #define X86_VENDORSTR_Intel "GenuineIntel" 1042 1043 #define X86_VENDOR_IntelClone 1 1044 1045 #define X86_VENDOR_AMD 2 1046 #define X86_VENDORSTR_AMD "AuthenticAMD" 1047 1048 #define X86_VENDOR_Cyrix 3 1049 #define X86_VENDORSTR_CYRIX "CyrixInstead" 1050 1051 #define X86_VENDOR_UMC 4 1052 #define X86_VENDORSTR_UMC "UMC UMC UMC " 1053 1054 #define X86_VENDOR_NexGen 5 1055 #define X86_VENDORSTR_NexGen "NexGenDriven" 1056 1057 #define X86_VENDOR_Centaur 6 1058 #define X86_VENDORSTR_Centaur "CentaurHauls" 1059 1060 #define X86_VENDOR_Rise 7 1061 #define X86_VENDORSTR_Rise "RiseRiseRise" 1062 1063 #define X86_VENDOR_SiS 8 1064 #define X86_VENDORSTR_SiS "SiS SiS SiS " 1065 1066 #define X86_VENDOR_TM 9 1067 #define X86_VENDORSTR_TM "GenuineTMx86" 1068 1069 #define X86_VENDOR_NSC 10 1070 #define X86_VENDORSTR_NSC "Geode by NSC" 1071 1072 #define X86_VENDOR_HYGON 11 1073 #define X86_VENDORSTR_HYGON "HygonGenuine" 1074 1075 /* 1076 * Vendor string max len + \0 1077 */ 1078 #define X86_VENDOR_STRLEN 13 1079 1080 /* 1081 * For lookups and matching functions only; not an actual vendor. 1082 */ 1083 #define _X86_VENDOR_MATCH_ALL 0xff 1084 1085 /* 1086 * See the big theory statement at the top of cpuid.c for information about how 1087 * processor families and microarchitecture families relate to cpuid families, 1088 * models, and steppings. 1089 */ 1090 1091 #define _X86_CHIPREV_VENDOR_SHIFT 24 1092 #define _X86_CHIPREV_FAMILY_SHIFT 16 1093 1094 #define _X86_CHIPREV_VENDOR(x) \ 1095 bitx32((uint32_t)(x), 31, _X86_CHIPREV_VENDOR_SHIFT) 1096 1097 #define _X86_CHIPREV_FAMILY(x) \ 1098 bitx32((uint32_t)(x), 23, _X86_CHIPREV_FAMILY_SHIFT) 1099 1100 #define _X86_CHIPREV_REV(x) \ 1101 bitx32((uint32_t)(x), 15, 0) 1102 1103 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 1104 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 1105 (uint32_t)(family) << _X86_CHIPREV_FAMILY_SHIFT | (uint32_t)(rev)) 1106 1107 /* 1108 * The legacy families here are a little bit unfortunate. Part of this is that 1109 * the way AMD used the cpuid family/model/stepping changed somewhat over time, 1110 * but the more immediate reason it's this way is more that the way we use 1111 * chiprev/processor family changed with it. The ancient amd_opteron and mc-amd 1112 * drivers used the chiprevs that were based on cpuid family, mainly 0xf and 1113 * 0x10. amdzen_umc wants the processor family, in part because AMD's 1114 * overloading of the cpuid family has made it effectively useless for 1115 * discerning anything about the processor. That also tied into the way 1116 * amd_revmap was previously organised in cpuid_subr.c: up to family 0x14 1117 * everything was just "rev A", "rev B", etc.; afterward we started using the 1118 * new shorthand, again tied to how AMD was presenting this information. 1119 * Because there are other consumers of the processor family, it no longer made 1120 * sense for amdzen to derive the processor family from the cpuid family/model 1121 * given that we have this collection of definitions already and code in 1122 * cpuid_subr.c to make use of them. The result is this unified approach that 1123 * tries to keep old consumers happy while allowing new ones to get the degree 1124 * of detail they need and expect. That required bending things a bit to make 1125 * them fit, though critically as long as AMD keep on their current path and all 1126 * new consumers look like the ones we are adding these days, we will be able to 1127 * continue making new additions that will match all the recent ones and the way 1128 * AMD are currently using families and models. There is absolutely no reason 1129 * we couldn't go back and dig through all the legacy parts and break them down 1130 * the same way, then change the old MC and CPU drivers to match, but I didn't 1131 * feel like doing a lot of work for processors that it's unlikely anyone is 1132 * still using and even more unlikely anyone will introduce new code to support. 1133 * My compromise was to flesh things out starting where we already had more 1134 * detail even if nothing was consuming it programmatically: at 0x15. Before 1135 * that, processor family and cpuid family were effectively the same, because 1136 * that's what those old consumers expect. 1137 */ 1138 1139 #ifndef _ASM 1140 typedef enum x86_processor_family { 1141 X86_PF_UNKNOWN, 1142 X86_PF_AMD_LEGACY_F = 0xf, 1143 X86_PF_AMD_LEGACY_10 = 0x10, 1144 X86_PF_AMD_LEGACY_11 = 0x11, 1145 X86_PF_AMD_LEGACY_12 = 0x12, 1146 X86_PF_AMD_LEGACY_14 = 0x14, 1147 X86_PF_AMD_OROCHI, 1148 X86_PF_AMD_TRINITY, 1149 X86_PF_AMD_KAVERI, 1150 X86_PF_AMD_CARRIZO, 1151 X86_PF_AMD_STONEY_RIDGE, 1152 X86_PF_AMD_KABINI, 1153 X86_PF_AMD_MULLINS, 1154 X86_PF_AMD_NAPLES, 1155 X86_PF_AMD_PINNACLE_RIDGE, 1156 X86_PF_AMD_RAVEN_RIDGE, 1157 X86_PF_AMD_PICASSO, 1158 X86_PF_AMD_DALI, 1159 X86_PF_AMD_ROME, 1160 X86_PF_AMD_RENOIR, 1161 X86_PF_AMD_MATISSE, 1162 X86_PF_AMD_VAN_GOGH, 1163 X86_PF_AMD_MENDOCINO, 1164 X86_PF_HYGON_DHYANA, 1165 X86_PF_AMD_MILAN, 1166 X86_PF_AMD_GENOA, 1167 X86_PF_AMD_VERMEER, 1168 X86_PF_AMD_REMBRANDT, 1169 X86_PF_AMD_CEZANNE, 1170 X86_PF_AMD_RAPHAEL, 1171 X86_PF_AMD_PHOENIX, 1172 X86_PF_AMD_BERGAMO, 1173 X86_PF_AMD_TURIN, 1174 X86_PF_AMD_DENSE_TURIN, 1175 X86_PF_AMD_STRIX, 1176 X86_PF_AMD_GRANITE_RIDGE, 1177 X86_PF_AMD_KRACKAN, 1178 X86_PF_AMD_STRIX_HALO, 1179 1180 X86_PF_ANY = 0xff 1181 } x86_processor_family_t; 1182 1183 #define _DECL_CHIPREV(_v, _f, _revn, _revb) \ 1184 X86_CHIPREV_ ## _v ## _ ## _f ## _ ## _revn = \ 1185 _X86_CHIPREV_MKREV(X86_VENDOR_ ## _v, X86_PF_ ## _v ## _ ## _f, _revb) 1186 1187 #define _X86_CHIPREV_REV_MATCH_ALL 0xffff 1188 1189 typedef enum x86_chiprev { 1190 X86_CHIPREV_UNKNOWN, 1191 _DECL_CHIPREV(AMD, LEGACY_F, REV_B, 0x0001), 1192 /* 1193 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 1194 * sufficiently different that we will distinguish them; in all other 1195 * case we will identify the major revision. 1196 */ 1197 _DECL_CHIPREV(AMD, LEGACY_F, REV_C0, 0x0002), 1198 _DECL_CHIPREV(AMD, LEGACY_F, REV_CG, 0x0004), 1199 _DECL_CHIPREV(AMD, LEGACY_F, REV_D, 0x0008), 1200 _DECL_CHIPREV(AMD, LEGACY_F, REV_E, 0x0010), 1201 _DECL_CHIPREV(AMD, LEGACY_F, REV_F, 0x0020), 1202 _DECL_CHIPREV(AMD, LEGACY_F, REV_G, 0x0040), 1203 _DECL_CHIPREV(AMD, LEGACY_F, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1204 1205 _DECL_CHIPREV(AMD, LEGACY_10, UNKNOWN, 0x0001), 1206 _DECL_CHIPREV(AMD, LEGACY_10, REV_A, 0x0002), 1207 _DECL_CHIPREV(AMD, LEGACY_10, REV_B, 0x0004), 1208 _DECL_CHIPREV(AMD, LEGACY_10, REV_C2, 0x0008), 1209 _DECL_CHIPREV(AMD, LEGACY_10, REV_C3, 0x0010), 1210 _DECL_CHIPREV(AMD, LEGACY_10, REV_D0, 0x0020), 1211 _DECL_CHIPREV(AMD, LEGACY_10, REV_D1, 0x0040), 1212 _DECL_CHIPREV(AMD, LEGACY_10, REV_E, 0x0080), 1213 _DECL_CHIPREV(AMD, LEGACY_10, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1214 1215 _DECL_CHIPREV(AMD, LEGACY_11, UNKNOWN, 0x0001), 1216 _DECL_CHIPREV(AMD, LEGACY_11, REV_B, 0x0002), 1217 _DECL_CHIPREV(AMD, LEGACY_11, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1218 1219 _DECL_CHIPREV(AMD, LEGACY_12, UNKNOWN, 0x0001), 1220 _DECL_CHIPREV(AMD, LEGACY_12, REV_B, 0x0002), 1221 _DECL_CHIPREV(AMD, LEGACY_12, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1222 1223 _DECL_CHIPREV(AMD, LEGACY_14, UNKNOWN, 0x0001), 1224 _DECL_CHIPREV(AMD, LEGACY_14, REV_B, 0x0002), 1225 _DECL_CHIPREV(AMD, LEGACY_14, REV_C, 0x0004), 1226 _DECL_CHIPREV(AMD, LEGACY_14, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1227 1228 _DECL_CHIPREV(AMD, OROCHI, UNKNOWN, 0x0001), 1229 _DECL_CHIPREV(AMD, OROCHI, REV_B2, 0x0002), 1230 _DECL_CHIPREV(AMD, OROCHI, REV_C0, 0x0004), 1231 _DECL_CHIPREV(AMD, OROCHI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1232 1233 _DECL_CHIPREV(AMD, TRINITY, UNKNOWN, 0x0001), 1234 _DECL_CHIPREV(AMD, TRINITY, REV_A1, 0x0002), 1235 _DECL_CHIPREV(AMD, TRINITY, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1236 1237 _DECL_CHIPREV(AMD, KAVERI, UNKNOWN, 0x0001), 1238 _DECL_CHIPREV(AMD, KAVERI, REV_A1, 0x0002), 1239 _DECL_CHIPREV(AMD, KAVERI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1240 1241 _DECL_CHIPREV(AMD, CARRIZO, UNKNOWN, 0x0001), 1242 _DECL_CHIPREV(AMD, CARRIZO, REV_A0, 0x0002), 1243 _DECL_CHIPREV(AMD, CARRIZO, REV_A1, 0x0004), 1244 _DECL_CHIPREV(AMD, CARRIZO, REV_DDR4, 0x0008), 1245 _DECL_CHIPREV(AMD, CARRIZO, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1246 1247 _DECL_CHIPREV(AMD, STONEY_RIDGE, UNKNOWN, 0x0001), 1248 _DECL_CHIPREV(AMD, STONEY_RIDGE, REV_A0, 0x0002), 1249 _DECL_CHIPREV(AMD, STONEY_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1250 1251 _DECL_CHIPREV(AMD, KABINI, UNKNOWN, 0x0001), 1252 _DECL_CHIPREV(AMD, KABINI, A1, 0x0002), 1253 _DECL_CHIPREV(AMD, KABINI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1254 1255 _DECL_CHIPREV(AMD, MULLINS, UNKNOWN, 0x0001), 1256 _DECL_CHIPREV(AMD, MULLINS, A1, 0x0002), 1257 _DECL_CHIPREV(AMD, MULLINS, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1258 1259 _DECL_CHIPREV(AMD, NAPLES, UNKNOWN, 0x0001), 1260 _DECL_CHIPREV(AMD, NAPLES, A0, 0x0002), 1261 _DECL_CHIPREV(AMD, NAPLES, B1, 0x0004), 1262 _DECL_CHIPREV(AMD, NAPLES, B2, 0x0008), 1263 _DECL_CHIPREV(AMD, NAPLES, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1264 1265 _DECL_CHIPREV(AMD, PINNACLE_RIDGE, UNKNOWN, 0x0001), 1266 _DECL_CHIPREV(AMD, PINNACLE_RIDGE, B2, 0x0002), 1267 _DECL_CHIPREV(AMD, PINNACLE_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1268 1269 _DECL_CHIPREV(AMD, RAVEN_RIDGE, UNKNOWN, 0x0001), 1270 _DECL_CHIPREV(AMD, RAVEN_RIDGE, B0, 0x0002), 1271 _DECL_CHIPREV(AMD, RAVEN_RIDGE, B1, 0x0004), 1272 _DECL_CHIPREV(AMD, RAVEN_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1273 1274 _DECL_CHIPREV(AMD, PICASSO, UNKNOWN, 0x0001), 1275 _DECL_CHIPREV(AMD, PICASSO, B1, 0x0002), 1276 _DECL_CHIPREV(AMD, PICASSO, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1277 1278 _DECL_CHIPREV(AMD, DALI, UNKNOWN, 0x0001), 1279 _DECL_CHIPREV(AMD, DALI, A1, 0x0002), 1280 _DECL_CHIPREV(AMD, DALI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1281 1282 _DECL_CHIPREV(AMD, ROME, UNKNOWN, 0x0001), 1283 _DECL_CHIPREV(AMD, ROME, A0, 0x0002), 1284 _DECL_CHIPREV(AMD, ROME, B0, 0x0004), 1285 _DECL_CHIPREV(AMD, ROME, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1286 1287 _DECL_CHIPREV(AMD, RENOIR, UNKNOWN, 0x0001), 1288 _DECL_CHIPREV(AMD, RENOIR, A1, 0x0002), 1289 _DECL_CHIPREV(AMD, RENOIR, LCN_A1, 0x0004), 1290 _DECL_CHIPREV(AMD, RENOIR, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1291 1292 _DECL_CHIPREV(AMD, MATISSE, UNKNOWN, 0x0001), 1293 _DECL_CHIPREV(AMD, MATISSE, B0, 0x0002), 1294 _DECL_CHIPREV(AMD, MATISSE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1295 1296 _DECL_CHIPREV(AMD, VAN_GOGH, UNKNOWN, 0x0001), 1297 _DECL_CHIPREV(AMD, VAN_GOGH, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1298 1299 _DECL_CHIPREV(AMD, MENDOCINO, UNKNOWN, 0x0001), 1300 _DECL_CHIPREV(AMD, MENDOCINO, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1301 1302 _DECL_CHIPREV(HYGON, DHYANA, UNKNOWN, 0x0001), 1303 _DECL_CHIPREV(HYGON, DHYANA, A1, 0x0002), 1304 _DECL_CHIPREV(HYGON, DHYANA, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1305 1306 _DECL_CHIPREV(AMD, MILAN, UNKNOWN, 0x0001), 1307 _DECL_CHIPREV(AMD, MILAN, A0, 0x0002), 1308 _DECL_CHIPREV(AMD, MILAN, B0, 0x0004), 1309 _DECL_CHIPREV(AMD, MILAN, B1, 0x0008), 1310 _DECL_CHIPREV(AMD, MILAN, B2, 0x0010), 1311 _DECL_CHIPREV(AMD, MILAN, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1312 1313 _DECL_CHIPREV(AMD, GENOA, UNKNOWN, 0x0001), 1314 _DECL_CHIPREV(AMD, GENOA, A0, 0x0002), 1315 _DECL_CHIPREV(AMD, GENOA, A1, 0x0004), 1316 _DECL_CHIPREV(AMD, GENOA, B0, 0x0008), 1317 _DECL_CHIPREV(AMD, GENOA, B1, 0x0010), 1318 _DECL_CHIPREV(AMD, GENOA, B2, 0x0020), 1319 _DECL_CHIPREV(AMD, GENOA, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1320 1321 _DECL_CHIPREV(AMD, VERMEER, UNKNOWN, 0x0001), 1322 _DECL_CHIPREV(AMD, VERMEER, A0, 0x0002), 1323 _DECL_CHIPREV(AMD, VERMEER, B0, 0x0004), 1324 _DECL_CHIPREV(AMD, VERMEER, B2, 0x0008), /* No B1 */ 1325 _DECL_CHIPREV(AMD, VERMEER, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1326 1327 _DECL_CHIPREV(AMD, REMBRANDT, UNKNOWN, 0x0001), 1328 _DECL_CHIPREV(AMD, REMBRANDT, A0, 0x0002), 1329 _DECL_CHIPREV(AMD, REMBRANDT, B0, 0x0004), 1330 _DECL_CHIPREV(AMD, REMBRANDT, B1, 0x0008), 1331 _DECL_CHIPREV(AMD, REMBRANDT, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1332 1333 _DECL_CHIPREV(AMD, CEZANNE, UNKNOWN, 0x0001), 1334 _DECL_CHIPREV(AMD, CEZANNE, A0, 0x0002), 1335 _DECL_CHIPREV(AMD, CEZANNE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1336 1337 _DECL_CHIPREV(AMD, RAPHAEL, UNKNOWN, 0x0001), 1338 _DECL_CHIPREV(AMD, RAPHAEL, B2, 0x0002), 1339 _DECL_CHIPREV(AMD, RAPHAEL, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1340 1341 _DECL_CHIPREV(AMD, PHOENIX, UNKNOWN, 0x0001), 1342 _DECL_CHIPREV(AMD, PHOENIX, A0, 0x0002), 1343 _DECL_CHIPREV(AMD, PHOENIX, A1, 0x0004), 1344 _DECL_CHIPREV(AMD, PHOENIX, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1345 1346 _DECL_CHIPREV(AMD, BERGAMO, UNKNOWN, 0x0001), 1347 _DECL_CHIPREV(AMD, BERGAMO, A0, 0x0002), 1348 _DECL_CHIPREV(AMD, BERGAMO, A1, 0x0004), 1349 _DECL_CHIPREV(AMD, BERGAMO, A2, 0x0008), 1350 _DECL_CHIPREV(AMD, BERGAMO, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1351 1352 _DECL_CHIPREV(AMD, TURIN, UNKNOWN, 0x0001), 1353 _DECL_CHIPREV(AMD, TURIN, A0, 0x0002), 1354 _DECL_CHIPREV(AMD, TURIN, B0, 0x0004), 1355 _DECL_CHIPREV(AMD, TURIN, B1, 0x0008), 1356 _DECL_CHIPREV(AMD, TURIN, C0, 0x0010), 1357 _DECL_CHIPREV(AMD, TURIN, C1, 0x0020), 1358 _DECL_CHIPREV(AMD, TURIN, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1359 _DECL_CHIPREV(AMD, DENSE_TURIN, UNKNOWN, 0x0001), 1360 _DECL_CHIPREV(AMD, DENSE_TURIN, A0, 0x0002), 1361 _DECL_CHIPREV(AMD, DENSE_TURIN, B0, 0x0004), 1362 _DECL_CHIPREV(AMD, DENSE_TURIN, B1, 0x0008), 1363 _DECL_CHIPREV(AMD, DENSE_TURIN, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1364 1365 _DECL_CHIPREV(AMD, STRIX, UNKNOWN, 0x0001), 1366 _DECL_CHIPREV(AMD, STRIX, B0, 0x0002), 1367 _DECL_CHIPREV(AMD, STRIX, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1368 1369 _DECL_CHIPREV(AMD, GRANITE_RIDGE, UNKNOWN, 0x0001), 1370 _DECL_CHIPREV(AMD, GRANITE_RIDGE, B0, 0x0002), 1371 _DECL_CHIPREV(AMD, GRANITE_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1372 1373 _DECL_CHIPREV(AMD, KRACKAN, UNKNOWN, 0x0001), 1374 _DECL_CHIPREV(AMD, KRACKAN, A0, 0x0002), 1375 _DECL_CHIPREV(AMD, KRACKAN, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1376 1377 _DECL_CHIPREV(AMD, STRIX_HALO, UNKNOWN, 0x0001), 1378 _DECL_CHIPREV(AMD, STRIX_HALO, A0, 0x0002), 1379 _DECL_CHIPREV(AMD, STRIX_HALO, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1380 1381 1382 /* Keep at the end */ 1383 X86_CHIPREV_ANY = _X86_CHIPREV_MKREV(_X86_VENDOR_MATCH_ALL, X86_PF_ANY, 1384 _X86_CHIPREV_REV_MATCH_ALL) 1385 } x86_chiprev_t; 1386 1387 #undef _DECL_CHIPREV 1388 1389 /* 1390 * Same thing, but for microarchitecture (core implementations). We are not 1391 * attempting to capture every possible fine-grained detail here; to the extent 1392 * that it matters, we do so in cpuid.c via ISA/feature bits. We use the same 1393 * number of bits for each field as in chiprev. 1394 */ 1395 1396 #define _X86_UARCHREV_VENDOR(x) _X86_CHIPREV_VENDOR(x) 1397 #define _X86_UARCHREV_UARCH(x) _X86_CHIPREV_FAMILY(x) 1398 #define _X86_UARCHREV_REV(x) _X86_CHIPREV_REV(x) 1399 1400 #define _X86_UARCHREV_MKREV(vendor, family, rev) \ 1401 _X86_CHIPREV_MKREV(vendor, family, rev) 1402 1403 typedef enum x86_uarch { 1404 X86_UARCH_UNKNOWN, 1405 1406 X86_UARCH_AMD_LEGACY, 1407 X86_UARCH_AMD_ZEN1, 1408 X86_UARCH_AMD_ZENPLUS, 1409 X86_UARCH_AMD_ZEN2, 1410 X86_UARCH_AMD_ZEN3, 1411 X86_UARCH_AMD_ZEN4, 1412 X86_UARCH_AMD_ZEN5, 1413 1414 X86_UARCH_ANY = 0xff 1415 } x86_uarch_t; 1416 1417 #define _DECL_UARCHREV(_v, _f, _revn, _revb) \ 1418 X86_UARCHREV_ ## _v ## _ ## _f ## _ ## _revn = \ 1419 _X86_UARCHREV_MKREV(X86_VENDOR_ ## _v, X86_UARCH_ ## _v ## _ ## _f, \ 1420 _revb) 1421 1422 #define _DECL_UARCHREV_NOREV(_v, _f, _revb) \ 1423 X86_UARCHREV_ ## _v ## _ ## _f = \ 1424 _X86_UARCHREV_MKREV(X86_VENDOR_ ## _v, X86_UARCH_ ## _v ## _ ## _f, \ 1425 _revb) 1426 1427 #define _X86_UARCHREV_REV_MATCH_ALL 0xffff 1428 1429 typedef enum x86_uarchrev { 1430 X86_UARCHREV_UNKNOWN, 1431 _DECL_UARCHREV_NOREV(AMD, LEGACY, 0x0001), 1432 _DECL_UARCHREV(AMD, LEGACY, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1433 1434 _DECL_UARCHREV_NOREV(AMD, ZEN1, 0x0001), 1435 _DECL_UARCHREV(AMD, ZEN1, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1436 1437 _DECL_UARCHREV_NOREV(AMD, ZENPLUS, 0x0001), 1438 _DECL_UARCHREV(AMD, ZENPLUS, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1439 1440 _DECL_UARCHREV(AMD, ZEN2, UNKNOWN, 0x0001), 1441 _DECL_UARCHREV(AMD, ZEN2, A0, 0x0002), 1442 _DECL_UARCHREV(AMD, ZEN2, B0, 0x0004), 1443 _DECL_UARCHREV(AMD, ZEN2, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1444 1445 _DECL_UARCHREV(AMD, ZEN3, UNKNOWN, 0x0001), 1446 _DECL_UARCHREV(AMD, ZEN3, A0, 0x0002), 1447 _DECL_UARCHREV(AMD, ZEN3, B0, 0x0004), 1448 _DECL_UARCHREV(AMD, ZEN3, B1, 0x0008), 1449 _DECL_UARCHREV(AMD, ZEN3, B2, 0x0010), 1450 _DECL_UARCHREV(AMD, ZEN3, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1451 1452 _DECL_UARCHREV(AMD, ZEN4, UNKNOWN, 0x0001), 1453 _DECL_UARCHREV(AMD, ZEN4, A0, 0x0002), 1454 _DECL_UARCHREV(AMD, ZEN4, A1, 0x0004), 1455 _DECL_UARCHREV(AMD, ZEN4, A2, 0x0008), 1456 _DECL_UARCHREV(AMD, ZEN4, B0, 0x0010), 1457 _DECL_UARCHREV(AMD, ZEN4, B1, 0x0020), 1458 _DECL_UARCHREV(AMD, ZEN4, B2, 0x0040), 1459 _DECL_UARCHREV(AMD, ZEN4, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1460 1461 _DECL_UARCHREV(AMD, ZEN5, UNKNOWN, 0x0001), 1462 _DECL_UARCHREV(AMD, ZEN5, A0, 0x0002), 1463 _DECL_UARCHREV(AMD, ZEN5, B0, 0x0004), 1464 _DECL_UARCHREV(AMD, ZEN5, B1, 0x0008), 1465 _DECL_UARCHREV(AMD, ZEN5, C0, 0x0010), 1466 _DECL_UARCHREV(AMD, ZEN5, C1, 0x0020), 1467 _DECL_UARCHREV(AMD, ZEN5, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1468 1469 /* Keep at the end */ 1470 _X86_UARCHREV_ANY = _X86_UARCHREV_MKREV(_X86_VENDOR_MATCH_ALL, 1471 X86_UARCH_ANY, _X86_UARCHREV_REV_MATCH_ALL) 1472 } x86_uarchrev_t; 1473 1474 #undef _DECL_UARCHREV 1475 1476 #endif /* !_ASM */ 1477 1478 /* 1479 * Various socket/package types, extended as the need to distinguish 1480 * a new type arises. The top 8 byte identfies the vendor and the 1481 * remaining 24 bits describe 24 socket types. 1482 */ 1483 1484 #define _X86_SOCKET_VENDOR_SHIFT 24 1485 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 1486 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 1487 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 1488 1489 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 1490 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 1491 1492 #define X86_SOCKET_MATCH(s, mask) \ 1493 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 1494 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 1495 1496 #define X86_SOCKET_UNKNOWN 0x0 1497 /* 1498 * AMD socket types 1499 */ 1500 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x01) 1501 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x02) 1502 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x03) 1503 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x04) 1504 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x05) 1505 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x06) 1506 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x07) 1507 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x08) 1508 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x09) 1509 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0a) 1510 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0b) 1511 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0c) 1512 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0d) 1513 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0e) 1514 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0f) 1515 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x10) 1516 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x11) 1517 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x12) 1518 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x13) 1519 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x14) 1520 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x15) 1521 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x16) 1522 #define X86_SOCKET_FP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x17) 1523 #define X86_SOCKET_FM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x18) 1524 #define X86_SOCKET_FP4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x19) 1525 #define X86_SOCKET_AM4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1a) 1526 #define X86_SOCKET_FT3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1b) 1527 #define X86_SOCKET_FT4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1c) 1528 #define X86_SOCKET_FS1B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1d) 1529 #define X86_SOCKET_FT3B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1e) 1530 #define X86_SOCKET_SP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1f) 1531 #define X86_SOCKET_SP3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x20) 1532 #define X86_SOCKET_FP5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x21) 1533 #define X86_SOCKET_FP6 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x22) 1534 #define X86_SOCKET_STRX4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x23) 1535 #define X86_SOCKET_SP5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x24) 1536 #define X86_SOCKET_AM5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x25) 1537 #define X86_SOCKET_FP7 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x26) 1538 #define X86_SOCKET_FP7R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x27) 1539 #define X86_SOCKET_FF3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x28) 1540 #define X86_SOCKET_FT6 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x29) 1541 #define X86_SOCKET_FP8 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x2a) 1542 #define X86_SOCKET_FL1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x2b) 1543 #define X86_SOCKET_SP6 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x2c) 1544 #define X86_SOCKET_TR5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x2d) 1545 #define X86_SOCKET_FP11 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x2e) 1546 #define X86_NUM_SOCKETS_AMD 0x2e 1547 1548 /* 1549 * Hygon socket types 1550 */ 1551 #define X86_SOCKET_SL1 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x01) 1552 #define X86_SOCKET_SL1R2 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x02) 1553 #define X86_SOCKET_DM1 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x03) 1554 #define X86_NUM_SOCKETS_HYGON 0x03 1555 1556 #define X86_NUM_SOCKETS (X86_NUM_SOCKETS_AMD + X86_NUM_SOCKETS_HYGON) 1557 1558 /* 1559 * Definitions for Intel processor models. These are all for Family 6 1560 * processors. This list and the Atom set below it are not exhuastive. 1561 */ 1562 #define INTC_MODEL_YONAH 0x0e 1563 #define INTC_MODEL_MEROM 0x0f 1564 #define INTC_MODEL_MEROM_L 0x16 1565 #define INTC_MODEL_PENRYN 0x17 1566 #define INTC_MODEL_DUNNINGTON 0x1d 1567 1568 #define INTC_MODEL_NEHALEM 0x1e 1569 #define INTC_MODEL_NEHALEM2 0x1f 1570 #define INTC_MODEL_NEHALEM_EP 0x1a 1571 #define INTC_MODEL_NEHALEM_EX 0x2e 1572 1573 #define INTC_MODEL_WESTMERE 0x25 1574 #define INTC_MODEL_WESTMERE_EP 0x2c 1575 #define INTC_MODEL_WESTMERE_EX 0x2f 1576 1577 #define INTC_MODEL_SANDYBRIDGE 0x2a 1578 #define INTC_MODEL_SANDYBRIDGE_XEON 0x2d 1579 #define INTC_MODEL_IVYBRIDGE 0x3a 1580 #define INTC_MODEL_IVYBRIDGE_XEON 0x3e 1581 1582 #define INTC_MODEL_HASWELL 0x3c 1583 #define INTC_MODEL_HASWELL_ULT 0x45 1584 #define INTC_MODEL_HASWELL_GT3E 0x46 1585 #define INTC_MODEL_HASWELL_XEON 0x3f 1586 1587 #define INTC_MODEL_BROADWELL 0x3d 1588 #define INTC_MODEL_BROADWELL_2 0x47 1589 #define INTC_MODEL_BROADWELL_XEON 0x4f 1590 #define INTC_MODEL_BROADWELL_XEON_D 0x56 1591 1592 #define INTC_MODEL_SKYLAKE_MOBILE 0x4e 1593 /* 1594 * Note, this model is shared with Cascade Lake and Cooper Lake. 1595 */ 1596 #define INTC_MODEL_SKYLAKE_XEON 0x55 1597 #define INTC_MODEL_SKYLAKE_DESKTOP 0x5e 1598 1599 #define INTC_MODEL_CANNON_LAKE 0x66 1600 1601 /* 1602 * Note, both Kaby Lake models are shared with Coffee Lake, Whiskey Lake, Amber 1603 * Lake, and some Comet Lake parts. 1604 */ 1605 #define INTC_MODEL_KABYLAKE_MOBILE 0x8e 1606 #define INTC_MODEL_KABYLAKE_DESKTOP 0x9e 1607 1608 #define INTC_MODEL_ICELAKE_XEON 0x6a 1609 #define INTC_MODEL_ICELAKE_MOBILE 0x7e 1610 #define INTC_MODEL_ICELAKE_XEON_DE 0x6c 1611 1612 #define INTC_MODEL_TIGERLAKE_MOBILE 0x8c 1613 #define INTC_MODEL_TIGERLAKE_MOBILE_2 0x8d 1614 #define INTC_MODEL_SAPPHIRE_RAPIDS 0x8f 1615 1616 #define INTC_MODEL_COMETLAKE 0xa5 1617 #define INTC_MODEL_COMETLAKE_MOBILE 0xa6 1618 #define INTC_MODEL_ROCKETLAKE 0xa7 1619 1620 #define INTC_MODEL_ALDER_LAKE_DESKTOP 0x97 1621 #define INTC_MODEL_ALDER_LAKE_MOBILE 0x9a /* And some Atom parts too */ 1622 #define INTC_MODEL_RAPTOR_LAKE_MOBILE_1 0xb7 1623 #define INTC_MODEL_RAPTOR_LAKE_MOBILE_2 0xba 1624 #define INTC_MODEL_RAPTOR_LAKE_MOBILE_3 0xbf 1625 1626 #define INTC_MODEL_METEOR_LAKE 0xaa 1627 1628 #define INTC_MODEL_EMERALD_RAPIDS 0xcf 1629 1630 /* 1631 * Atom Processors 1632 */ 1633 #define INTC_MODEL_SILVERTHORNE 0x1c 1634 #define INTC_MODEL_LINCROFT 0x26 1635 #define INTC_MODEL_PENWELL 0x27 1636 #define INTC_MODEL_CLOVERVIEW 0x35 1637 #define INTC_MODEL_CEDARVIEW 0x36 1638 #define INTC_MODEL_BAY_TRAIL 0x37 1639 #define INTC_MODEL_MERRIFIELD 0x4a 1640 #define INTC_MODEL_AVATON 0x4d 1641 #define INTC_MODEL_AIRMONT 0x4c 1642 #define INTC_MODEL_MOOREFIELD 0x5a 1643 #define INTC_MODEL_APOLLO_LAKE 0x5c 1644 #define INTC_MODEL_SOFIA_3G_R 0x5d 1645 #define INTC_MODEL_DENVERTON 0x5f 1646 #define INTC_MODEL_GEMINI_LAKE 0x7a 1647 #define INTC_MODEL_TREMONT 0x86 /* Parker Ridge & Snow Ridge */ 1648 #define INTC_MODEL_LAKEFIELD 0x8a 1649 #define INTC_MODEL_ELKHART_LAKE 0x96 1650 #define INTC_MODEL_JASPER_LAKE 0x9c 1651 #define INTC_MODEL_ALDER_LAKE_N 0xbe /* And some {desk,lap}top too */ 1652 1653 /* 1654 * xgetbv/xsetbv support 1655 * See section 13.3 in vol. 1 of the Intel Developer's manual. 1656 */ 1657 1658 #define XFEATURE_ENABLED_MASK 0x0 1659 /* 1660 * XFEATURE_ENABLED_MASK values (eax) 1661 * See setup_xfem(). 1662 */ 1663 #define XFEATURE_LEGACY_FP (1 << 0) 1664 #define XFEATURE_SSE (1 << 1) 1665 #define XFEATURE_AVX (1 << 2) 1666 /* 1667 * MPX is meant to be all or nothing, therefore for most of the kernel prefer 1668 * the XFEATURE_MPX definition over the individual state bits. 1669 */ 1670 #define XFEATURE_MPX_BNDREGS (1 << 3) 1671 #define XFEATURE_MPX_BNDCSR (1 << 4) 1672 #define XFEATURE_MPX (XFEATURE_MPX_BNDREGS | XFEATURE_MPX_BNDCSR) 1673 /* 1674 * AX512 is meant to be all or nothing, therefore for most of the kernel prefer 1675 * the XFEATURE_AVX512 definition over the individual state bits. 1676 */ 1677 #define XFEATURE_AVX512_OPMASK (1 << 5) 1678 #define XFEATURE_AVX512_ZMM (1 << 6) 1679 #define XFEATURE_AVX512_HI_ZMM (1 << 7) 1680 #define XFEATURE_AVX512 (XFEATURE_AVX512_OPMASK | \ 1681 XFEATURE_AVX512_ZMM | XFEATURE_AVX512_HI_ZMM) 1682 /* bit 8 unused */ 1683 #define XFEATURE_PKRU (1 << 9) 1684 #define XFEATURE_FP_ALL \ 1685 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \ 1686 XFEATURE_AVX512 | XFEATURE_PKRU) 1687 1688 /* 1689 * Define the set of xfeature flags that should be considered valid in the xsave 1690 * state vector when we initialize an lwp. This is distinct from the full set so 1691 * that all of the processor's normal logic and tracking of the xsave state is 1692 * usable. This should correspond to the state that's been initialized by the 1693 * ABI to hold meaningful values. Adding additional bits here can have serious 1694 * performance implications and cause performance degradations when using the 1695 * FPU vector (xmm) registers. 1696 */ 1697 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE) 1698 1699 #if !defined(_ASM) 1700 1701 #if defined(_KERNEL) || defined(_KMEMUSER) 1702 1703 #define NUM_X86_FEATURES 114 1704 extern uchar_t x86_featureset[]; 1705 1706 extern void free_x86_featureset(void *featureset); 1707 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 1708 extern void add_x86_feature(void *featureset, uint_t feature); 1709 extern void remove_x86_feature(void *featureset, uint_t feature); 1710 extern boolean_t compare_x86_featureset(void *setA, void *setB); 1711 extern void print_x86_featureset(void *featureset); 1712 1713 1714 extern uint_t x86_type; 1715 extern uint_t x86_vendor; 1716 extern uint_t x86_clflush_size; 1717 1718 extern uint_t pentiumpro_bug4046376; 1719 1720 /* 1721 * These functions are all used to perform various side-channel mitigations. 1722 * Please see uts/intel/os/cpuid.c for more information. 1723 */ 1724 extern void (*spec_uarch_flush)(void); 1725 extern void x86_rsb_stuff(void); 1726 extern void x86_rsb_stuff_vmexit(void); 1727 extern void x86_bhb_clear(void); 1728 extern void x86_md_clear(void); 1729 1730 #endif 1731 1732 #if defined(_KERNEL) 1733 1734 /* 1735 * This structure is used to pass arguments and get return values back 1736 * from the CPUID instruction in __cpuid_insn() routine. 1737 */ 1738 struct cpuid_regs { 1739 uint32_t cp_eax; 1740 uint32_t cp_ebx; 1741 uint32_t cp_ecx; 1742 uint32_t cp_edx; 1743 }; 1744 1745 extern int x86_use_pcid; 1746 extern int x86_use_invpcid; 1747 1748 /* 1749 * Utility functions to get/set extended control registers (XCR) 1750 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 1751 */ 1752 extern uint64_t get_xcr(uint_t); 1753 extern void set_xcr(uint_t, uint64_t); 1754 1755 extern uint64_t rdmsr(uint_t); 1756 extern void wrmsr(uint_t, const uint64_t); 1757 extern uint64_t xrdmsr(uint_t); 1758 extern void xwrmsr(uint_t, const uint64_t); 1759 extern int checked_rdmsr(uint_t, uint64_t *); 1760 extern int checked_wrmsr(uint_t, uint64_t); 1761 extern void wrmsr_and_test(uint_t, const uint64_t); 1762 1763 extern void invalidate_cache(void); 1764 extern ulong_t getcr4(void); 1765 extern void setcr4(ulong_t); 1766 1767 extern void mtrr_sync(void); 1768 1769 extern void cpu_fast_syscall_enable(void); 1770 extern void cpu_fast_syscall_disable(void); 1771 1772 typedef enum cpuid_pass { 1773 CPUID_PASS_NONE = 0, 1774 CPUID_PASS_PRELUDE, 1775 CPUID_PASS_IDENT, 1776 CPUID_PASS_BASIC, 1777 CPUID_PASS_EXTENDED, 1778 CPUID_PASS_DYNAMIC, 1779 CPUID_PASS_RESOLVE 1780 } cpuid_pass_t; 1781 1782 struct cpu; 1783 1784 extern boolean_t cpuid_checkpass(const struct cpu *const, const cpuid_pass_t); 1785 extern void cpuid_execpass(struct cpu *, const cpuid_pass_t, void *); 1786 extern void cpuid_pass_ucode(struct cpu *, uchar_t *); 1787 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 1788 extern uint32_t __cpuid_insn(struct cpuid_regs *); 1789 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 1790 extern int cpuid_getidstr(struct cpu *, char *, size_t); 1791 extern const char *cpuid_getvendorstr(struct cpu *); 1792 extern uint_t cpuid_getvendor(struct cpu *); 1793 extern uint_t cpuid_getfamily(struct cpu *); 1794 extern uint_t cpuid_getmodel(struct cpu *); 1795 extern uint_t cpuid_getstep(struct cpu *); 1796 extern uint_t cpuid_getsig(struct cpu *); 1797 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 1798 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 1799 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 1800 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 1801 extern int cpuid_get_chipid(struct cpu *); 1802 extern id_t cpuid_get_coreid(struct cpu *); 1803 extern int cpuid_get_pkgcoreid(struct cpu *); 1804 extern int cpuid_get_clogid(struct cpu *); 1805 extern int cpuid_get_cacheid(struct cpu *); 1806 extern uint32_t cpuid_get_apicid(struct cpu *); 1807 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 1808 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 1809 extern uint_t cpuid_get_compunitid(struct cpu *cpu); 1810 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 1811 extern size_t cpuid_get_xsave_size(void); 1812 extern void cpuid_get_xsave_info(uint64_t, size_t *, size_t *); 1813 extern boolean_t cpuid_need_fp_excp_handling(void); 1814 extern int cpuid_is_cmt(struct cpu *); 1815 extern int cpuid_syscall32_insn(struct cpu *); 1816 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 1817 1818 extern x86_chiprev_t cpuid_getchiprev(struct cpu *); 1819 extern const char *cpuid_getchiprevstr(struct cpu *); 1820 extern uint32_t cpuid_getsockettype(struct cpu *); 1821 extern const char *cpuid_getsocketstr(struct cpu *); 1822 extern x86_uarchrev_t cpuid_getuarchrev(struct cpu *); 1823 1824 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 1825 1826 struct cpuid_info; 1827 1828 extern void setx86isalist(void); 1829 extern void cpuid_alloc_space(struct cpu *); 1830 extern void cpuid_free_space(struct cpu *); 1831 extern void cpuid_set_cpu_properties(void *, processorid_t, 1832 struct cpuid_info *); 1833 extern void cpuid_post_ucodeadm(void); 1834 1835 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 1836 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 1837 1838 #if !defined(__xpv) 1839 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 1840 extern void cpuid_mwait_free(struct cpu *); 1841 extern int cpuid_deep_cstates_supported(void); 1842 extern int cpuid_arat_supported(void); 1843 extern int cpuid_iepb_supported(struct cpu *); 1844 extern int cpuid_deadline_tsc_supported(void); 1845 extern void vmware_port(int, uint32_t *); 1846 #endif 1847 1848 extern x86_processor_family_t chiprev_family(const x86_chiprev_t); 1849 extern boolean_t chiprev_matches(const x86_chiprev_t, const x86_chiprev_t); 1850 extern boolean_t chiprev_at_least(const x86_chiprev_t, const x86_chiprev_t); 1851 1852 extern x86_uarch_t uarchrev_uarch(const x86_uarchrev_t); 1853 extern boolean_t uarchrev_matches(const x86_uarchrev_t, const x86_uarchrev_t); 1854 extern boolean_t uarchrev_at_least(const x86_uarchrev_t, const x86_uarchrev_t); 1855 1856 /* 1857 * Cache information intended for topology and wider use. 1858 */ 1859 typedef enum { 1860 X86_CACHE_TYPE_DATA, 1861 X86_CACHE_TYPE_INST, 1862 X86_CACHE_TYPE_UNIFIED 1863 } x86_cache_type_t; 1864 1865 typedef enum { 1866 X86_CACHE_F_FULL_ASSOC = 1 << 0 1867 } x86_cache_flags_t; 1868 1869 typedef struct x86_cache { 1870 uint32_t xc_level; 1871 x86_cache_type_t xc_type; 1872 x86_cache_flags_t xc_flags; 1873 uint32_t xc_nparts; 1874 uint32_t xc_nways; 1875 uint32_t xc_line_size; 1876 uint64_t xc_nsets; 1877 uint64_t xc_size; 1878 uint64_t xc_id; 1879 uint32_t xc_apic_shift; 1880 } x86_cache_t; 1881 1882 extern int cpuid_getncaches(struct cpu *, uint32_t *); 1883 extern int cpuid_getcache(struct cpu *, uint32_t, x86_cache_t *); 1884 1885 struct cpu_ucode_info; 1886 1887 extern void ucode_alloc_space(struct cpu *); 1888 extern void ucode_free_space(struct cpu *); 1889 extern void ucode_init(void); 1890 extern void ucode_check_boot(void); 1891 extern void ucode_read_rev(struct cpu *); 1892 extern void ucode_locate(struct cpu *); 1893 extern void ucode_apply(struct cpu *); 1894 extern void ucode_finish(struct cpu *); 1895 extern void ucode_cleanup(); 1896 1897 #if !defined(__xpv) 1898 extern char _tsc_mfence_start; 1899 extern char _tsc_mfence_end; 1900 extern char _tscp_start; 1901 extern char _tscp_end; 1902 extern char _no_rdtsc_start; 1903 extern char _no_rdtsc_end; 1904 extern char _tsc_lfence_start; 1905 extern char _tsc_lfence_end; 1906 #endif 1907 1908 #if !defined(__xpv) 1909 extern char bcopy_patch_start; 1910 extern char bcopy_patch_end; 1911 extern char bcopy_ck_size; 1912 #endif 1913 1914 extern void post_startup_cpu_fixups(void); 1915 1916 extern uint_t workaround_errata(struct cpu *); 1917 1918 #if defined(OPTERON_ERRATUM_93) 1919 extern int opteron_erratum_93; 1920 #endif 1921 1922 #if defined(OPTERON_ERRATUM_91) 1923 extern int opteron_erratum_91; 1924 #endif 1925 1926 #if defined(OPTERON_ERRATUM_100) 1927 extern int opteron_erratum_100; 1928 #endif 1929 1930 #if defined(OPTERON_ERRATUM_121) 1931 extern int opteron_erratum_121; 1932 #endif 1933 1934 #if defined(OPTERON_ERRATUM_147) 1935 extern int opteron_erratum_147; 1936 extern void patch_erratum_147(void); 1937 #endif 1938 1939 #if !defined(__xpv) 1940 extern void determine_platform(void); 1941 #endif 1942 extern int get_hwenv(void); 1943 extern int is_controldom(void); 1944 1945 extern void enable_pcid(void); 1946 1947 extern void xsave_setup_msr(struct cpu *); 1948 1949 #if !defined(__xpv) 1950 extern void reset_gdtr_limit(void); 1951 #endif 1952 1953 extern int enable_platform_detection; 1954 1955 /* 1956 * Hypervisor signatures 1957 */ 1958 #define HVSIG_XEN_HVM "XenVMMXenVMM" 1959 #define HVSIG_VMWARE "VMwareVMware" 1960 #define HVSIG_KVM "KVMKVMKVM" 1961 #define HVSIG_MICROSOFT "Microsoft Hv" 1962 #define HVSIG_BHYVE "bhyve bhyve " 1963 #define HVSIG_QEMU_TCG "TCGTCGTCGTCG" 1964 #define HVSIG_VIRTUALBOX "VBoxVBoxVBox" 1965 #define HVSIG_ACRN "ACRNACRNACRN" 1966 1967 /* 1968 * Defined hardware environments 1969 */ 1970 #define HW_NATIVE (1 << 0) /* Running on bare metal */ 1971 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 1972 1973 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 1974 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 1975 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 1976 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 1977 #define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */ 1978 #define HW_QEMU_TCG (1 << 7) /* Running on QEMU TCG hypervisor */ 1979 #define HW_VIRTUALBOX (1 << 8) /* Running on VirtualBox hypervisor */ 1980 #define HW_ACRN (1 << 9) /* Running on ACRN hypervisor */ 1981 1982 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \ 1983 HW_BHYVE | HW_QEMU_TCG | HW_VIRTUALBOX | HW_ACRN) 1984 1985 #endif /* _KERNEL */ 1986 1987 #endif /* !_ASM */ 1988 1989 /* 1990 * VMware hypervisor related defines 1991 */ 1992 #define VMWARE_HVMAGIC 0x564d5868 1993 #define VMWARE_HVPORT 0x5658 1994 #define VMWARE_HVCMD_GETVERSION 0x0a 1995 #define VMWARE_HVCMD_GETTSCFREQ 0x2d 1996 1997 #ifdef __cplusplus 1998 } 1999 #endif 2000 2001 #endif /* _SYS_X86_ARCHEXT_H */ 2002