1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2017-2023 Broadcom Inc. All rights reserved. 4 */ 5 #ifndef MPI30_CNFG_H 6 #define MPI30_CNFG_H 1 7 #define MPI3_CONFIG_PAGETYPE_IO_UNIT (0x00) 8 #define MPI3_CONFIG_PAGETYPE_MANUFACTURING (0x01) 9 #define MPI3_CONFIG_PAGETYPE_IOC (0x02) 10 #define MPI3_CONFIG_PAGETYPE_DRIVER (0x03) 11 #define MPI3_CONFIG_PAGETYPE_SECURITY (0x04) 12 #define MPI3_CONFIG_PAGETYPE_ENCLOSURE (0x11) 13 #define MPI3_CONFIG_PAGETYPE_DEVICE (0x12) 14 #define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT (0x20) 15 #define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER (0x21) 16 #define MPI3_CONFIG_PAGETYPE_SAS_PHY (0x23) 17 #define MPI3_CONFIG_PAGETYPE_SAS_PORT (0x24) 18 #define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT (0x30) 19 #define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH (0x31) 20 #define MPI3_CONFIG_PAGETYPE_PCIE_LINK (0x33) 21 #define MPI3_CONFIG_PAGEATTR_MASK (0xf0) 22 #define MPI3_CONFIG_PAGEATTR_SHIFT (4) 23 #define MPI3_CONFIG_PAGEATTR_READ_ONLY (0x00) 24 #define MPI3_CONFIG_PAGEATTR_CHANGEABLE (0x10) 25 #define MPI3_CONFIG_PAGEATTR_PERSISTENT (0x20) 26 #define MPI3_CONFIG_ACTION_PAGE_HEADER (0x00) 27 #define MPI3_CONFIG_ACTION_READ_DEFAULT (0x01) 28 #define MPI3_CONFIG_ACTION_READ_CURRENT (0x02) 29 #define MPI3_CONFIG_ACTION_WRITE_CURRENT (0x03) 30 #define MPI3_CONFIG_ACTION_READ_PERSISTENT (0x04) 31 #define MPI3_CONFIG_ACTION_WRITE_PERSISTENT (0x05) 32 #define MPI3_DEVICE_PGAD_FORM_MASK (0xf0000000) 33 #define MPI3_DEVICE_PGAD_FORM_SHIFT (28) 34 #define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 35 #define MPI3_DEVICE_PGAD_FORM_HANDLE (0x20000000) 36 #define MPI3_DEVICE_PGAD_HANDLE_MASK (0x0000ffff) 37 #define MPI3_DEVICE_PGAD_HANDLE_SHIFT (0) 38 #define MPI3_SAS_EXPAND_PGAD_FORM_MASK (0xf0000000) 39 #define MPI3_SAS_EXPAND_PGAD_FORM_SHIFT (28) 40 #define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 41 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x10000000) 42 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE (0x20000000) 43 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00ff0000) 44 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 45 #define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000ffff) 46 #define MPI3_SAS_PHY_PGAD_FORM_MASK (0xf0000000) 47 #define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 48 #define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000ff) 49 #define MPI3_SASPORT_PGAD_FORM_MASK (0xf0000000) 50 #define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 51 #define MPI3_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 52 #define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK (0x000000ff) 53 #define MPI3_ENCLOS_PGAD_FORM_MASK (0xf0000000) 54 #define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 55 #define MPI3_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 56 #define MPI3_ENCLOS_PGAD_HANDLE_MASK (0x0000ffff) 57 #define MPI3_PCIE_SWITCH_PGAD_FORM_MASK (0xf0000000) 58 #define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 59 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM (0x10000000) 60 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE (0x20000000) 61 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00ff0000) 62 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 63 #define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000ffff) 64 #define MPI3_PCIE_LINK_PGAD_FORM_MASK (0xf0000000) 65 #define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 66 #define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 67 #define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK (0x000000ff) 68 #define MPI3_SECURITY_PGAD_FORM_MASK (0xf0000000) 69 #define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT (0x00000000) 70 #define MPI3_SECURITY_PGAD_FORM_SLOT_NUM (0x10000000) 71 #define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK (0x0000ff00) 72 #define MPI3_SECURITY_PGAD_SLOT_GROUP_SHIFT (8) 73 #define MPI3_SECURITY_PGAD_SLOT_MASK (0x000000ff) 74 #define MPI3_INSTANCE_PGAD_INSTANCE_MASK (0x0000ffff) 75 struct mpi3_config_request { 76 __le16 host_tag; 77 u8 ioc_use_only02; 78 u8 function; 79 __le16 ioc_use_only04; 80 u8 ioc_use_only06; 81 u8 msg_flags; 82 __le16 change_count; 83 u8 proxy_ioc_number; 84 u8 reserved0b; 85 u8 page_version; 86 u8 page_number; 87 u8 page_type; 88 u8 action; 89 __le32 page_address; 90 __le16 page_length; 91 __le16 reserved16; 92 __le32 reserved18[2]; 93 union mpi3_sge_union sgl; 94 }; 95 96 struct mpi3_config_page_header { 97 u8 page_version; 98 u8 reserved01; 99 u8 page_number; 100 u8 page_attribute; 101 __le16 page_length; 102 u8 page_type; 103 u8 reserved07; 104 }; 105 106 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK (0xf0) 107 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT (4) 108 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK (0x0f) 109 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT (0) 110 #define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 111 #define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 112 #define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 113 #define MPI3_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 114 #define MPI3_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 115 #define MPI3_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 116 #define MPI3_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 117 #define MPI3_SAS_NEG_LINK_RATE_1_5 (0x08) 118 #define MPI3_SAS_NEG_LINK_RATE_3_0 (0x09) 119 #define MPI3_SAS_NEG_LINK_RATE_6_0 (0x0a) 120 #define MPI3_SAS_NEG_LINK_RATE_12_0 (0x0b) 121 #define MPI3_SAS_NEG_LINK_RATE_22_5 (0x0c) 122 #define MPI3_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 123 #define MPI3_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 124 #define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 125 #define MPI3_SAS_APHYINFO_REASON_MASK (0x0000000f) 126 #define MPI3_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 127 #define MPI3_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 128 #define MPI3_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 129 #define MPI3_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 130 #define MPI3_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 131 #define MPI3_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 132 #define MPI3_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 133 #define MPI3_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 134 #define MPI3_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 135 #define MPI3_SAS_APHYINFO_REASON_EXP_REDUCED_FUNC (0x00000009) 136 #define MPI3_SAS_PHYINFO_STATUS_MASK (0xc0000000) 137 #define MPI3_SAS_PHYINFO_STATUS_SHIFT (30) 138 #define MPI3_SAS_PHYINFO_STATUS_ACCESSIBLE (0x00000000) 139 #define MPI3_SAS_PHYINFO_STATUS_NOT_EXIST (0x40000000) 140 #define MPI3_SAS_PHYINFO_STATUS_VACANT (0x80000000) 141 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 142 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE (0x00000000) 143 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL (0x08000000) 144 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER (0x10000000) 145 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_MASK (0x04000000) 146 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_SHIFT (26) 147 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_MASK (0x02000000) 148 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_SHIFT (25) 149 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_MASK (0x01000000) 150 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_SHIFT (24) 151 #define MPI3_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 152 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_WITHIN (0x00200000) 153 #define MPI3_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 154 #define MPI3_SAS_PHYINFO_REASON_MASK (0x000f0000) 155 #define MPI3_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 156 #define MPI3_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 157 #define MPI3_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 158 #define MPI3_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 159 #define MPI3_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 160 #define MPI3_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 161 #define MPI3_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 162 #define MPI3_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 163 #define MPI3_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 164 #define MPI3_SAS_PHYINFO_REASON_EXP_REDUCED_FUNC (0x00090000) 165 #define MPI3_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 166 #define MPI3_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 167 #define MPI3_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 168 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_MASK (0x00000f00) 169 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT (8) 170 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK (0x000000f0) 171 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT (0x00000000) 172 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE (0x00000010) 173 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE (0x00000020) 174 #define MPI3_SAS_PRATE_MAX_RATE_MASK (0xf0) 175 #define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 176 #define MPI3_SAS_PRATE_MAX_RATE_1_5 (0x80) 177 #define MPI3_SAS_PRATE_MAX_RATE_3_0 (0x90) 178 #define MPI3_SAS_PRATE_MAX_RATE_6_0 (0xa0) 179 #define MPI3_SAS_PRATE_MAX_RATE_12_0 (0xb0) 180 #define MPI3_SAS_PRATE_MAX_RATE_22_5 (0xc0) 181 #define MPI3_SAS_PRATE_MIN_RATE_MASK (0x0f) 182 #define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 183 #define MPI3_SAS_PRATE_MIN_RATE_1_5 (0x08) 184 #define MPI3_SAS_PRATE_MIN_RATE_3_0 (0x09) 185 #define MPI3_SAS_PRATE_MIN_RATE_6_0 (0x0a) 186 #define MPI3_SAS_PRATE_MIN_RATE_12_0 (0x0b) 187 #define MPI3_SAS_PRATE_MIN_RATE_22_5 (0x0c) 188 #define MPI3_SAS_HWRATE_MAX_RATE_MASK (0xf0) 189 #define MPI3_SAS_HWRATE_MAX_RATE_1_5 (0x80) 190 #define MPI3_SAS_HWRATE_MAX_RATE_3_0 (0x90) 191 #define MPI3_SAS_HWRATE_MAX_RATE_6_0 (0xa0) 192 #define MPI3_SAS_HWRATE_MAX_RATE_12_0 (0xb0) 193 #define MPI3_SAS_HWRATE_MAX_RATE_22_5 (0xc0) 194 #define MPI3_SAS_HWRATE_MIN_RATE_MASK (0x0f) 195 #define MPI3_SAS_HWRATE_MIN_RATE_1_5 (0x08) 196 #define MPI3_SAS_HWRATE_MIN_RATE_3_0 (0x09) 197 #define MPI3_SAS_HWRATE_MIN_RATE_6_0 (0x0a) 198 #define MPI3_SAS_HWRATE_MIN_RATE_12_0 (0x0b) 199 #define MPI3_SAS_HWRATE_MIN_RATE_22_5 (0x0c) 200 #define MPI3_SLOT_INVALID (0xffff) 201 #define MPI3_SLOT_INDEX_INVALID (0xffff) 202 #define MPI3_LINK_CHANGE_COUNT_INVALID (0xffff) 203 #define MPI3_RATE_CHANGE_COUNT_INVALID (0xffff) 204 #define MPI3_TEMP_SENSOR_LOCATION_INTERNAL (0x0) 205 #define MPI3_TEMP_SENSOR_LOCATION_INLET (0x1) 206 #define MPI3_TEMP_SENSOR_LOCATION_OUTLET (0x2) 207 #define MPI3_TEMP_SENSOR_LOCATION_DRAM (0x3) 208 #define MPI3_MFGPAGE_VENDORID_BROADCOM (0x1000) 209 #define MPI3_MFGPAGE_DEVID_SAS4116 (0x00a5) 210 #define MPI3_MFGPAGE_DEVID_SAS5116_MPI (0x00b3) 211 #define MPI3_MFGPAGE_DEVID_SAS5116_NVME (0x00b4) 212 #define MPI3_MFGPAGE_DEVID_SAS5116_MPI_MGMT (0x00b5) 213 #define MPI3_MFGPAGE_DEVID_SAS5116_NVME_MGMT (0x00b6) 214 #define MPI3_MFGPAGE_DEVID_SAS5116_PCIE_SWITCH (0x00b8) 215 #define MPI3_MFGPAGE_DEVID_SAS5248_MPI (0x00f0) 216 #define MPI3_MFGPAGE_DEVID_SAS5248_MPI_NS (0x00f1) 217 #define MPI3_MFGPAGE_DEVID_SAS5248_PCIE_SWITCH (0x00f2) 218 struct mpi3_man_page0 { 219 struct mpi3_config_page_header header; 220 u8 chip_revision[8]; 221 u8 chip_name[32]; 222 u8 board_name[32]; 223 u8 board_assembly[32]; 224 u8 board_tracer_number[32]; 225 __le32 board_power; 226 __le32 reserved94; 227 __le32 reserved98; 228 u8 oem; 229 u8 profile_identifier; 230 __le16 flags; 231 u8 board_mfg_day; 232 u8 board_mfg_month; 233 __le16 board_mfg_year; 234 u8 board_rework_day; 235 u8 board_rework_month; 236 __le16 board_rework_year; 237 u8 board_revision[8]; 238 u8 e_pack_fru[16]; 239 u8 product_name[256]; 240 }; 241 242 #define MPI3_MAN0_PAGEVERSION (0x00) 243 #define MPI3_MAN0_FLAGS_SWITCH_PRESENT (0x0002) 244 #define MPI3_MAN0_FLAGS_EXPANDER_PRESENT (0x0001) 245 #define MPI3_MAN1_VPD_SIZE (512) 246 struct mpi3_man_page1 { 247 struct mpi3_config_page_header header; 248 __le32 reserved08[2]; 249 u8 vpd[MPI3_MAN1_VPD_SIZE]; 250 }; 251 252 #define MPI3_MAN1_PAGEVERSION (0x00) 253 struct mpi3_man_page2 { 254 struct mpi3_config_page_header header; 255 u8 flags; 256 u8 reserved09[3]; 257 __le32 reserved0c[3]; 258 u8 oem_board_tracer_number[32]; 259 }; 260 #define MPI3_MAN2_PAGEVERSION (0x00) 261 #define MPI3_MAN2_FLAGS_TRACER_PRESENT (0x01) 262 struct mpi3_man5_phy_entry { 263 __le64 ioc_wwid; 264 __le64 device_name; 265 __le64 sata_wwid; 266 }; 267 268 #ifndef MPI3_MAN5_PHY_MAX 269 #define MPI3_MAN5_PHY_MAX (1) 270 #endif 271 struct mpi3_man_page5 { 272 struct mpi3_config_page_header header; 273 u8 num_phys; 274 u8 reserved09[3]; 275 __le32 reserved0c; 276 struct mpi3_man5_phy_entry phy[MPI3_MAN5_PHY_MAX]; 277 }; 278 279 #define MPI3_MAN5_PAGEVERSION (0x00) 280 struct mpi3_man6_gpio_entry { 281 u8 function_code; 282 u8 function_flags; 283 __le16 flags; 284 u8 param1; 285 u8 param2; 286 __le16 reserved06; 287 __le32 param3; 288 }; 289 290 #define MPI3_MAN6_GPIO_FUNCTION_GENERIC (0x00) 291 #define MPI3_MAN6_GPIO_FUNCTION_ALTERNATE (0x01) 292 #define MPI3_MAN6_GPIO_FUNCTION_EXT_INTERRUPT (0x02) 293 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_ACTIVITY (0x03) 294 #define MPI3_MAN6_GPIO_FUNCTION_OVER_TEMPERATURE (0x04) 295 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_GREEN (0x05) 296 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW (0x06) 297 #define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT (0x07) 298 #define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE (0x08) 299 #define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET (0x0a) 300 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET (0x0b) 301 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT (0x0c) 302 #define MPI3_MAN6_GPIO_FUNCTION_PBLP_STATUS_CHANGE (0x0d) 303 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_ONLINE (0x0e) 304 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_FAULT (0x0f) 305 #define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE (0x10) 306 #define MPI3_MAN6_GPIO_FUNCTION_LICENSE (0x11) 307 #define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL (0x12) 308 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET_CLAMP (0x13) 309 #define MPI3_MAN6_GPIO_FUNCTION_AUXILIARY_POWER (0x14) 310 #define MPI3_MAN6_GPIO_FUNCTION_RAID_DATA_CACHE_DIRTY (0x15) 311 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_CONTROL (0x16) 312 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_FAULT (0x17) 313 #define MPI3_MAN6_GPIO_FUNCTION_POWER_BRAKE (0x18) 314 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK (0x01) 315 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI (0x00) 316 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID (0x01) 317 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK (0xf0) 318 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC (0x00) 319 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT (0x10) 320 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT (0x20) 321 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_ACK_REQUIRED (0x02) 322 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01) 323 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00) 324 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01) 325 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP (0x00) 326 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP (0x01) 327 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT (0x00) 328 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE (0x01) 329 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE (0x02) 330 #define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON (0x00) 331 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK (0x0100) 332 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE (0x0100) 333 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE (0x0000) 334 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK (0x00c0) 335 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM (0x0000) 336 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM (0x0040) 337 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM (0x0080) 338 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_33OHM (0x00c0) 339 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_MASK (0x0030) 340 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_SHIFT (4) 341 #define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH (0x0008) 342 #define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED (0x0004) 343 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK (0x0003) 344 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT (0x0000) 345 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT (0x0001) 346 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT (0x0002) 347 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_PUSH_PULL_OUTPUT (0x0003) 348 #ifndef MPI3_MAN6_GPIO_MAX 349 #define MPI3_MAN6_GPIO_MAX (1) 350 #endif 351 struct mpi3_man_page6 { 352 struct mpi3_config_page_header header; 353 __le16 flags; 354 __le16 reserved0a; 355 u8 num_gpio; 356 u8 reserved0d[3]; 357 struct mpi3_man6_gpio_entry gpio[MPI3_MAN6_GPIO_MAX]; 358 }; 359 360 #define MPI3_MAN6_PAGEVERSION (0x00) 361 #define MPI3_MAN6_FLAGS_HEARTBEAT_LED_DISABLED (0x0001) 362 struct mpi3_man7_receptacle_info { 363 __le32 name[4]; 364 u8 location; 365 u8 connector_type; 366 u8 ped_clk; 367 u8 connector_id; 368 __le32 reserved14; 369 }; 370 371 #define MPI3_MAN7_LOCATION_UNKNOWN (0x00) 372 #define MPI3_MAN7_LOCATION_INTERNAL (0x01) 373 #define MPI3_MAN7_LOCATION_EXTERNAL (0x02) 374 #define MPI3_MAN7_LOCATION_VIRTUAL (0x03) 375 #define MPI3_MAN7_LOCATION_HOST (0x04) 376 #define MPI3_MAN7_CONNECTOR_TYPE_NO_INFO (0x00) 377 #define MPI3_MAN7_PEDCLK_ROUTING_MASK (0x10) 378 #define MPI3_MAN7_PEDCLK_ROUTING_DIRECT (0x00) 379 #define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER (0x10) 380 #define MPI3_MAN7_PEDCLK_ID_MASK (0x0f) 381 #ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX 382 #define MPI3_MAN7_RECEPTACLE_INFO_MAX (1) 383 #endif 384 struct mpi3_man_page7 { 385 struct mpi3_config_page_header header; 386 __le32 flags; 387 u8 num_receptacles; 388 u8 reserved0d[3]; 389 __le32 enclosure_name[4]; 390 struct mpi3_man7_receptacle_info receptacle_info[MPI3_MAN7_RECEPTACLE_INFO_MAX]; 391 }; 392 393 #define MPI3_MAN7_PAGEVERSION (0x00) 394 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK (0x01) 395 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0 (0x00) 396 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1 (0x01) 397 struct mpi3_man8_phy_info { 398 u8 receptacle_id; 399 u8 connector_lane; 400 __le16 reserved02; 401 __le16 slotx1; 402 __le16 slotx2; 403 __le16 slotx4; 404 __le16 reserved0a; 405 __le32 reserved0c; 406 }; 407 408 #define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_NOT_ASSOCIATED (0xff) 409 #define MPI3_MAN8_PHY_INFO_CONNECTOR_LANE_NOT_ASSOCIATED (0xff) 410 #ifndef MPI3_MAN8_PHY_INFO_MAX 411 #define MPI3_MAN8_PHY_INFO_MAX (1) 412 #endif 413 struct mpi3_man_page8 { 414 struct mpi3_config_page_header header; 415 __le32 reserved08; 416 u8 num_phys; 417 u8 reserved0d[3]; 418 struct mpi3_man8_phy_info phy_info[MPI3_MAN8_PHY_INFO_MAX]; 419 }; 420 421 #define MPI3_MAN8_PAGEVERSION (0x00) 422 struct mpi3_man9_rsrc_entry { 423 __le32 maximum; 424 __le32 decrement; 425 __le32 minimum; 426 __le32 actual; 427 }; 428 429 enum mpi3_man9_resources { 430 MPI3_MAN9_RSRC_OUTSTANDING_REQS = 0, 431 MPI3_MAN9_RSRC_TARGET_CMDS = 1, 432 MPI3_MAN9_RSRC_RESERVED02 = 2, 433 MPI3_MAN9_RSRC_NVME = 3, 434 MPI3_MAN9_RSRC_INITIATORS = 4, 435 MPI3_MAN9_RSRC_VDS = 5, 436 MPI3_MAN9_RSRC_ENCLOSURES = 6, 437 MPI3_MAN9_RSRC_ENCLOSURE_PHYS = 7, 438 MPI3_MAN9_RSRC_EXPANDERS = 8, 439 MPI3_MAN9_RSRC_PCIE_SWITCHES = 9, 440 MPI3_MAN9_RSRC_RESERVED10 = 10, 441 MPI3_MAN9_RSRC_HOST_PD_DRIVES = 11, 442 MPI3_MAN9_RSRC_ADV_HOST_PD_DRIVES = 12, 443 MPI3_MAN9_RSRC_RAID_PD_DRIVES = 13, 444 MPI3_MAN9_RSRC_DRV_DIAG_BUF = 14, 445 MPI3_MAN9_RSRC_NAMESPACE_COUNT = 15, 446 MPI3_MAN9_RSRC_NUM_RESOURCES 447 }; 448 449 #define MPI3_MAN9_MIN_OUTSTANDING_REQS (1) 450 #define MPI3_MAN9_MAX_OUTSTANDING_REQS (65000) 451 #define MPI3_MAN9_MIN_TARGET_CMDS (0) 452 #define MPI3_MAN9_MAX_TARGET_CMDS (65535) 453 #define MPI3_MAN9_MIN_NVME_TARGETS (0) 454 #define MPI3_MAN9_MIN_INITIATORS (0) 455 #define MPI3_MAN9_MIN_VDS (0) 456 #define MPI3_MAN9_MIN_ENCLOSURES (1) 457 #define MPI3_MAN9_MAX_ENCLOSURES (65535) 458 #define MPI3_MAN9_MIN_ENCLOSURE_PHYS (0) 459 #define MPI3_MAN9_MIN_EXPANDERS (0) 460 #define MPI3_MAN9_MAX_EXPANDERS (65535) 461 #define MPI3_MAN9_MIN_PCIE_SWITCHES (0) 462 #define MPI3_MAN9_MIN_HOST_PD_DRIVES (0) 463 #define MPI3_MAN9_ADV_HOST_PD_DRIVES (0) 464 #define MPI3_MAN9_RAID_PD_DRIVES (0) 465 #define MPI3_MAN9_DRIVER_DIAG_BUFFER (0) 466 #define MPI3_MAN9_MIN_NAMESPACE_COUNT (1) 467 #define MPI3_MAN9_MIN_EXPANDERS (0) 468 #define MPI3_MAN9_MAX_EXPANDERS (65535) 469 struct mpi3_man_page9 { 470 struct mpi3_config_page_header header; 471 u8 num_resources; 472 u8 reserved09; 473 __le16 reserved0a; 474 __le32 reserved0c; 475 __le32 reserved10; 476 __le32 reserved14; 477 __le32 reserved18; 478 __le32 reserved1c; 479 struct mpi3_man9_rsrc_entry resource[MPI3_MAN9_RSRC_NUM_RESOURCES]; 480 }; 481 482 #define MPI3_MAN9_PAGEVERSION (0x00) 483 struct mpi3_man10_istwi_ctrlr_entry { 484 __le16 target_address; 485 __le16 flags; 486 u8 scl_low_override; 487 u8 scl_high_override; 488 __le16 reserved06; 489 }; 490 491 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK (0x000c) 492 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100K (0x0000) 493 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400K (0x0004) 494 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_TARGET_ENABLED (0x0002) 495 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_INITIATOR_ENABLED (0x0001) 496 #ifndef MPI3_MAN10_ISTWI_CTRLR_MAX 497 #define MPI3_MAN10_ISTWI_CTRLR_MAX (1) 498 #endif 499 struct mpi3_man_page10 { 500 struct mpi3_config_page_header header; 501 __le32 reserved08; 502 u8 num_istwi_ctrl; 503 u8 reserved0d[3]; 504 struct mpi3_man10_istwi_ctrlr_entry istwi_controller[MPI3_MAN10_ISTWI_CTRLR_MAX]; 505 }; 506 507 #define MPI3_MAN10_PAGEVERSION (0x00) 508 struct mpi3_man11_mux_device_format { 509 u8 max_channel; 510 u8 reserved01[3]; 511 __le32 reserved04; 512 }; 513 514 struct mpi3_man11_temp_sensor_device_format { 515 u8 type; 516 u8 reserved01[3]; 517 u8 temp_channel[4]; 518 }; 519 520 #define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654 (0x00) 521 #define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442 (0x01) 522 #define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476 (0x02) 523 #define MPI3_MAN11_TEMP_SENSOR_TYPE_SE97B (0x03) 524 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_MASK (0xe0) 525 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_SHIFT (5) 526 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED (0x01) 527 struct mpi3_man11_seeprom_device_format { 528 u8 size; 529 u8 page_write_size; 530 __le16 reserved02; 531 __le32 reserved04; 532 }; 533 534 #define MPI3_MAN11_SEEPROM_SIZE_1KBITS (0x01) 535 #define MPI3_MAN11_SEEPROM_SIZE_2KBITS (0x02) 536 #define MPI3_MAN11_SEEPROM_SIZE_4KBITS (0x03) 537 #define MPI3_MAN11_SEEPROM_SIZE_8KBITS (0x04) 538 #define MPI3_MAN11_SEEPROM_SIZE_16KBITS (0x05) 539 #define MPI3_MAN11_SEEPROM_SIZE_32KBITS (0x06) 540 #define MPI3_MAN11_SEEPROM_SIZE_64KBITS (0x07) 541 #define MPI3_MAN11_SEEPROM_SIZE_128KBITS (0x08) 542 struct mpi3_man11_ddr_spd_device_format { 543 u8 channel; 544 u8 reserved01[3]; 545 __le32 reserved04; 546 }; 547 548 struct mpi3_man11_cable_mgmt_device_format { 549 u8 type; 550 u8 receptacle_id; 551 __le16 reserved02; 552 __le32 reserved04; 553 }; 554 555 #define MPI3_MAN11_CABLE_MGMT_TYPE_SFF_8636 (0x00) 556 struct mpi3_man11_bkplane_spec_ubm_format { 557 __le16 flags; 558 __le16 reserved02; 559 }; 560 561 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200) 562 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_FORCE_POLLING (0x0100) 563 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_MASK (0x00f0) 564 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_SHIFT (4) 565 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_MASK (0x000f) 566 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_SHIFT (0) 567 struct mpi3_man11_bkplane_spec_non_ubm_format { 568 __le16 flags; 569 u8 reserved02; 570 u8 type; 571 }; 572 573 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_MASK (0xf000) 574 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_SHIFT (12) 575 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200) 576 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_MASK (0x00c0) 577 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_4 (0x0000) 578 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_2 (0x0040) 579 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_1 (0x0080) 580 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_MASK (0x0030) 581 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_GPIO (0x0000) 582 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_REG (0x0010) 583 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_MASK (0x000f) 584 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_SHIFT (0) 585 #define MPI3_MAN11_BKPLANE_NON_UBM_TYPE_VPP (0x00) 586 union mpi3_man11_bkplane_spec_format { 587 struct mpi3_man11_bkplane_spec_ubm_format ubm; 588 struct mpi3_man11_bkplane_spec_non_ubm_format non_ubm; 589 }; 590 591 struct mpi3_man11_bkplane_mgmt_device_format { 592 u8 type; 593 u8 receptacle_id; 594 u8 reset_info; 595 u8 reserved03; 596 union mpi3_man11_bkplane_spec_format backplane_mgmt_specific; 597 }; 598 599 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_UBM (0x00) 600 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_NON_UBM (0x01) 601 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_MASK (0xf0) 602 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_SHIFT (4) 603 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_MASK (0x0f) 604 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_SHIFT (0) 605 struct mpi3_man11_gas_gauge_device_format { 606 u8 type; 607 u8 reserved01[3]; 608 __le32 reserved04; 609 }; 610 611 #define MPI3_MAN11_GAS_GAUGE_TYPE_STANDARD (0x00) 612 struct mpi3_man11_mgmt_ctrlr_device_format { 613 __le32 reserved00; 614 __le32 reserved04; 615 }; 616 struct mpi3_man11_board_fan_device_format { 617 u8 flags; 618 u8 reserved01; 619 u8 min_fan_speed; 620 u8 max_fan_speed; 621 __le32 reserved04; 622 }; 623 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_MASK (0x07) 624 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_AMC6821 (0x00) 625 union mpi3_man11_device_specific_format { 626 struct mpi3_man11_mux_device_format mux; 627 struct mpi3_man11_temp_sensor_device_format temp_sensor; 628 struct mpi3_man11_seeprom_device_format seeprom; 629 struct mpi3_man11_ddr_spd_device_format ddr_spd; 630 struct mpi3_man11_cable_mgmt_device_format cable_mgmt; 631 struct mpi3_man11_bkplane_mgmt_device_format bkplane_mgmt; 632 struct mpi3_man11_gas_gauge_device_format gas_gauge; 633 struct mpi3_man11_mgmt_ctrlr_device_format mgmt_controller; 634 struct mpi3_man11_board_fan_device_format board_fan; 635 __le32 words[2]; 636 }; 637 struct mpi3_man11_istwi_device_format { 638 u8 device_type; 639 u8 controller; 640 u8 reserved02; 641 u8 flags; 642 __le16 device_address; 643 u8 mux_channel; 644 u8 mux_index; 645 union mpi3_man11_device_specific_format device_specific; 646 }; 647 648 #define MPI3_MAN11_ISTWI_DEVTYPE_MUX (0x00) 649 #define MPI3_MAN11_ISTWI_DEVTYPE_TEMP_SENSOR (0x01) 650 #define MPI3_MAN11_ISTWI_DEVTYPE_SEEPROM (0x02) 651 #define MPI3_MAN11_ISTWI_DEVTYPE_DDR_SPD (0x03) 652 #define MPI3_MAN11_ISTWI_DEVTYPE_CABLE_MGMT (0x04) 653 #define MPI3_MAN11_ISTWI_DEVTYPE_BACKPLANE_MGMT (0x05) 654 #define MPI3_MAN11_ISTWI_DEVTYPE_GAS_GAUGE (0x06) 655 #define MPI3_MAN11_ISTWI_DEVTYPE_MGMT_CONTROLLER (0x07) 656 #define MPI3_MAN11_ISTWI_DEVTYPE_BOARD_FAN (0x08) 657 #define MPI3_MAN11_ISTWI_FLAGS_MUX_PRESENT (0x01) 658 #ifndef MPI3_MAN11_ISTWI_DEVICE_MAX 659 #define MPI3_MAN11_ISTWI_DEVICE_MAX (1) 660 #endif 661 struct mpi3_man_page11 { 662 struct mpi3_config_page_header header; 663 __le32 reserved08; 664 u8 num_istwi_dev; 665 u8 reserved0d[3]; 666 struct mpi3_man11_istwi_device_format istwi_device[MPI3_MAN11_ISTWI_DEVICE_MAX]; 667 }; 668 669 #define MPI3_MAN11_PAGEVERSION (0x00) 670 #ifndef MPI3_MAN12_NUM_SGPIO_MAX 671 #define MPI3_MAN12_NUM_SGPIO_MAX (1) 672 #endif 673 struct mpi3_man12_sgpio_info { 674 u8 slot_count; 675 u8 reserved01[3]; 676 __le32 reserved04; 677 u8 phy_order[32]; 678 }; 679 680 struct mpi3_man_page12 { 681 struct mpi3_config_page_header header; 682 __le32 flags; 683 __le32 s_clock_freq; 684 __le32 activity_modulation; 685 u8 num_sgpio; 686 u8 reserved15[3]; 687 __le32 reserved18; 688 __le32 reserved1c; 689 __le32 pattern[8]; 690 struct mpi3_man12_sgpio_info sgpio_info[MPI3_MAN12_NUM_SGPIO_MAX]; 691 }; 692 693 #define MPI3_MAN12_PAGEVERSION (0x00) 694 #define MPI3_MAN12_FLAGS_ERROR_PRESENCE_ENABLED (0x0400) 695 #define MPI3_MAN12_FLAGS_ACTIVITY_INVERT_ENABLED (0x0200) 696 #define MPI3_MAN12_FLAGS_GROUP_ID_DISABLED (0x0100) 697 #define MPI3_MAN12_FLAGS_SIO_CLK_FILTER_ENABLED (0x0004) 698 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_MASK (0x0002) 699 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_PUSH_PULL (0x0000) 700 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_OPEN_DRAIN (0x0002) 701 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_MASK (0x0001) 702 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_PUSH_PULL (0x0000) 703 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_OPEN_DRAIN (0x0001) 704 #define MPI3_MAN12_SIO_CLK_FREQ_MIN (32) 705 #define MPI3_MAN12_SIO_CLK_FREQ_MAX (100000) 706 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_MASK (0x0000f000) 707 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_SHIFT (12) 708 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_MASK (0x00000f00) 709 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_SHIFT (8) 710 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_MASK (0x000000f0) 711 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_SHIFT (4) 712 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_MASK (0x0000000f) 713 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_SHIFT (0) 714 #define MPI3_MAN12_PATTERN_RATE_MASK (0xe0000000) 715 #define MPI3_MAN12_PATTERN_RATE_2_HZ (0x00000000) 716 #define MPI3_MAN12_PATTERN_RATE_4_HZ (0x20000000) 717 #define MPI3_MAN12_PATTERN_RATE_8_HZ (0x40000000) 718 #define MPI3_MAN12_PATTERN_RATE_16_HZ (0x60000000) 719 #define MPI3_MAN12_PATTERN_RATE_10_HZ (0x80000000) 720 #define MPI3_MAN12_PATTERN_RATE_20_HZ (0xa0000000) 721 #define MPI3_MAN12_PATTERN_RATE_40_HZ (0xc0000000) 722 #define MPI3_MAN12_PATTERN_LENGTH_MASK (0x1f000000) 723 #define MPI3_MAN12_PATTERN_LENGTH_SHIFT (24) 724 #define MPI3_MAN12_PATTERN_BIT_PATTERN_MASK (0x00ffffff) 725 #define MPI3_MAN12_PATTERN_BIT_PATTERN_SHIFT (0) 726 #ifndef MPI3_MAN13_NUM_TRANSLATION_MAX 727 #define MPI3_MAN13_NUM_TRANSLATION_MAX (1) 728 #endif 729 struct mpi3_man13_translation_info { 730 __le32 slot_status; 731 __le32 mask; 732 u8 activity; 733 u8 locate; 734 u8 error; 735 u8 reserved0b; 736 }; 737 738 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_FAULT (0x20000000) 739 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_OFF (0x10000000) 740 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_ACTIVITY (0x00800000) 741 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DO_NOT_REMOVE (0x00400000) 742 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_MISSING (0x00100000) 743 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_INSERT (0x00080000) 744 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REMOVAL (0x00040000) 745 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IDENTIFY (0x00020000) 746 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_OK (0x00008000) 747 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_RESERVED_DEVICE (0x00004000) 748 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_HOT_SPARE (0x00002000) 749 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_CONSISTENCY_CHECK (0x00001000) 750 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000800) 751 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_FAILED_ARRAY (0x00000400) 752 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP (0x00000200) 753 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP_ABORT (0x00000100) 754 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_PREDICTED_FAILURE (0x00000040) 755 #define MPI3_MAN13_BLINK_PATTERN_FORCE_OFF (0x00) 756 #define MPI3_MAN13_BLINK_PATTERN_FORCE_ON (0x01) 757 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_0 (0x02) 758 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_1 (0x03) 759 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_2 (0x04) 760 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_3 (0x05) 761 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_4 (0x06) 762 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_5 (0x07) 763 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_6 (0x08) 764 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_7 (0x09) 765 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY (0x0a) 766 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY_TRAIL (0x0b) 767 struct mpi3_man_page13 { 768 struct mpi3_config_page_header header; 769 u8 num_trans; 770 u8 reserved09[3]; 771 __le32 reserved0c; 772 struct mpi3_man13_translation_info translation[MPI3_MAN13_NUM_TRANSLATION_MAX]; 773 }; 774 775 #define MPI3_MAN13_PAGEVERSION (0x00) 776 struct mpi3_man_page14 { 777 struct mpi3_config_page_header header; 778 __le32 reserved08; 779 u8 num_slot_groups; 780 u8 num_slots; 781 __le16 max_cert_chain_length; 782 __le32 sealed_slots; 783 __le32 populated_slots; 784 __le32 mgmt_pt_updatable_slots; 785 }; 786 #define MPI3_MAN14_PAGEVERSION (0x00) 787 #define MPI3_MAN14_NUMSLOTS_MAX (32) 788 #ifndef MPI3_MAN15_VERSION_RECORD_MAX 789 #define MPI3_MAN15_VERSION_RECORD_MAX 1 790 #endif 791 struct mpi3_man15_version_record { 792 __le16 spdm_version; 793 __le16 reserved02; 794 }; 795 796 struct mpi3_man_page15 { 797 struct mpi3_config_page_header header; 798 u8 num_version_records; 799 u8 reserved09[3]; 800 __le32 reserved0c; 801 struct mpi3_man15_version_record version_record[MPI3_MAN15_VERSION_RECORD_MAX]; 802 }; 803 804 #define MPI3_MAN15_PAGEVERSION (0x00) 805 #ifndef MPI3_MAN16_CERT_ALGO_MAX 806 #define MPI3_MAN16_CERT_ALGO_MAX 1 807 #endif 808 struct mpi3_man16_certificate_algorithm { 809 u8 slot_group; 810 u8 reserved01[3]; 811 __le32 base_asym_algo; 812 __le32 base_hash_algo; 813 __le32 reserved0c[3]; 814 }; 815 816 struct mpi3_man_page16 { 817 struct mpi3_config_page_header header; 818 __le32 reserved08; 819 u8 num_cert_algos; 820 u8 reserved0d[3]; 821 struct mpi3_man16_certificate_algorithm certificate_algorithm[MPI3_MAN16_CERT_ALGO_MAX]; 822 }; 823 824 #define MPI3_MAN16_PAGEVERSION (0x00) 825 #ifndef MPI3_MAN17_HASH_ALGORITHM_MAX 826 #define MPI3_MAN17_HASH_ALGORITHM_MAX 1 827 #endif 828 struct mpi3_man17_hash_algorithm { 829 u8 meas_specification; 830 u8 reserved01[3]; 831 __le32 measurement_hash_algo; 832 __le32 reserved08[2]; 833 }; 834 835 struct mpi3_man_page17 { 836 struct mpi3_config_page_header header; 837 __le32 reserved08; 838 u8 num_hash_algos; 839 u8 reserved0d[3]; 840 struct mpi3_man17_hash_algorithm hash_algorithm[MPI3_MAN17_HASH_ALGORITHM_MAX]; 841 }; 842 843 #define MPI3_MAN17_PAGEVERSION (0x00) 844 struct mpi3_man_page20 { 845 struct mpi3_config_page_header header; 846 __le32 reserved08; 847 __le32 nonpremium_features; 848 u8 allowed_personalities; 849 u8 reserved11[3]; 850 }; 851 852 #define MPI3_MAN20_PAGEVERSION (0x00) 853 #define MPI3_MAN20_ALLOWEDPERSON_RAID_MASK (0x02) 854 #define MPI3_MAN20_ALLOWEDPERSON_RAID_ALLOWED (0x02) 855 #define MPI3_MAN20_ALLOWEDPERSON_RAID_NOT_ALLOWED (0x00) 856 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_MASK (0x01) 857 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_ALLOWED (0x01) 858 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_NOT_ALLOWED (0x00) 859 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_MASK (0x01) 860 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_ENABLED (0x00) 861 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_DISABLED (0x01) 862 struct mpi3_man_page21 { 863 struct mpi3_config_page_header header; 864 __le32 reserved08; 865 __le32 flags; 866 }; 867 868 #define MPI3_MAN21_PAGEVERSION (0x00) 869 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK (0x00000060) 870 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK (0x00000000) 871 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW (0x00000020) 872 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN (0x00000040) 873 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK (0x00000008) 874 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW (0x00000000) 875 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT (0x00000008) 876 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK (0x00000001) 877 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT (0x00000000) 878 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC (0x00000001) 879 #ifndef MPI3_MAN_PROD_SPECIFIC_MAX 880 #define MPI3_MAN_PROD_SPECIFIC_MAX (1) 881 #endif 882 struct mpi3_man_page_product_specific { 883 struct mpi3_config_page_header header; 884 __le32 product_specific_info[MPI3_MAN_PROD_SPECIFIC_MAX]; 885 }; 886 887 struct mpi3_io_unit_page0 { 888 struct mpi3_config_page_header header; 889 __le64 unique_value; 890 __le32 nvdata_version_default; 891 __le32 nvdata_version_persistent; 892 }; 893 894 #define MPI3_IOUNIT0_PAGEVERSION (0x00) 895 struct mpi3_io_unit_page1 { 896 struct mpi3_config_page_header header; 897 __le32 flags; 898 u8 dmd_io_delay; 899 u8 dmd_report_pcie; 900 u8 dmd_report_sata; 901 u8 dmd_report_sas; 902 }; 903 904 #define MPI3_IOUNIT1_PAGEVERSION (0x00) 905 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_MASK (0x00000030) 906 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_ENABLE (0x00000000) 907 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_DISABLE (0x00000010) 908 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_NO_MODIFY (0x00000020) 909 #define MPI3_IOUNIT1_FLAGS_ATA_SECURITY_FREEZE_LOCK (0x00000008) 910 #define MPI3_IOUNIT1_FLAGS_WRITE_SAME_BUFFER (0x00000004) 911 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_MASK (0x00000003) 912 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_ENABLE (0x00000000) 913 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_DISABLE (0x00000001) 914 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_UNCHANGED (0x00000002) 915 #define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_MASK (0x7f) 916 #define MPI3_IOUNIT1_DMD_REPORT_UNIT_16_SEC (0x80) 917 #ifndef MPI3_IO_UNIT2_GPIO_VAL_MAX 918 #define MPI3_IO_UNIT2_GPIO_VAL_MAX (1) 919 #endif 920 struct mpi3_io_unit_page2 { 921 struct mpi3_config_page_header header; 922 u8 gpio_count; 923 u8 reserved09[3]; 924 __le16 gpio_val[MPI3_IO_UNIT2_GPIO_VAL_MAX]; 925 }; 926 927 #define MPI3_IOUNIT2_PAGEVERSION (0x00) 928 #define MPI3_IOUNIT2_GPIO_FUNCTION_MASK (0xfffc) 929 #define MPI3_IOUNIT2_GPIO_FUNCTION_SHIFT (2) 930 #define MPI3_IOUNIT2_GPIO_SETTING_MASK (0x0001) 931 #define MPI3_IOUNIT2_GPIO_SETTING_OFF (0x0000) 932 #define MPI3_IOUNIT2_GPIO_SETTING_ON (0x0001) 933 struct mpi3_io_unit3_sensor { 934 __le16 flags; 935 u8 threshold_margin; 936 u8 reserved03; 937 __le16 threshold[3]; 938 __le16 reserved0a; 939 __le32 reserved0c; 940 __le32 reserved10; 941 __le32 reserved14; 942 }; 943 944 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_EVENT_ENABLED (0x0010) 945 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_ACTION_ENABLED (0x0008) 946 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_EVENT_ENABLED (0x0004) 947 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_ACTION_ENABLED (0x0002) 948 #define MPI3_IOUNIT3_SENSOR_FLAGS_WARNING_EVENT_ENABLED (0x0001) 949 #ifndef MPI3_IO_UNIT3_SENSOR_MAX 950 #define MPI3_IO_UNIT3_SENSOR_MAX (1) 951 #endif 952 struct mpi3_io_unit_page3 { 953 struct mpi3_config_page_header header; 954 __le32 reserved08; 955 u8 num_sensors; 956 u8 nominal_poll_interval; 957 u8 warning_poll_interval; 958 u8 reserved0f; 959 struct mpi3_io_unit3_sensor sensor[MPI3_IO_UNIT3_SENSOR_MAX]; 960 }; 961 962 #define MPI3_IOUNIT3_PAGEVERSION (0x00) 963 struct mpi3_io_unit4_sensor { 964 __le16 current_temperature; 965 __le16 reserved02; 966 u8 flags; 967 u8 reserved05[3]; 968 __le16 istwi_index; 969 u8 channel; 970 u8 reserved0b; 971 __le32 reserved0c; 972 }; 973 974 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_MASK (0xe0) 975 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_SHIFT (5) 976 #define MPI3_IOUNIT4_SENSOR_FLAGS_TEMP_VALID (0x01) 977 #define MPI3_IOUNIT4_SENSOR_ISTWI_INDEX_INTERNAL (0xffff) 978 #define MPI3_IOUNIT4_SENSOR_CHANNEL_RESERVED (0xff) 979 #ifndef MPI3_IO_UNIT4_SENSOR_MAX 980 #define MPI3_IO_UNIT4_SENSOR_MAX (1) 981 #endif 982 struct mpi3_io_unit_page4 { 983 struct mpi3_config_page_header header; 984 __le32 reserved08; 985 u8 num_sensors; 986 u8 reserved0d[3]; 987 struct mpi3_io_unit4_sensor sensor[MPI3_IO_UNIT4_SENSOR_MAX]; 988 }; 989 990 #define MPI3_IOUNIT4_PAGEVERSION (0x00) 991 struct mpi3_io_unit5_spinup_group { 992 u8 max_target_spinup; 993 u8 spinup_delay; 994 u8 spinup_flags; 995 u8 reserved03; 996 }; 997 998 #define MPI3_IOUNIT5_SPINUP_FLAGS_DISABLE (0x01) 999 #ifndef MPI3_IO_UNIT5_PHY_MAX 1000 #define MPI3_IO_UNIT5_PHY_MAX (4) 1001 #endif 1002 struct mpi3_io_unit_page5 { 1003 struct mpi3_config_page_header header; 1004 struct mpi3_io_unit5_spinup_group spinup_group_parameters[4]; 1005 __le32 reserved18; 1006 __le32 reserved1c; 1007 __le16 device_shutdown; 1008 __le16 reserved22; 1009 u8 pcie_device_wait_time; 1010 u8 sata_device_wait_time; 1011 u8 spinup_encl_drive_count; 1012 u8 spinup_encl_delay; 1013 u8 num_phys; 1014 u8 pe_initial_spinup_delay; 1015 u8 topology_stable_time; 1016 u8 flags; 1017 u8 phy[MPI3_IO_UNIT5_PHY_MAX]; 1018 }; 1019 1020 #define MPI3_IOUNIT5_PAGEVERSION (0x00) 1021 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NO_ACTION (0x00) 1022 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_ATTACHED (0x01) 1023 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_EXPANDER_ATTACHED (0x02) 1024 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SWITCH_ATTACHED (0x02) 1025 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_EXPANDER (0x03) 1026 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_SWITCH (0x03) 1027 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_MASK (0x0300) 1028 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_SHIFT (8) 1029 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_MASK (0x00c0) 1030 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_SHIFT (6) 1031 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_MASK (0x0030) 1032 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_SHIFT (4) 1033 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_MASK (0x000c) 1034 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_SHIFT (2) 1035 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_MASK (0x0003) 1036 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_SHIFT (0) 1037 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_MASK (0x0c) 1038 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_NOT_SUPPORTED (0x00) 1039 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_OS_CONTROLLED (0x04) 1040 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_APP_CONTROLLED (0x08) 1041 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_BLOCKED (0x0c) 1042 #define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP (0x02) 1043 #define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE (0x01) 1044 #define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK (0x03) 1045 struct mpi3_io_unit_page6 { 1046 struct mpi3_config_page_header header; 1047 __le32 board_power_requirement; 1048 __le32 pci_slot_power_allocation; 1049 u8 flags; 1050 u8 reserved11[3]; 1051 }; 1052 1053 #define MPI3_IOUNIT6_PAGEVERSION (0x00) 1054 #define MPI3_IOUNIT6_FLAGS_ACT_CABLE_PWR_EXC (0x01) 1055 #ifndef MPI3_IOUNIT8_DIGEST_MAX 1056 #define MPI3_IOUNIT8_DIGEST_MAX (1) 1057 #endif 1058 union mpi3_iounit8_digest { 1059 __le32 dword[16]; 1060 __le16 word[32]; 1061 u8 byte[64]; 1062 }; 1063 1064 struct mpi3_io_unit_page8 { 1065 struct mpi3_config_page_header header; 1066 u8 sb_mode; 1067 u8 sb_state; 1068 __le16 reserved0a; 1069 u8 num_slots; 1070 u8 slots_available; 1071 u8 current_key_encryption_algo; 1072 u8 key_digest_hash_algo; 1073 union mpi3_version_union current_svn; 1074 __le32 reserved14; 1075 __le32 current_key[128]; 1076 union mpi3_iounit8_digest digest[MPI3_IOUNIT8_DIGEST_MAX]; 1077 }; 1078 1079 #define MPI3_IOUNIT8_PAGEVERSION (0x00) 1080 #define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG (0x04) 1081 #define MPI3_IOUNIT8_SBMODE_HARD_SECURE (0x02) 1082 #define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE (0x01) 1083 #define MPI3_IOUNIT8_SBSTATE_SVN_UPDATE_PENDING (0x04) 1084 #define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING (0x02) 1085 #define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED (0x01) 1086 #define MPI3_IOUNIT8_SBMODE_CURRENT_KEY_IOUNIT17 (0x10) 1087 #define MPI3_IOUNIT8_SBMODE_HARD_SECURE_RECERTIFIED (0x08) 1088 struct mpi3_io_unit_page9 { 1089 struct mpi3_config_page_header header; 1090 __le32 flags; 1091 __le16 first_device; 1092 __le16 reserved0e; 1093 }; 1094 1095 #define MPI3_IOUNIT9_PAGEVERSION (0x00) 1096 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_MASK (0x00000006) 1097 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_SHIFT (1) 1098 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_NONE (0x00000000) 1099 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_RECEPTACLE (0x00000002) 1100 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_BACKPLANE_TYPE (0x00000004) 1101 #define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED (0x00000001) 1102 #define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN (0xffff) 1103 #define MPI3_IOUNIT9_FIRSTDEVICE_IN_DRIVER_PAGE_0 (0xfffe) 1104 1105 struct mpi3_io_unit_page10 { 1106 struct mpi3_config_page_header header; 1107 u8 flags; 1108 u8 reserved09[3]; 1109 __le32 silicon_id; 1110 u8 fw_version_minor; 1111 u8 fw_version_major; 1112 u8 hw_version_minor; 1113 u8 hw_version_major; 1114 u8 part_number[16]; 1115 }; 1116 #define MPI3_IOUNIT10_PAGEVERSION (0x00) 1117 #define MPI3_IOUNIT10_FLAGS_VALID (0x01) 1118 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_MASK (0x02) 1119 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_FIRST_REGION (0x00) 1120 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_SECOND_REGION (0x02) 1121 #define MPI3_IOUNIT10_FLAGS_PBLP_EXPECTED (0x80) 1122 #ifndef MPI3_IOUNIT11_PROFILE_MAX 1123 #define MPI3_IOUNIT11_PROFILE_MAX (1) 1124 #endif 1125 struct mpi3_iounit11_profile { 1126 u8 profile_identifier; 1127 u8 reserved01[3]; 1128 __le16 max_vds; 1129 __le16 max_host_pds; 1130 __le16 max_adv_host_pds; 1131 __le16 max_raid_pds; 1132 __le16 max_nvme; 1133 __le16 max_outstanding_requests; 1134 __le16 subsystem_id; 1135 __le16 reserved12; 1136 __le32 reserved14[2]; 1137 }; 1138 struct mpi3_io_unit_page11 { 1139 struct mpi3_config_page_header header; 1140 __le32 reserved08; 1141 u8 num_profiles; 1142 u8 current_profile_identifier; 1143 __le16 reserved0e; 1144 struct mpi3_iounit11_profile profile[MPI3_IOUNIT11_PROFILE_MAX]; 1145 }; 1146 #define MPI3_IOUNIT11_PAGEVERSION (0x00) 1147 #ifndef MPI3_IOUNIT12_BUCKET_MAX 1148 #define MPI3_IOUNIT12_BUCKET_MAX (1) 1149 #endif 1150 struct mpi3_iounit12_bucket { 1151 u8 coalescing_depth; 1152 u8 coalescing_timeout; 1153 __le16 io_count_low_boundary; 1154 __le32 reserved04; 1155 }; 1156 struct mpi3_io_unit_page12 { 1157 struct mpi3_config_page_header header; 1158 __le32 flags; 1159 __le32 reserved0c[4]; 1160 u8 num_buckets; 1161 u8 reserved1d[3]; 1162 struct mpi3_iounit12_bucket bucket[MPI3_IOUNIT12_BUCKET_MAX]; 1163 }; 1164 #define MPI3_IOUNIT12_PAGEVERSION (0x00) 1165 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_MASK (0x00000300) 1166 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_SHIFT (8) 1167 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_8 (0x00000000) 1168 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_16 (0x00000100) 1169 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_32 (0x00000200) 1170 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_64 (0x00000300) 1171 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_MASK (0x00000003) 1172 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_DISABLED (0x00000000) 1173 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_500US (0x00000001) 1174 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_1MS (0x00000002) 1175 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_2MS (0x00000003) 1176 #ifndef MPI3_IOUNIT13_FUNC_MAX 1177 #define MPI3_IOUNIT13_FUNC_MAX (1) 1178 #endif 1179 struct mpi3_iounit13_allowed_function { 1180 __le16 sub_function; 1181 u8 function_code; 1182 u8 function_flags; 1183 }; 1184 #define MPI3_IOUNIT13_FUNCTION_FLAGS_ADMIN_BLOCKED (0x04) 1185 #define MPI3_IOUNIT13_FUNCTION_FLAGS_OOB_BLOCKED (0x02) 1186 #define MPI3_IOUNIT13_FUNCTION_FLAGS_CHECK_SUBFUNCTION_ENABLED (0x01) 1187 struct mpi3_io_unit_page13 { 1188 struct mpi3_config_page_header header; 1189 __le16 flags; 1190 __le16 reserved0a; 1191 u8 num_allowed_functions; 1192 u8 reserved0d[3]; 1193 struct mpi3_iounit13_allowed_function allowed_function[MPI3_IOUNIT13_FUNC_MAX]; 1194 }; 1195 #define MPI3_IOUNIT13_PAGEVERSION (0x00) 1196 #define MPI3_IOUNIT13_FLAGS_ADMIN_BLOCKED (0x0002) 1197 #define MPI3_IOUNIT13_FLAGS_OOB_BLOCKED (0x0001) 1198 #ifndef MPI3_IOUNIT14_MD_MAX 1199 #define MPI3_IOUNIT14_MD_MAX (1) 1200 #endif 1201 struct mpi3_iounit14_pagemetadata { 1202 u8 page_type; 1203 u8 page_number; 1204 u8 reserved02; 1205 u8 page_flags; 1206 }; 1207 #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_OOBWRITE_ALLOWED (0x02) 1208 #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_HOSTWRITE_ALLOWED (0x01) 1209 struct mpi3_io_unit_page14 { 1210 struct mpi3_config_page_header header; 1211 u8 flags; 1212 u8 reserved09[3]; 1213 u8 num_pages; 1214 u8 reserved0d[3]; 1215 struct mpi3_iounit14_pagemetadata page_metadata[MPI3_IOUNIT14_MD_MAX]; 1216 }; 1217 #define MPI3_IOUNIT14_PAGEVERSION (0x00) 1218 #define MPI3_IOUNIT14_FLAGS_READONLY (0x01) 1219 #ifndef MPI3_IOUNIT15_PBD_MAX 1220 #define MPI3_IOUNIT15_PBD_MAX (1) 1221 #endif 1222 struct mpi3_io_unit_page15 { 1223 struct mpi3_config_page_header header; 1224 u8 flags; 1225 u8 reserved09[3]; 1226 __le32 reserved0c; 1227 u8 power_budgeting_capability; 1228 u8 reserved11[3]; 1229 u8 num_power_budget_data; 1230 u8 reserved15[3]; 1231 __le32 power_budget_data[MPI3_IOUNIT15_PBD_MAX]; 1232 }; 1233 #define MPI3_IOUNIT15_PAGEVERSION (0x00) 1234 #define MPI3_IOUNIT15_FLAGS_EPRINIT_INITREQUIRED (0x04) 1235 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_MASK (0x03) 1236 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_NOT_SUPPORTED (0x00) 1237 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITHOUT_POWER_BRAKE_GPIO (0x01) 1238 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITH_POWER_BRAKE_GPIO (0x02) 1239 #define MPI3_IOUNIT15_NUMPOWERBUDGETDATA_POWER_BUDGETING_DISABLED (0x00) 1240 1241 struct mpi3_io_unit_page17 { 1242 struct mpi3_config_page_header header; 1243 u8 num_instances; 1244 u8 instance; 1245 __le16 reserved0a; 1246 __le32 reserved0c[4]; 1247 __le16 key_length; 1248 u8 encryption_algorithm; 1249 u8 reserved1f; 1250 __le32 current_key[]; 1251 }; 1252 #define MPI3_IOUNIT17_PAGEVERSION (0x00) 1253 struct mpi3_ioc_page0 { 1254 struct mpi3_config_page_header header; 1255 __le32 reserved08; 1256 __le16 vendor_id; 1257 __le16 device_id; 1258 u8 revision_id; 1259 u8 reserved11[3]; 1260 __le32 class_code; 1261 __le16 subsystem_vendor_id; 1262 __le16 subsystem_id; 1263 }; 1264 1265 #define MPI3_IOC0_PAGEVERSION (0x00) 1266 struct mpi3_ioc_page1 { 1267 struct mpi3_config_page_header header; 1268 __le32 coalescing_timeout; 1269 u8 coalescing_depth; 1270 u8 obsolete; 1271 __le16 reserved0e; 1272 }; 1273 #define MPI3_IOC1_PAGEVERSION (0x00) 1274 #ifndef MPI3_IOC2_EVENTMASK_WORDS 1275 #define MPI3_IOC2_EVENTMASK_WORDS (4) 1276 #endif 1277 struct mpi3_ioc_page2 { 1278 struct mpi3_config_page_header header; 1279 __le32 reserved08; 1280 __le16 sas_broadcast_primitive_masks; 1281 __le16 sas_notify_primitive_masks; 1282 __le32 event_masks[MPI3_IOC2_EVENTMASK_WORDS]; 1283 }; 1284 1285 #define MPI3_IOC2_PAGEVERSION (0x00) 1286 #define MPI3_DRIVER_FLAGS_ADMINRAIDPD_BLOCKED (0x0010) 1287 #define MPI3_DRIVER_FLAGS_OOBRAIDPD_BLOCKED (0x0008) 1288 #define MPI3_DRIVER_FLAGS_OOBRAIDVD_BLOCKED (0x0004) 1289 #define MPI3_DRIVER_FLAGS_OOBADVHOSTPD_BLOCKED (0x0002) 1290 #define MPI3_DRIVER_FLAGS_OOBHOSTPD_BLOCKED (0x0001) 1291 struct mpi3_allowed_cmd_scsi { 1292 __le16 service_action; 1293 u8 operation_code; 1294 u8 command_flags; 1295 }; 1296 1297 struct mpi3_allowed_cmd_ata { 1298 u8 subcommand; 1299 u8 reserved01; 1300 u8 command; 1301 u8 command_flags; 1302 }; 1303 1304 struct mpi3_allowed_cmd_nvme { 1305 u8 reserved00; 1306 u8 nvme_cmd_flags; 1307 u8 op_code; 1308 u8 command_flags; 1309 }; 1310 1311 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_MASK (0x80) 1312 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_IO (0x00) 1313 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_ADMIN (0x80) 1314 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_MASK (0x3f) 1315 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_NVM (0x00) 1316 union mpi3_allowed_cmd { 1317 struct mpi3_allowed_cmd_scsi scsi; 1318 struct mpi3_allowed_cmd_ata ata; 1319 struct mpi3_allowed_cmd_nvme nvme; 1320 }; 1321 1322 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_ADMINRAIDPD_BLOCKED (0x20) 1323 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDPD_BLOCKED (0x10) 1324 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDVD_BLOCKED (0x08) 1325 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBADVHOSTPD_BLOCKED (0x04) 1326 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBHOSTPD_BLOCKED (0x02) 1327 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_CHECKSUBCMD_ENABLED (0x01) 1328 #ifndef MPI3_ALLOWED_CMDS_MAX 1329 #define MPI3_ALLOWED_CMDS_MAX (1) 1330 #endif 1331 struct mpi3_driver_page0 { 1332 struct mpi3_config_page_header header; 1333 __le32 bsd_options; 1334 u8 ssu_timeout; 1335 u8 io_timeout; 1336 u8 tur_retries; 1337 u8 tur_interval; 1338 u8 reserved10; 1339 u8 security_key_timeout; 1340 __le16 first_device; 1341 __le32 reserved14; 1342 __le32 reserved18; 1343 }; 1344 #define MPI3_DRIVER0_PAGEVERSION (0x00) 1345 #define MPI3_DRIVER0_BSDOPTS_DEVICEEXPOSURE_DISABLE (0x00000020) 1346 #define MPI3_DRIVER0_BSDOPTS_WRITECACHE_DISABLE (0x00000010) 1347 #define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE (0x00000008) 1348 #define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL (0x00000004) 1349 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK (0x00000003) 1350 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS (0x00000000) 1351 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY (0x00000001) 1352 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_INTERNAL_DEVS (0x00000002) 1353 #define MPI3_DRIVER0_FIRSTDEVICE_IGNORE1 (0x0000) 1354 #define MPI3_DRIVER0_FIRSTDEVICE_IGNORE2 (0xffff) 1355 struct mpi3_driver_page1 { 1356 struct mpi3_config_page_header header; 1357 __le32 flags; 1358 u8 time_stamp_update; 1359 u8 reserved0d[3]; 1360 __le16 host_diag_trace_max_size; 1361 __le16 host_diag_trace_min_size; 1362 __le16 host_diag_trace_decrement_size; 1363 __le16 reserved16; 1364 __le16 host_diag_fw_max_size; 1365 __le16 host_diag_fw_min_size; 1366 __le16 host_diag_fw_decrement_size; 1367 __le16 reserved1e; 1368 __le16 host_diag_driver_max_size; 1369 __le16 host_diag_driver_min_size; 1370 __le16 host_diag_driver_decrement_size; 1371 __le16 reserved26; 1372 }; 1373 1374 #define MPI3_DRIVER1_PAGEVERSION (0x00) 1375 #ifndef MPI3_DRIVER2_TRIGGER_MAX 1376 #define MPI3_DRIVER2_TRIGGER_MAX (1) 1377 #endif 1378 struct mpi3_driver2_trigger_event { 1379 u8 type; 1380 u8 flags; 1381 u8 reserved02; 1382 u8 event; 1383 __le32 reserved04[3]; 1384 }; 1385 1386 struct mpi3_driver2_trigger_scsi_sense { 1387 u8 type; 1388 u8 flags; 1389 __le16 reserved02; 1390 u8 ascq; 1391 u8 asc; 1392 u8 sense_key; 1393 u8 reserved07; 1394 __le32 reserved08[2]; 1395 }; 1396 1397 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASCQ_MATCH_ALL (0xff) 1398 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASC_MATCH_ALL (0xff) 1399 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_SENSE_KEY_MATCH_ALL (0xff) 1400 struct mpi3_driver2_trigger_reply { 1401 u8 type; 1402 u8 flags; 1403 __le16 ioc_status; 1404 __le32 ioc_log_info; 1405 __le32 ioc_log_info_mask; 1406 __le32 reserved0c; 1407 }; 1408 1409 #define MPI3_DRIVER2_TRIGGER_REPLY_IOCSTATUS_MATCH_ALL (0xffff) 1410 union mpi3_driver2_trigger_element { 1411 struct mpi3_driver2_trigger_event event; 1412 struct mpi3_driver2_trigger_scsi_sense scsi_sense; 1413 struct mpi3_driver2_trigger_reply reply; 1414 }; 1415 1416 #define MPI3_DRIVER2_TRIGGER_TYPE_EVENT (0x00) 1417 #define MPI3_DRIVER2_TRIGGER_TYPE_SCSI_SENSE (0x01) 1418 #define MPI3_DRIVER2_TRIGGER_TYPE_REPLY (0x02) 1419 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_TRACE_RELEASE (0x02) 1420 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_FW_RELEASE (0x01) 1421 struct mpi3_driver_page2 { 1422 struct mpi3_config_page_header header; 1423 __le64 global_trigger; 1424 __le32 reserved10[3]; 1425 u8 num_triggers; 1426 u8 reserved1d[3]; 1427 union mpi3_driver2_trigger_element trigger[MPI3_DRIVER2_TRIGGER_MAX]; 1428 }; 1429 1430 #define MPI3_DRIVER2_PAGEVERSION (0x00) 1431 #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_TRACE_RELEASE (0x8000000000000000ULL) 1432 #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_FW_RELEASE (0x4000000000000000ULL) 1433 #define MPI3_DRIVER2_GLOBALTRIGGER_SNAPDUMP_ENABLED (0x2000000000000000ULL) 1434 #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED (0x1000000000000000ULL) 1435 #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED (0x0800000000000000ULL) 1436 #define MPI3_DRIVER2_GLOBALTRIGGER_DEVICE_REMOVAL_ENABLED (0x0000000000000004ULL) 1437 #define MPI3_DRIVER2_GLOBALTRIGGER_TASK_MANAGEMENT_ENABLED (0x0000000000000002ULL) 1438 struct mpi3_driver_page10 { 1439 struct mpi3_config_page_header header; 1440 __le16 flags; 1441 __le16 reserved0a; 1442 u8 num_allowed_commands; 1443 u8 reserved0d[3]; 1444 union mpi3_allowed_cmd allowed_command[MPI3_ALLOWED_CMDS_MAX]; 1445 }; 1446 1447 #define MPI3_DRIVER10_PAGEVERSION (0x00) 1448 struct mpi3_driver_page20 { 1449 struct mpi3_config_page_header header; 1450 __le16 flags; 1451 __le16 reserved0a; 1452 u8 num_allowed_commands; 1453 u8 reserved0d[3]; 1454 union mpi3_allowed_cmd allowed_command[MPI3_ALLOWED_CMDS_MAX]; 1455 }; 1456 1457 #define MPI3_DRIVER20_PAGEVERSION (0x00) 1458 struct mpi3_driver_page30 { 1459 struct mpi3_config_page_header header; 1460 __le16 flags; 1461 __le16 reserved0a; 1462 u8 num_allowed_commands; 1463 u8 reserved0d[3]; 1464 union mpi3_allowed_cmd allowed_command[MPI3_ALLOWED_CMDS_MAX]; 1465 }; 1466 1467 #define MPI3_DRIVER30_PAGEVERSION (0x00) 1468 union mpi3_security_mac { 1469 __le32 dword[16]; 1470 __le16 word[32]; 1471 u8 byte[64]; 1472 }; 1473 1474 union mpi3_security_nonce { 1475 __le32 dword[16]; 1476 __le16 word[32]; 1477 u8 byte[64]; 1478 }; 1479 1480 union mpi3_security_root_digest { 1481 __le32 dword[16]; 1482 __le16 word[32]; 1483 u8 byte[64]; 1484 }; 1485 1486 union mpi3_security0_cert_chain { 1487 __le32 dword[1024]; 1488 __le16 word[2048]; 1489 u8 byte[4096]; 1490 }; 1491 1492 struct mpi3_security_page0 { 1493 struct mpi3_config_page_header header; 1494 u8 slot_num_group; 1495 u8 slot_num; 1496 __le16 cert_chain_length; 1497 u8 cert_chain_flags; 1498 u8 reserved0d[3]; 1499 __le32 base_asym_algo; 1500 __le32 base_hash_algo; 1501 __le32 reserved18[4]; 1502 union mpi3_security_mac mac; 1503 union mpi3_security_nonce nonce; 1504 union mpi3_security0_cert_chain certificate_chain; 1505 }; 1506 1507 #define MPI3_SECURITY0_PAGEVERSION (0x00) 1508 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_MASK (0x0e) 1509 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_UNUSED (0x00) 1510 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_CERBERUS (0x02) 1511 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SPDM (0x04) 1512 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_SEALED (0x01) 1513 #ifndef MPI3_SECURITY1_KEY_RECORD_MAX 1514 #define MPI3_SECURITY1_KEY_RECORD_MAX 1 1515 #endif 1516 #ifndef MPI3_SECURITY1_PAD_MAX 1517 #define MPI3_SECURITY1_PAD_MAX 4 1518 #endif 1519 union mpi3_security1_key_data { 1520 __le32 dword[128]; 1521 __le16 word[256]; 1522 u8 byte[512]; 1523 }; 1524 1525 struct mpi3_security1_key_record { 1526 u8 flags; 1527 u8 consumer; 1528 __le16 key_data_size; 1529 __le32 additional_key_data; 1530 __le32 reserved08[2]; 1531 union mpi3_security1_key_data key_data; 1532 }; 1533 1534 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_MASK (0x1f) 1535 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_NOT_VALID (0x00) 1536 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_HMAC (0x01) 1537 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_AES (0x02) 1538 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PRIVATE (0x03) 1539 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PUBLIC (0x04) 1540 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_NOT_VALID (0x00) 1541 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_SAFESTORE (0x01) 1542 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CERT_CHAIN (0x02) 1543 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_DEVICE_KEY (0x03) 1544 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CACHE_OFFLOAD (0x04) 1545 struct mpi3_security_page1 { 1546 struct mpi3_config_page_header header; 1547 __le32 reserved08[2]; 1548 union mpi3_security_mac mac; 1549 union mpi3_security_nonce nonce; 1550 u8 num_keys; 1551 u8 reserved91[3]; 1552 __le32 reserved94[3]; 1553 struct mpi3_security1_key_record key_record[MPI3_SECURITY1_KEY_RECORD_MAX]; 1554 u8 pad[MPI3_SECURITY1_PAD_MAX]; 1555 }; 1556 1557 #define MPI3_SECURITY1_PAGEVERSION (0x00) 1558 #ifndef MPI3_SECURITY2_TRUSTED_ROOT_MAX 1559 #define MPI3_SECURITY2_TRUSTED_ROOT_MAX 1 1560 #endif 1561 struct mpi3_security2_trusted_root { 1562 u8 level; 1563 u8 hash_algorithm; 1564 __le16 trusted_root_flags; 1565 __le32 reserved04[3]; 1566 union mpi3_security_root_digest root_digest; 1567 }; 1568 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_MASK (0x0006) 1569 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_SHIFT (1) 1570 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_HA_FIELD (0x0000) 1571 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_AKI (0x0002) 1572 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_USERPROVISIONED_YES (0x0001) 1573 struct mpi3_security_page2 { 1574 struct mpi3_config_page_header header; 1575 __le32 reserved08[2]; 1576 union mpi3_security_mac mac; 1577 union mpi3_security_nonce nonce; 1578 __le32 reserved90[3]; 1579 u8 num_roots; 1580 u8 reserved9d[3]; 1581 struct mpi3_security2_trusted_root trusted_root[MPI3_SECURITY2_TRUSTED_ROOT_MAX]; 1582 }; 1583 #define MPI3_SECURITY2_PAGEVERSION (0x00) 1584 struct mpi3_sas_io_unit0_phy_data { 1585 u8 io_unit_port; 1586 u8 port_flags; 1587 u8 phy_flags; 1588 u8 negotiated_link_rate; 1589 __le16 controller_phy_device_info; 1590 __le16 reserved06; 1591 __le16 attached_dev_handle; 1592 __le16 controller_dev_handle; 1593 __le32 discovery_status; 1594 __le32 reserved10; 1595 }; 1596 1597 struct mpi3_sas_io_unit_page0 { 1598 struct mpi3_config_page_header header; 1599 __le32 reserved08; 1600 u8 num_phys; 1601 u8 init_status; 1602 __le16 reserved0e; 1603 struct mpi3_sas_io_unit0_phy_data phy_data[]; 1604 }; 1605 1606 #define MPI3_SASIOUNIT0_PAGEVERSION (0x00) 1607 #define MPI3_SASIOUNIT0_INITSTATUS_NO_ERRORS (0x00) 1608 #define MPI3_SASIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01) 1609 #define MPI3_SASIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02) 1610 #define MPI3_SASIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04) 1611 #define MPI3_SASIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05) 1612 #define MPI3_SASIOUNIT0_INITSTATUS_HOST_PHYS_ENABLED (0x06) 1613 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MIN (0xf0) 1614 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MAX (0xff) 1615 #define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS (0x08) 1616 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_MASK (0x03) 1617 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_IOUNIT1 (0x00) 1618 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_DYNAMIC (0x01) 1619 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_BACKPLANE (0x02) 1620 #define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 1621 #define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 1622 #define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1623 #define MPI3_SASIOUNIT0_PHYFLAGS_VIRTUAL_PHY (0x02) 1624 #define MPI3_SASIOUNIT0_PHYFLAGS_HOST_PHY (0x01) 1625 struct mpi3_sas_io_unit1_phy_data { 1626 u8 io_unit_port; 1627 u8 port_flags; 1628 u8 phy_flags; 1629 u8 max_min_link_rate; 1630 __le16 controller_phy_device_info; 1631 __le16 max_target_port_connect_time; 1632 __le32 reserved08; 1633 }; 1634 1635 struct mpi3_sas_io_unit_page1 { 1636 struct mpi3_config_page_header header; 1637 __le16 control_flags; 1638 __le16 sas_narrow_max_queue_depth; 1639 __le16 additional_control_flags; 1640 __le16 sas_wide_max_queue_depth; 1641 u8 num_phys; 1642 u8 sata_max_q_depth; 1643 __le16 reserved12; 1644 struct mpi3_sas_io_unit1_phy_data phy_data[]; 1645 }; 1646 1647 #define MPI3_SASIOUNIT1_PAGEVERSION (0x00) 1648 #define MPI3_SASIOUNIT1_CONTROL_CONTROLLER_DEVICE_SELF_TEST (0x8000) 1649 #define MPI3_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 1650 #define MPI3_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 1651 #define MPI3_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 1652 #define MPI3_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 1653 #define MPI3_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 1654 #define MPI3_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 1655 #define MPI3_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 1656 #define MPI3_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 1657 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_MASK (0x0001) 1658 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_DEVICE_NAME (0x0000) 1659 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SAS_ADDRESS (0x0001) 1660 #define MPI3_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 1661 #define MPI3_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 1662 #define MPI3_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 1663 #define MPI3_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 1664 #define MPI3_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 1665 #define MPI3_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 1666 #define MPI3_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 1667 #define MPI3_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 1668 #define MPI3_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 1669 #define MPI3_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 1670 #define MPI3_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 1671 #define MPI3_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 1672 #define MPI3_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1673 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_MASK (0xf0) 1674 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_SHIFT (4) 1675 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_6_0 (0xa0) 1676 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_12_0 (0xb0) 1677 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_22_5 (0xc0) 1678 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_MASK (0x0f) 1679 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_6_0 (0x0a) 1680 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_12_0 (0x0b) 1681 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_22_5 (0x0c) 1682 struct mpi3_sas_io_unit2_phy_pm_settings { 1683 u8 control_flags; 1684 u8 reserved01; 1685 __le16 inactivity_timer_exponent; 1686 u8 sata_partial_timeout; 1687 u8 reserved05; 1688 u8 sata_slumber_timeout; 1689 u8 reserved07; 1690 u8 sas_partial_timeout; 1691 u8 reserved09; 1692 u8 sas_slumber_timeout; 1693 u8 reserved0b; 1694 }; 1695 1696 #ifndef MPI3_SAS_IO_UNIT2_PHY_MAX 1697 #define MPI3_SAS_IO_UNIT2_PHY_MAX (1) 1698 #endif 1699 struct mpi3_sas_io_unit_page2 { 1700 struct mpi3_config_page_header header; 1701 u8 num_phys; 1702 u8 reserved09[3]; 1703 __le32 reserved0c; 1704 struct mpi3_sas_io_unit2_phy_pm_settings sas_phy_power_management_settings[MPI3_SAS_IO_UNIT2_PHY_MAX]; 1705 }; 1706 1707 #define MPI3_SASIOUNIT2_PAGEVERSION (0x00) 1708 #define MPI3_SASIOUNIT2_CONTROL_SAS_SLUMBER_ENABLE (0x08) 1709 #define MPI3_SASIOUNIT2_CONTROL_SAS_PARTIAL_ENABLE (0x04) 1710 #define MPI3_SASIOUNIT2_CONTROL_SATA_SLUMBER_ENABLE (0x02) 1711 #define MPI3_SASIOUNIT2_CONTROL_SATA_PARTIAL_ENABLE (0x01) 1712 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_MASK (0x7000) 1713 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_SHIFT (12) 1714 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_MASK (0x0700) 1715 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_SHIFT (8) 1716 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_MASK (0x0070) 1717 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_SHIFT (4) 1718 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_MASK (0x0007) 1719 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_SHIFT (0) 1720 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_SECONDS (7) 1721 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_SECOND (6) 1722 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MILLISECONDS (5) 1723 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MILLISECONDS (4) 1724 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MILLISECOND (3) 1725 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MICROSECONDS (2) 1726 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MICROSECONDS (1) 1727 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MICROSECOND (0) 1728 struct mpi3_sas_io_unit_page3 { 1729 struct mpi3_config_page_header header; 1730 __le32 reserved08; 1731 __le32 power_management_capabilities; 1732 }; 1733 1734 #define MPI3_SASIOUNIT3_PAGEVERSION (0x00) 1735 #define MPI3_SASIOUNIT3_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 1736 #define MPI3_SASIOUNIT3_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 1737 #define MPI3_SASIOUNIT3_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 1738 #define MPI3_SASIOUNIT3_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 1739 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 1740 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 1741 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 1742 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 1743 struct mpi3_sas_expander_page0 { 1744 struct mpi3_config_page_header header; 1745 u8 io_unit_port; 1746 u8 report_gen_length; 1747 __le16 enclosure_handle; 1748 __le32 reserved0c; 1749 __le64 sas_address; 1750 __le32 discovery_status; 1751 __le16 dev_handle; 1752 __le16 parent_dev_handle; 1753 __le16 expander_change_count; 1754 __le16 expander_route_indexes; 1755 u8 num_phys; 1756 u8 sas_level; 1757 __le16 flags; 1758 __le16 stp_bus_inactivity_time_limit; 1759 __le16 stp_max_connect_time_limit; 1760 __le16 stp_smp_nexus_loss_time; 1761 __le16 max_num_routed_sas_addresses; 1762 __le64 active_zone_manager_sas_address; 1763 __le16 zone_lock_inactivity_limit; 1764 __le16 reserved3a; 1765 u8 time_to_reduced_func; 1766 u8 initial_time_to_reduced_func; 1767 u8 max_reduced_func_time; 1768 u8 exp_status; 1769 }; 1770 1771 #define MPI3_SASEXPANDER0_PAGEVERSION (0x00) 1772 #define MPI3_SASEXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 1773 #define MPI3_SASEXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 1774 #define MPI3_SASEXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 1775 #define MPI3_SASEXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 1776 #define MPI3_SASEXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 1777 #define MPI3_SASEXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 1778 #define MPI3_SASEXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 1779 #define MPI3_SASEXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 1780 #define MPI3_SASEXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 1781 #define MPI3_SASEXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 1782 #define MPI3_SASEXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 1783 #define MPI3_SASEXPANDER0_ES_NOT_RESPONDING (0x02) 1784 #define MPI3_SASEXPANDER0_ES_RESPONDING (0x03) 1785 #define MPI3_SASEXPANDER0_ES_DELAY_NOT_RESPONDING (0x04) 1786 struct mpi3_sas_expander_page1 { 1787 struct mpi3_config_page_header header; 1788 u8 io_unit_port; 1789 u8 reserved09[3]; 1790 u8 num_phys; 1791 u8 phy; 1792 __le16 num_table_entries_programmed; 1793 u8 programmed_link_rate; 1794 u8 hw_link_rate; 1795 __le16 attached_dev_handle; 1796 __le32 phy_info; 1797 __le16 attached_device_info; 1798 __le16 reserved1a; 1799 __le16 expander_dev_handle; 1800 u8 change_count; 1801 u8 negotiated_link_rate; 1802 u8 phy_identifier; 1803 u8 attached_phy_identifier; 1804 u8 reserved22; 1805 u8 discovery_info; 1806 __le32 attached_phy_info; 1807 u8 zone_group; 1808 u8 self_config_status; 1809 __le16 reserved2a; 1810 __le16 slot; 1811 __le16 slot_index; 1812 }; 1813 1814 #define MPI3_SASEXPANDER1_PAGEVERSION (0x00) 1815 #define MPI3_SASEXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 1816 #define MPI3_SASEXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 1817 #define MPI3_SASEXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 1818 #ifndef MPI3_SASEXPANDER2_MAX_NUM_PHYS 1819 #define MPI3_SASEXPANDER2_MAX_NUM_PHYS (1) 1820 #endif 1821 struct mpi3_sasexpander2_phy_element { 1822 u8 link_change_count; 1823 u8 reserved01; 1824 __le16 rate_change_count; 1825 __le32 reserved04; 1826 }; 1827 1828 struct mpi3_sas_expander_page2 { 1829 struct mpi3_config_page_header header; 1830 u8 num_phys; 1831 u8 reserved09; 1832 __le16 dev_handle; 1833 __le32 reserved0c; 1834 struct mpi3_sasexpander2_phy_element phy[MPI3_SASEXPANDER2_MAX_NUM_PHYS]; 1835 }; 1836 1837 #define MPI3_SASEXPANDER2_PAGEVERSION (0x00) 1838 struct mpi3_sas_port_page0 { 1839 struct mpi3_config_page_header header; 1840 u8 port_number; 1841 u8 reserved09; 1842 u8 port_width; 1843 u8 reserved0b; 1844 u8 zone_group; 1845 u8 reserved0d[3]; 1846 __le64 sas_address; 1847 __le16 device_info; 1848 __le16 reserved1a; 1849 __le32 reserved1c; 1850 }; 1851 1852 #define MPI3_SASPORT0_PAGEVERSION (0x00) 1853 struct mpi3_sas_phy_page0 { 1854 struct mpi3_config_page_header header; 1855 __le16 owner_dev_handle; 1856 __le16 reserved0a; 1857 __le16 attached_dev_handle; 1858 u8 attached_phy_identifier; 1859 u8 reserved0f; 1860 __le32 attached_phy_info; 1861 u8 programmed_link_rate; 1862 u8 hw_link_rate; 1863 u8 change_count; 1864 u8 flags; 1865 __le32 phy_info; 1866 u8 negotiated_link_rate; 1867 u8 reserved1d[3]; 1868 __le16 slot; 1869 __le16 slot_index; 1870 }; 1871 1872 #define MPI3_SASPHY0_PAGEVERSION (0x00) 1873 #define MPI3_SASPHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 1874 struct mpi3_sas_phy_page1 { 1875 struct mpi3_config_page_header header; 1876 __le32 reserved08; 1877 __le32 invalid_dword_count; 1878 __le32 running_disparity_error_count; 1879 __le32 loss_dword_synch_count; 1880 __le32 phy_reset_problem_count; 1881 }; 1882 1883 #define MPI3_SASPHY1_PAGEVERSION (0x00) 1884 struct mpi3_sas_phy2_phy_event { 1885 u8 phy_event_code; 1886 u8 reserved01[3]; 1887 __le32 phy_event_info; 1888 }; 1889 1890 #ifndef MPI3_SAS_PHY2_PHY_EVENT_MAX 1891 #define MPI3_SAS_PHY2_PHY_EVENT_MAX (1) 1892 #endif 1893 struct mpi3_sas_phy_page2 { 1894 struct mpi3_config_page_header header; 1895 __le32 reserved08; 1896 u8 num_phy_events; 1897 u8 reserved0d[3]; 1898 struct mpi3_sas_phy2_phy_event phy_event[MPI3_SAS_PHY2_PHY_EVENT_MAX]; 1899 }; 1900 1901 #define MPI3_SASPHY2_PAGEVERSION (0x00) 1902 struct mpi3_sas_phy3_phy_event_config { 1903 u8 phy_event_code; 1904 u8 reserved01[3]; 1905 u8 counter_type; 1906 u8 threshold_window; 1907 u8 time_units; 1908 u8 reserved07; 1909 __le32 event_threshold; 1910 __le16 threshold_flags; 1911 __le16 reserved0e; 1912 }; 1913 1914 #define MPI3_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 1915 #define MPI3_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 1916 #define MPI3_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 1917 #define MPI3_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 1918 #define MPI3_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 1919 #define MPI3_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 1920 #define MPI3_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 1921 #define MPI3_SASPHY3_EVENT_CODE_INV_SPL_PACKETS (0x07) 1922 #define MPI3_SASPHY3_EVENT_CODE_LOSS_SPL_PACKET_SYNC (0x08) 1923 #define MPI3_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 1924 #define MPI3_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 1925 #define MPI3_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 1926 #define MPI3_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 1927 #define MPI3_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 1928 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 1929 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 1930 #define MPI3_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 1931 #define MPI3_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 1932 #define MPI3_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 1933 #define MPI3_SASPHY3_EVENT_CODE_CONNECTION (0x2a) 1934 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2b) 1935 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2c) 1936 #define MPI3_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2d) 1937 #define MPI3_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2e) 1938 #define MPI3_SASPHY3_EVENT_CODE_PERSIST_CONN (0x2f) 1939 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 1940 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 1941 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 1942 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 1943 #define MPI3_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 1944 #define MPI3_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 1945 #define MPI3_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 1946 #define MPI3_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 1947 #define MPI3_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 1948 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 1949 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 1950 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 1951 #define MPI3_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xd0) 1952 #define MPI3_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xd1) 1953 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP (0xd2) 1954 #define MPI3_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xd3) 1955 #define MPI3_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xd4) 1956 #define MPI3_SASPHY3_EVENT_CODE_LCCONN_TIME (0xd5) 1957 #define MPI3_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xd6) 1958 #define MPI3_SASPHY3_EVENT_CODE_SATA_TX_START (0xd7) 1959 #define MPI3_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xd8) 1960 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xd9) 1961 #define MPI3_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xda) 1962 #define MPI3_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xdb) 1963 #define MPI3_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xdc) 1964 #define MPI3_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 1965 #define MPI3_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 1966 #define MPI3_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 1967 #define MPI3_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 1968 #define MPI3_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 1969 #define MPI3_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 1970 #define MPI3_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 1971 #define MPI3_SASPHY3_TFLAGS_PHY_RESET (0x0002) 1972 #define MPI3_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 1973 #ifndef MPI3_SAS_PHY3_PHY_EVENT_MAX 1974 #define MPI3_SAS_PHY3_PHY_EVENT_MAX (1) 1975 #endif 1976 struct mpi3_sas_phy_page3 { 1977 struct mpi3_config_page_header header; 1978 __le32 reserved08; 1979 u8 num_phy_events; 1980 u8 reserved0d[3]; 1981 struct mpi3_sas_phy3_phy_event_config phy_event_config[MPI3_SAS_PHY3_PHY_EVENT_MAX]; 1982 }; 1983 1984 #define MPI3_SASPHY3_PAGEVERSION (0x00) 1985 struct mpi3_sas_phy_page4 { 1986 struct mpi3_config_page_header header; 1987 u8 reserved08[3]; 1988 u8 flags; 1989 u8 initial_frame[28]; 1990 }; 1991 1992 #define MPI3_SASPHY4_PAGEVERSION (0x00) 1993 #define MPI3_SASPHY4_FLAGS_FRAME_VALID (0x02) 1994 #define MPI3_SASPHY4_FLAGS_SATA_FRAME (0x01) 1995 #define MPI3_PCIE_LINK_RETIMERS_MASK (0x30) 1996 #define MPI3_PCIE_LINK_RETIMERS_SHIFT (4) 1997 #define MPI3_PCIE_NEG_LINK_RATE_MASK (0x0f) 1998 #define MPI3_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 1999 #define MPI3_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 2000 #define MPI3_PCIE_NEG_LINK_RATE_2_5 (0x02) 2001 #define MPI3_PCIE_NEG_LINK_RATE_5_0 (0x03) 2002 #define MPI3_PCIE_NEG_LINK_RATE_8_0 (0x04) 2003 #define MPI3_PCIE_NEG_LINK_RATE_16_0 (0x05) 2004 #define MPI3_PCIE_NEG_LINK_RATE_32_0 (0x06) 2005 #define MPI3_PCIE_ASPM_ENABLE_NONE (0x0) 2006 #define MPI3_PCIE_ASPM_ENABLE_L0S (0x1) 2007 #define MPI3_PCIE_ASPM_ENABLE_L1 (0x2) 2008 #define MPI3_PCIE_ASPM_ENABLE_L0S_L1 (0x3) 2009 #define MPI3_PCIE_ASPM_SUPPORT_NONE (0x0) 2010 #define MPI3_PCIE_ASPM_SUPPORT_L0S (0x1) 2011 #define MPI3_PCIE_ASPM_SUPPORT_L1 (0x2) 2012 #define MPI3_PCIE_ASPM_SUPPORT_L0S_L1 (0x3) 2013 struct mpi3_pcie_io_unit0_phy_data { 2014 u8 link; 2015 u8 link_flags; 2016 u8 phy_flags; 2017 u8 negotiated_link_rate; 2018 __le16 attached_dev_handle; 2019 __le16 controller_dev_handle; 2020 __le32 enumeration_status; 2021 u8 io_unit_port; 2022 u8 reserved0d[3]; 2023 }; 2024 2025 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_MASK (0x10) 2026 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_IOUNIT1 (0x00) 2027 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_BKPLANE (0x10) 2028 #define MPI3_PCIEIOUNIT0_LINKFLAGS_ENUM_IN_PROGRESS (0x08) 2029 #define MPI3_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2030 #define MPI3_PCIEIOUNIT0_PHYFLAGS_HOST_PHY (0x01) 2031 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCH_DEPTH_EXCEEDED (0x80000000) 2032 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 2033 #define MPI3_PCIEIOUNIT0_ES_MAX_ENDPOINTS_EXCEEDED (0x20000000) 2034 #define MPI3_PCIEIOUNIT0_ES_INSUFFICIENT_RESOURCES (0x10000000) 2035 #ifndef MPI3_PCIE_IO_UNIT0_PHY_MAX 2036 #define MPI3_PCIE_IO_UNIT0_PHY_MAX (1) 2037 #endif 2038 struct mpi3_pcie_io_unit_page0 { 2039 struct mpi3_config_page_header header; 2040 __le32 reserved08; 2041 u8 num_phys; 2042 u8 init_status; 2043 u8 aspm; 2044 u8 reserved0f; 2045 struct mpi3_pcie_io_unit0_phy_data phy_data[MPI3_PCIE_IO_UNIT0_PHY_MAX]; 2046 }; 2047 2048 #define MPI3_PCIEIOUNIT0_PAGEVERSION (0x00) 2049 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_ERRORS (0x00) 2050 #define MPI3_PCIEIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01) 2051 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02) 2052 #define MPI3_PCIEIOUNIT0_INITSTATUS_RESOURCE_ALLOC_FAILED (0x03) 2053 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04) 2054 #define MPI3_PCIEIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05) 2055 #define MPI3_PCIEIOUNIT0_INITSTATUS_HOST_PORT_MISMATCH (0x06) 2056 #define MPI3_PCIEIOUNIT0_INITSTATUS_PHYS_NOT_CONSECUTIVE (0x07) 2057 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_CLOCKING_MODE (0x08) 2058 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_START (0xf0) 2059 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_END (0xff) 2060 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_MASK (0xc0) 2061 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_SHIFT (6) 2062 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_MASK (0x30) 2063 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_SHIFT (4) 2064 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_MASK (0x0c) 2065 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_SHIFT (2) 2066 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_MASK (0x03) 2067 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_SHIFT (0) 2068 struct mpi3_pcie_io_unit1_phy_data { 2069 u8 link; 2070 u8 link_flags; 2071 u8 phy_flags; 2072 u8 max_min_link_rate; 2073 __le32 reserved04; 2074 __le32 reserved08; 2075 }; 2076 2077 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_MASK (0x03) 2078 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK (0x00) 2079 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS (0x01) 2080 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS (0x02) 2081 #define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2082 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK (0xf0) 2083 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT (4) 2084 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5 (0x20) 2085 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0 (0x30) 2086 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0 (0x40) 2087 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0 (0x50) 2088 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0 (0x60) 2089 #ifndef MPI3_PCIE_IO_UNIT1_PHY_MAX 2090 #define MPI3_PCIE_IO_UNIT1_PHY_MAX (1) 2091 #endif 2092 struct mpi3_pcie_io_unit_page1 { 2093 struct mpi3_config_page_header header; 2094 __le32 control_flags; 2095 __le32 reserved0c; 2096 u8 num_phys; 2097 u8 reserved11; 2098 u8 aspm; 2099 u8 reserved13; 2100 struct mpi3_pcie_io_unit1_phy_data phy_data[MPI3_PCIE_IO_UNIT1_PHY_MAX]; 2101 }; 2102 2103 #define MPI3_PCIEIOUNIT1_PAGEVERSION (0x00) 2104 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_MASK (0xe0000000) 2105 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_NONE (0x00000000) 2106 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_DEASSERT (0x20000000) 2107 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_ASSERT (0x40000000) 2108 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_BACKPLANE_ERROR (0x60000000) 2109 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_MASK (0x1c000000) 2110 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_NONE (0x00000000) 2111 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_DEASSERT (0x04000000) 2112 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_ASSERT (0x08000000) 2113 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_BACKPLANE_ERROR (0x0c000000) 2114 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE (0x00000080) 2115 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE (0x00000040) 2116 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK (0x00000030) 2117 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SHIFT (4) 2118 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED (0x00000000) 2119 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED (0x00000010) 2120 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED (0x00000020) 2121 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK (0x0000000f) 2122 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_USE_BACKPLANE (0x00000000) 2123 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5 (0x00000002) 2124 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0 (0x00000003) 2125 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0 (0x00000004) 2126 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0 (0x00000005) 2127 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0 (0x00000006) 2128 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_MASK (0x0c) 2129 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_SHIFT (2) 2130 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_MASK (0x03) 2131 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_SHIFT (0) 2132 struct mpi3_pcie_io_unit_page2 { 2133 struct mpi3_config_page_header header; 2134 __le16 nvme_max_q_dx1; 2135 __le16 nvme_max_q_dx2; 2136 u8 nvme_abort_to; 2137 u8 reserved0d; 2138 __le16 nvme_max_q_dx4; 2139 }; 2140 2141 #define MPI3_PCIEIOUNIT2_PAGEVERSION (0x00) 2142 #define MPI3_PCIEIOUNIT3_ERROR_RECEIVER_ERROR (0) 2143 #define MPI3_PCIEIOUNIT3_ERROR_RECOVERY (1) 2144 #define MPI3_PCIEIOUNIT3_ERROR_CORRECTABLE_ERROR_MSG (2) 2145 #define MPI3_PCIEIOUNIT3_ERROR_BAD_DLLP (3) 2146 #define MPI3_PCIEIOUNIT3_ERROR_BAD_TLP (4) 2147 #define MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX (5) 2148 struct mpi3_pcie_io_unit3_error { 2149 __le16 threshold_count; 2150 __le16 reserved02; 2151 }; 2152 2153 struct mpi3_pcie_io_unit_page3 { 2154 struct mpi3_config_page_header header; 2155 u8 threshold_window; 2156 u8 threshold_action; 2157 u8 escalation_count; 2158 u8 escalation_action; 2159 u8 num_errors; 2160 u8 reserved0d[3]; 2161 struct mpi3_pcie_io_unit3_error error[MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX]; 2162 }; 2163 2164 #define MPI3_PCIEIOUNIT3_PAGEVERSION (0x00) 2165 #define MPI3_PCIEIOUNIT3_ACTION_NO_ACTION (0x00) 2166 #define MPI3_PCIEIOUNIT3_ACTION_HOT_RESET (0x01) 2167 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_ONLY (0x02) 2168 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_NO_ACCESS (0x03) 2169 struct mpi3_pcie_switch_page0 { 2170 struct mpi3_config_page_header header; 2171 u8 io_unit_port; 2172 u8 switch_status; 2173 u8 reserved0a[2]; 2174 __le16 dev_handle; 2175 __le16 parent_dev_handle; 2176 u8 num_ports; 2177 u8 pcie_level; 2178 __le16 reserved12; 2179 __le32 reserved14; 2180 __le32 reserved18; 2181 __le32 reserved1c; 2182 }; 2183 2184 #define MPI3_PCIESWITCH0_PAGEVERSION (0x00) 2185 #define MPI3_PCIESWITCH0_SS_NOT_RESPONDING (0x02) 2186 #define MPI3_PCIESWITCH0_SS_RESPONDING (0x03) 2187 #define MPI3_PCIESWITCH0_SS_DELAY_NOT_RESPONDING (0x04) 2188 struct mpi3_pcie_switch_page1 { 2189 struct mpi3_config_page_header header; 2190 u8 io_unit_port; 2191 u8 flags; 2192 __le16 reserved0a; 2193 u8 num_ports; 2194 u8 port_num; 2195 __le16 attached_dev_handle; 2196 __le16 switch_dev_handle; 2197 u8 negotiated_port_width; 2198 u8 negotiated_link_rate; 2199 __le16 slot; 2200 __le16 slot_index; 2201 __le32 reserved18; 2202 }; 2203 2204 #define MPI3_PCIESWITCH1_PAGEVERSION (0x00) 2205 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_MASK (0x0c) 2206 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_SHIFT (2) 2207 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_MASK (0x03) 2208 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_SHIFT (0) 2209 #ifndef MPI3_PCIESWITCH2_MAX_NUM_PORTS 2210 #define MPI3_PCIESWITCH2_MAX_NUM_PORTS (1) 2211 #endif 2212 struct mpi3_pcieswitch2_port_element { 2213 __le16 link_change_count; 2214 __le16 rate_change_count; 2215 __le32 reserved04; 2216 }; 2217 2218 struct mpi3_pcie_switch_page2 { 2219 struct mpi3_config_page_header header; 2220 u8 num_ports; 2221 u8 reserved09; 2222 __le16 dev_handle; 2223 __le32 reserved0c; 2224 struct mpi3_pcieswitch2_port_element port[MPI3_PCIESWITCH2_MAX_NUM_PORTS]; 2225 }; 2226 2227 #define MPI3_PCIESWITCH2_PAGEVERSION (0x00) 2228 struct mpi3_pcie_link_page0 { 2229 struct mpi3_config_page_header header; 2230 u8 link; 2231 u8 reserved09[3]; 2232 __le32 reserved0c; 2233 __le32 receiver_error_count; 2234 __le32 recovery_count; 2235 __le32 corr_error_msg_count; 2236 __le32 non_fatal_error_msg_count; 2237 __le32 fatal_error_msg_count; 2238 __le32 non_fatal_error_count; 2239 __le32 fatal_error_count; 2240 __le32 bad_dllp_count; 2241 __le32 bad_tlp_count; 2242 }; 2243 2244 #define MPI3_PCIELINK0_PAGEVERSION (0x00) 2245 struct mpi3_enclosure_page0 { 2246 struct mpi3_config_page_header header; 2247 __le64 enclosure_logical_id; 2248 __le16 flags; 2249 __le16 enclosure_handle; 2250 __le16 num_slots; 2251 __le16 reserved16; 2252 u8 io_unit_port; 2253 u8 enclosure_level; 2254 __le16 sep_dev_handle; 2255 u8 chassis_slot; 2256 u8 reserved1d[3]; 2257 }; 2258 2259 #define MPI3_ENCLOSURE0_PAGEVERSION (0x00) 2260 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_MASK (0xc000) 2261 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL (0x0000) 2262 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS (0x4000) 2263 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE (0x8000) 2264 #define MPI3_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 2265 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK (0x0010) 2266 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND (0x0000) 2267 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT (0x0010) 2268 #define MPI3_ENCLS0_FLAGS_MNG_MASK (0x000f) 2269 #define MPI3_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 2270 #define MPI3_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 2271 #define MPI3_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0002) 2272 #define MPI3_DEVICE_DEVFORM_SAS_SATA (0x00) 2273 #define MPI3_DEVICE_DEVFORM_PCIE (0x01) 2274 #define MPI3_DEVICE_DEVFORM_VD (0x02) 2275 struct mpi3_device0_sas_sata_format { 2276 __le64 sas_address; 2277 __le16 flags; 2278 __le16 device_info; 2279 u8 phy_num; 2280 u8 attached_phy_identifier; 2281 u8 max_port_connections; 2282 u8 zone_group; 2283 }; 2284 2285 #define MPI3_DEVICE0_SASSATA_FLAGS_WRITE_SAME_UNMAP_NCQ (0x0400) 2286 #define MPI3_DEVICE0_SASSATA_FLAGS_SLUMBER_CAP (0x0200) 2287 #define MPI3_DEVICE0_SASSATA_FLAGS_PARTIAL_CAP (0x0100) 2288 #define MPI3_DEVICE0_SASSATA_FLAGS_ASYNC_NOTIFY (0x0080) 2289 #define MPI3_DEVICE0_SASSATA_FLAGS_SW_PRESERVE (0x0040) 2290 #define MPI3_DEVICE0_SASSATA_FLAGS_UNSUPP_DEV (0x0020) 2291 #define MPI3_DEVICE0_SASSATA_FLAGS_48BIT_LBA (0x0010) 2292 #define MPI3_DEVICE0_SASSATA_FLAGS_SMART_SUPP (0x0008) 2293 #define MPI3_DEVICE0_SASSATA_FLAGS_NCQ_SUPP (0x0004) 2294 #define MPI3_DEVICE0_SASSATA_FLAGS_FUA_SUPP (0x0002) 2295 #define MPI3_DEVICE0_SASSATA_FLAGS_PERSIST_CAP (0x0001) 2296 struct mpi3_device0_pcie_format { 2297 u8 supported_link_rates; 2298 u8 max_port_width; 2299 u8 negotiated_port_width; 2300 u8 negotiated_link_rate; 2301 u8 port_num; 2302 u8 controller_reset_to; 2303 __le16 device_info; 2304 __le32 maximum_data_transfer_size; 2305 __le32 capabilities; 2306 __le16 noiob; 2307 u8 nvme_abort_to; 2308 u8 page_size; 2309 __le16 shutdown_latency; 2310 u8 recovery_info; 2311 u8 reserved17; 2312 }; 2313 2314 #define MPI3_DEVICE0_PCIE_LINK_RATE_32_0_SUPP (0x10) 2315 #define MPI3_DEVICE0_PCIE_LINK_RATE_16_0_SUPP (0x08) 2316 #define MPI3_DEVICE0_PCIE_LINK_RATE_8_0_SUPP (0x04) 2317 #define MPI3_DEVICE0_PCIE_LINK_RATE_5_0_SUPP (0x02) 2318 #define MPI3_DEVICE0_PCIE_LINK_RATE_2_5_SUPP (0x01) 2319 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK (0x0007) 2320 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE (0x0000) 2321 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE (0x0001) 2322 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE (0x0002) 2323 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE (0x0003) 2324 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_MASK (0x0030) 2325 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_SHIFT (4) 2326 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_MASK (0x00c0) 2327 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_SHIFT (6) 2328 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_0 (0x0000) 2329 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_1 (0x0040) 2330 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_2 (0x0080) 2331 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_3 (0x00c0) 2332 #define MPI3_DEVICE0_PCIE_CAP_SGL_EXTRA_LENGTH_SUPPORTED (0x00000020) 2333 #define MPI3_DEVICE0_PCIE_CAP_METADATA_SEPARATED (0x00000010) 2334 #define MPI3_DEVICE0_PCIE_CAP_SGL_DWORD_ALIGN_REQUIRED (0x00000008) 2335 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_SGL (0x00000004) 2336 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_PRP (0x00000000) 2337 #define MPI3_DEVICE0_PCIE_CAP_BIT_BUCKET_SGL_SUPP (0x00000002) 2338 #define MPI3_DEVICE0_PCIE_CAP_SGL_SUPP (0x00000001) 2339 #define MPI3_DEVICE0_PCIE_CAP_ASPM_MASK (0x000000c0) 2340 #define MPI3_DEVICE0_PCIE_CAP_ASPM_SHIFT (6) 2341 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_MASK (0xe0) 2342 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_NS_MGMT (0x00) 2343 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_FORMAT (0x20) 2344 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_MASK (0x1f) 2345 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NS (0x00) 2346 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NSID_1 (0x01) 2347 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_TOO_MANY_NS (0x02) 2348 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_PROTECTION (0x03) 2349 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_METADATA_SZ (0x04) 2350 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_LBA_DATA_SZ (0x05) 2351 struct mpi3_device0_vd_format { 2352 u8 vd_state; 2353 u8 raid_level; 2354 __le16 device_info; 2355 __le16 flags; 2356 __le16 io_throttle_group; 2357 __le16 io_throttle_group_low; 2358 __le16 io_throttle_group_high; 2359 __le32 reserved0c; 2360 }; 2361 #define MPI3_DEVICE0_VD_STATE_OFFLINE (0x00) 2362 #define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED (0x01) 2363 #define MPI3_DEVICE0_VD_STATE_DEGRADED (0x02) 2364 #define MPI3_DEVICE0_VD_STATE_OPTIMAL (0x03) 2365 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_0 (0) 2366 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_1 (1) 2367 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_5 (5) 2368 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_6 (6) 2369 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_10 (10) 2370 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_50 (50) 2371 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_60 (60) 2372 #define MPI3_DEVICE0_VD_DEVICE_INFO_HDD (0x0010) 2373 #define MPI3_DEVICE0_VD_DEVICE_INFO_SSD (0x0008) 2374 #define MPI3_DEVICE0_VD_DEVICE_INFO_NVME (0x0004) 2375 #define MPI3_DEVICE0_VD_DEVICE_INFO_SATA (0x0002) 2376 #define MPI3_DEVICE0_VD_DEVICE_INFO_SAS (0x0001) 2377 #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_MASK (0xf000) 2378 #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_SHIFT (12) 2379 #define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_MASK (0x0003) 2380 #define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_HDD (0x0000) 2381 #define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_SSD (0x0001) 2382 #define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_NO_GUIDANCE (0x0002) 2383 union mpi3_device0_dev_spec_format { 2384 struct mpi3_device0_sas_sata_format sas_sata_format; 2385 struct mpi3_device0_pcie_format pcie_format; 2386 struct mpi3_device0_vd_format vd_format; 2387 }; 2388 2389 struct mpi3_device_page0 { 2390 struct mpi3_config_page_header header; 2391 __le16 dev_handle; 2392 __le16 parent_dev_handle; 2393 __le16 slot; 2394 __le16 enclosure_handle; 2395 __le64 wwid; 2396 __le16 persistent_id; 2397 u8 io_unit_port; 2398 u8 access_status; 2399 __le16 flags; 2400 __le16 reserved1e; 2401 __le16 slot_index; 2402 __le16 queue_depth; 2403 u8 reserved24[3]; 2404 u8 device_form; 2405 union mpi3_device0_dev_spec_format device_specific; 2406 }; 2407 2408 #define MPI3_DEVICE0_PAGEVERSION (0x00) 2409 #define MPI3_DEVICE0_PARENT_INVALID (0xffff) 2410 #define MPI3_DEVICE0_ENCLOSURE_HANDLE_NO_ENCLOSURE (0x0000) 2411 #define MPI3_DEVICE0_WWID_INVALID (0xffffffffffffffff) 2412 #define MPI3_DEVICE0_PERSISTENTID_INVALID (0xffff) 2413 #define MPI3_DEVICE0_IOUNITPORT_INVALID (0xff) 2414 #define MPI3_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2415 #define MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION (0x01) 2416 #define MPI3_DEVICE0_ASTATUS_CAP_UNSUPPORTED (0x02) 2417 #define MPI3_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x03) 2418 #define MPI3_DEVICE0_ASTATUS_UNAUTHORIZED (0x04) 2419 #define MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY (0x05) 2420 #define MPI3_DEVICE0_ASTATUS_PREPARE (0x06) 2421 #define MPI3_DEVICE0_ASTATUS_SAFE_MODE (0x07) 2422 #define MPI3_DEVICE0_ASTATUS_GENERIC_MAX (0x0f) 2423 #define MPI3_DEVICE0_ASTATUS_SAS_UNKNOWN (0x10) 2424 #define MPI3_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x11) 2425 #define MPI3_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x12) 2426 #define MPI3_DEVICE0_ASTATUS_SAS_MAX (0x1f) 2427 #define MPI3_DEVICE0_ASTATUS_SIF_UNKNOWN (0x20) 2428 #define MPI3_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x21) 2429 #define MPI3_DEVICE0_ASTATUS_SIF_DIAG (0x22) 2430 #define MPI3_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x23) 2431 #define MPI3_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x24) 2432 #define MPI3_DEVICE0_ASTATUS_SIF_PIO_SN (0x25) 2433 #define MPI3_DEVICE0_ASTATUS_SIF_MDMA_SN (0x26) 2434 #define MPI3_DEVICE0_ASTATUS_SIF_UDMA_SN (0x27) 2435 #define MPI3_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x28) 2436 #define MPI3_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x29) 2437 #define MPI3_DEVICE0_ASTATUS_SIF_MAX (0x2f) 2438 #define MPI3_DEVICE0_ASTATUS_PCIE_UNKNOWN (0x30) 2439 #define MPI3_DEVICE0_ASTATUS_PCIE_MEM_SPACE_ACCESS (0x31) 2440 #define MPI3_DEVICE0_ASTATUS_PCIE_UNSUPPORTED (0x32) 2441 #define MPI3_DEVICE0_ASTATUS_PCIE_MSIX_REQUIRED (0x33) 2442 #define MPI3_DEVICE0_ASTATUS_PCIE_ECRC_REQUIRED (0x34) 2443 #define MPI3_DEVICE0_ASTATUS_PCIE_MAX (0x3f) 2444 #define MPI3_DEVICE0_ASTATUS_NVME_UNKNOWN (0x40) 2445 #define MPI3_DEVICE0_ASTATUS_NVME_READY_TIMEOUT (0x41) 2446 #define MPI3_DEVICE0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x42) 2447 #define MPI3_DEVICE0_ASTATUS_NVME_IDENTIFY_FAILED (0x43) 2448 #define MPI3_DEVICE0_ASTATUS_NVME_QCONFIG_FAILED (0x44) 2449 #define MPI3_DEVICE0_ASTATUS_NVME_QCREATION_FAILED (0x45) 2450 #define MPI3_DEVICE0_ASTATUS_NVME_EVENTCFG_FAILED (0x46) 2451 #define MPI3_DEVICE0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x47) 2452 #define MPI3_DEVICE0_ASTATUS_NVME_IDLE_TIMEOUT (0x48) 2453 #define MPI3_DEVICE0_ASTATUS_NVME_CTRL_FAILURE_STATUS (0x49) 2454 #define MPI3_DEVICE0_ASTATUS_NVME_INSUFFICIENT_POWER (0x4a) 2455 #define MPI3_DEVICE0_ASTATUS_NVME_DOORBELL_STRIDE (0x4b) 2456 #define MPI3_DEVICE0_ASTATUS_NVME_MEM_PAGE_MIN_SIZE (0x4c) 2457 #define MPI3_DEVICE0_ASTATUS_NVME_MEMORY_ALLOCATION (0x4d) 2458 #define MPI3_DEVICE0_ASTATUS_NVME_COMPLETION_TIME (0x4e) 2459 #define MPI3_DEVICE0_ASTATUS_NVME_BAR (0x4f) 2460 #define MPI3_DEVICE0_ASTATUS_NVME_NS_DESCRIPTOR (0x50) 2461 #define MPI3_DEVICE0_ASTATUS_NVME_INCOMPATIBLE_SETTINGS (0x51) 2462 #define MPI3_DEVICE0_ASTATUS_NVME_TOO_MANY_ERRORS (0x52) 2463 #define MPI3_DEVICE0_ASTATUS_NVME_MAX (0x5f) 2464 #define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN (0x80) 2465 #define MPI3_DEVICE0_ASTATUS_VD_MAX (0x8f) 2466 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_MASK (0xe000) 2467 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_NO_LIMIT (0x0000) 2468 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_256_LB (0x2000) 2469 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_2048_LB (0x4000) 2470 #define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE (0x0080) 2471 #define MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED (0x0010) 2472 #define MPI3_DEVICE0_FLAGS_HIDDEN (0x0008) 2473 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_VIRTUAL (0x0004) 2474 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_DIR_ATTACHED (0x0002) 2475 #define MPI3_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2476 #define MPI3_DEVICE0_QUEUE_DEPTH_NOT_APPLICABLE (0x0000) 2477 struct mpi3_device1_sas_sata_format { 2478 __le32 reserved00; 2479 }; 2480 struct mpi3_device1_pcie_format { 2481 __le16 vendor_id; 2482 __le16 device_id; 2483 __le16 subsystem_vendor_id; 2484 __le16 subsystem_id; 2485 __le32 reserved08; 2486 u8 revision_id; 2487 u8 reserved0d; 2488 __le16 pci_parameters; 2489 }; 2490 2491 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_128B (0x0) 2492 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_256B (0x1) 2493 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_512B (0x2) 2494 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_1024B (0x3) 2495 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_2048B (0x4) 2496 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_4096B (0x5) 2497 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_MASK (0x01c0) 2498 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_SHIFT (6) 2499 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_MASK (0x0038) 2500 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_SHIFT (3) 2501 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_MASK (0x0007) 2502 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_SHIFT (0) 2503 struct mpi3_device1_vd_format { 2504 __le32 reserved00; 2505 }; 2506 2507 union mpi3_device1_dev_spec_format { 2508 struct mpi3_device1_sas_sata_format sas_sata_format; 2509 struct mpi3_device1_pcie_format pcie_format; 2510 struct mpi3_device1_vd_format vd_format; 2511 }; 2512 2513 struct mpi3_device_page1 { 2514 struct mpi3_config_page_header header; 2515 __le16 dev_handle; 2516 __le16 reserved0a; 2517 __le16 link_change_count; 2518 __le16 rate_change_count; 2519 __le16 tm_count; 2520 __le16 reserved12; 2521 __le32 reserved14[10]; 2522 u8 reserved3c[3]; 2523 u8 device_form; 2524 union mpi3_device1_dev_spec_format device_specific; 2525 }; 2526 2527 #define MPI3_DEVICE1_PAGEVERSION (0x00) 2528 #define MPI3_DEVICE1_COUNTER_MAX (0xfffe) 2529 #define MPI3_DEVICE1_COUNTER_INVALID (0xffff) 2530 #endif 2531