1 /* 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. 5 * Support: <fbsd-storage-driver.pdl@broadcom.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation and/or other 15 * materials provided with the distribution. 16 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors 17 * may be used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 * 32 * The views and conclusions contained in the software and documentation are 33 * those of the authors and should not be interpreted as representing 34 * official policies,either expressed or implied, of the FreeBSD Project. 35 * 36 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 37 * 38 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD 39 * 40 * 41 * 42 * Version History 43 * --------------- 44 * 45 * Date Version Description 46 * -------- ----------- ------------------------------------------------------ 47 * 11-30-18 03.00.00.08 Corresponds to Fusion-MPT MPI 3.0 Specification Rev H. 48 * 02-08-19 03.00.00.09 Corresponds to Fusion-MPT MPI 3.0 Specification Rev I. 49 * 05-03-19 03.00.00.10 Corresponds to Fusion-MPT MPI 3.0 Specification Rev J. 50 * 08-30-19 03.00.00.12 Corresponds to Fusion-MPT MPI 3.0 Specification Rev L. 51 * 11-01-19 03.00.00.13 Corresponds to Fusion-MPT MPI 3.0 Specification Rev M. 52 * 12-16-19 03.00.00.14 Corresponds to Fusion-MPT MPI 3.0 Specification Rev N. 53 * 02-28-20 03.00.00.15 Corresponds to Fusion-MPT MPI 3.0 Specification Rev O. 54 * 05-01-20 03.00.00.16 Corresponds to Fusion-MPT MPI 3.0 Specification Rev P. 55 * 06-26-20 03.00.00.17 Corresponds to Fusion-MPT MPI 3.0 Specification Rev Q. 56 * 08-28-20 03.00.00.18 Corresponds to Fusion-MPT MPI 3.0 Specification Rev R. 57 * 10-30-20 03.00.00.19 Corresponds to Fusion-MPT MPI 3.0 Specification Rev S. 58 * 12-18-20 03.00.00.20 Corresponds to Fusion-MPT MPI 3.0 Specification Rev T. 59 * 02-09-21 03.00.20.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev T - Interim Release 1. 60 * 02-26-21 03.00.21.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev U. 61 * 04-16-21 03.00.21.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev U - Interim Release 1. 62 * 04-28-21 03.00.21.02 Corresponds to Fusion-MPT MPI 3.0 Specification Rev U - Interim Release 2. 63 * 05-28-21 03.00.22.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev V. 64 * 07-23-21 03.00.22.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev V - Interim Release 1. 65 * 09-03-21 03.00.23.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 23. 66 * 10-23-21 03.00.23.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 23 - Interim Release 1. 67 * 12-03-21 03.00.24.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 24. 68 * 02-25-22 03.00.25.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 25. 69 * 06-03-22 03.00.26.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 26. 70 * 08-09-22 03.00.26.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 26 - Interim Release 1. 71 * 09-02-22 03.00.27.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 27. 72 * 10-20-22 03.00.27.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 27 - Interim Release 1. 73 * 12-02-22 03.00.28.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 28. 74 * 02-24-23 03.00.29.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 29. 75 * 05-19-23 03.00.30.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 30. 76 * 08-18-23 03.00.30.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 30 - Interim Release 1. 77 * 11-17-23 03.00.31.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 31 78 * 02-16-24 03.00.32.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 32 79 * 02-23-24 03.00.32.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 32 - Interim Release 1. 80 * 04-19-24 03.00.32.02 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 32 - Interim Release 2. 81 * 05-10-24 03.00.33.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 33 82 * 06-14-24 03.00.33.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 33 - Interim Release 1. 83 * 07-26-24 03.00.34.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 34 84 * 11-08-24 03.00.35.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 35 85 * 02-14-25 03.00.36.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 36 86 */ 87 88 #ifndef MPI30_TRANSPORT_H 89 #define MPI30_TRANSPORT_H 1 90 91 /***************************************************************************** 92 * Common version structure/union used in * 93 * messages and configuration pages * 94 ****************************************************************************/ 95 96 typedef struct _MPI3_VERSION_STRUCT 97 { 98 U8 Dev; /* 0x00 */ 99 U8 Unit; /* 0x01 */ 100 U8 Minor; /* 0x02 */ 101 U8 Major; /* 0x03 */ 102 } MPI3_VERSION_STRUCT, MPI3_POINTER PTR_MPI3_VERSION_STRUCT, 103 Mpi3VersionStruct_t, MPI3_POINTER pMpi3VersionStruct_t; 104 105 typedef union _MPI3_VERSION_UNION 106 { 107 MPI3_VERSION_STRUCT Struct; 108 U32 Word; 109 } MPI3_VERSION_UNION, MPI3_POINTER PTR_MPI3_VERSION_UNION, 110 Mpi3VersionUnion_t, MPI3_POINTER pMpi3VersionUnion_t; 111 112 /****** Version constants for this revision ****/ 113 #define MPI3_VERSION_MAJOR (3) 114 #define MPI3_VERSION_MINOR (0) 115 #define MPI3_VERSION_UNIT (36) 116 #define MPI3_VERSION_DEV (0) 117 118 /****** DevHandle definitions *****/ 119 #define MPI3_DEVHANDLE_INVALID (0xFFFF) 120 121 /***************************************************************************** 122 * System Interface Register Definitions * 123 ****************************************************************************/ 124 typedef struct _MPI3_SYSIF_OPER_QUEUE_INDEXES 125 { 126 U16 ProducerIndex; /* 0x00 */ 127 U16 Reserved02; /* 0x02 */ 128 U16 ConsumerIndex; /* 0x04 */ 129 U16 Reserved06; /* 0x06 */ 130 } MPI3_SYSIF_OPER_QUEUE_INDEXES, MPI3_POINTER PTR_MPI3_SYSIF_OPER_QUEUE_INDEXES; 131 132 typedef volatile struct _MPI3_SYSIF_REGISTERS 133 { 134 U64 IOCInformation; /* 0x00 */ 135 MPI3_VERSION_UNION Version; /* 0x08 */ 136 U32 Reserved0C[2]; /* 0x0C */ 137 U32 IOCConfiguration; /* 0x14 */ 138 U32 Reserved18; /* 0x18 */ 139 U32 IOCStatus; /* 0x1C */ 140 U32 Reserved20; /* 0x20 */ 141 U32 AdminQueueNumEntries; /* 0x24 */ 142 U64 AdminRequestQueueAddress; /* 0x28 */ 143 U64 AdminReplyQueueAddress; /* 0x30 */ 144 U32 Reserved38[2]; /* 0x38 */ 145 U32 CoalesceControl; /* 0x40 */ 146 U32 Reserved44[1007]; /* 0x44 */ 147 U16 AdminRequestQueuePI; /* 0x1000 */ 148 U16 Reserved1002; /* 0x1002 */ 149 U16 AdminReplyQueueCI; /* 0x1004 */ 150 U16 Reserved1006; /* 0x1006 */ 151 MPI3_SYSIF_OPER_QUEUE_INDEXES OperQueueIndexes[383]; /* 0x1008 */ 152 U32 Reserved1C00; /* 0x1C00 */ 153 U32 WriteSequence; /* 0x1C04 */ 154 U32 HostDiagnostic; /* 0x1C08 */ 155 U32 Reserved1C0C; /* 0x1C0C */ 156 U32 Fault; /* 0x1C10 */ 157 U32 FaultInfo[3]; /* 0x1C14 */ 158 U32 Reserved1C20[4]; /* 0x1C20 */ 159 U64 HCBAddress; /* 0x1C30 */ 160 U32 HCBSize; /* 0x1C38 */ 161 U32 Reserved1C3C; /* 0x1C3C */ 162 U32 ReplyFreeHostIndex; /* 0x1C40 */ 163 U32 SenseBufferFreeHostIndex; /* 0x1C44 */ 164 U32 Reserved1C48[2]; /* 0x1C48 */ 165 U64 DiagRWData; /* 0x1C50 */ 166 U64 DiagRWAddress; /* 0x1C58 */ 167 U16 DiagRWControl; /* 0x1C60 */ 168 U16 DiagRWStatus; /* 0x1C62 */ 169 U32 Reserved1C64[35]; /* 0x1C64 */ 170 U32 Scratchpad[4]; /* 0x1CF0 */ 171 U32 Reserved1D00[192]; /* 0x1D00 */ 172 U32 DeviceAssignedRegisters[2048]; /* 0x2000 */ 173 } MPI3_SYSIF_REGS, MPI3_POINTER PTR_MPI3_SYSIF_REGS, 174 Mpi3SysIfRegs_t, MPI3_POINTER pMpi3SysIfRegs_t; 175 176 /**** Defines for the IOCInformation register ****/ 177 #define MPI3_SYSIF_IOC_INFO_LOW_OFFSET (0x00000000) 178 #define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET (0x00000004) 179 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK (0xFF000000) 180 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT (24) 181 #define MPI3_SYSIF_IOC_INFO_LOW_HCB_DISABLED (0x00000001) 182 183 /**** Defines for the IOCConfiguration register ****/ 184 #define MPI3_SYSIF_IOC_CONFIG_OFFSET (0x00000014) 185 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ (0x00F00000) 186 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT (20) 187 #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ (0x000F0000) 188 #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT (16) 189 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_MASK (0x0000C000) 190 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_SHIFT (14) 191 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NO (0x00000000) 192 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL (0x00004000) 193 #define MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ (0x00002000) 194 #define MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE (0x00000010) 195 #define MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC (0x00000001) 196 197 /**** Defines for the IOCStatus register ****/ 198 #define MPI3_SYSIF_IOC_STATUS_OFFSET (0x0000001C) 199 #define MPI3_SYSIF_IOC_STATUS_RESET_HISTORY (0x00000010) 200 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK (0x0000000C) 201 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_SHIFT (0x00000002) 202 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_NONE (0x00000000) 203 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS (0x00000004) 204 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE (0x00000008) 205 #define MPI3_SYSIF_IOC_STATUS_FAULT (0x00000002) 206 #define MPI3_SYSIF_IOC_STATUS_READY (0x00000001) 207 208 /**** Defines for the AdminQueueNumEntries register ****/ 209 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_OFFSET (0x00000024) 210 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REQ_MASK (0x0FFF) 211 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REQ_SHIFT (0) 212 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_OFFSET (0x00000026) 213 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_MASK (0x0FFF0000) 214 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_SHIFT (16) 215 216 /**** Defines for the AdminRequestQueueAddress register ****/ 217 #define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_LOW_OFFSET (0x00000028) 218 #define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_HIGH_OFFSET (0x0000002C) 219 220 /**** Defines for the AdminReplyQueueAddress register ****/ 221 #define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_LOW_OFFSET (0x00000030) 222 #define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_HIGH_OFFSET (0x00000034) 223 224 /**** Defines for the CoalesceControl register ****/ 225 #define MPI3_SYSIF_COALESCE_CONTROL_OFFSET (0x00000040) 226 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_MASK (0xC0000000) 227 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_SHIFT (30) 228 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_NO_CHANGE (0x00000000) 229 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_DISABLE (0x40000000) 230 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_ENABLE (0xC0000000) 231 #define MPI3_SYSIF_COALESCE_CONTROL_VALID (0x20000000) 232 #define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_MASK (0x01FF0000) 233 #define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_SHIFT (16) 234 #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_MASK (0x0000FF00) 235 #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_SHIFT (8) 236 #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_MASK (0x000000FF) 237 #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_SHIFT (0) 238 239 /**** Defines for the AdminRequestQueuePI register ****/ 240 #define MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET (0x00001000) 241 242 /**** Defines for the AdminReplyQueueCI register ****/ 243 #define MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET (0x00001004) 244 245 /**** Defines for the OperationalRequestQueuePI register */ 246 #define MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET (0x00001008) 247 #define MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(N) (MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET + (((N)-1)*8)) /* N = 1, 2, 3, ..., 255 */ 248 249 /**** Defines for the OperationalReplyQueueCI register */ 250 #define MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET (0x0000100C) 251 #define MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(N) (MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET + (((N)-1)*8)) /* N = 1, 2, 3, ..., 255 */ 252 253 /**** Defines for the WriteSequence register *****/ 254 #define MPI3_SYSIF_WRITE_SEQUENCE_OFFSET (0x00001C04) 255 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_MASK (0x0000000F) 256 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_SHIFT (0) 257 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH (0x0) 258 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST (0xF) 259 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND (0x4) 260 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD (0xB) 261 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH (0x2) 262 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH (0x7) 263 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH (0xD) 264 265 /**** Defines for the HostDiagnostic register *****/ 266 #define MPI3_SYSIF_HOST_DIAG_OFFSET (0x00001C08) 267 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_MASK (0x00000700) 268 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SHIFT (8) 269 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_NO_RESET (0x00000000) 270 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET (0x00000100) 271 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_HOST_CONTROL_BOOT_RESET (0x00000200) 272 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_COMPLETE_RESET (0x00000300) 273 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT (0x00000700) 274 #define MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS (0x00000080) 275 #define MPI3_SYSIF_HOST_DIAG_SECURE_BOOT (0x00000040) 276 #define MPI3_SYSIF_HOST_DIAG_CLEAR_INVALID_FW_IMAGE (0x00000020) 277 #define MPI3_SYSIF_HOST_DIAG_INVALID_FW_IMAGE (0x00000010) 278 #define MPI3_SYSIF_HOST_DIAG_HCBENABLE (0x00000008) 279 #define MPI3_SYSIF_HOST_DIAG_HCBMODE (0x00000004) 280 #define MPI3_SYSIF_HOST_DIAG_DIAG_RW_ENABLE (0x00000002) 281 #define MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE (0x00000001) 282 283 /**** Defines for the Fault register ****/ 284 #define MPI3_SYSIF_FAULT_OFFSET (0x00001C10) 285 #define MPI3_SYSIF_FAULT_CODE_MASK (0x0000FFFF) 286 #define MPI3_SYSIF_FAULT_CODE_SHIFT (0) 287 #define MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET (0x0000F000) 288 #define MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET (0x0000F001) 289 #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS (0x0000F002) 290 #define MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED (0x0000F003) 291 #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_NEEDED (0x0000F004) 292 #define MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED (0x0000F005) 293 #define MPI3_SYSIF_FAULT_CODE_TEMP_THRESHOLD_EXCEEDED (0x0000F006) 294 #define MPI3_SYSIF_FAULT_CODE_INSUFFICIENT_PCI_SLOT_POWER (0x0000F007) 295 296 /**** Defines for FaultCodeAdditionalInfo registers ****/ 297 #define MPI3_SYSIF_FAULT_INFO0_OFFSET (0x00001C14) 298 #define MPI3_SYSIF_FAULT_INFO1_OFFSET (0x00001C18) 299 #define MPI3_SYSIF_FAULT_INFO2_OFFSET (0x00001C1C) 300 301 /**** Defines for HCBAddress register ****/ 302 #define MPI3_SYSIF_HCB_ADDRESS_LOW_OFFSET (0x00001C30) 303 #define MPI3_SYSIF_HCB_ADDRESS_HIGH_OFFSET (0x00001C34) 304 305 /**** Defines for HCBSize register ****/ 306 #define MPI3_SYSIF_HCB_SIZE_OFFSET (0x00001C38) 307 #define MPI3_SYSIF_HCB_SIZE_SIZE_MASK (0xFFFFF000) 308 #define MPI3_SYSIF_HCB_SIZE_SIZE_SHIFT (12) 309 #define MPI3_SYSIF_HCB_SIZE_HCDW_ENABLE (0x00000001) 310 311 /**** Defines for ReplyFreeHostIndex register ****/ 312 #define MPI3_SYSIF_REPLY_FREE_HOST_INDEX_OFFSET (0x00001C40) 313 314 /**** Defines for SenseBufferFreeHostIndex register ****/ 315 #define MPI3_SYSIF_SENSE_BUF_FREE_HOST_INDEX_OFFSET (0x00001C44) 316 317 /**** Defines for DiagRWData register ****/ 318 #define MPI3_SYSIF_DIAG_RW_DATA_LOW_OFFSET (0x00001C50) 319 #define MPI3_SYSIF_DIAG_RW_DATA_HIGH_OFFSET (0x00001C54) 320 321 /**** Defines for DiagRWAddress ****/ 322 #define MPI3_SYSIF_DIAG_RW_ADDRESS_LOW_OFFSET (0x00001C58) 323 #define MPI3_SYSIF_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00001C5C) 324 325 /**** Defines for DiagRWControl register ****/ 326 #define MPI3_SYSIF_DIAG_RW_CONTROL_OFFSET (0x00001C60) 327 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_MASK (0x00000030) 328 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_SHIFT (4) 329 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_1BYTE (0x00000000) 330 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_2BYTES (0x00000010) 331 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_4BYTES (0x00000020) 332 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_8BYTES (0x00000030) 333 #define MPI3_SYSIF_DIAG_RW_CONTROL_RESET (0x00000004) 334 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_MASK (0x00000002) 335 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_SHIFT (1) 336 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_READ (0x00000000) 337 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_WRITE (0x00000002) 338 #define MPI3_SYSIF_DIAG_RW_CONTROL_START (0x00000001) 339 340 /**** Defines for DiagRWStatus register ****/ 341 #define MPI3_SYSIF_DIAG_RW_STATUS_OFFSET (0x00001C62) 342 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_MASK (0x0000000E) 343 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_SHIFT (1) 344 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_SUCCESS (0x00000000) 345 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_INV_ADDR (0x00000002) 346 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_ACC_ERR (0x00000004) 347 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_PAR_ERR (0x00000006) 348 #define MPI3_SYSIF_DIAG_RW_STATUS_BUSY (0x00000001) 349 350 /**** Defines for Scratchpad registers ****/ 351 #define MPI3_SYSIF_SCRATCHPAD0_OFFSET (0x00001CF0) 352 #define MPI3_SYSIF_SCRATCHPAD1_OFFSET (0x00001CF4) 353 #define MPI3_SYSIF_SCRATCHPAD2_OFFSET (0x00001CF8) 354 #define MPI3_SYSIF_SCRATCHPAD3_OFFSET (0x00001CFC) 355 356 /**** Defines for Device Assigned registers ****/ 357 #define MPI3_SYSIF_DEVICE_ASSIGNED_REGS_OFFSET (0x00002000) 358 359 /**** Default Defines for Diag Save Timeout ****/ 360 #define MPI3_SYSIF_DIAG_SAVE_TIMEOUT (60) /* seconds */ 361 362 /***************************************************************************** 363 * Reply Descriptors * 364 ****************************************************************************/ 365 366 /***************************************************************************** 367 * Default Reply Descriptor * 368 ****************************************************************************/ 369 typedef struct _MPI3_DEFAULT_REPLY_DESCRIPTOR 370 { 371 U32 DescriptorTypeDependent1[2]; /* 0x00 */ 372 U16 RequestQueueCI; /* 0x08 */ 373 U16 RequestQueueID; /* 0x0A */ 374 U16 DescriptorTypeDependent2; /* 0x0C */ 375 U16 ReplyFlags; /* 0x0E */ 376 } MPI3_DEFAULT_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_DEFAULT_REPLY_DESCRIPTOR, 377 Mpi3DefaultReplyDescriptor_t, MPI3_POINTER pMpi3DefaultReplyDescriptor_t; 378 379 /**** Defines for the ReplyFlags field ****/ 380 #define MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK (0x0001) 381 #define MPI3_REPLY_DESCRIPT_FLAGS_PHASE_SHIFT (0) 382 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK (0xF000) 383 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SHIFT (12) 384 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY (0x0000) 385 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS (0x1000) 386 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_TARGET_COMMAND_BUFFER (0x2000) 387 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS (0x3000) 388 389 /**** Defines for the RequestQueueID field ****/ 390 #define MPI3_REPLY_DESCRIPT_REQUEST_QUEUE_ID_INVALID (0xFFFF) 391 392 /***************************************************************************** 393 * Address Reply Descriptor * 394 ****************************************************************************/ 395 typedef struct _MPI3_ADDRESS_REPLY_DESCRIPTOR 396 { 397 U64 ReplyFrameAddress; /* 0x00 */ 398 U16 RequestQueueCI; /* 0x08 */ 399 U16 RequestQueueID; /* 0x0A */ 400 U16 Reserved0C; /* 0x0C */ 401 U16 ReplyFlags; /* 0x0E */ 402 } MPI3_ADDRESS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_ADDRESS_REPLY_DESCRIPTOR, 403 Mpi3AddressReplyDescriptor_t, MPI3_POINTER pMpi3AddressReplyDescriptor_t; 404 405 /***************************************************************************** 406 * Success Reply Descriptor * 407 ****************************************************************************/ 408 typedef struct _MPI3_SUCCESS_REPLY_DESCRIPTOR 409 { 410 U32 Reserved00[2]; /* 0x00 */ 411 U16 RequestQueueCI; /* 0x08 */ 412 U16 RequestQueueID; /* 0x0A */ 413 U16 HostTag; /* 0x0C */ 414 U16 ReplyFlags; /* 0x0E */ 415 } MPI3_SUCCESS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_SUCCESS_REPLY_DESCRIPTOR, 416 Mpi3SuccessReplyDescriptor_t, MPI3_POINTER pMpi3SuccessReplyDescriptor_t; 417 418 /***************************************************************************** 419 * Target Command Buffer Reply Descriptor * 420 ****************************************************************************/ 421 typedef struct _MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 422 { 423 U32 Reserved00; /* 0x00 */ 424 U16 InitiatorDevHandle; /* 0x04 */ 425 U8 PhyNum; /* 0x06 */ 426 U8 Reserved07; /* 0x07 */ 427 U16 RequestQueueCI; /* 0x08 */ 428 U16 RequestQueueID; /* 0x0A */ 429 U16 IOIndex; /* 0x0C */ 430 U16 ReplyFlags; /* 0x0E */ 431 } MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 432 Mpi3TargetCommandBufferReplyDescriptor_t, MPI3_POINTER pMpi3TargetCommandBufferReplyDescriptor_t; 433 434 /**** See Default Reply Descriptor Defines above for definitions in the ReplyFlags field ****/ 435 436 /***************************************************************************** 437 * Status Reply Descriptor * 438 ****************************************************************************/ 439 typedef struct _MPI3_STATUS_REPLY_DESCRIPTOR 440 { 441 U16 IOCStatus; /* 0x00 */ 442 U16 Reserved02; /* 0x02 */ 443 U32 IOCLogInfo; /* 0x04 */ 444 U16 RequestQueueCI; /* 0x08 */ 445 U16 RequestQueueID; /* 0x0A */ 446 U16 HostTag; /* 0x0C */ 447 U16 ReplyFlags; /* 0x0E */ 448 } MPI3_STATUS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_STATUS_REPLY_DESCRIPTOR, 449 Mpi3StatusReplyDescriptor_t, MPI3_POINTER pMpi3StatusReplyDescriptor_t; 450 451 /**** Use MPI3_IOCSTATUS_ defines for the IOCStatus field ****/ 452 453 /**** Use MPI3_IOCLOGINFO_ defines for the IOCLogInfo field ****/ 454 455 /***************************************************************************** 456 * Union of Reply Descriptors * 457 ****************************************************************************/ 458 typedef union _MPI3_REPLY_DESCRIPTORS_UNION 459 { 460 MPI3_DEFAULT_REPLY_DESCRIPTOR Default; 461 MPI3_ADDRESS_REPLY_DESCRIPTOR AddressReply; 462 MPI3_SUCCESS_REPLY_DESCRIPTOR Success; 463 MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 464 MPI3_STATUS_REPLY_DESCRIPTOR Status; 465 U32 Words[4]; 466 } MPI3_REPLY_DESCRIPTORS_UNION, MPI3_POINTER PTR_MPI3_REPLY_DESCRIPTORS_UNION, 467 Mpi3ReplyDescriptorsUnion_t, MPI3_POINTER pMpi3ReplyDescriptorsUnion_t; 468 469 470 /***************************************************************************** 471 * Scatter Gather Elements * 472 ****************************************************************************/ 473 474 /***************************************************************************** 475 * Common structure for Simple, Chain, and Last Chain * 476 * scatter gather elements * 477 ****************************************************************************/ 478 typedef struct _MPI3_SGE_COMMON 479 { 480 U64 Address; /* 0x00 */ 481 U32 Length; /* 0x08 */ 482 U8 Reserved0C[3]; /* 0x0C */ 483 U8 Flags; /* 0x0F */ 484 } MPI3_SGE_SIMPLE, MPI3_POINTER PTR_MPI3_SGE_SIMPLE, 485 Mpi3SGESimple_t, MPI3_POINTER pMpi3SGESimple_t, 486 MPI3_SGE_CHAIN, MPI3_POINTER PTR_MPI3_SGE_CHAIN, 487 Mpi3SGEChain_t, MPI3_POINTER pMpi3SGEChain_t, 488 MPI3_SGE_LAST_CHAIN, MPI3_POINTER PTR_MPI3_SGE_LAST_CHAIN, 489 Mpi3SGELastChain_t, MPI3_POINTER pMpi3SGELastChain_t; 490 491 /***************************************************************************** 492 * Bit Bucket scatter gather element * 493 ****************************************************************************/ 494 typedef struct _MPI3_SGE_BIT_BUCKET 495 { 496 U64 Reserved00; /* 0x00 */ 497 U32 Length; /* 0x08 */ 498 U8 Reserved0C[3]; /* 0x0C */ 499 U8 Flags; /* 0x0F */ 500 } MPI3_SGE_BIT_BUCKET, MPI3_POINTER PTR_MPI3_SGE_BIT_BUCKET, 501 Mpi3SGEBitBucket_t, MPI3_POINTER pMpi3SGEBitBucket_t; 502 503 /***************************************************************************** 504 * Extended EEDP scatter gather element * 505 ****************************************************************************/ 506 typedef struct _MPI3_SGE_EXTENDED_EEDP 507 { 508 U8 UserDataSize; /* 0x00 */ 509 U8 Reserved01; /* 0x01 */ 510 U16 EEDPFlags; /* 0x02 */ 511 U32 SecondaryReferenceTag; /* 0x04 */ 512 U16 SecondaryApplicationTag; /* 0x08 */ 513 U16 ApplicationTagTranslationMask; /* 0x0A */ 514 U16 Reserved0C; /* 0x0C */ 515 U8 ExtendedOperation; /* 0x0E */ 516 U8 Flags; /* 0x0F */ 517 } MPI3_SGE_EXTENDED_EEDP, MPI3_POINTER PTR_MPI3_SGE_EXTENDED_EEDP, 518 Mpi3SGEExtendedEEDP_t, MPI3_POINTER pMpi3SGEExtendedEEDP_t; 519 520 /***************************************************************************** 521 * Union of scatter gather elements * 522 ****************************************************************************/ 523 typedef union _MPI3_SGE_UNION 524 { 525 MPI3_SGE_SIMPLE Simple; 526 MPI3_SGE_CHAIN Chain; 527 MPI3_SGE_LAST_CHAIN LastChain; 528 MPI3_SGE_BIT_BUCKET BitBucket; 529 MPI3_SGE_EXTENDED_EEDP Eedp; 530 U32 Words[4]; 531 } MPI3_SGE_UNION, MPI3_POINTER PTR_MPI3_SGE_UNION, 532 Mpi3SGEUnion_t, MPI3_POINTER pMpi3SGEUnion_t; 533 534 /**** Definitions for the Flags field ****/ 535 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_MASK (0xF0) 536 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_SHIFT (4) 537 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE (0x00) 538 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_BIT_BUCKET (0x10) 539 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_CHAIN (0x20) 540 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_LAST_CHAIN (0x30) 541 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_EXTENDED (0xF0) 542 #define MPI3_SGE_FLAGS_END_OF_LIST (0x08) 543 #define MPI3_SGE_FLAGS_END_OF_BUFFER (0x04) 544 #define MPI3_SGE_FLAGS_DLAS_MASK (0x03) 545 #define MPI3_SGE_FLAGS_DLAS_SHIFT (0) 546 #define MPI3_SGE_FLAGS_DLAS_SYSTEM (0x00) 547 #define MPI3_SGE_FLAGS_DLAS_IOC_UDP (0x01) 548 #define MPI3_SGE_FLAGS_DLAS_IOC_CTL (0x02) 549 550 /**** Definitions for the ExtendedOperation field of Extended element ****/ 551 #define MPI3_SGE_EXT_OPER_EEDP (0x00) 552 553 /**** Definitions for the EEDPFlags field of Extended EEDP element ****/ 554 #define MPI3_EEDPFLAGS_INCR_PRI_REF_TAG (0x8000) 555 #define MPI3_EEDPFLAGS_INCR_SEC_REF_TAG (0x4000) 556 #define MPI3_EEDPFLAGS_INCR_PRI_APP_TAG (0x2000) 557 #define MPI3_EEDPFLAGS_INCR_SEC_APP_TAG (0x1000) 558 #define MPI3_EEDPFLAGS_ESC_PASSTHROUGH (0x0800) 559 #define MPI3_EEDPFLAGS_CHK_REF_TAG (0x0400) 560 #define MPI3_EEDPFLAGS_CHK_APP_TAG (0x0200) 561 #define MPI3_EEDPFLAGS_CHK_GUARD (0x0100) 562 #define MPI3_EEDPFLAGS_ESC_MODE_MASK (0x00C0) 563 #define MPI3_EEDPFLAGS_ESC_MODE_SHIFT (6) 564 #define MPI3_EEDPFLAGS_ESC_MODE_DO_NOT_DISABLE (0x0040) 565 #define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_DISABLE (0x0080) 566 #define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_REFTAG_DISABLE (0x00C0) 567 #define MPI3_EEDPFLAGS_HOST_GUARD_MASK (0x0030) 568 #define MPI3_EEDPFLAGS_HOST_GUARD_SHIFT (4) 569 #define MPI3_EEDPFLAGS_HOST_GUARD_T10_CRC (0x0000) 570 #define MPI3_EEDPFLAGS_HOST_GUARD_IP_CHKSUM (0x0010) 571 #define MPI3_EEDPFLAGS_HOST_GUARD_OEM_SPECIFIC (0x0020) 572 #define MPI3_EEDPFLAGS_PT_REF_TAG (0x0008) 573 #define MPI3_EEDPFLAGS_EEDP_OP_MASK (0x0007) 574 #define MPI3_EEDPFLAGS_EEDP_OP_SHIFT (0) 575 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK (0x0001) 576 #define MPI3_EEDPFLAGS_EEDP_OP_STRIP (0x0002) 577 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REMOVE (0x0003) 578 #define MPI3_EEDPFLAGS_EEDP_OP_INSERT (0x0004) 579 #define MPI3_EEDPFLAGS_EEDP_OP_REPLACE (0x0006) 580 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REGEN (0x0007) 581 582 /**** Definitions for the UserDataSize field of Extended EEDP element ****/ 583 #define MPI3_EEDP_UDS_512 (0x01) 584 #define MPI3_EEDP_UDS_520 (0x02) 585 #define MPI3_EEDP_UDS_4080 (0x03) 586 #define MPI3_EEDP_UDS_4088 (0x04) 587 #define MPI3_EEDP_UDS_4096 (0x05) 588 #define MPI3_EEDP_UDS_4104 (0x06) 589 #define MPI3_EEDP_UDS_4160 (0x07) 590 591 /***************************************************************************** 592 * Standard Message Structures * 593 ****************************************************************************/ 594 595 /***************************************************************************** 596 * Request Message Header for all request messages * 597 ****************************************************************************/ 598 typedef struct _MPI3_REQUEST_HEADER 599 { 600 U16 HostTag; /* 0x00 */ 601 U8 IOCUseOnly02; /* 0x02 */ 602 U8 Function; /* 0x03 */ 603 U16 IOCUseOnly04; /* 0x04 */ 604 U8 IOCUseOnly06; /* 0x06 */ 605 U8 MsgFlags; /* 0x07 */ 606 U16 ChangeCount; /* 0x08 */ 607 U16 FunctionDependent; /* 0x0A */ 608 } MPI3_REQUEST_HEADER, MPI3_POINTER PTR_MPI3_REQUEST_HEADER, 609 Mpi3RequestHeader_t, MPI3_POINTER pMpi3RequestHeader_t; 610 611 /***************************************************************************** 612 * Default Reply * 613 ****************************************************************************/ 614 typedef struct _MPI3_DEFAULT_REPLY 615 { 616 U16 HostTag; /* 0x00 */ 617 U8 IOCUseOnly02; /* 0x02 */ 618 U8 Function; /* 0x03 */ 619 U16 IOCUseOnly04; /* 0x04 */ 620 U8 IOCUseOnly06; /* 0x06 */ 621 U8 MsgFlags; /* 0x07 */ 622 U16 IOCUseOnly08; /* 0x08 */ 623 U16 IOCStatus; /* 0x0A */ 624 U32 IOCLogInfo; /* 0x0C */ 625 } MPI3_DEFAULT_REPLY, MPI3_POINTER PTR_MPI3_DEFAULT_REPLY, 626 Mpi3DefaultReply_t, MPI3_POINTER pMpi3DefaultReply_t; 627 628 /**** Defines for the HostTag field ****/ 629 #define MPI3_HOST_TAG_INVALID (0xFFFF) 630 631 /**** Defines for message Function ****/ 632 /* I/O Controller functions */ 633 #define MPI3_FUNCTION_IOC_FACTS (0x01) /* IOC Facts */ 634 #define MPI3_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 635 #define MPI3_FUNCTION_PORT_ENABLE (0x03) /* Port Enable */ 636 #define MPI3_FUNCTION_EVENT_NOTIFICATION (0x04) /* Event Notification */ 637 #define MPI3_FUNCTION_EVENT_ACK (0x05) /* Event Acknowledge */ 638 #define MPI3_FUNCTION_CI_DOWNLOAD (0x06) /* Component Image Download */ 639 #define MPI3_FUNCTION_CI_UPLOAD (0x07) /* Component Image Upload */ 640 #define MPI3_FUNCTION_IO_UNIT_CONTROL (0x08) /* IO Unit Control */ 641 #define MPI3_FUNCTION_PERSISTENT_EVENT_LOG (0x09) /* Persistent Event Log */ 642 #define MPI3_FUNCTION_MGMT_PASSTHROUGH (0x0A) /* Management Passthrough */ 643 #define MPI3_FUNCTION_CONFIG (0x10) /* Configuration */ 644 645 /* SCSI Initiator I/O functions */ 646 #define MPI3_FUNCTION_SCSI_IO (0x20) /* SCSI IO */ 647 #define MPI3_FUNCTION_SCSI_TASK_MGMT (0x21) /* SCSI Task Management */ 648 #define MPI3_FUNCTION_SMP_PASSTHROUGH (0x22) /* SMP Passthrough */ 649 #define MPI3_FUNCTION_NVME_ENCAPSULATED (0x24) /* NVMe Encapsulated */ 650 651 /* SCSI Target I/O functions */ 652 #define MPI3_FUNCTION_TARGET_ASSIST (0x30) /* Target Assist */ 653 #define MPI3_FUNCTION_TARGET_STATUS_SEND (0x31) /* Target Status Send */ 654 #define MPI3_FUNCTION_TARGET_MODE_ABORT (0x32) /* Target Mode Abort */ 655 #define MPI3_FUNCTION_TARGET_CMD_BUF_POST_BASE (0x33) /* Target Command Buffer Post Base */ 656 #define MPI3_FUNCTION_TARGET_CMD_BUF_POST_LIST (0x34) /* Target Command Buffer Post List */ 657 658 /* Queue Management functions */ 659 #define MPI3_FUNCTION_CREATE_REQUEST_QUEUE (0x70) /* Create an operational request queue */ 660 #define MPI3_FUNCTION_DELETE_REQUEST_QUEUE (0x71) /* Delete an operational request queue */ 661 #define MPI3_FUNCTION_CREATE_REPLY_QUEUE (0x72) /* Create an operational reply queue */ 662 #define MPI3_FUNCTION_DELETE_REPLY_QUEUE (0x73) /* Delete an operational reply queue */ 663 664 /* Diagnostic Tools */ 665 #define MPI3_FUNCTION_TOOLBOX (0x80) /* Toolbox */ 666 #define MPI3_FUNCTION_DIAG_BUFFER_POST (0x81) /* Post a Diagnostic Buffer to the I/O Unit */ 667 #define MPI3_FUNCTION_DIAG_BUFFER_MANAGE (0x82) /* Manage a Diagnostic Buffer */ 668 #define MPI3_FUNCTION_DIAG_BUFFER_UPLOAD (0x83) /* Upload a Diagnostic Buffer */ 669 670 /* Miscellaneous functions */ 671 #define MPI3_FUNCTION_MIN_IOC_USE_ONLY (0xC0) /* Beginning of IOC Use Only range of function codes */ 672 #define MPI3_FUNCTION_MAX_IOC_USE_ONLY (0xEF) /* End of IOC Use Only range of function codes */ 673 #define MPI3_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* Beginning of the product-specific range of function codes */ 674 #define MPI3_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* End of the product-specific range of function codes */ 675 676 /**** Defines for IOCStatus ****/ 677 #define MPI3_IOCSTATUS_LOG_INFO_AVAILABLE (0x8000) 678 #define MPI3_IOCSTATUS_STATUS_MASK (0x7FFF) 679 #define MPI3_IOCSTATUS_STATUS_SHIFT (0) 680 681 /* Common IOCStatus values for all replies */ 682 #define MPI3_IOCSTATUS_SUCCESS (0x0000) 683 #define MPI3_IOCSTATUS_INVALID_FUNCTION (0x0001) 684 #define MPI3_IOCSTATUS_BUSY (0x0002) 685 #define MPI3_IOCSTATUS_INVALID_SGL (0x0003) 686 #define MPI3_IOCSTATUS_INTERNAL_ERROR (0x0004) 687 #define MPI3_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 688 #define MPI3_IOCSTATUS_INVALID_FIELD (0x0007) 689 #define MPI3_IOCSTATUS_INVALID_STATE (0x0008) 690 #define MPI3_IOCSTATUS_SHUTDOWN_ACTIVE (0x0009) 691 #define MPI3_IOCSTATUS_INSUFFICIENT_POWER (0x000A) 692 #define MPI3_IOCSTATUS_INVALID_CHANGE_COUNT (0x000B) 693 #define MPI3_IOCSTATUS_ALLOWED_CMD_BLOCK (0x000C) 694 #define MPI3_IOCSTATUS_SUPERVISOR_ONLY (0x000D) 695 #define MPI3_IOCSTATUS_FAILURE (0x001F) 696 697 /* Config IOCStatus values */ 698 #define MPI3_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 699 #define MPI3_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 700 #define MPI3_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 701 #define MPI3_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 702 #define MPI3_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 703 #define MPI3_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 704 705 /* SCSI IO IOCStatus values */ 706 #define MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 707 #define MPI3_IOCSTATUS_SCSI_TM_NOT_SUPPORTED (0x0041) 708 #define MPI3_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 709 #define MPI3_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 710 #define MPI3_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 711 #define MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 712 #define MPI3_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 713 #define MPI3_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 714 #define MPI3_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 715 #define MPI3_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 716 #define MPI3_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 717 #define MPI3_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 718 #define MPI3_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 719 720 /* SCSI Initiator and SCSI Target end-to-end data protection values */ 721 #define MPI3_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 722 #define MPI3_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 723 #define MPI3_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 724 725 /* SCSI Target IOCStatus values */ 726 #define MPI3_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 727 #define MPI3_IOCSTATUS_TARGET_ABORTED (0x0063) 728 #define MPI3_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 729 #define MPI3_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 730 #define MPI3_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 731 #define MPI3_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 732 #define MPI3_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 733 #define MPI3_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 734 #define MPI3_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 735 #define MPI3_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 736 737 /* Serial Attached SCSI IOCStatus values */ 738 #define MPI3_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 739 #define MPI3_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 740 741 /* Diagnostic Buffer Post/Release IOCStatus values */ 742 #define MPI3_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 743 744 /* Component Image Upload/Download */ 745 #define MPI3_IOCSTATUS_CI_UNSUPPORTED (0x00B0) 746 #define MPI3_IOCSTATUS_CI_UPDATE_SEQUENCE (0x00B1) 747 #define MPI3_IOCSTATUS_CI_VALIDATION_FAILED (0x00B2) 748 #define MPI3_IOCSTATUS_CI_KEY_UPDATE_PENDING (0x00B3) 749 #define MPI3_IOCSTATUS_CI_KEY_UPDATE_NOT_POSSIBLE (0x00B4) 750 751 /* Security values */ 752 #define MPI3_IOCSTATUS_SECURITY_KEY_REQUIRED (0x00C0) 753 #define MPI3_IOCSTATUS_SECURITY_VIOLATION (0x00C1) 754 755 /* Request and Reply Queues related IOCStatus values */ 756 #define MPI3_IOCSTATUS_INVALID_QUEUE_ID (0x0F00) 757 #define MPI3_IOCSTATUS_INVALID_QUEUE_SIZE (0x0F01) 758 #define MPI3_IOCSTATUS_INVALID_MSIX_VECTOR (0x0F02) 759 #define MPI3_IOCSTATUS_INVALID_REPLY_QUEUE_ID (0x0F03) 760 #define MPI3_IOCSTATUS_INVALID_QUEUE_DELETION (0x0F04) 761 762 /**** Defines for IOCLogInfo ****/ 763 #define MPI3_IOCLOGINFO_TYPE_MASK (0xF0000000) 764 #define MPI3_IOCLOGINFO_TYPE_SHIFT (28) 765 #define MPI3_IOCLOGINFO_TYPE_NONE (0x0) 766 #define MPI3_IOCLOGINFO_TYPE_SAS (0x3) 767 #define MPI3_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 768 #define MPI3_IOCLOGINFO_LOG_DATA_SHIFT (0) 769 770 #endif /* MPI30_TRANSPORT_H */ 771 772 773