1 /*- 2 * Copyright (c) 2012-2015 LSI Corp. 3 * Copyright (c) 2013-2016 Avago Technologies 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Copyright (c) 2000-2015 LSI Corporation. 33 * Copyright (c) 2013-2016 Avago Technologies 34 * All rights reserved. 35 * 36 * 37 * Name: mpi2_cnfg.h 38 * Title: MPI Configuration messages and pages 39 * Creation Date: November 10, 2006 40 * 41 * mpi2_cnfg.h Version: 02.00.39 42 * 43 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 44 * prefix are for use only on MPI v2.5 products, and must not be used 45 * with MPI v2.0 products. Unless otherwise noted, names beginning with 46 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 47 * 48 * Version History 49 * --------------- 50 * 51 * Date Version Description 52 * -------- -------- ------------------------------------------------------ 53 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 54 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 55 * Added Manufacturing Page 11. 56 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 57 * define. 58 * 06-26-07 02.00.02 Adding generic structure for product-specific 59 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 60 * Rework of BIOS Page 2 configuration page. 61 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 62 * forms. 63 * Added configuration pages IOC Page 8 and Driver 64 * Persistent Mapping Page 0. 65 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 66 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 67 * RAID Physical Disk Pages 0 and 1, RAID Configuration 68 * Page 0). 69 * Added new value for AccessStatus field of SAS Device 70 * Page 0 (_SATA_NEEDS_INITIALIZATION). 71 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 72 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 73 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 74 * NVDATA. 75 * Modified IOC Page 7 to use masks and added field for 76 * SASBroadcastPrimitiveMasks. 77 * Added MPI2_CONFIG_PAGE_BIOS_4. 78 * Added MPI2_CONFIG_PAGE_LOG_0. 79 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 80 * Added SAS Device IDs. 81 * Updated Integrated RAID configuration pages including 82 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 83 * Page 0. 84 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 85 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 86 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 87 * Added missing MaxNumRoutedSasAddresses field to 88 * MPI2_CONFIG_PAGE_EXPANDER_0. 89 * Added SAS Port Page 0. 90 * Modified structure layout for 91 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 92 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 93 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 94 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 95 * to 0x000000FF. 96 * Added two new values for the Physical Disk Coercion Size 97 * bits in the Flags field of Manufacturing Page 4. 98 * Added product-specific Manufacturing pages 16 to 31. 99 * Modified Flags bits for controlling write cache on SATA 100 * drives in IO Unit Page 1. 101 * Added new bit to AdditionalControlFlags of SAS IO Unit 102 * Page 1 to control Invalid Topology Correction. 103 * Added additional defines for RAID Volume Page 0 104 * VolumeStatusFlags field. 105 * Modified meaning of RAID Volume Page 0 VolumeSettings 106 * define for auto-configure of hot-swap drives. 107 * Added SupportedPhysDisks field to RAID Volume Page 1 and 108 * added related defines. 109 * Added PhysDiskAttributes field (and related defines) to 110 * RAID Physical Disk Page 0. 111 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 112 * Added three new DiscoveryStatus bits for SAS IO Unit 113 * Page 0 and SAS Expander Page 0. 114 * Removed multiplexing information from SAS IO Unit pages. 115 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 116 * Removed Zone Address Resolved bit from PhyInfo and from 117 * Expander Page 0 Flags field. 118 * Added two new AccessStatus values to SAS Device Page 0 119 * for indicating routing problems. Added 3 reserved words 120 * to this page. 121 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 122 * Inserted missing reserved field into structure for IOC 123 * Page 6. 124 * Added more pending task bits to RAID Volume Page 0 125 * VolumeStatusFlags defines. 126 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 127 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 128 * and SAS Expander Page 0 to flag a downstream initiator 129 * when in simplified routing mode. 130 * Removed SATA Init Failure defines for DiscoveryStatus 131 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 132 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 133 * Added PortGroups, DmaGroup, and ControlGroup fields to 134 * SAS Device Page 0. 135 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 136 * Unit Page 6. 137 * Added expander reduced functionality data to SAS 138 * Expander Page 0. 139 * Added SAS PHY Page 2 and SAS PHY Page 3. 140 * 07-30-09 02.00.12 Added IO Unit Page 7. 141 * Added new device ids. 142 * Added SAS IO Unit Page 5. 143 * Added partial and slumber power management capable flags 144 * to SAS Device Page 0 Flags field. 145 * Added PhyInfo defines for power condition. 146 * Added Ethernet configuration pages. 147 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 148 * Added SAS PHY Page 4 structure and defines. 149 * 02-10-10 02.00.14 Modified the comments for the configuration page 150 * structures that contain an array of data. The host 151 * should use the "count" field in the page data (e.g. the 152 * NumPhys field) to determine the number of valid elements 153 * in the array. 154 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 155 * Added PowerManagementCapabilities to IO Unit Page 7. 156 * Added PortWidthModGroup field to 157 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 158 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 159 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 160 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 161 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 162 * define. 163 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 164 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 165 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 166 * defines. 167 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 168 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 169 * the Pinout field. 170 * Added BoardTemperature and BoardTemperatureUnits fields 171 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 172 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 173 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 174 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 175 * Added IO Unit Page 8, IO Unit Page 9, 176 * and IO Unit Page 10. 177 * Added SASNotifyPrimitiveMasks field to 178 * MPI2_CONFIG_PAGE_IOC_7. 179 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 180 * 05-25-11 02.00.20 Cleaned up a few comments. 181 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 182 * for PCIe link as obsolete. 183 * Added SpinupFlags field containing a Disable Spin-up bit 184 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 185 * Unit Page 4. 186 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 187 * Added UEFIVersion field to BIOS Page 1 and defined new 188 * BiosOptions bits. 189 * Incorporating additions for MPI v2.5. 190 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 191 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 192 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 193 * obsolete for MPI v2.5 and later. 194 * Added some defines for 12G SAS speeds. 195 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 196 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 197 * match the specification. 198 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for 199 * future use. 200 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for 201 * MPI2_CONFIG_PAGE_MAN_7. 202 * Added EnclosureLevel and ConnectorName fields to 203 * MPI2_CONFIG_PAGE_SAS_DEV_0. 204 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for 205 * MPI2_CONFIG_PAGE_SAS_DEV_0. 206 * Added EnclosureLevel field to 207 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 208 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for 209 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 210 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of 211 * MPI2_CONFIG_PAGE_BIOS_1. 212 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and 213 * more defines for the BiosOptions field. 214 * 11-18-14 02.00.30 Updated copyright information. 215 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. 216 * Added AdapterOrderAux fields to BIOS Page 3. 217 * 03-16-15 02.00.31 Updated for MPI v2.6. 218 * Added BoardPowerRequirement, PCISlotPowerAllocation, and 219 * Flags field to IO Unit Page 7. 220 * Added IO Unit Page 11. 221 * Added new SAS Phy Event codes 222 * Added PCIe configuration pages. 223 * 03-19-15 02.00.32 Fixed PCIe Link Config page structure names to be 224 * unique in first 32 characters. 225 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of 226 * MPI2_CONFIG_PAGE_BIOS_1. 227 * 08-25-15 02.00.34 Added PCIe Device Page 2 SGL format capability. 228 * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. 229 * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines. 230 * Added Link field to PCIe Link Pages 231 * Added EnclosureLevel and ConnectorName to PCIe 232 * Device Page 0. 233 * Added define for PCIE IoUnit page 1 max rate shift. 234 * Added comment for reserved ExtPageTypes. 235 * Added SAS 4 22.5 gbs speed support. 236 * Added PCIe 4 16.0 GT/sec speec support. 237 * Removed AHCI support. 238 * Removed SOP support. 239 * Added NegotiatedLinkRate and NegotiatedPortWidth to 240 * PCIe device page 0. 241 * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines 242 * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types. 243 * Changed declaration of ConnectorName in PCIe DevicePage0 244 * to match SAS DevicePage 0. 245 * Added SATADeviceWaitTime to IO Unit Page 11. 246 * Added MPI26_MFGPAGE_DEVID_SAS4008 247 * Added x16 PCIe width to IO Unit Page 7 248 * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1 249 * phy data. 250 * Added InitStatus to PCIe IO Unit Page 1 header. 251 * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines. 252 * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and 253 * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats. 254 * -------------------------------------------------------------------------- 255 */ 256 257 #ifndef MPI2_CNFG_H 258 #define MPI2_CNFG_H 259 260 /***************************************************************************** 261 * Configuration Page Header and defines 262 *****************************************************************************/ 263 264 /* Config Page Header */ 265 typedef struct _MPI2_CONFIG_PAGE_HEADER 266 { 267 U8 PageVersion; /* 0x00 */ 268 U8 PageLength; /* 0x01 */ 269 U8 PageNumber; /* 0x02 */ 270 U8 PageType; /* 0x03 */ 271 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 272 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 273 274 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION 275 { 276 MPI2_CONFIG_PAGE_HEADER Struct; 277 U8 Bytes[4]; 278 U16 Word16[2]; 279 U32 Word32; 280 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 281 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 282 283 /* Extended Config Page Header */ 284 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 285 { 286 U8 PageVersion; /* 0x00 */ 287 U8 Reserved1; /* 0x01 */ 288 U8 PageNumber; /* 0x02 */ 289 U8 PageType; /* 0x03 */ 290 U16 ExtPageLength; /* 0x04 */ 291 U8 ExtPageType; /* 0x06 */ 292 U8 Reserved2; /* 0x07 */ 293 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 294 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 295 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 296 297 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 298 { 299 MPI2_CONFIG_PAGE_HEADER Struct; 300 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 301 U8 Bytes[8]; 302 U16 Word16[4]; 303 U32 Word32[2]; 304 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 305 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 306 307 308 /* PageType field values */ 309 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 310 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 311 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 312 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 313 314 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 315 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 316 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 317 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 318 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 319 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 320 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 321 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 322 323 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 324 325 326 /* ExtPageType field values */ 327 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 328 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 329 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 330 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 331 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 332 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 333 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 334 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 335 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 336 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 337 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 338 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT (0x1B) /* MPI v2.6 and later */ 339 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH (0x1C) /* MPI v2.6 and later */ 340 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE (0x1D) /* MPI v2.6 and later */ 341 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK (0x1E) /* MPI v2.6 and later */ 342 /* Product specific reserved values 0xE0 - 0xEF */ 343 /* Vendor specific reserved values 0xF0 - 0xFF */ 344 345 346 /***************************************************************************** 347 * PageAddress defines 348 *****************************************************************************/ 349 350 /* RAID Volume PageAddress format */ 351 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 352 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 353 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 354 355 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 356 357 358 /* RAID Physical Disk PageAddress format */ 359 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 360 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 361 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 362 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 363 364 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 365 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 366 367 368 /* SAS Expander PageAddress format */ 369 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 370 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 371 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 372 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 373 374 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 375 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 376 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 377 378 379 /* SAS Device PageAddress format */ 380 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 381 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 382 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 383 384 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 385 386 387 /* SAS PHY PageAddress format */ 388 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 389 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 390 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 391 392 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 393 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 394 395 396 /* SAS Port PageAddress format */ 397 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 398 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 399 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 400 401 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 402 403 404 /* SAS Enclosure PageAddress format */ 405 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 406 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 407 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 408 409 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 410 411 /* Enclosure PageAddress format */ 412 #define MPI26_ENCLOS_PGAD_FORM_MASK (0xF0000000) 413 #define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 414 #define MPI26_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 415 416 #define MPI26_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 417 418 /* RAID Configuration PageAddress format */ 419 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 420 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 421 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 422 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 423 424 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 425 426 427 /* Driver Persistent Mapping PageAddress format */ 428 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 429 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 430 431 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 432 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 433 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 434 435 436 /* Ethernet PageAddress format */ 437 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 438 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 439 440 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 441 442 443 /* PCIe Switch PageAddress format */ 444 #define MPI26_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) 445 #define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 446 #define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM (0x10000000) 447 #define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL (0x20000000) 448 449 #define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) 450 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) 451 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 452 453 454 /* PCIe Device PageAddress format */ 455 #define MPI26_PCIE_DEVICE_PGAD_FORM_MASK (0xF0000000) 456 #define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 457 #define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE (0x20000000) 458 459 #define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 460 461 /* PCIe Link PageAddress format */ 462 #define MPI26_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) 463 #define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 464 #define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 465 466 #define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK (0x000000FF) 467 468 469 470 /**************************************************************************** 471 * Configuration messages 472 ****************************************************************************/ 473 474 /* Configuration Request Message */ 475 typedef struct _MPI2_CONFIG_REQUEST 476 { 477 U8 Action; /* 0x00 */ 478 U8 SGLFlags; /* 0x01 */ 479 U8 ChainOffset; /* 0x02 */ 480 U8 Function; /* 0x03 */ 481 U16 ExtPageLength; /* 0x04 */ 482 U8 ExtPageType; /* 0x06 */ 483 U8 MsgFlags; /* 0x07 */ 484 U8 VP_ID; /* 0x08 */ 485 U8 VF_ID; /* 0x09 */ 486 U16 Reserved1; /* 0x0A */ 487 U8 Reserved2; /* 0x0C */ 488 U8 ProxyVF_ID; /* 0x0D */ 489 U16 Reserved4; /* 0x0E */ 490 U32 Reserved3; /* 0x10 */ 491 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 492 U32 PageAddress; /* 0x18 */ 493 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 494 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 495 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 496 497 /* values for the Action field */ 498 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 499 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 500 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 501 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 502 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 503 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 504 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 505 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 506 507 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 508 509 510 /* Config Reply Message */ 511 typedef struct _MPI2_CONFIG_REPLY 512 { 513 U8 Action; /* 0x00 */ 514 U8 SGLFlags; /* 0x01 */ 515 U8 MsgLength; /* 0x02 */ 516 U8 Function; /* 0x03 */ 517 U16 ExtPageLength; /* 0x04 */ 518 U8 ExtPageType; /* 0x06 */ 519 U8 MsgFlags; /* 0x07 */ 520 U8 VP_ID; /* 0x08 */ 521 U8 VF_ID; /* 0x09 */ 522 U16 Reserved1; /* 0x0A */ 523 U16 Reserved2; /* 0x0C */ 524 U16 IOCStatus; /* 0x0E */ 525 U32 IOCLogInfo; /* 0x10 */ 526 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 527 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 528 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 529 530 531 532 /***************************************************************************** 533 * 534 * C o n f i g u r a t i o n P a g e s 535 * 536 *****************************************************************************/ 537 538 /**************************************************************************** 539 * Manufacturing Config pages 540 ****************************************************************************/ 541 542 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 543 544 /* MPI v2.0 SAS products */ 545 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 546 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 547 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 548 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 549 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 550 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 551 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 552 553 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 554 555 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 556 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 557 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 558 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 559 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 560 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 561 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 562 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 563 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 564 565 /* MPI v2.5 SAS products */ 566 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 567 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 568 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 569 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 570 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 571 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 572 573 /* MPI v2.6 SAS Products */ 574 #define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) 575 #define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) 576 #define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) 577 #define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) 578 #define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) 579 #define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) 580 #define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) 581 #define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) 582 #define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) 583 #define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) 584 585 #define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA) 586 #define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB) 587 #define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC) 588 #define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD) 589 #define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE) 590 #define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF) 591 592 #define MPI26_MFGPAGE_DEVID_SAS3716 (0x00D0) 593 #define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1) 594 #define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2) 595 596 #define MPI26_MFGPAGE_DEVID_SAS4008 (0x00A1) 597 598 599 /* Manufacturing Page 0 */ 600 601 typedef struct _MPI2_CONFIG_PAGE_MAN_0 602 { 603 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 604 U8 ChipName[16]; /* 0x04 */ 605 U8 ChipRevision[8]; /* 0x14 */ 606 U8 BoardName[16]; /* 0x1C */ 607 U8 BoardAssembly[16]; /* 0x2C */ 608 U8 BoardTracerNumber[16]; /* 0x3C */ 609 } MPI2_CONFIG_PAGE_MAN_0, 610 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 611 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 612 613 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 614 615 616 /* Manufacturing Page 1 */ 617 618 typedef struct _MPI2_CONFIG_PAGE_MAN_1 619 { 620 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 621 U8 VPD[256]; /* 0x04 */ 622 } MPI2_CONFIG_PAGE_MAN_1, 623 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 624 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 625 626 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 627 628 629 typedef struct _MPI2_CHIP_REVISION_ID 630 { 631 U16 DeviceID; /* 0x00 */ 632 U8 PCIRevisionID; /* 0x02 */ 633 U8 Reserved; /* 0x03 */ 634 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 635 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 636 637 638 /* Manufacturing Page 2 */ 639 640 /* 641 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 642 * one and check Header.PageLength at runtime. 643 */ 644 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 645 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 646 #endif 647 648 typedef struct _MPI2_CONFIG_PAGE_MAN_2 649 { 650 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 651 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 652 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 653 } MPI2_CONFIG_PAGE_MAN_2, 654 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 655 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 656 657 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 658 659 660 /* Manufacturing Page 3 */ 661 662 /* 663 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 664 * one and check Header.PageLength at runtime. 665 */ 666 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 667 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 668 #endif 669 670 typedef struct _MPI2_CONFIG_PAGE_MAN_3 671 { 672 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 673 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 674 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 675 } MPI2_CONFIG_PAGE_MAN_3, 676 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 677 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 678 679 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 680 681 682 /* Manufacturing Page 4 */ 683 684 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 685 { 686 U8 PowerSaveFlags; /* 0x00 */ 687 U8 InternalOperationsSleepTime; /* 0x01 */ 688 U8 InternalOperationsRunTime; /* 0x02 */ 689 U8 HostIdleTime; /* 0x03 */ 690 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 691 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 692 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 693 694 /* defines for the PowerSaveFlags field */ 695 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 696 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 697 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 698 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 699 700 typedef struct _MPI2_CONFIG_PAGE_MAN_4 701 { 702 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 703 U32 Reserved1; /* 0x04 */ 704 U32 Flags; /* 0x08 */ 705 U8 InquirySize; /* 0x0C */ 706 U8 Reserved2; /* 0x0D */ 707 U16 Reserved3; /* 0x0E */ 708 U8 InquiryData[56]; /* 0x10 */ 709 U32 RAID0VolumeSettings; /* 0x48 */ 710 U32 RAID1EVolumeSettings; /* 0x4C */ 711 U32 RAID1VolumeSettings; /* 0x50 */ 712 U32 RAID10VolumeSettings; /* 0x54 */ 713 U32 Reserved4; /* 0x58 */ 714 U32 Reserved5; /* 0x5C */ 715 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 716 U8 MaxOCEDisks; /* 0x64 */ 717 U8 ResyncRate; /* 0x65 */ 718 U16 DataScrubDuration; /* 0x66 */ 719 U8 MaxHotSpares; /* 0x68 */ 720 U8 MaxPhysDisksPerVol; /* 0x69 */ 721 U8 MaxPhysDisks; /* 0x6A */ 722 U8 MaxVolumes; /* 0x6B */ 723 } MPI2_CONFIG_PAGE_MAN_4, 724 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 725 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 726 727 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 728 729 /* Manufacturing Page 4 Flags field */ 730 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 731 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 732 733 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 734 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 735 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 736 737 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 738 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 739 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 740 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 741 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 742 743 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 744 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 745 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 746 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 747 748 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 749 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 750 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 751 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 752 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 753 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 754 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 755 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 756 757 758 /* Manufacturing Page 5 */ 759 760 /* 761 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 762 * one and check the value returned for NumPhys at runtime. 763 */ 764 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 765 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 766 #endif 767 768 typedef struct _MPI2_MANUFACTURING5_ENTRY 769 { 770 U64 WWID; /* 0x00 */ 771 U64 DeviceName; /* 0x08 */ 772 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 773 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 774 775 typedef struct _MPI2_CONFIG_PAGE_MAN_5 776 { 777 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 778 U8 NumPhys; /* 0x04 */ 779 U8 Reserved1; /* 0x05 */ 780 U16 Reserved2; /* 0x06 */ 781 U32 Reserved3; /* 0x08 */ 782 U32 Reserved4; /* 0x0C */ 783 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 784 } MPI2_CONFIG_PAGE_MAN_5, 785 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 786 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 787 788 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 789 790 791 /* Manufacturing Page 6 */ 792 793 typedef struct _MPI2_CONFIG_PAGE_MAN_6 794 { 795 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 796 U32 ProductSpecificInfo;/* 0x04 */ 797 } MPI2_CONFIG_PAGE_MAN_6, 798 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 799 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 800 801 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 802 803 804 /* Manufacturing Page 7 */ 805 806 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 807 { 808 U32 Pinout; /* 0x00 */ 809 U8 Connector[16]; /* 0x04 */ 810 U8 Location; /* 0x14 */ 811 U8 ReceptacleID; /* 0x15 */ 812 U16 Slot; /* 0x16 */ 813 U32 Reserved2; /* 0x18 */ 814 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 815 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 816 817 /* defines for the Pinout field */ 818 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 819 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 820 821 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 822 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 823 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 824 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 825 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 826 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 827 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 828 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 829 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 830 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 831 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 832 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 833 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 834 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 835 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 836 #define MPI2_MANPAGE7_PINOUT_SFF_8088_A (0x0E) 837 #define MPI2_MANPAGE7_PINOUT_SFF_8643_16i (0x0F) 838 #define MPI2_MANPAGE7_PINOUT_SFF_8654_4i (0x10) 839 #define MPI2_MANPAGE7_PINOUT_SFF_8654_8i (0x11) 840 #define MPI2_MANPAGE7_PINOUT_SFF_8611_4i (0x12) 841 #define MPI2_MANPAGE7_PINOUT_SFF_8611_8i (0x13) 842 843 /* defines for the Location field */ 844 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 845 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 846 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 847 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 848 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 849 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 850 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 851 852 /* 853 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 854 * one and check the value returned for NumPhys at runtime. 855 */ 856 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 857 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 858 #endif 859 860 typedef struct _MPI2_CONFIG_PAGE_MAN_7 861 { 862 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 863 U32 Reserved1; /* 0x04 */ 864 U32 Reserved2; /* 0x08 */ 865 U32 Flags; /* 0x0C */ 866 U8 EnclosureName[16]; /* 0x10 */ 867 U8 NumPhys; /* 0x20 */ 868 U8 Reserved3; /* 0x21 */ 869 U16 Reserved4; /* 0x22 */ 870 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 871 } MPI2_CONFIG_PAGE_MAN_7, 872 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 873 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 874 875 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 876 877 /* defines for the Flags field */ 878 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008) 879 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 880 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 881 882 883 /* 884 * Generic structure to use for product-specific manufacturing pages 885 * (currently Manufacturing Page 8 through Manufacturing Page 31). 886 */ 887 888 typedef struct _MPI2_CONFIG_PAGE_MAN_PS 889 { 890 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 891 U32 ProductSpecificInfo;/* 0x04 */ 892 } MPI2_CONFIG_PAGE_MAN_PS, 893 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 894 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 895 896 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 897 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 898 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 899 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 900 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 901 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 902 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 903 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 904 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 905 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 906 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 907 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 908 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 909 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 910 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 911 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 912 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 913 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 914 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 915 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 916 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 917 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 918 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 919 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 920 921 922 /**************************************************************************** 923 * IO Unit Config Pages 924 ****************************************************************************/ 925 926 /* IO Unit Page 0 */ 927 928 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 929 { 930 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 931 U64 UniqueValue; /* 0x04 */ 932 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 933 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 934 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 935 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 936 937 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 938 939 940 /* IO Unit Page 1 */ 941 942 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 943 { 944 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 945 U32 Flags; /* 0x04 */ 946 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 947 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 948 949 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 950 951 /* IO Unit Page 1 Flags defines */ 952 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 953 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 954 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 955 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 956 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 957 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 958 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 959 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 960 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 961 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 962 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 963 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 964 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 965 966 967 /* IO Unit Page 3 */ 968 969 /* 970 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 971 * one and check the value returned for GPIOCount at runtime. 972 */ 973 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 974 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 975 #endif 976 977 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 978 { 979 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 980 U8 GPIOCount; /* 0x04 */ 981 U8 Reserved1; /* 0x05 */ 982 U16 Reserved2; /* 0x06 */ 983 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 984 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 985 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 986 987 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 988 989 /* defines for IO Unit Page 3 GPIOVal field */ 990 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 991 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 992 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 993 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 994 995 996 /* IO Unit Page 5 */ 997 998 /* 999 * Upper layer code (drivers, utilities, etc.) should leave this define set to 1000 * one and check the value returned for NumDmaEngines at runtime. 1001 */ 1002 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 1003 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 1004 #endif 1005 1006 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 1007 { 1008 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1009 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */ 1010 U64 RaidAcceleratorBufferSize; /* 0x0C */ 1011 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */ 1012 U8 RAControlSize; /* 0x1C */ 1013 U8 NumDmaEngines; /* 0x1D */ 1014 U8 RAMinControlSize; /* 0x1E */ 1015 U8 RAMaxControlSize; /* 0x1F */ 1016 U32 Reserved1; /* 0x20 */ 1017 U32 Reserved2; /* 0x24 */ 1018 U32 Reserved3; /* 0x28 */ 1019 U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */ 1020 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 1021 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t; 1022 1023 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 1024 1025 /* defines for IO Unit Page 5 DmaEngineCapabilities field */ 1026 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 1027 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 1028 1029 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 1030 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 1031 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 1032 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 1033 1034 1035 /* IO Unit Page 6 */ 1036 1037 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 1038 { 1039 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1040 U16 Flags; /* 0x04 */ 1041 U8 RAHostControlSize; /* 0x06 */ 1042 U8 Reserved0; /* 0x07 */ 1043 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */ 1044 U32 Reserved1; /* 0x10 */ 1045 U32 Reserved2; /* 0x14 */ 1046 U32 Reserved3; /* 0x18 */ 1047 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 1048 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t; 1049 1050 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 1051 1052 /* defines for IO Unit Page 6 Flags field */ 1053 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 1054 1055 1056 /* IO Unit Page 7 */ 1057 1058 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 1059 { 1060 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1061 U8 CurrentPowerMode; /* 0x04 */ /* reserved in MPI 2.0 */ 1062 U8 PreviousPowerMode; /* 0x05 */ /* reserved in MPI 2.0 */ 1063 U8 PCIeWidth; /* 0x06 */ 1064 U8 PCIeSpeed; /* 0x07 */ 1065 U32 ProcessorState; /* 0x08 */ 1066 U32 PowerManagementCapabilities; /* 0x0C */ 1067 U16 IOCTemperature; /* 0x10 */ 1068 U8 IOCTemperatureUnits; /* 0x12 */ 1069 U8 IOCSpeed; /* 0x13 */ 1070 U16 BoardTemperature; /* 0x14 */ 1071 U8 BoardTemperatureUnits; /* 0x16 */ 1072 U8 Reserved3; /* 0x17 */ 1073 U32 BoardPowerRequirement; /* 0x18 */ /* reserved prior to MPI v2.6 */ 1074 U32 PCISlotPowerAllocation; /* 0x1C */ /* reserved prior to MPI v2.6 */ 1075 U8 Flags; /* 0x20 */ /* reserved prior to MPI v2.6 */ 1076 U8 Reserved6; /* 0x21 */ 1077 U16 Reserved7; /* 0x22 */ 1078 U32 Reserved8; /* 0x24 */ 1079 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 1080 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; 1081 1082 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x05) 1083 1084 /* defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 1085 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 1086 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 1087 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 1088 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 1089 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 1090 1091 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 1092 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 1093 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 1094 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 1095 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 1096 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 1097 1098 1099 /* defines for IO Unit Page 7 PCIeWidth field */ 1100 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 1101 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 1102 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 1103 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 1104 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 (0x10) 1105 1106 /* defines for IO Unit Page 7 PCIeSpeed field */ 1107 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 1108 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 1109 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 1110 #define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS (0x03) 1111 1112 /* defines for IO Unit Page 7 ProcessorState field */ 1113 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 1114 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 1115 1116 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 1117 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 1118 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 1119 1120 /* defines for IO Unit Page 7 PowerManagementCapabilities field */ 1121 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 1122 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 1123 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 1124 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 1125 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 1126 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 1127 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 1128 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 1129 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 1130 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 1131 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 1132 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 1133 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 1134 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 1135 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 1136 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) /* obsolete */ 1137 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) /* obsolete */ 1138 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) /* obsolete */ 1139 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) /* obsolete */ 1140 1141 /* obsolete names for the PowerManagementCapabilities bits (above) */ 1142 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 1143 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 1144 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 1145 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /* obsolete */ 1146 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /* obsolete */ 1147 1148 1149 /* defines for IO Unit Page 7 IOCTemperatureUnits field */ 1150 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 1151 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 1152 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 1153 1154 /* defines for IO Unit Page 7 IOCSpeed field */ 1155 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 1156 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 1157 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 1158 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 1159 1160 /* defines for IO Unit Page 7 BoardTemperatureUnits field */ 1161 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 1162 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1163 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1164 1165 /* defines for IO Unit Page 7 Flags field */ 1166 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01) 1167 1168 1169 /* IO Unit Page 8 */ 1170 1171 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1172 1173 typedef struct _MPI2_IOUNIT8_SENSOR 1174 { 1175 U16 Flags; /* 0x00 */ 1176 U16 Reserved1; /* 0x02 */ 1177 U16 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */ 1178 U32 Reserved2; /* 0x0C */ 1179 U32 Reserved3; /* 0x10 */ 1180 U32 Reserved4; /* 0x14 */ 1181 } MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR, 1182 Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t; 1183 1184 /* defines for IO Unit Page 8 Sensor Flags field */ 1185 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1186 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1187 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1188 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1189 1190 /* 1191 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1192 * one and check the value returned for NumSensors at runtime. 1193 */ 1194 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 1195 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 1196 #endif 1197 1198 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 1199 { 1200 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1201 U32 Reserved1; /* 0x04 */ 1202 U32 Reserved2; /* 0x08 */ 1203 U8 NumSensors; /* 0x0C */ 1204 U8 PollingInterval; /* 0x0D */ 1205 U16 Reserved3; /* 0x0E */ 1206 MPI2_IOUNIT8_SENSOR Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */ 1207 } MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1208 Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t; 1209 1210 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1211 1212 1213 /* IO Unit Page 9 */ 1214 1215 typedef struct _MPI2_IOUNIT9_SENSOR 1216 { 1217 U16 CurrentTemperature; /* 0x00 */ 1218 U16 Reserved1; /* 0x02 */ 1219 U8 Flags; /* 0x04 */ 1220 U8 Reserved2; /* 0x05 */ 1221 U16 Reserved3; /* 0x06 */ 1222 U32 Reserved4; /* 0x08 */ 1223 U32 Reserved5; /* 0x0C */ 1224 } MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR, 1225 Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t; 1226 1227 /* defines for IO Unit Page 9 Sensor Flags field */ 1228 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1229 1230 /* 1231 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1232 * one and check the value returned for NumSensors at runtime. 1233 */ 1234 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1235 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1236 #endif 1237 1238 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 1239 { 1240 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1241 U32 Reserved1; /* 0x04 */ 1242 U32 Reserved2; /* 0x08 */ 1243 U8 NumSensors; /* 0x0C */ 1244 U8 Reserved4; /* 0x0D */ 1245 U16 Reserved3; /* 0x0E */ 1246 MPI2_IOUNIT9_SENSOR Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */ 1247 } MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1248 Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t; 1249 1250 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1251 1252 1253 /* IO Unit Page 10 */ 1254 1255 typedef struct _MPI2_IOUNIT10_FUNCTION 1256 { 1257 U8 CreditPercent; /* 0x00 */ 1258 U8 Reserved1; /* 0x01 */ 1259 U16 Reserved2; /* 0x02 */ 1260 } MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION, 1261 Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t; 1262 1263 /* 1264 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1265 * one and check the value returned for NumFunctions at runtime. 1266 */ 1267 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1268 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1269 #endif 1270 1271 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 1272 { 1273 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1274 U8 NumFunctions; /* 0x04 */ 1275 U8 Reserved1; /* 0x05 */ 1276 U16 Reserved2; /* 0x06 */ 1277 U32 Reserved3; /* 0x08 */ 1278 U32 Reserved4; /* 0x0C */ 1279 MPI2_IOUNIT10_FUNCTION Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES]; /* 0x10 */ 1280 } MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1281 Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t; 1282 1283 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1284 1285 1286 /* IO Unit Page 11 (for MPI v2.6 and later) */ 1287 1288 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP 1289 { 1290 U8 MaxTargetSpinup; /* 0x00 */ 1291 U8 SpinupDelay; /* 0x01 */ 1292 U8 SpinupFlags; /* 0x02 */ 1293 U8 Reserved1; /* 0x03 */ 1294 } MPI26_IOUNIT11_SPINUP_GROUP, MPI2_POINTER PTR_MPI26_IOUNIT11_SPINUP_GROUP, 1295 Mpi26IOUnit11SpinupGroup_t, MPI2_POINTER pMpi26IOUnit11SpinupGroup_t; 1296 1297 /* defines for IO Unit Page 11 SpinupFlags */ 1298 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) 1299 1300 1301 /* 1302 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1303 * four and check the value returned for NumPhys at runtime. 1304 */ 1305 #ifndef MPI26_IOUNITPAGE11_PHY_MAX 1306 #define MPI26_IOUNITPAGE11_PHY_MAX (4) 1307 #endif 1308 1309 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 1310 { 1311 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1312 U32 Reserved1; /* 0x04 */ 1313 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1314 U32 Reserved2; /* 0x18 */ 1315 U32 Reserved3; /* 0x1C */ 1316 U32 Reserved4; /* 0x20 */ 1317 U8 BootDeviceWaitTime; /* 0x24 */ 1318 U8 SATADeviceWaitTime; /* 0x25 */ 1319 U16 Reserved6; /* 0x26 */ 1320 U8 NumPhys; /* 0x28 */ 1321 U8 PEInitialSpinupDelay; /* 0x29 */ 1322 U8 PEReplyDelay; /* 0x2A */ 1323 U8 Flags; /* 0x2B */ 1324 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/* 0x2C */ 1325 } MPI26_CONFIG_PAGE_IO_UNIT_11, 1326 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, 1327 Mpi26IOUnitPage11_t, MPI2_POINTER pMpi26IOUnitPage11_t; 1328 1329 #define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) 1330 1331 /* defines for Flags field */ 1332 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) 1333 1334 /* defines for PHY field */ 1335 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) 1336 1337 1338 1339 /**************************************************************************** 1340 * IOC Config Pages 1341 ****************************************************************************/ 1342 1343 /* IOC Page 0 */ 1344 1345 typedef struct _MPI2_CONFIG_PAGE_IOC_0 1346 { 1347 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1348 U32 Reserved1; /* 0x04 */ 1349 U32 Reserved2; /* 0x08 */ 1350 U16 VendorID; /* 0x0C */ 1351 U16 DeviceID; /* 0x0E */ 1352 U8 RevisionID; /* 0x10 */ 1353 U8 Reserved3; /* 0x11 */ 1354 U16 Reserved4; /* 0x12 */ 1355 U32 ClassCode; /* 0x14 */ 1356 U16 SubsystemVendorID; /* 0x18 */ 1357 U16 SubsystemID; /* 0x1A */ 1358 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 1359 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 1360 1361 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1362 1363 1364 /* IOC Page 1 */ 1365 1366 typedef struct _MPI2_CONFIG_PAGE_IOC_1 1367 { 1368 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1369 U32 Flags; /* 0x04 */ 1370 U32 CoalescingTimeout; /* 0x08 */ 1371 U8 CoalescingDepth; /* 0x0C */ 1372 U8 PCISlotNum; /* 0x0D */ 1373 U8 PCIBusNum; /* 0x0E */ 1374 U8 PCIDomainSegment; /* 0x0F */ 1375 U32 Reserved1; /* 0x10 */ 1376 U32 Reserved2; /* 0x14 */ 1377 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 1378 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 1379 1380 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1381 1382 /* defines for IOC Page 1 Flags field */ 1383 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1384 1385 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1386 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1387 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1388 1389 /* IOC Page 6 */ 1390 1391 typedef struct _MPI2_CONFIG_PAGE_IOC_6 1392 { 1393 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1394 U32 CapabilitiesFlags; /* 0x04 */ 1395 U8 MaxDrivesRAID0; /* 0x08 */ 1396 U8 MaxDrivesRAID1; /* 0x09 */ 1397 U8 MaxDrivesRAID1E; /* 0x0A */ 1398 U8 MaxDrivesRAID10; /* 0x0B */ 1399 U8 MinDrivesRAID0; /* 0x0C */ 1400 U8 MinDrivesRAID1; /* 0x0D */ 1401 U8 MinDrivesRAID1E; /* 0x0E */ 1402 U8 MinDrivesRAID10; /* 0x0F */ 1403 U32 Reserved1; /* 0x10 */ 1404 U8 MaxGlobalHotSpares; /* 0x14 */ 1405 U8 MaxPhysDisks; /* 0x15 */ 1406 U8 MaxVolumes; /* 0x16 */ 1407 U8 MaxConfigs; /* 0x17 */ 1408 U8 MaxOCEDisks; /* 0x18 */ 1409 U8 Reserved2; /* 0x19 */ 1410 U16 Reserved3; /* 0x1A */ 1411 U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 1412 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 1413 U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 1414 U32 Reserved4; /* 0x28 */ 1415 U32 Reserved5; /* 0x2C */ 1416 U16 DefaultMetadataSize; /* 0x30 */ 1417 U16 Reserved6; /* 0x32 */ 1418 U16 MaxBadBlockTableEntries; /* 0x34 */ 1419 U16 Reserved7; /* 0x36 */ 1420 U32 IRNvsramVersion; /* 0x38 */ 1421 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 1422 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 1423 1424 #define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1425 1426 /* defines for IOC Page 6 CapabilitiesFlags */ 1427 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1428 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1429 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1430 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1431 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1432 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1433 1434 1435 /* IOC Page 7 */ 1436 1437 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1438 1439 typedef struct _MPI2_CONFIG_PAGE_IOC_7 1440 { 1441 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1442 U32 Reserved1; /* 0x04 */ 1443 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 1444 U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 1445 U16 SASNotifyPrimitiveMasks; /* 0x1A */ 1446 U32 Reserved3; /* 0x1C */ 1447 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 1448 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 1449 1450 #define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1451 1452 1453 /* IOC Page 8 */ 1454 1455 typedef struct _MPI2_CONFIG_PAGE_IOC_8 1456 { 1457 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1458 U8 NumDevsPerEnclosure; /* 0x04 */ 1459 U8 Reserved1; /* 0x05 */ 1460 U16 Reserved2; /* 0x06 */ 1461 U16 MaxPersistentEntries; /* 0x08 */ 1462 U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 1463 U16 Flags; /* 0x0C */ 1464 U16 Reserved3; /* 0x0E */ 1465 U16 IRVolumeMappingFlags; /* 0x10 */ 1466 U16 Reserved4; /* 0x12 */ 1467 U32 Reserved5; /* 0x14 */ 1468 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 1469 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 1470 1471 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1472 1473 /* defines for IOC Page 8 Flags field */ 1474 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1475 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1476 1477 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1478 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1479 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1480 1481 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1482 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1483 1484 /* defines for IOC Page 8 IRVolumeMappingFlags */ 1485 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1486 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1487 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1488 1489 1490 /**************************************************************************** 1491 * BIOS Config Pages 1492 ****************************************************************************/ 1493 1494 /* BIOS Page 1 */ 1495 1496 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 1497 { 1498 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1499 U32 BiosOptions; /* 0x04 */ 1500 U32 IOCSettings; /* 0x08 */ 1501 U8 SSUTimeout; /* 0x0C */ 1502 U8 Reserved1; /* 0x0D */ 1503 U16 Reserved2; /* 0x0E */ 1504 U32 DeviceSettings; /* 0x10 */ 1505 U16 NumberOfDevices; /* 0x14 */ 1506 U16 UEFIVersion; /* 0x16 */ 1507 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 1508 U16 IOTimeoutSequential; /* 0x1A */ 1509 U16 IOTimeoutOther; /* 0x1C */ 1510 U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 1511 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 1512 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 1513 1514 #define MPI2_BIOSPAGE1_PAGEVERSION (0x07) 1515 1516 /* values for BIOS Page 1 BiosOptions field */ 1517 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) 1518 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) 1519 1520 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1521 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) 1522 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) 1523 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) 1524 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) 1525 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) 1526 1527 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) 1528 1529 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) 1530 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) 1531 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) 1532 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) 1533 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) 1534 1535 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1536 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1537 1538 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1539 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1540 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1541 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1542 1543 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1544 1545 /* values for BIOS Page 1 IOCSettings field */ 1546 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1547 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1548 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1549 1550 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1551 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1552 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1553 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1554 1555 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1556 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1557 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1558 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1559 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1560 1561 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1562 1563 /* values for BIOS Page 1 DeviceSettings field */ 1564 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1565 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1566 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1567 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1568 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1569 1570 /* defines for BIOS Page 1 UEFIVersion field */ 1571 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1572 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1573 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1574 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1575 1576 1577 1578 /* BIOS Page 2 */ 1579 1580 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 1581 { 1582 U32 Reserved1; /* 0x00 */ 1583 U32 Reserved2; /* 0x04 */ 1584 U32 Reserved3; /* 0x08 */ 1585 U32 Reserved4; /* 0x0C */ 1586 U32 Reserved5; /* 0x10 */ 1587 U32 Reserved6; /* 0x14 */ 1588 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1589 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1590 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 1591 1592 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID 1593 { 1594 U64 SASAddress; /* 0x00 */ 1595 U8 LUN[8]; /* 0x08 */ 1596 U32 Reserved1; /* 0x10 */ 1597 U32 Reserved2; /* 0x14 */ 1598 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1599 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 1600 1601 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 1602 { 1603 U64 EnclosureLogicalID; /* 0x00 */ 1604 U32 Reserved1; /* 0x08 */ 1605 U32 Reserved2; /* 0x0C */ 1606 U16 SlotNumber; /* 0x10 */ 1607 U16 Reserved3; /* 0x12 */ 1608 U32 Reserved4; /* 0x14 */ 1609 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1610 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1611 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1612 1613 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1614 { 1615 U64 DeviceName; /* 0x00 */ 1616 U8 LUN[8]; /* 0x08 */ 1617 U32 Reserved1; /* 0x10 */ 1618 U32 Reserved2; /* 0x14 */ 1619 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1620 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1621 1622 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1623 { 1624 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1625 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1626 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1627 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1628 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1629 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1630 1631 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 1632 { 1633 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1634 U32 Reserved1; /* 0x04 */ 1635 U32 Reserved2; /* 0x08 */ 1636 U32 Reserved3; /* 0x0C */ 1637 U32 Reserved4; /* 0x10 */ 1638 U32 Reserved5; /* 0x14 */ 1639 U32 Reserved6; /* 0x18 */ 1640 U8 ReqBootDeviceForm; /* 0x1C */ 1641 U8 Reserved7; /* 0x1D */ 1642 U16 Reserved8; /* 0x1E */ 1643 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1644 U8 ReqAltBootDeviceForm; /* 0x38 */ 1645 U8 Reserved9; /* 0x39 */ 1646 U16 Reserved10; /* 0x3A */ 1647 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1648 U8 CurrentBootDeviceForm; /* 0x58 */ 1649 U8 Reserved11; /* 0x59 */ 1650 U16 Reserved12; /* 0x5A */ 1651 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1652 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1653 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1654 1655 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1656 1657 /* values for BIOS Page 2 BootDeviceForm fields */ 1658 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1659 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1660 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1661 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1662 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1663 1664 1665 /* BIOS Page 3 */ 1666 1667 #define MPI2_BIOSPAGE3_NUM_ADAPTER (4) 1668 1669 typedef struct _MPI2_ADAPTER_INFO 1670 { 1671 U8 PciBusNumber; /* 0x00 */ 1672 U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1673 U16 AdapterFlags; /* 0x02 */ 1674 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1675 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1676 1677 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1678 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1679 1680 typedef struct _MPI2_ADAPTER_ORDER_AUX 1681 { 1682 U64 WWID; /* 0x00 */ 1683 U32 Reserved1; /* 0x08 */ 1684 U32 Reserved2; /* 0x0C */ 1685 } MPI2_ADAPTER_ORDER_AUX, MPI2_POINTER PTR_MPI2_ADAPTER_ORDER_AUX, 1686 Mpi2AdapterOrderAux_t, MPI2_POINTER pMpi2AdapterOrderAux_t; 1687 1688 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 1689 { 1690 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1691 U32 GlobalFlags; /* 0x04 */ 1692 U32 BiosVersion; /* 0x08 */ 1693 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x0C */ 1694 U32 Reserved1; /* 0x1C */ 1695 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x20 */ /* MPI v2.5 and newer */ 1696 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1697 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1698 1699 #define MPI2_BIOSPAGE3_PAGEVERSION (0x01) 1700 1701 /* values for BIOS Page 3 GlobalFlags */ 1702 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1703 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1704 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1705 1706 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1707 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1708 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1709 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1710 1711 1712 /* BIOS Page 4 */ 1713 1714 /* 1715 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1716 * one and check the value returned for NumPhys at runtime. 1717 */ 1718 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1719 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1720 #endif 1721 1722 typedef struct _MPI2_BIOS4_ENTRY 1723 { 1724 U64 ReassignmentWWID; /* 0x00 */ 1725 U64 ReassignmentDeviceName; /* 0x08 */ 1726 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1727 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1728 1729 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 1730 { 1731 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1732 U8 NumPhys; /* 0x04 */ 1733 U8 Reserved1; /* 0x05 */ 1734 U16 Reserved2; /* 0x06 */ 1735 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1736 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1737 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1738 1739 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1740 1741 1742 /**************************************************************************** 1743 * RAID Volume Config Pages 1744 ****************************************************************************/ 1745 1746 /* RAID Volume Page 0 */ 1747 1748 typedef struct _MPI2_RAIDVOL0_PHYS_DISK 1749 { 1750 U8 RAIDSetNum; /* 0x00 */ 1751 U8 PhysDiskMap; /* 0x01 */ 1752 U8 PhysDiskNum; /* 0x02 */ 1753 U8 Reserved; /* 0x03 */ 1754 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1755 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1756 1757 /* defines for the PhysDiskMap field */ 1758 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1759 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1760 1761 typedef struct _MPI2_RAIDVOL0_SETTINGS 1762 { 1763 U16 Settings; /* 0x00 */ 1764 U8 HotSparePool; /* 0x01 */ 1765 U8 Reserved; /* 0x02 */ 1766 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1767 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1768 1769 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1770 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1771 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1772 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1773 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1774 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1775 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1776 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1777 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1778 1779 /* RAID Volume Page 0 VolumeSettings defines */ 1780 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1781 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1782 1783 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1784 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1785 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1786 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1787 1788 /* 1789 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1790 * one and check the value returned for NumPhysDisks at runtime. 1791 */ 1792 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1793 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1794 #endif 1795 1796 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1797 { 1798 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1799 U16 DevHandle; /* 0x04 */ 1800 U8 VolumeState; /* 0x06 */ 1801 U8 VolumeType; /* 0x07 */ 1802 U32 VolumeStatusFlags; /* 0x08 */ 1803 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1804 U64 MaxLBA; /* 0x10 */ 1805 U32 StripeSize; /* 0x18 */ 1806 U16 BlockSize; /* 0x1C */ 1807 U16 Reserved1; /* 0x1E */ 1808 U8 SupportedPhysDisks; /* 0x20 */ 1809 U8 ResyncRate; /* 0x21 */ 1810 U16 DataScrubDuration; /* 0x22 */ 1811 U8 NumPhysDisks; /* 0x24 */ 1812 U8 Reserved2; /* 0x25 */ 1813 U8 Reserved3; /* 0x26 */ 1814 U8 InactiveStatus; /* 0x27 */ 1815 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1816 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1817 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1818 1819 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1820 1821 /* values for RAID VolumeState */ 1822 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1823 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1824 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1825 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1826 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1827 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1828 1829 /* values for RAID VolumeType */ 1830 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1831 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1832 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1833 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1834 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1835 1836 /* values for RAID Volume Page 0 VolumeStatusFlags field */ 1837 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1838 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1839 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1840 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1841 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1842 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1843 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1844 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1845 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1846 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1847 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1848 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1849 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1850 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1851 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1852 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1853 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1854 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1855 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1856 1857 /* values for RAID Volume Page 0 SupportedPhysDisks field */ 1858 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1859 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1860 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1861 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1862 1863 /* values for RAID Volume Page 0 InactiveStatus field */ 1864 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1865 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1866 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1867 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1868 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1869 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1870 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1871 1872 1873 /* RAID Volume Page 1 */ 1874 1875 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1876 { 1877 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1878 U16 DevHandle; /* 0x04 */ 1879 U16 Reserved0; /* 0x06 */ 1880 U8 GUID[24]; /* 0x08 */ 1881 U8 Name[16]; /* 0x20 */ 1882 U64 WWID; /* 0x30 */ 1883 U32 Reserved1; /* 0x38 */ 1884 U32 Reserved2; /* 0x3C */ 1885 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1886 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1887 1888 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1889 1890 1891 /**************************************************************************** 1892 * RAID Physical Disk Config Pages 1893 ****************************************************************************/ 1894 1895 /* RAID Physical Disk Page 0 */ 1896 1897 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1898 { 1899 U16 Reserved1; /* 0x00 */ 1900 U8 HotSparePool; /* 0x02 */ 1901 U8 Reserved2; /* 0x03 */ 1902 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1903 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1904 1905 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1906 1907 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1908 { 1909 U8 VendorID[8]; /* 0x00 */ 1910 U8 ProductID[16]; /* 0x08 */ 1911 U8 ProductRevLevel[4]; /* 0x18 */ 1912 U8 SerialNum[32]; /* 0x1C */ 1913 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1914 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1915 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1916 1917 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1918 { 1919 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1920 U16 DevHandle; /* 0x04 */ 1921 U8 Reserved1; /* 0x06 */ 1922 U8 PhysDiskNum; /* 0x07 */ 1923 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1924 U32 Reserved2; /* 0x0C */ 1925 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1926 U32 Reserved3; /* 0x4C */ 1927 U8 PhysDiskState; /* 0x50 */ 1928 U8 OfflineReason; /* 0x51 */ 1929 U8 IncompatibleReason; /* 0x52 */ 1930 U8 PhysDiskAttributes; /* 0x53 */ 1931 U32 PhysDiskStatusFlags; /* 0x54 */ 1932 U64 DeviceMaxLBA; /* 0x58 */ 1933 U64 HostMaxLBA; /* 0x60 */ 1934 U64 CoercedMaxLBA; /* 0x68 */ 1935 U16 BlockSize; /* 0x70 */ 1936 U16 Reserved5; /* 0x72 */ 1937 U32 Reserved6; /* 0x74 */ 1938 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1939 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1940 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1941 1942 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1943 1944 /* PhysDiskState defines */ 1945 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1946 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1947 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1948 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1949 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1950 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1951 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1952 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1953 1954 /* OfflineReason defines */ 1955 #define MPI2_PHYSDISK0_ONLINE (0x00) 1956 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1957 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1958 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1959 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1960 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1961 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1962 1963 /* IncompatibleReason defines */ 1964 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1965 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1966 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1967 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1968 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1969 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1970 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1971 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1972 1973 /* PhysDiskAttributes defines */ 1974 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1975 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1976 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1977 1978 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1979 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1980 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1981 1982 /* PhysDiskStatusFlags defines */ 1983 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1984 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1985 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1986 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1987 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1988 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1989 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1990 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1991 1992 1993 /* RAID Physical Disk Page 1 */ 1994 1995 /* 1996 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1997 * one and check the value returned for NumPhysDiskPaths at runtime. 1998 */ 1999 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 2000 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 2001 #endif 2002 2003 typedef struct _MPI2_RAIDPHYSDISK1_PATH 2004 { 2005 U16 DevHandle; /* 0x00 */ 2006 U16 Reserved1; /* 0x02 */ 2007 U64 WWID; /* 0x04 */ 2008 U64 OwnerWWID; /* 0x0C */ 2009 U8 OwnerIdentifier; /* 0x14 */ 2010 U8 Reserved2; /* 0x15 */ 2011 U16 Flags; /* 0x16 */ 2012 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 2013 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 2014 2015 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 2016 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 2017 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2018 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2019 2020 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 2021 { 2022 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2023 U8 NumPhysDiskPaths; /* 0x04 */ 2024 U8 PhysDiskNum; /* 0x05 */ 2025 U16 Reserved1; /* 0x06 */ 2026 U32 Reserved2; /* 0x08 */ 2027 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 2028 } MPI2_CONFIG_PAGE_RD_PDISK_1, 2029 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 2030 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 2031 2032 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 2033 2034 2035 /**************************************************************************** 2036 * values for fields used by several types of SAS Config Pages 2037 ****************************************************************************/ 2038 2039 /* values for NegotiatedLinkRates fields */ 2040 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 2041 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 2042 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 2043 /* link rates used for Negotiated Physical and Logical Link Rate */ 2044 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 2045 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 2046 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 2047 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 2048 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 2049 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 2050 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 2051 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 2052 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 2053 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 2054 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 2055 #define MPI26_SAS_NEG_LINK_RATE_22_5 (0x0C) 2056 2057 2058 /* values for AttachedPhyInfo fields */ 2059 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 2060 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 2061 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 2062 2063 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 2064 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 2065 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 2066 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 2067 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 2068 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 2069 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 2070 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 2071 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 2072 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 2073 2074 2075 /* values for PhyInfo fields */ 2076 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 2077 2078 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 2079 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 2080 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 2081 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 2082 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 2083 2084 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 2085 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 2086 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 2087 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 2088 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 2089 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 2090 2091 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 2092 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 2093 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 2094 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 2095 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 2096 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 2097 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 2098 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 2099 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 2100 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 2101 2102 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 2103 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2104 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 2105 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 2106 2107 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2108 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2109 2110 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2111 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 2112 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2113 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 2114 2115 2116 /* values for SAS ProgrammedLinkRate fields */ 2117 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 2118 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2119 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 2120 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 2121 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 2122 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 2123 #define MPI26_SAS_PRATE_MAX_RATE_22_5 (0xC0) 2124 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 2125 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2126 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 2127 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 2128 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 2129 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 2130 #define MPI26_SAS_PRATE_MIN_RATE_22_5 (0x0C) 2131 2132 2133 /* values for SAS HwLinkRate fields */ 2134 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 2135 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 2136 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 2137 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 2138 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 2139 #define MPI26_SAS_HWRATE_MAX_RATE_22_5 (0xC0) 2140 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 2141 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 2142 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 2143 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 2144 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 2145 #define MPI26_SAS_HWRATE_MIN_RATE_22_5 (0x0C) 2146 2147 2148 2149 /**************************************************************************** 2150 * SAS IO Unit Config Pages 2151 ****************************************************************************/ 2152 2153 /* SAS IO Unit Page 0 */ 2154 2155 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 2156 { 2157 U8 Port; /* 0x00 */ 2158 U8 PortFlags; /* 0x01 */ 2159 U8 PhyFlags; /* 0x02 */ 2160 U8 NegotiatedLinkRate; /* 0x03 */ 2161 U32 ControllerPhyDeviceInfo;/* 0x04 */ 2162 U16 AttachedDevHandle; /* 0x08 */ 2163 U16 ControllerDevHandle; /* 0x0A */ 2164 U32 DiscoveryStatus; /* 0x0C */ 2165 U32 Reserved; /* 0x10 */ 2166 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 2167 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 2168 2169 /* 2170 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2171 * one and check the value returned for NumPhys at runtime. 2172 */ 2173 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 2174 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 2175 #endif 2176 2177 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 2178 { 2179 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2180 U32 Reserved1; /* 0x08 */ 2181 U8 NumPhys; /* 0x0C */ 2182 U8 Reserved2; /* 0x0D */ 2183 U16 Reserved3; /* 0x0E */ 2184 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 2185 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 2186 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 2187 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 2188 2189 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 2190 2191 /* values for SAS IO Unit Page 0 PortFlags */ 2192 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 2193 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 2194 2195 /* values for SAS IO Unit Page 0 PhyFlags */ 2196 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2197 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2198 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 2199 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2200 2201 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2202 2203 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2204 2205 /* values for SAS IO Unit Page 0 DiscoveryStatus */ 2206 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2207 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2208 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 2209 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2210 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2211 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2212 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2213 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2214 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2215 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2216 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 2217 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2218 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2219 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2220 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2221 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2222 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2223 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2224 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2225 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 2226 2227 2228 /* SAS IO Unit Page 1 */ 2229 2230 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 2231 { 2232 U8 Port; /* 0x00 */ 2233 U8 PortFlags; /* 0x01 */ 2234 U8 PhyFlags; /* 0x02 */ 2235 U8 MaxMinLinkRate; /* 0x03 */ 2236 U32 ControllerPhyDeviceInfo; /* 0x04 */ 2237 U16 MaxTargetPortConnectTime; /* 0x08 */ 2238 U16 Reserved1; /* 0x0A */ 2239 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 2240 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 2241 2242 /* 2243 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2244 * one and check the value returned for NumPhys at runtime. 2245 */ 2246 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 2247 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 2248 #endif 2249 2250 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 2251 { 2252 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2253 U16 ControlFlags; /* 0x08 */ 2254 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 2255 U16 AdditionalControlFlags; /* 0x0C */ 2256 U16 SASWideMaxQueueDepth; /* 0x0E */ 2257 U8 NumPhys; /* 0x10 */ 2258 U8 SATAMaxQDepth; /* 0x11 */ 2259 U8 ReportDeviceMissingDelay; /* 0x12 */ 2260 U8 IODeviceMissingDelay; /* 0x13 */ 2261 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 2262 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 2263 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2264 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 2265 2266 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2267 2268 /* values for SAS IO Unit Page 1 ControlFlags */ 2269 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2270 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2271 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */ 2272 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2273 2274 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2275 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2276 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2277 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2278 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2279 2280 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2281 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2282 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2283 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2284 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2285 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2286 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2287 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */ 2288 2289 /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 2290 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2291 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2292 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2293 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2294 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2295 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2296 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2297 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2298 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2299 2300 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2301 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2302 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2303 2304 /* values for SAS IO Unit Page 1 PortFlags */ 2305 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2306 2307 /* values for SAS IO Unit Page 1 PhyFlags */ 2308 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2309 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2310 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2311 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2312 2313 /* values for SAS IO Unit Page 1 MaxMinLinkRate */ 2314 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2315 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2316 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2317 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2318 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2319 #define MPI26_SASIOUNIT1_MAX_RATE_22_5 (0xC0) 2320 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2321 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2322 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2323 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2324 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2325 #define MPI26_SASIOUNIT1_MIN_RATE_22_5 (0x0C) 2326 2327 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2328 2329 2330 /* SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ 2331 2332 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 2333 { 2334 U8 MaxTargetSpinup; /* 0x00 */ 2335 U8 SpinupDelay; /* 0x01 */ 2336 U8 SpinupFlags; /* 0x02 */ 2337 U8 Reserved1; /* 0x03 */ 2338 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2339 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 2340 2341 /* defines for SAS IO Unit Page 4 SpinupFlags */ 2342 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2343 2344 2345 /* 2346 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2347 * one and check the value returned for NumPhys at runtime. 2348 */ 2349 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2350 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2351 #endif 2352 2353 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 2354 { 2355 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2356 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 2357 U32 Reserved1; /* 0x18 */ 2358 U32 Reserved2; /* 0x1C */ 2359 U32 Reserved3; /* 0x20 */ 2360 U8 BootDeviceWaitTime; /* 0x24 */ 2361 U8 SATADeviceWaitTime; /* 0x25 */ 2362 U16 Reserved5; /* 0x26 */ 2363 U8 NumPhys; /* 0x28 */ 2364 U8 PEInitialSpinupDelay; /* 0x29 */ 2365 U8 PEReplyDelay; /* 0x2A */ 2366 U8 Flags; /* 0x2B */ 2367 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 2368 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 2369 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2370 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 2371 2372 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2373 2374 /* defines for Flags field */ 2375 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2376 2377 /* defines for PHY field */ 2378 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2379 2380 2381 /* SAS IO Unit Page 5 */ 2382 2383 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2384 { 2385 U8 ControlFlags; /* 0x00 */ 2386 U8 PortWidthModGroup; /* 0x01 */ 2387 U16 InactivityTimerExponent; /* 0x02 */ 2388 U8 SATAPartialTimeout; /* 0x04 */ 2389 U8 Reserved2; /* 0x05 */ 2390 U8 SATASlumberTimeout; /* 0x06 */ 2391 U8 Reserved3; /* 0x07 */ 2392 U8 SASPartialTimeout; /* 0x08 */ 2393 U8 Reserved4; /* 0x09 */ 2394 U8 SASSlumberTimeout; /* 0x0A */ 2395 U8 Reserved5; /* 0x0B */ 2396 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2397 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2398 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t; 2399 2400 /* defines for ControlFlags field */ 2401 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2402 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2403 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2404 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2405 2406 /* defines for PortWidthModeGroup field */ 2407 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2408 2409 /* defines for InactivityTimerExponent field */ 2410 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2411 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2412 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2413 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2414 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2415 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2416 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2417 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2418 2419 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2420 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2421 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2422 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2423 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2424 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2425 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2426 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2427 2428 /* 2429 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2430 * one and check the value returned for NumPhys at runtime. 2431 */ 2432 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2433 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2434 #endif 2435 2436 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 2437 { 2438 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2439 U8 NumPhys; /* 0x08 */ 2440 U8 Reserved1; /* 0x09 */ 2441 U16 Reserved2; /* 0x0A */ 2442 U32 Reserved3; /* 0x0C */ 2443 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */ 2444 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 2445 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2446 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t; 2447 2448 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2449 2450 2451 /* SAS IO Unit Page 6 */ 2452 2453 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2454 { 2455 U8 CurrentStatus; /* 0x00 */ 2456 U8 CurrentModulation; /* 0x01 */ 2457 U8 CurrentUtilization; /* 0x02 */ 2458 U8 Reserved1; /* 0x03 */ 2459 U32 Reserved2; /* 0x04 */ 2460 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2461 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2462 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2463 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2464 2465 /* defines for CurrentStatus field */ 2466 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2467 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2468 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2469 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2470 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2471 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2472 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2473 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2474 2475 /* defines for CurrentModulation field */ 2476 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2477 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2478 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2479 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2480 2481 /* 2482 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2483 * one and check the value returned for NumGroups at runtime. 2484 */ 2485 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2486 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2487 #endif 2488 2489 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 2490 { 2491 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2492 U32 Reserved1; /* 0x08 */ 2493 U32 Reserved2; /* 0x0C */ 2494 U8 NumGroups; /* 0x10 */ 2495 U8 Reserved3; /* 0x11 */ 2496 U16 Reserved4; /* 0x12 */ 2497 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2498 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */ 2499 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2500 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2501 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t; 2502 2503 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2504 2505 2506 /* SAS IO Unit Page 7 */ 2507 2508 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2509 { 2510 U8 Flags; /* 0x00 */ 2511 U8 Reserved1; /* 0x01 */ 2512 U16 Reserved2; /* 0x02 */ 2513 U8 Threshold75Pct; /* 0x04 */ 2514 U8 Threshold50Pct; /* 0x05 */ 2515 U8 Threshold25Pct; /* 0x06 */ 2516 U8 Reserved3; /* 0x07 */ 2517 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2518 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2519 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2520 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2521 2522 /* defines for Flags field */ 2523 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2524 2525 2526 /* 2527 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2528 * one and check the value returned for NumGroups at runtime. 2529 */ 2530 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2531 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2532 #endif 2533 2534 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 2535 { 2536 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2537 U8 SamplingInterval; /* 0x08 */ 2538 U8 WindowLength; /* 0x09 */ 2539 U16 Reserved1; /* 0x0A */ 2540 U32 Reserved2; /* 0x0C */ 2541 U32 Reserved3; /* 0x10 */ 2542 U8 NumGroups; /* 0x14 */ 2543 U8 Reserved4; /* 0x15 */ 2544 U16 Reserved5; /* 0x16 */ 2545 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2546 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */ 2547 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2548 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2549 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t; 2550 2551 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2552 2553 2554 /* SAS IO Unit Page 8 */ 2555 2556 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 2557 { 2558 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2559 U32 Reserved1; /* 0x08 */ 2560 U32 PowerManagementCapabilities; /* 0x0C */ 2561 U8 TxRxSleepStatus; /* 0x10 */ /* reserved in MPI 2.0 */ 2562 U8 Reserved2; /* 0x11 */ 2563 U16 Reserved3; /* 0x12 */ 2564 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2565 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2566 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t; 2567 2568 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2569 2570 /* defines for PowerManagementCapabilities field */ 2571 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2572 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2573 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2574 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2575 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2576 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2577 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2578 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2579 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2580 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2581 2582 /* defines for TxRxSleepStatus field */ 2583 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2584 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2585 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2586 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2587 2588 2589 2590 /* SAS IO Unit Page 16 */ 2591 2592 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 2593 { 2594 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2595 U64 TimeStamp; /* 0x08 */ 2596 U32 Reserved1; /* 0x10 */ 2597 U32 Reserved2; /* 0x14 */ 2598 U32 FastPathPendedRequests; /* 0x18 */ 2599 U32 FastPathUnPendedRequests; /* 0x1C */ 2600 U32 FastPathHostRequestStarts; /* 0x20 */ 2601 U32 FastPathFirmwareRequestStarts; /* 0x24 */ 2602 U32 FastPathHostCompletions; /* 0x28 */ 2603 U32 FastPathFirmwareCompletions; /* 0x2C */ 2604 U32 NonFastPathRequestStarts; /* 0x30 */ 2605 U32 NonFastPathHostCompletions; /* 0x30 */ 2606 } MPI2_CONFIG_PAGE_SASIOUNIT16, 2607 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2608 Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t; 2609 2610 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2611 2612 2613 /**************************************************************************** 2614 * SAS Expander Config Pages 2615 ****************************************************************************/ 2616 2617 /* SAS Expander Page 0 */ 2618 2619 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 2620 { 2621 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2622 U8 PhysicalPort; /* 0x08 */ 2623 U8 ReportGenLength; /* 0x09 */ 2624 U16 EnclosureHandle; /* 0x0A */ 2625 U64 SASAddress; /* 0x0C */ 2626 U32 DiscoveryStatus; /* 0x14 */ 2627 U16 DevHandle; /* 0x18 */ 2628 U16 ParentDevHandle; /* 0x1A */ 2629 U16 ExpanderChangeCount; /* 0x1C */ 2630 U16 ExpanderRouteIndexes; /* 0x1E */ 2631 U8 NumPhys; /* 0x20 */ 2632 U8 SASLevel; /* 0x21 */ 2633 U16 Flags; /* 0x22 */ 2634 U16 STPBusInactivityTimeLimit; /* 0x24 */ 2635 U16 STPMaxConnectTimeLimit; /* 0x26 */ 2636 U16 STP_SMP_NexusLossTime; /* 0x28 */ 2637 U16 MaxNumRoutedSasAddresses; /* 0x2A */ 2638 U64 ActiveZoneManagerSASAddress;/* 0x2C */ 2639 U16 ZoneLockInactivityLimit; /* 0x34 */ 2640 U16 Reserved1; /* 0x36 */ 2641 U8 TimeToReducedFunc; /* 0x38 */ 2642 U8 InitialTimeToReducedFunc; /* 0x39 */ 2643 U8 MaxReducedFuncTime; /* 0x3A */ 2644 U8 Reserved2; /* 0x3B */ 2645 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2646 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 2647 2648 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2649 2650 /* values for SAS Expander Page 0 DiscoveryStatus field */ 2651 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2652 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2653 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2654 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2655 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2656 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2657 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2658 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2659 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2660 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2661 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2662 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2663 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2664 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2665 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2666 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2667 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2668 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2669 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2670 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2671 2672 /* values for SAS Expander Page 0 Flags field */ 2673 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2674 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2675 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2676 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2677 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2678 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2679 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2680 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2681 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2682 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2683 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2684 2685 2686 /* SAS Expander Page 1 */ 2687 2688 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 2689 { 2690 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2691 U8 PhysicalPort; /* 0x08 */ 2692 U8 Reserved1; /* 0x09 */ 2693 U16 Reserved2; /* 0x0A */ 2694 U8 NumPhys; /* 0x0C */ 2695 U8 Phy; /* 0x0D */ 2696 U16 NumTableEntriesProgrammed; /* 0x0E */ 2697 U8 ProgrammedLinkRate; /* 0x10 */ 2698 U8 HwLinkRate; /* 0x11 */ 2699 U16 AttachedDevHandle; /* 0x12 */ 2700 U32 PhyInfo; /* 0x14 */ 2701 U32 AttachedDeviceInfo; /* 0x18 */ 2702 U16 ExpanderDevHandle; /* 0x1C */ 2703 U8 ChangeCount; /* 0x1E */ 2704 U8 NegotiatedLinkRate; /* 0x1F */ 2705 U8 PhyIdentifier; /* 0x20 */ 2706 U8 AttachedPhyIdentifier; /* 0x21 */ 2707 U8 Reserved3; /* 0x22 */ 2708 U8 DiscoveryInfo; /* 0x23 */ 2709 U32 AttachedPhyInfo; /* 0x24 */ 2710 U8 ZoneGroup; /* 0x28 */ 2711 U8 SelfConfigStatus; /* 0x29 */ 2712 U16 Reserved4; /* 0x2A */ 2713 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2714 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 2715 2716 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2717 2718 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2719 2720 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2721 2722 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2723 2724 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 2725 2726 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2727 2728 /* values for SAS Expander Page 1 DiscoveryInfo field */ 2729 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2730 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2731 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2732 2733 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2734 2735 2736 /**************************************************************************** 2737 * SAS Device Config Pages 2738 ****************************************************************************/ 2739 2740 /* SAS Device Page 0 */ 2741 2742 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 2743 { 2744 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2745 U16 Slot; /* 0x08 */ 2746 U16 EnclosureHandle; /* 0x0A */ 2747 U64 SASAddress; /* 0x0C */ 2748 U16 ParentDevHandle; /* 0x14 */ 2749 U8 PhyNum; /* 0x16 */ 2750 U8 AccessStatus; /* 0x17 */ 2751 U16 DevHandle; /* 0x18 */ 2752 U8 AttachedPhyIdentifier; /* 0x1A */ 2753 U8 ZoneGroup; /* 0x1B */ 2754 U32 DeviceInfo; /* 0x1C */ 2755 U16 Flags; /* 0x20 */ 2756 U8 PhysicalPort; /* 0x22 */ 2757 U8 MaxPortConnections; /* 0x23 */ 2758 U64 DeviceName; /* 0x24 */ 2759 U8 PortGroups; /* 0x2C */ 2760 U8 DmaGroup; /* 0x2D */ 2761 U8 ControlGroup; /* 0x2E */ 2762 U8 EnclosureLevel; /* 0x2F */ 2763 U8 ConnectorName[4]; /* 0x30 */ 2764 U32 Reserved3; /* 0x34 */ 2765 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2766 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 2767 2768 #define MPI2_SASDEVICE0_PAGEVERSION (0x09) 2769 2770 /* values for SAS Device Page 0 AccessStatus field */ 2771 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2772 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2773 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2774 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2775 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2776 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2777 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2778 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2779 /* specific values for SATA Init failures */ 2780 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2781 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2782 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2783 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2784 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2785 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2786 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2787 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2788 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2789 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2790 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2791 2792 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2793 2794 /* values for SAS Device Page 0 Flags field */ 2795 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2796 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2797 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2798 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2799 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2800 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2801 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2802 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2803 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2804 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2805 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2806 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2807 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2808 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) 2809 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) 2810 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2811 2812 /* SAS Device Page 1 */ 2813 2814 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 2815 { 2816 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2817 U32 Reserved1; /* 0x08 */ 2818 U64 SASAddress; /* 0x0C */ 2819 U32 Reserved2; /* 0x14 */ 2820 U16 DevHandle; /* 0x18 */ 2821 U16 Reserved3; /* 0x1A */ 2822 U8 InitialRegDeviceFIS[20];/* 0x1C */ 2823 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2824 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 2825 2826 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2827 2828 2829 /**************************************************************************** 2830 * SAS PHY Config Pages 2831 ****************************************************************************/ 2832 2833 /* SAS PHY Page 0 */ 2834 2835 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 2836 { 2837 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2838 U16 OwnerDevHandle; /* 0x08 */ 2839 U16 Reserved1; /* 0x0A */ 2840 U16 AttachedDevHandle; /* 0x0C */ 2841 U8 AttachedPhyIdentifier; /* 0x0E */ 2842 U8 Reserved2; /* 0x0F */ 2843 U32 AttachedPhyInfo; /* 0x10 */ 2844 U8 ProgrammedLinkRate; /* 0x14 */ 2845 U8 HwLinkRate; /* 0x15 */ 2846 U8 ChangeCount; /* 0x16 */ 2847 U8 Flags; /* 0x17 */ 2848 U32 PhyInfo; /* 0x18 */ 2849 U8 NegotiatedLinkRate; /* 0x1C */ 2850 U8 Reserved3; /* 0x1D */ 2851 U16 Reserved4; /* 0x1E */ 2852 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2853 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 2854 2855 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2856 2857 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2858 2859 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2860 2861 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2862 2863 /* values for SAS PHY Page 0 Flags field */ 2864 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2865 2866 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2867 2868 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2869 2870 2871 /* SAS PHY Page 1 */ 2872 2873 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 2874 { 2875 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2876 U32 Reserved1; /* 0x08 */ 2877 U32 InvalidDwordCount; /* 0x0C */ 2878 U32 RunningDisparityErrorCount; /* 0x10 */ 2879 U32 LossDwordSynchCount; /* 0x14 */ 2880 U32 PhyResetProblemCount; /* 0x18 */ 2881 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2882 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 2883 2884 #define MPI2_SASPHY1_PAGEVERSION (0x01) 2885 2886 2887 /* SAS PHY Page 2 */ 2888 2889 typedef struct _MPI2_SASPHY2_PHY_EVENT 2890 { 2891 U8 PhyEventCode; /* 0x00 */ 2892 U8 Reserved1; /* 0x01 */ 2893 U16 Reserved2; /* 0x02 */ 2894 U32 PhyEventInfo; /* 0x04 */ 2895 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT, 2896 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t; 2897 2898 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2899 2900 2901 /* 2902 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2903 * one and check the value returned for NumPhyEvents at runtime. 2904 */ 2905 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2906 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2907 #endif 2908 2909 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 2910 { 2911 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2912 U32 Reserved1; /* 0x08 */ 2913 U8 NumPhyEvents; /* 0x0C */ 2914 U8 Reserved2; /* 0x0D */ 2915 U16 Reserved3; /* 0x0E */ 2916 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */ 2917 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2918 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t; 2919 2920 #define MPI2_SASPHY2_PAGEVERSION (0x00) 2921 2922 2923 /* SAS PHY Page 3 */ 2924 2925 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG 2926 { 2927 U8 PhyEventCode; /* 0x00 */ 2928 U8 Reserved1; /* 0x01 */ 2929 U16 Reserved2; /* 0x02 */ 2930 U8 CounterType; /* 0x04 */ 2931 U8 ThresholdWindow; /* 0x05 */ 2932 U8 TimeUnits; /* 0x06 */ 2933 U8 Reserved3; /* 0x07 */ 2934 U32 EventThreshold; /* 0x08 */ 2935 U16 ThresholdFlags; /* 0x0C */ 2936 U16 Reserved4; /* 0x0E */ 2937 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2938 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t; 2939 2940 /* values for PhyEventCode field */ 2941 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2942 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2943 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2944 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2945 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2946 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2947 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2948 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2949 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2950 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2951 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2952 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2953 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2954 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2955 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2956 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2957 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2958 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2959 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2960 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2961 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2962 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2963 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2964 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2965 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2966 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2967 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2968 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2969 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2970 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2971 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2972 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2973 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2974 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2975 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2976 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2977 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2978 /* Following codes are product specific and in MPI v2.6 and later */ 2979 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 2980 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 2981 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 2982 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 2983 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 2984 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 2985 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 2986 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 2987 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 2988 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 2989 2990 /* values for the CounterType field */ 2991 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 2992 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2993 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2994 2995 /* values for the TimeUnits field */ 2996 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 2997 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 2998 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 2999 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 3000 3001 /* values for the ThresholdFlags field */ 3002 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 3003 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 3004 3005 /* 3006 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3007 * one and check the value returned for NumPhyEvents at runtime. 3008 */ 3009 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 3010 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 3011 #endif 3012 3013 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 3014 { 3015 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3016 U32 Reserved1; /* 0x08 */ 3017 U8 NumPhyEvents; /* 0x0C */ 3018 U8 Reserved2; /* 0x0D */ 3019 U16 Reserved3; /* 0x0E */ 3020 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */ 3021 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 3022 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t; 3023 3024 #define MPI2_SASPHY3_PAGEVERSION (0x00) 3025 3026 3027 /* SAS PHY Page 4 */ 3028 3029 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 3030 { 3031 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3032 U16 Reserved1; /* 0x08 */ 3033 U8 Reserved2; /* 0x0A */ 3034 U8 Flags; /* 0x0B */ 3035 U8 InitialFrame[28]; /* 0x0C */ 3036 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 3037 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t; 3038 3039 #define MPI2_SASPHY4_PAGEVERSION (0x00) 3040 3041 /* values for the Flags field */ 3042 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 3043 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 3044 3045 3046 3047 3048 /**************************************************************************** 3049 * SAS Port Config Pages 3050 ****************************************************************************/ 3051 3052 /* SAS Port Page 0 */ 3053 3054 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 3055 { 3056 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3057 U8 PortNumber; /* 0x08 */ 3058 U8 PhysicalPort; /* 0x09 */ 3059 U8 PortWidth; /* 0x0A */ 3060 U8 PhysicalPortWidth; /* 0x0B */ 3061 U8 ZoneGroup; /* 0x0C */ 3062 U8 Reserved1; /* 0x0D */ 3063 U16 Reserved2; /* 0x0E */ 3064 U64 SASAddress; /* 0x10 */ 3065 U32 DeviceInfo; /* 0x18 */ 3066 U32 Reserved3; /* 0x1C */ 3067 U32 Reserved4; /* 0x20 */ 3068 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 3069 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 3070 3071 #define MPI2_SASPORT0_PAGEVERSION (0x00) 3072 3073 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 3074 3075 3076 /**************************************************************************** 3077 * SAS Enclosure Config Pages 3078 ****************************************************************************/ 3079 3080 /* SAS Enclosure Page 0, Enclosure Page 0 */ 3081 3082 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 3083 { 3084 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3085 U32 Reserved1; /* 0x08 */ 3086 U64 EnclosureLogicalID; /* 0x0C */ 3087 U16 Flags; /* 0x14 */ 3088 U16 EnclosureHandle; /* 0x16 */ 3089 U16 NumSlots; /* 0x18 */ 3090 U16 StartSlot; /* 0x1A */ 3091 U8 Reserved2; /* 0x1C */ 3092 U8 EnclosureLevel; /* 0x1D */ 3093 U16 SEPDevHandle; /* 0x1E */ 3094 U32 Reserved3; /* 0x20 */ 3095 U32 Reserved4; /* 0x24 */ 3096 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3097 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3098 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t, 3099 MPI26_CONFIG_PAGE_ENCLOSURE_0, 3100 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0, 3101 Mpi26EnclosurePage0_t, MPI2_POINTER pMpi26EnclosurePage0_t; 3102 3103 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) 3104 3105 /* values for SAS Enclosure Page 0 Flags field */ 3106 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3107 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3108 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3109 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3110 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3111 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3112 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3113 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3114 3115 #define MPI26_ENCLOSURE0_PAGEVERSION (0x04) 3116 3117 /* Values for Enclosure Page 0 Flags field */ 3118 #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3119 #define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F) 3120 #define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3121 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3122 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3123 #define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3124 #define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3125 #define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3126 3127 /**************************************************************************** 3128 * Log Config Page 3129 ****************************************************************************/ 3130 3131 /* Log Page 0 */ 3132 3133 /* 3134 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3135 * one and check the value returned for NumLogEntries at runtime. 3136 */ 3137 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 3138 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 3139 #endif 3140 3141 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3142 3143 typedef struct _MPI2_LOG_0_ENTRY 3144 { 3145 U64 TimeStamp; /* 0x00 */ 3146 U32 Reserved1; /* 0x08 */ 3147 U16 LogSequence; /* 0x0C */ 3148 U16 LogEntryQualifier; /* 0x0E */ 3149 U8 VP_ID; /* 0x10 */ 3150 U8 VF_ID; /* 0x11 */ 3151 U16 Reserved2; /* 0x12 */ 3152 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 3153 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 3154 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 3155 3156 /* values for Log Page 0 LogEntry LogEntryQualifier field */ 3157 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3158 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3159 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3160 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3161 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3162 3163 typedef struct _MPI2_CONFIG_PAGE_LOG_0 3164 { 3165 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3166 U32 Reserved1; /* 0x08 */ 3167 U32 Reserved2; /* 0x0C */ 3168 U16 NumLogEntries; /* 0x10 */ 3169 U16 Reserved3; /* 0x12 */ 3170 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 3171 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 3172 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 3173 3174 #define MPI2_LOG_0_PAGEVERSION (0x02) 3175 3176 3177 /**************************************************************************** 3178 * RAID Config Page 3179 ****************************************************************************/ 3180 3181 /* RAID Page 0 */ 3182 3183 /* 3184 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3185 * one and check the value returned for NumElements at runtime. 3186 */ 3187 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 3188 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 3189 #endif 3190 3191 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 3192 { 3193 U16 ElementFlags; /* 0x00 */ 3194 U16 VolDevHandle; /* 0x02 */ 3195 U8 HotSparePool; /* 0x04 */ 3196 U8 PhysDiskNum; /* 0x05 */ 3197 U16 PhysDiskDevHandle; /* 0x06 */ 3198 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3199 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3200 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 3201 3202 /* values for the ElementFlags field */ 3203 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3204 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3205 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3206 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3207 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3208 3209 3210 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 3211 { 3212 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3213 U8 NumHotSpares; /* 0x08 */ 3214 U8 NumPhysDisks; /* 0x09 */ 3215 U8 NumVolumes; /* 0x0A */ 3216 U8 ConfigNum; /* 0x0B */ 3217 U32 Flags; /* 0x0C */ 3218 U8 ConfigGUID[24]; /* 0x10 */ 3219 U32 Reserved1; /* 0x28 */ 3220 U8 NumElements; /* 0x2C */ 3221 U8 Reserved2; /* 0x2D */ 3222 U16 Reserved3; /* 0x2E */ 3223 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 3224 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3225 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3226 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 3227 3228 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3229 3230 /* values for RAID Configuration Page 0 Flags field */ 3231 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3232 3233 3234 /**************************************************************************** 3235 * Driver Persistent Mapping Config Pages 3236 ****************************************************************************/ 3237 3238 /* Driver Persistent Mapping Page 0 */ 3239 3240 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 3241 { 3242 U64 PhysicalIdentifier; /* 0x00 */ 3243 U16 MappingInformation; /* 0x08 */ 3244 U16 DeviceIndex; /* 0x0A */ 3245 U32 PhysicalBitsMapping; /* 0x0C */ 3246 U32 Reserved1; /* 0x10 */ 3247 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3248 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3249 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 3250 3251 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 3252 { 3253 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3254 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 3255 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3256 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3257 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 3258 3259 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3260 3261 /* values for Driver Persistent Mapping Page 0 MappingInformation field */ 3262 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3263 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3264 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3265 3266 3267 /**************************************************************************** 3268 * Ethernet Config Pages 3269 ****************************************************************************/ 3270 3271 /* Ethernet Page 0 */ 3272 3273 /* IP address (union of IPv4 and IPv6) */ 3274 typedef union _MPI2_ETHERNET_IP_ADDR 3275 { 3276 U32 IPv4Addr; 3277 U32 IPv6Addr[4]; 3278 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR, 3279 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t; 3280 3281 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3282 3283 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 3284 { 3285 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3286 U8 NumInterfaces; /* 0x08 */ 3287 U8 Reserved0; /* 0x09 */ 3288 U16 Reserved1; /* 0x0A */ 3289 U32 Status; /* 0x0C */ 3290 U8 MediaState; /* 0x10 */ 3291 U8 Reserved2; /* 0x11 */ 3292 U16 Reserved3; /* 0x12 */ 3293 U8 MacAddress[6]; /* 0x14 */ 3294 U8 Reserved4; /* 0x1A */ 3295 U8 Reserved5; /* 0x1B */ 3296 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */ 3297 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */ 3298 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */ 3299 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */ 3300 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */ 3301 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */ 3302 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 3303 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3304 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t; 3305 3306 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3307 3308 /* values for Ethernet Page 0 Status field */ 3309 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3310 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3311 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3312 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3313 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3314 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3315 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3316 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3317 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3318 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3319 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3320 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3321 3322 /* values for Ethernet Page 0 MediaState field */ 3323 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3324 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3325 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3326 3327 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3328 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3329 #define MPI2_ETHPG0_MS_10MBIT (0x01) 3330 #define MPI2_ETHPG0_MS_100MBIT (0x02) 3331 #define MPI2_ETHPG0_MS_1GBIT (0x03) 3332 3333 3334 /* Ethernet Page 1 */ 3335 3336 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 3337 { 3338 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3339 U32 Reserved0; /* 0x08 */ 3340 U32 Flags; /* 0x0C */ 3341 U8 MediaState; /* 0x10 */ 3342 U8 Reserved1; /* 0x11 */ 3343 U16 Reserved2; /* 0x12 */ 3344 U8 MacAddress[6]; /* 0x14 */ 3345 U8 Reserved3; /* 0x1A */ 3346 U8 Reserved4; /* 0x1B */ 3347 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */ 3348 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */ 3349 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */ 3350 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */ 3351 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */ 3352 U32 Reserved5; /* 0x6C */ 3353 U32 Reserved6; /* 0x70 */ 3354 U32 Reserved7; /* 0x74 */ 3355 U32 Reserved8; /* 0x78 */ 3356 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 3357 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3358 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t; 3359 3360 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3361 3362 /* values for Ethernet Page 1 Flags field */ 3363 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3364 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3365 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3366 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3367 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3368 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3369 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3370 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3371 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3372 3373 /* values for Ethernet Page 1 MediaState field */ 3374 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3375 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3376 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3377 3378 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3379 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3380 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3381 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3382 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3383 3384 3385 /**************************************************************************** 3386 * Extended Manufacturing Config Pages 3387 ****************************************************************************/ 3388 3389 /* 3390 * Generic structure to use for product-specific extended manufacturing pages 3391 * (currently Extended Manufacturing Page 40 through Extended Manufacturing 3392 * Page 60). 3393 */ 3394 3395 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS 3396 { 3397 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3398 U32 ProductSpecificInfo; /* 0x08 */ 3399 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 3400 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3401 Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t; 3402 3403 /* PageVersion should be provided by product-specific code */ 3404 3405 3406 /**************************************************************************** 3407 * values for fields used by several types of PCIe Config Pages 3408 ****************************************************************************/ 3409 3410 /* values for NegotiatedLinkRates fields */ 3411 #define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 3412 /* link rates used for Negotiated Physical Link Rate */ 3413 #define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 3414 #define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 3415 #define MPI26_PCIE_NEG_LINK_RATE_2_5 (0x02) 3416 #define MPI26_PCIE_NEG_LINK_RATE_5_0 (0x03) 3417 #define MPI26_PCIE_NEG_LINK_RATE_8_0 (0x04) 3418 #define MPI26_PCIE_NEG_LINK_RATE_16_0 (0x05) 3419 3420 3421 /**************************************************************************** 3422 * PCIe IO Unit Config Pages (MPI v2.6 and later) 3423 ****************************************************************************/ 3424 3425 /* PCIe IO Unit Page 0 */ 3426 3427 typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA 3428 { 3429 U8 Link; /* 0x00 */ 3430 U8 LinkFlags; /* 0x01 */ 3431 U8 PhyFlags; /* 0x02 */ 3432 U8 NegotiatedLinkRate; /* 0x03 */ 3433 U32 ControllerPhyDeviceInfo;/* 0x04 */ 3434 U16 AttachedDevHandle; /* 0x08 */ 3435 U16 ControllerDevHandle; /* 0x0A */ 3436 U32 EnumerationStatus; /* 0x0C */ 3437 U32 Reserved1; /* 0x10 */ 3438 } MPI26_PCIE_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA, 3439 Mpi26PCIeIOUnit0PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit0PhyData_t; 3440 3441 /* 3442 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3443 * one and check the value returned for NumPhys at runtime. 3444 */ 3445 #ifndef MPI26_PCIE_IOUNIT0_PHY_MAX 3446 #define MPI26_PCIE_IOUNIT0_PHY_MAX (1) 3447 #endif 3448 3449 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 3450 { 3451 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3452 U32 Reserved1; /* 0x08 */ 3453 U8 NumPhys; /* 0x0C */ 3454 U8 InitStatus; /* 0x0D */ 3455 U16 Reserved3; /* 0x0E */ 3456 MPI26_PCIE_IO_UNIT0_PHY_DATA PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX]; /* 0x10 */ 3457 } MPI26_CONFIG_PAGE_PIOUNIT_0, 3458 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_0, 3459 Mpi26PCIeIOUnitPage0_t, MPI2_POINTER pMpi26PCIeIOUnitPage0_t; 3460 3461 #define MPI26_PCIEIOUNITPAGE0_PAGEVERSION (0x00) 3462 3463 /* values for PCIe IO Unit Page 0 LinkFlags */ 3464 #define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08) 3465 3466 /* values for PCIe IO Unit Page 0 PhyFlags */ 3467 #define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 3468 3469 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3470 3471 /* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */ 3472 3473 /* values for PCIe IO Unit Page 0 EnumerationStatus */ 3474 #define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 3475 #define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED (0x20000000) 3476 3477 3478 /* PCIe IO Unit Page 1 */ 3479 3480 typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA 3481 { 3482 U8 Link; /* 0x00 */ 3483 U8 LinkFlags; /* 0x01 */ 3484 U8 PhyFlags; /* 0x02 */ 3485 U8 MaxMinLinkRate; /* 0x03 */ 3486 U32 ControllerPhyDeviceInfo; /* 0x04 */ 3487 U32 Reserved1; /* 0x08 */ 3488 } MPI26_PCIE_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA, 3489 Mpi26PCIeIOUnit1PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit1PhyData_t; 3490 3491 /* values for LinkFlags */ 3492 #define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS (0x00) 3493 #define MPI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS (0x01) 3494 3495 /* 3496 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3497 * one and check the value returned for NumPhys at runtime. 3498 */ 3499 #ifndef MPI26_PCIE_IOUNIT1_PHY_MAX 3500 #define MPI26_PCIE_IOUNIT1_PHY_MAX (1) 3501 #endif 3502 3503 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 3504 { 3505 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3506 U16 ControlFlags; /* 0x08 */ 3507 U16 Reserved; /* 0x0A */ 3508 U16 AdditionalControlFlags; /* 0x0C */ 3509 U16 NVMeMaxQueueDepth; /* 0x0E */ 3510 U8 NumPhys; /* 0x10 */ 3511 U8 Reserved1; /* 0x11 */ 3512 U16 Reserved2; /* 0x12 */ 3513 MPI26_PCIE_IO_UNIT1_PHY_DATA PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/* 0x14 */ 3514 } MPI26_CONFIG_PAGE_PIOUNIT_1, 3515 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_1, 3516 Mpi26PCIeIOUnitPage1_t, MPI2_POINTER pMpi26PCIeIOUnitPage1_t; 3517 3518 #define MPI26_PCIEIOUNITPAGE1_PAGEVERSION (0x00) 3519 3520 /* values for PCIe IO Unit Page 1 PhyFlags */ 3521 #define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 3522 #define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY (0x01) 3523 3524 /* values for PCIe IO Unit Page 1 MaxMinLinkRate */ 3525 #define MPI26_PCIEIOUNIT1_MAX_RATE_MASK (0xF0) 3526 #define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT (4) 3527 #define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 (0x20) 3528 #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 (0x30) 3529 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40) 3530 #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50) 3531 3532 /* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */ 3533 3534 3535 /**************************************************************************** 3536 * PCIe Switch Config Pages (MPI v2.6 and later) 3537 ****************************************************************************/ 3538 3539 /* PCIe Switch Page 0 */ 3540 3541 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 3542 { 3543 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3544 U8 PhysicalPort; /* 0x08 */ 3545 U8 Reserved1; /* 0x09 */ 3546 U16 Reserved2; /* 0x0A */ 3547 U16 DevHandle; /* 0x0C */ 3548 U16 ParentDevHandle; /* 0x0E */ 3549 U8 NumPorts; /* 0x10 */ 3550 U8 PCIeLevel; /* 0x11 */ 3551 U16 Reserved3; /* 0x12 */ 3552 U32 Reserved4; /* 0x14 */ 3553 U32 Reserved5; /* 0x18 */ 3554 U32 Reserved6; /* 0x1C */ 3555 } MPI26_CONFIG_PAGE_PSWITCH_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_0, 3556 Mpi26PCIeSwitchPage0_t, MPI2_POINTER pMpi26PCIeSwitchPage0_t; 3557 3558 #define MPI26_PCIESWITCH0_PAGEVERSION (0x00) 3559 3560 3561 /* PCIe Switch Page 1 */ 3562 3563 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 3564 { 3565 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3566 U8 PhysicalPort; /* 0x08 */ 3567 U8 Reserved1; /* 0x09 */ 3568 U16 Reserved2; /* 0x0A */ 3569 U8 NumPorts; /* 0x0C */ 3570 U8 PortNum; /* 0x0D */ 3571 U16 AttachedDevHandle; /* 0x0E */ 3572 U16 SwitchDevHandle; /* 0x10 */ 3573 U8 NegotiatedPortWidth; /* 0x12 */ 3574 U8 NegotiatedLinkRate; /* 0x13 */ 3575 U32 Reserved4; /* 0x14 */ 3576 U32 Reserved5; /* 0x18 */ 3577 } MPI26_CONFIG_PAGE_PSWITCH_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_1, 3578 Mpi26PCIeSwitchPage1_t, MPI2_POINTER pMpi26PCIeSwitchPage1_t; 3579 3580 #define MPI26_PCIESWITCH1_PAGEVERSION (0x00) 3581 3582 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3583 3584 3585 /**************************************************************************** 3586 * PCIe Device Config Pages (MPI v2.6 and later) 3587 ****************************************************************************/ 3588 3589 /* PCIe Device Page 0 */ 3590 3591 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 3592 { 3593 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3594 U16 Slot; /* 0x08 */ 3595 U16 EnclosureHandle; /* 0x0A */ 3596 U64 WWID; /* 0x0C */ 3597 U16 ParentDevHandle; /* 0x14 */ 3598 U8 PortNum; /* 0x16 */ 3599 U8 AccessStatus; /* 0x17 */ 3600 U16 DevHandle; /* 0x18 */ 3601 U8 PhysicalPort; /* 0x1A */ 3602 U8 Reserved1; /* 0x1B */ 3603 U32 DeviceInfo; /* 0x1C */ 3604 U32 Flags; /* 0x20 */ 3605 U8 SupportedLinkRates; /* 0x24 */ 3606 U8 MaxPortWidth; /* 0x25 */ 3607 U8 NegotiatedPortWidth; /* 0x26 */ 3608 U8 NegotiatedLinkRate; /* 0x27 */ 3609 U8 EnclosureLevel; /* 0x28 */ 3610 U8 Reserved2; /* 0x29 */ 3611 U16 Reserved3; /* 0x2A */ 3612 U8 ConnectorName[4]; /* 0x2C */ 3613 U32 Reserved4; /* 0x30 */ 3614 U32 Reserved5; /* 0x34 */ 3615 } MPI26_CONFIG_PAGE_PCIEDEV_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_0, 3616 Mpi26PCIeDevicePage0_t, MPI2_POINTER pMpi26PCIeDevicePage0_t; 3617 3618 #define MPI26_PCIEDEVICE0_PAGEVERSION (0x01) 3619 3620 /* values for PCIe Device Page 0 AccessStatus field */ 3621 #define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS (0x00) 3622 #define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION (0x04) 3623 #define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED (0x02) 3624 #define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED (0x07) 3625 #define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED (0x08) 3626 #define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE (0x09) 3627 #define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED (0x0A) 3628 #define MPI26_PCIEDEV0_ASTATUS_UNKNOWN (0x10) 3629 3630 #define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT (0x30) 3631 #define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x31) 3632 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED (0x32) 3633 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED (0x33) 3634 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED (0x34) 3635 #define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED (0x35) 3636 #define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36) 3637 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT (0x37) 3638 #define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS (0x38) 3639 3640 #define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX (0x3F) 3641 3642 /* see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo field */ 3643 3644 /* values for PCIe Device Page 0 Flags field */ 3645 #define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 3646 #define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x4000) 3647 #define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x2000) 3648 #define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x0400) 3649 #define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x0200) 3650 #define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 3651 #define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x0080) 3652 #define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x0040) 3653 #define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x0020) 3654 #define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x0010) 3655 #define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x0002) 3656 #define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x0001) 3657 3658 /* values for PCIe Device Page 0 SupportedLinkRates field */ 3659 #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08) 3660 #define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED (0x04) 3661 #define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED (0x02) 3662 #define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED (0x01) 3663 3664 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3665 3666 3667 /* PCIe Device Page 2 */ 3668 3669 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 3670 { 3671 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3672 U16 DevHandle; /* 0x08 */ 3673 U16 Reserved1; /* 0x0A */ 3674 U32 MaximumDataTransferSize;/* 0x0C */ 3675 U32 Capabilities; /* 0x10 */ 3676 U32 Reserved2; /* 0x14 */ 3677 } MPI26_CONFIG_PAGE_PCIEDEV_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_2, 3678 Mpi26PCIeDevicePage2_t, MPI2_POINTER pMpi26PCIeDevicePage2_t; 3679 3680 #define MPI26_PCIEDEVICE2_PAGEVERSION (0x00) 3681 3682 /* defines for PCIe Device Page 2 Capabilities field */ 3683 #define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004) 3684 #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002) 3685 #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001) 3686 3687 3688 /**************************************************************************** 3689 * PCIe Link Config Pages (MPI v2.6 and later) 3690 ****************************************************************************/ 3691 3692 /* PCIe Link Page 1 */ 3693 3694 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 3695 { 3696 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3697 U8 Link; /* 0x08 */ 3698 U8 Reserved1; /* 0x09 */ 3699 U16 Reserved2; /* 0x0A */ 3700 U32 CorrectableErrorCount; /* 0x0C */ 3701 U16 NonFatalErrorCount; /* 0x10 */ 3702 U16 Reserved3; /* 0x12 */ 3703 U16 FatalErrorCount; /* 0x14 */ 3704 U16 Reserved4; /* 0x16 */ 3705 } MPI26_CONFIG_PAGE_PCIELINK_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_1, 3706 Mpi26PcieLinkPage1_t, MPI2_POINTER pMpi26PcieLinkPage1_t; 3707 3708 #define MPI26_PCIELINK1_PAGEVERSION (0x00) 3709 3710 /* PCIe Link Page 2 */ 3711 3712 typedef struct _MPI26_PCIELINK2_LINK_EVENT 3713 { 3714 U8 LinkEventCode; /* 0x00 */ 3715 U8 Reserved1; /* 0x01 */ 3716 U16 Reserved2; /* 0x02 */ 3717 U32 LinkEventInfo; /* 0x04 */ 3718 } MPI26_PCIELINK2_LINK_EVENT, MPI2_POINTER PTR_MPI26_PCIELINK2_LINK_EVENT, 3719 Mpi26PcieLink2LinkEvent_t, MPI2_POINTER pMpi26PcieLink2LinkEvent_t; 3720 3721 /* use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */ 3722 3723 3724 /* 3725 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3726 * one and check the value returned for NumLinkEvents at runtime. 3727 */ 3728 #ifndef MPI26_PCIELINK2_LINK_EVENT_MAX 3729 #define MPI26_PCIELINK2_LINK_EVENT_MAX (1) 3730 #endif 3731 3732 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 3733 { 3734 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3735 U8 Link; /* 0x08 */ 3736 U8 Reserved1; /* 0x09 */ 3737 U16 Reserved2; /* 0x0A */ 3738 U8 NumLinkEvents; /* 0x0C */ 3739 U8 Reserved3; /* 0x0D */ 3740 U16 Reserved4; /* 0x0E */ 3741 MPI26_PCIELINK2_LINK_EVENT LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX]; /* 0x10 */ 3742 } MPI26_CONFIG_PAGE_PCIELINK_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_2, 3743 Mpi26PcieLinkPage2_t, MPI2_POINTER pMpi26PcieLinkPage2_t; 3744 3745 #define MPI26_PCIELINK2_PAGEVERSION (0x00) 3746 3747 3748 /* PCIe Link Page 3 */ 3749 3750 typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG 3751 { 3752 U8 LinkEventCode; /* 0x00 */ 3753 U8 Reserved1; /* 0x01 */ 3754 U16 Reserved2; /* 0x02 */ 3755 U8 CounterType; /* 0x04 */ 3756 U8 ThresholdWindow; /* 0x05 */ 3757 U8 TimeUnits; /* 0x06 */ 3758 U8 Reserved3; /* 0x07 */ 3759 U32 EventThreshold; /* 0x08 */ 3760 U16 ThresholdFlags; /* 0x0C */ 3761 U16 Reserved4; /* 0x0E */ 3762 } MPI26_PCIELINK3_LINK_EVENT_CONFIG, MPI2_POINTER PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG, 3763 Mpi26PcieLink3LinkEventConfig_t, MPI2_POINTER pMpi26PcieLink3LinkEventConfig_t; 3764 3765 /* values for LinkEventCode field */ 3766 #define MPI26_PCIELINK3_EVTCODE_NO_EVENT (0x00) 3767 #define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED (0x01) 3768 #define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED (0x02) 3769 #define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED (0x03) 3770 #define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED (0x04) 3771 #define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED (0x05) 3772 #define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED (0x06) 3773 #define MPI26_PCIELINK3_EVTCODE_POISONED_TLP (0x07) 3774 #define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP (0x08) 3775 #define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP (0x09) 3776 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE (0x0A) 3777 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE (0x0B) 3778 #define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE (0x0C) 3779 #define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE (0x0D) 3780 #define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE (0x0E) 3781 #define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE (0x0F) 3782 #define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR (0x10) 3783 #define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR (0x11) 3784 #define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR (0x12) 3785 3786 /* values for the CounterType field */ 3787 #define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING (0x00) 3788 #define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING (0x01) 3789 #define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE (0x02) 3790 3791 /* values for the TimeUnits field */ 3792 #define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS (0x00) 3793 #define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS (0x01) 3794 #define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND (0x02) 3795 #define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS (0x03) 3796 3797 /* values for the ThresholdFlags field */ 3798 #define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY (0x0001) 3799 3800 /* 3801 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3802 * one and check the value returned for NumLinkEvents at runtime. 3803 */ 3804 #ifndef MPI26_PCIELINK3_LINK_EVENT_MAX 3805 #define MPI26_PCIELINK3_LINK_EVENT_MAX (1) 3806 #endif 3807 3808 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 3809 { 3810 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3811 U8 Link; /* 0x08 */ 3812 U8 Reserved1; /* 0x09 */ 3813 U16 Reserved2; /* 0x0A */ 3814 U8 NumLinkEvents; /* 0x0C */ 3815 U8 Reserved3; /* 0x0D */ 3816 U16 Reserved4; /* 0x0E */ 3817 MPI26_PCIELINK3_LINK_EVENT_CONFIG LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /* 0x10 */ 3818 } MPI26_CONFIG_PAGE_PCIELINK_3, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_3, 3819 Mpi26PcieLinkPage3_t, MPI2_POINTER pMpi26PcieLinkPage3_t; 3820 3821 #define MPI26_PCIELINK3_PAGEVERSION (0x00) 3822 3823 3824 #endif 3825 3826