1 /*- 2 * Copyright (c) 2012-2015 LSI Corp. 3 * Copyright (c) 2013-2016 Avago Technologies 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Copyright (c) 2000-2015 LSI Corporation. 33 * Copyright (c) 2013-2016 Avago Technologies 34 * All rights reserved. 35 * 36 * 37 * Name: mpi2_ioc.h 38 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 39 * Creation Date: October 11, 2006 40 * 41 * mpi2_ioc.h Version: 02.00.30 42 * 43 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 44 * prefix are for use only on MPI v2.5 products, and must not be used 45 * with MPI v2.0 products. Unless otherwise noted, names beginning with 46 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 47 * 48 * Version History 49 * --------------- 50 * 51 * Date Version Description 52 * -------- -------- ------------------------------------------------------ 53 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 54 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to 55 * MaxTargets. 56 * Added TotalImageSize field to FWDownload Request. 57 * Added reserved words to FWUpload Request. 58 * 06-26-07 02.00.02 Added IR Configuration Change List Event. 59 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit 60 * request and replaced it with 61 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. 62 * Replaced the MinReplyQueueDepth field of the IOCFacts 63 * reply with MaxReplyDescriptorPostQueueDepth. 64 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum 65 * depth for the Reply Descriptor Post Queue. 66 * Added SASAddress field to Initiator Device Table 67 * Overflow Event data. 68 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING 69 * for SAS Initiator Device Status Change Event data. 70 * Modified Reason Code defines for SAS Topology Change 71 * List Event data, including adding a bit for PHY Vacant 72 * status, and adding a mask for the Reason Code. 73 * Added define for 74 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. 75 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. 76 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of 77 * the IOCFacts Reply. 78 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 79 * Moved MPI2_VERSION_UNION to mpi2.h. 80 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks 81 * instead of enables, and added SASBroadcastPrimitiveMasks 82 * field. 83 * Added Log Entry Added Event and related structure. 84 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. 85 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. 86 * Added MaxVolumes and MaxPersistentEntries fields to 87 * IOCFacts reply. 88 * Added ProtocalFlags and IOCCapabilities fields to 89 * MPI2_FW_IMAGE_HEADER. 90 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. 91 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to 92 * a U16 (from a U32). 93 * Removed extra 's' from EventMasks name. 94 * 06-27-08 02.00.08 Fixed an offset in a comment. 95 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. 96 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and 97 * renamed MinReplyFrameSize to ReplyFrameSize. 98 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. 99 * Added two new RAIDOperation values for Integrated RAID 100 * Operations Status Event data. 101 * Added four new IR Configuration Change List Event data 102 * ReasonCode values. 103 * Added two new ReasonCode defines for SAS Device Status 104 * Change Event data. 105 * Added three new DiscoveryStatus bits for the SAS 106 * Discovery event data. 107 * Added Multiplexing Status Change bit to the PhyStatus 108 * field of the SAS Topology Change List event data. 109 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. 110 * BootFlags are now product-specific. 111 * Added defines for the indivdual signature bytes 112 * for MPI2_INIT_IMAGE_FOOTER. 113 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. 114 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR 115 * define. 116 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE 117 * define. 118 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. 119 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define. 120 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define. 121 * Added two new reason codes for SAS Device Status Change 122 * Event. 123 * Added new event: SAS PHY Counter. 124 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure. 125 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 126 * Added new product id family for 2208. 127 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST. 128 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY. 129 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY. 130 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY. 131 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define. 132 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define. 133 * Added Host Based Discovery Phy Event data. 134 * Added defines for ProductID Product field 135 * (MPI2_FW_HEADER_PID_). 136 * Modified values for SAS ProductID Family 137 * (MPI2_FW_HEADER_PID_FAMILY_). 138 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines. 139 * Added PowerManagementControl Request structures and 140 * defines. 141 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete. 142 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define. 143 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC. 144 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added 145 * SASNotifyPrimitiveMasks field to 146 * MPI2_EVENT_NOTIFICATION_REQUEST. 147 * Added Temperature Threshold Event. 148 * Added Host Message Event. 149 * Added Send Host Message request and reply. 150 * 05-25-11 02.00.18 For Extended Image Header, added 151 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and 152 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines. 153 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define. 154 * 08-24-11 02.00.19 Added PhysicalPort field to 155 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure. 156 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete. 157 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5. 158 * 03-29-12 02.00.21 Added a product specific range to event values. 159 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE. 160 * Added ElapsedSeconds field to 161 * MPI2_EVENT_DATA_IR_OPERATION_STATUS. 162 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE 163 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY. 164 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE. 165 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY. 166 * Added Encrypted Hash Extended Image. 167 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS. 168 * 11-18-14 02.00.25 Updated copyright information. 169 * 03-16-15 02.00.26 Updated for MPI v2.6. 170 * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and 171 * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT. 172 * Added MPI2_EVENT_PCIE_LINK_COUNTER and 173 * MPI26_EVENT_DATA_PCIE_LINK_COUNTER. 174 * Added MPI26_CTRL_OP_SHUTDOWN. 175 * Added MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG 176 * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and 177 * MPI26_FW_HEADER_PID_FAMILY_3516_SAS. 178 * 08-25-15 02.00.27 Added IC ARCH Class based signature defines. 179 * Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event. 180 * Added ConigurationFlags field to IOCInit message to 181 * support NVMe SGL format control. 182 * Added PCIe SRIOV support. 183 * 02-17-16 02.00.28 Added SAS 4 22.5 gbs speed support. 184 * Added PCIe 4 16.0 GT/sec speec support. 185 * Removed AHCI support. 186 * Removed SOP support. 187 * 07-01-16 02.00.29 Added Archclass for 4008 product. 188 * Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED 189 * 08-23-16 02.00.30 Added new defines for the ImageType field of FWDownload 190 * Request Message. 191 * Added new defines for the ImageType field of FWUpload 192 * Request Message. 193 * Added new values for the RegionType field in the Layout 194 * Data sections of the FLASH Layout Extended Image Data. 195 * Added new defines for the ReasonCode field of 196 * Active Cable Exception Event. 197 * Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and 198 * MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE. 199 * -------------------------------------------------------------------------- 200 */ 201 202 #ifndef MPI2_IOC_H 203 #define MPI2_IOC_H 204 205 /***************************************************************************** 206 * 207 * IOC Messages 208 * 209 *****************************************************************************/ 210 211 /**************************************************************************** 212 * IOCInit message 213 ****************************************************************************/ 214 215 /* IOCInit Request message */ 216 typedef struct _MPI2_IOC_INIT_REQUEST 217 { 218 U8 WhoInit; /* 0x00 */ 219 U8 Reserved1; /* 0x01 */ 220 U8 ChainOffset; /* 0x02 */ 221 U8 Function; /* 0x03 */ 222 U16 Reserved2; /* 0x04 */ 223 U8 Reserved3; /* 0x06 */ 224 U8 MsgFlags; /* 0x07 */ 225 U8 VP_ID; /* 0x08 */ 226 U8 VF_ID; /* 0x09 */ 227 U16 Reserved4; /* 0x0A */ 228 U16 MsgVersion; /* 0x0C */ 229 U16 HeaderVersion; /* 0x0E */ 230 U32 Reserved5; /* 0x10 */ 231 U16 ConfigurationFlags; /* 0x14 */ 232 U8 HostPageSize; /* 0x16 */ 233 U8 HostMSIxVectors; /* 0x17 */ 234 U16 Reserved8; /* 0x18 */ 235 U16 SystemRequestFrameSize; /* 0x1A */ 236 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 237 U16 ReplyFreeQueueDepth; /* 0x1E */ 238 U32 SenseBufferAddressHigh; /* 0x20 */ 239 U32 SystemReplyAddressHigh; /* 0x24 */ 240 U64 SystemRequestFrameBaseAddress; /* 0x28 */ 241 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 242 U64 ReplyFreeQueueAddress; /* 0x38 */ 243 U64 TimeStamp; /* 0x40 */ 244 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 245 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 246 247 /* WhoInit values */ 248 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 249 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 250 #define MPI2_WHOINIT_ROM_BIOS (0x02) 251 #define MPI2_WHOINIT_PCI_PEER (0x03) 252 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 253 #define MPI2_WHOINIT_MANUFACTURER (0x05) 254 255 /* MsgFlags */ 256 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) 257 258 /* MsgVersion */ 259 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 260 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 261 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 262 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 263 264 /* HeaderVersion */ 265 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) 266 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) 267 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) 268 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) 269 270 /* ConfigurationFlags */ 271 #define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT (0x0001) 272 273 /* minimum depth for a Reply Descriptor Post Queue */ 274 #define MPI2_RDPQ_DEPTH_MIN (16) 275 276 /* Reply Descriptor Post Queue Array Entry */ 277 typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY 278 { 279 U64 RDPQBaseAddress; /* 0x00 */ 280 U32 Reserved1; /* 0x08 */ 281 U32 Reserved2; /* 0x0C */ 282 } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 283 MPI2_POINTER PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 284 Mpi2IOCInitRDPQArrayEntry, MPI2_POINTER pMpi2IOCInitRDPQArrayEntry; 285 286 /* IOCInit Reply message */ 287 typedef struct _MPI2_IOC_INIT_REPLY 288 { 289 U8 WhoInit; /* 0x00 */ 290 U8 Reserved1; /* 0x01 */ 291 U8 MsgLength; /* 0x02 */ 292 U8 Function; /* 0x03 */ 293 U16 Reserved2; /* 0x04 */ 294 U8 Reserved3; /* 0x06 */ 295 U8 MsgFlags; /* 0x07 */ 296 U8 VP_ID; /* 0x08 */ 297 U8 VF_ID; /* 0x09 */ 298 U16 Reserved4; /* 0x0A */ 299 U16 Reserved5; /* 0x0C */ 300 U16 IOCStatus; /* 0x0E */ 301 U32 IOCLogInfo; /* 0x10 */ 302 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY, 303 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t; 304 305 306 /**************************************************************************** 307 * IOCFacts message 308 ****************************************************************************/ 309 310 /* IOCFacts Request message */ 311 typedef struct _MPI2_IOC_FACTS_REQUEST 312 { 313 U16 Reserved1; /* 0x00 */ 314 U8 ChainOffset; /* 0x02 */ 315 U8 Function; /* 0x03 */ 316 U16 Reserved2; /* 0x04 */ 317 U8 Reserved3; /* 0x06 */ 318 U8 MsgFlags; /* 0x07 */ 319 U8 VP_ID; /* 0x08 */ 320 U8 VF_ID; /* 0x09 */ 321 U16 Reserved4; /* 0x0A */ 322 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST, 323 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t; 324 325 326 /* IOCFacts Reply message */ 327 typedef struct _MPI2_IOC_FACTS_REPLY 328 { 329 U16 MsgVersion; /* 0x00 */ 330 U8 MsgLength; /* 0x02 */ 331 U8 Function; /* 0x03 */ 332 U16 HeaderVersion; /* 0x04 */ 333 U8 IOCNumber; /* 0x06 */ 334 U8 MsgFlags; /* 0x07 */ 335 U8 VP_ID; /* 0x08 */ 336 U8 VF_ID; /* 0x09 */ 337 U16 Reserved1; /* 0x0A */ 338 U16 IOCExceptions; /* 0x0C */ 339 U16 IOCStatus; /* 0x0E */ 340 U32 IOCLogInfo; /* 0x10 */ 341 U8 MaxChainDepth; /* 0x14 */ 342 U8 WhoInit; /* 0x15 */ 343 U8 NumberOfPorts; /* 0x16 */ 344 U8 MaxMSIxVectors; /* 0x17 */ 345 U16 RequestCredit; /* 0x18 */ 346 U16 ProductID; /* 0x1A */ 347 U32 IOCCapabilities; /* 0x1C */ 348 MPI2_VERSION_UNION FWVersion; /* 0x20 */ 349 U16 IOCRequestFrameSize; /* 0x24 */ 350 U16 IOCMaxChainSegmentSize; /* 0x26 */ /* MPI 2.5 only; Reserved in MPI 2.0 */ 351 U16 MaxInitiators; /* 0x28 */ 352 U16 MaxTargets; /* 0x2A */ 353 U16 MaxSasExpanders; /* 0x2C */ 354 U16 MaxEnclosures; /* 0x2E */ 355 U16 ProtocolFlags; /* 0x30 */ 356 U16 HighPriorityCredit; /* 0x32 */ 357 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */ 358 U8 ReplyFrameSize; /* 0x36 */ 359 U8 MaxVolumes; /* 0x37 */ 360 U16 MaxDevHandle; /* 0x38 */ 361 U16 MaxPersistentEntries; /* 0x3A */ 362 U16 MinDevHandle; /* 0x3C */ 363 U8 CurrentHostPageSize; /* 0x3E */ 364 U8 Reserved4; /* 0x3F */ 365 U8 SGEModifierMask; /* 0x40 */ 366 U8 SGEModifierValue; /* 0x41 */ 367 U8 SGEModifierShift; /* 0x42 */ 368 U8 Reserved5; /* 0x43 */ 369 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY, 370 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t; 371 372 /* MsgVersion */ 373 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 374 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 375 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 376 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 377 378 /* HeaderVersion */ 379 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 380 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 381 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 382 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 383 384 /* IOCExceptions */ 385 #define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0400) 386 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200) 387 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) 388 389 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) 390 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) 391 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) 392 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) 393 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) 394 395 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 396 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) 397 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 398 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 399 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 400 401 /* defines for WhoInit field are after the IOCInit Request */ 402 403 /* ProductID field uses MPI2_FW_HEADER_PID_ */ 404 405 /* IOCCapabilities */ 406 #define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV (0x00100000) 407 #define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000) 408 #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000) 409 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000) 410 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) 411 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000) 412 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000) 413 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) 414 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) 415 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) 416 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 417 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) 418 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) 419 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 420 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 421 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 422 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) 423 424 /* ProtocolFlags */ 425 #define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES (0x0008) /* MPI v2.6 and later */ 426 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 427 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 428 429 430 /**************************************************************************** 431 * PortFacts message 432 ****************************************************************************/ 433 434 /* PortFacts Request message */ 435 typedef struct _MPI2_PORT_FACTS_REQUEST 436 { 437 U16 Reserved1; /* 0x00 */ 438 U8 ChainOffset; /* 0x02 */ 439 U8 Function; /* 0x03 */ 440 U16 Reserved2; /* 0x04 */ 441 U8 PortNumber; /* 0x06 */ 442 U8 MsgFlags; /* 0x07 */ 443 U8 VP_ID; /* 0x08 */ 444 U8 VF_ID; /* 0x09 */ 445 U16 Reserved3; /* 0x0A */ 446 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST, 447 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t; 448 449 /* PortFacts Reply message */ 450 typedef struct _MPI2_PORT_FACTS_REPLY 451 { 452 U16 Reserved1; /* 0x00 */ 453 U8 MsgLength; /* 0x02 */ 454 U8 Function; /* 0x03 */ 455 U16 Reserved2; /* 0x04 */ 456 U8 PortNumber; /* 0x06 */ 457 U8 MsgFlags; /* 0x07 */ 458 U8 VP_ID; /* 0x08 */ 459 U8 VF_ID; /* 0x09 */ 460 U16 Reserved3; /* 0x0A */ 461 U16 Reserved4; /* 0x0C */ 462 U16 IOCStatus; /* 0x0E */ 463 U32 IOCLogInfo; /* 0x10 */ 464 U8 Reserved5; /* 0x14 */ 465 U8 PortType; /* 0x15 */ 466 U16 Reserved6; /* 0x16 */ 467 U16 MaxPostedCmdBuffers; /* 0x18 */ 468 U16 Reserved7; /* 0x1A */ 469 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY, 470 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t; 471 472 /* PortType values */ 473 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) 474 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10) 475 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) 476 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 477 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 478 #define MPI2_PORTFACTS_PORTTYPE_TRI_MODE (0x40) /* MPI v2.6 and later */ 479 480 481 /**************************************************************************** 482 * PortEnable message 483 ****************************************************************************/ 484 485 /* PortEnable Request message */ 486 typedef struct _MPI2_PORT_ENABLE_REQUEST 487 { 488 U16 Reserved1; /* 0x00 */ 489 U8 ChainOffset; /* 0x02 */ 490 U8 Function; /* 0x03 */ 491 U8 Reserved2; /* 0x04 */ 492 U8 PortFlags; /* 0x05 */ 493 U8 Reserved3; /* 0x06 */ 494 U8 MsgFlags; /* 0x07 */ 495 U8 VP_ID; /* 0x08 */ 496 U8 VF_ID; /* 0x09 */ 497 U16 Reserved4; /* 0x0A */ 498 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST, 499 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t; 500 501 502 /* PortEnable Reply message */ 503 typedef struct _MPI2_PORT_ENABLE_REPLY 504 { 505 U16 Reserved1; /* 0x00 */ 506 U8 MsgLength; /* 0x02 */ 507 U8 Function; /* 0x03 */ 508 U8 Reserved2; /* 0x04 */ 509 U8 PortFlags; /* 0x05 */ 510 U8 Reserved3; /* 0x06 */ 511 U8 MsgFlags; /* 0x07 */ 512 U8 VP_ID; /* 0x08 */ 513 U8 VF_ID; /* 0x09 */ 514 U16 Reserved4; /* 0x0A */ 515 U16 Reserved5; /* 0x0C */ 516 U16 IOCStatus; /* 0x0E */ 517 U32 IOCLogInfo; /* 0x10 */ 518 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY, 519 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t; 520 521 522 /**************************************************************************** 523 * EventNotification message 524 ****************************************************************************/ 525 526 /* EventNotification Request message */ 527 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) 528 529 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST 530 { 531 U16 Reserved1; /* 0x00 */ 532 U8 ChainOffset; /* 0x02 */ 533 U8 Function; /* 0x03 */ 534 U16 Reserved2; /* 0x04 */ 535 U8 Reserved3; /* 0x06 */ 536 U8 MsgFlags; /* 0x07 */ 537 U8 VP_ID; /* 0x08 */ 538 U8 VF_ID; /* 0x09 */ 539 U16 Reserved4; /* 0x0A */ 540 U32 Reserved5; /* 0x0C */ 541 U32 Reserved6; /* 0x10 */ 542 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */ 543 U16 SASBroadcastPrimitiveMasks; /* 0x24 */ 544 U16 SASNotifyPrimitiveMasks; /* 0x26 */ 545 U32 Reserved8; /* 0x28 */ 546 } MPI2_EVENT_NOTIFICATION_REQUEST, 547 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST, 548 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t; 549 550 551 /* EventNotification Reply message */ 552 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY 553 { 554 U16 EventDataLength; /* 0x00 */ 555 U8 MsgLength; /* 0x02 */ 556 U8 Function; /* 0x03 */ 557 U16 Reserved1; /* 0x04 */ 558 U8 AckRequired; /* 0x06 */ 559 U8 MsgFlags; /* 0x07 */ 560 U8 VP_ID; /* 0x08 */ 561 U8 VF_ID; /* 0x09 */ 562 U16 Reserved2; /* 0x0A */ 563 U16 Reserved3; /* 0x0C */ 564 U16 IOCStatus; /* 0x0E */ 565 U32 IOCLogInfo; /* 0x10 */ 566 U16 Event; /* 0x14 */ 567 U16 Reserved4; /* 0x16 */ 568 U32 EventContext; /* 0x18 */ 569 U32 EventData[1]; /* 0x1C */ 570 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY, 571 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t; 572 573 /* AckRequired */ 574 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 575 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 576 577 /* Event */ 578 #define MPI2_EVENT_LOG_DATA (0x0001) 579 #define MPI2_EVENT_STATE_CHANGE (0x0002) 580 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) 581 #define MPI2_EVENT_EVENT_CHANGE (0x000A) 582 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */ 583 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) 584 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) 585 #define MPI2_EVENT_SAS_DISCOVERY (0x0016) 586 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) 587 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) 588 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) 589 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) 590 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) 591 #define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x001D) /* MPI v2.6 and later */ 592 #define MPI2_EVENT_IR_VOLUME (0x001E) 593 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) 594 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) 595 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) 596 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) 597 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023) 598 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024) 599 #define MPI2_EVENT_SAS_QUIESCE (0x0025) 600 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026) 601 #define MPI2_EVENT_TEMP_THRESHOLD (0x0027) 602 #define MPI2_EVENT_HOST_MESSAGE (0x0028) 603 #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029) 604 #define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE (0x0030) /* MPI v2.6 and later */ 605 #define MPI2_EVENT_PCIE_ENUMERATION (0x0031) /* MPI v2.6 and later */ 606 #define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x0032) /* MPI v2.6 and later */ 607 #define MPI2_EVENT_PCIE_LINK_COUNTER (0x0033) /* MPI v2.6 and later */ 608 #define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034) /* MPI v2.6 and later */ 609 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E) 610 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F) 611 612 613 /* Log Entry Added Event data */ 614 615 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ 616 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) 617 618 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED 619 { 620 U64 TimeStamp; /* 0x00 */ 621 U32 Reserved1; /* 0x08 */ 622 U16 LogSequence; /* 0x0C */ 623 U16 LogEntryQualifier; /* 0x0E */ 624 U8 VP_ID; /* 0x10 */ 625 U8 VF_ID; /* 0x11 */ 626 U16 Reserved2; /* 0x12 */ 627 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */ 628 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 629 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 630 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t; 631 632 633 /* GPIO Interrupt Event data */ 634 635 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT 636 { 637 U8 GPIONum; /* 0x00 */ 638 U8 Reserved1; /* 0x01 */ 639 U16 Reserved2; /* 0x02 */ 640 } MPI2_EVENT_DATA_GPIO_INTERRUPT, 641 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT, 642 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t; 643 644 645 /* Temperature Threshold Event data */ 646 647 typedef struct _MPI2_EVENT_DATA_TEMPERATURE 648 { 649 U16 Status; /* 0x00 */ 650 U8 SensorNum; /* 0x02 */ 651 U8 Reserved1; /* 0x03 */ 652 U16 CurrentTemperature; /* 0x04 */ 653 U16 Reserved2; /* 0x06 */ 654 U32 Reserved3; /* 0x08 */ 655 U32 Reserved4; /* 0x0C */ 656 } MPI2_EVENT_DATA_TEMPERATURE, 657 MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE, 658 Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t; 659 660 /* Temperature Threshold Event data Status bits */ 661 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008) 662 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004) 663 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002) 664 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001) 665 666 667 /* Host Message Event data */ 668 669 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE 670 { 671 U8 SourceVF_ID; /* 0x00 */ 672 U8 Reserved1; /* 0x01 */ 673 U16 Reserved2; /* 0x02 */ 674 U32 Reserved3; /* 0x04 */ 675 U32 HostData[1]; /* 0x08 */ 676 } MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE, 677 Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t; 678 679 680 /* Power Performance Change Event data */ 681 682 typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE 683 { 684 U8 CurrentPowerMode; /* 0x00 */ 685 U8 PreviousPowerMode; /* 0x01 */ 686 U16 Reserved1; /* 0x02 */ 687 } MPI2_EVENT_DATA_POWER_PERF_CHANGE, 688 MPI2_POINTER PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE, 689 Mpi2EventDataPowerPerfChange_t, MPI2_POINTER pMpi2EventDataPowerPerfChange_t; 690 691 /* defines for CurrentPowerMode and PreviousPowerMode fields */ 692 #define MPI2_EVENT_PM_INIT_MASK (0xC0) 693 #define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00) 694 #define MPI2_EVENT_PM_INIT_HOST (0x40) 695 #define MPI2_EVENT_PM_INIT_IO_UNIT (0x80) 696 #define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0) 697 698 #define MPI2_EVENT_PM_MODE_MASK (0x07) 699 #define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00) 700 #define MPI2_EVENT_PM_MODE_UNKNOWN (0x01) 701 #define MPI2_EVENT_PM_MODE_FULL_POWER (0x04) 702 #define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05) 703 #define MPI2_EVENT_PM_MODE_STANDBY (0x06) 704 705 706 /* Active Cable Exception Event data */ 707 708 typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT 709 { 710 U32 ActiveCablePowerRequirement; /* 0x00 */ 711 U8 ReasonCode; /* 0x04 */ 712 U8 ReceptacleID; /* 0x05 */ 713 U16 Reserved1; /* 0x06 */ 714 } MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT, 715 MPI2_POINTER PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT, 716 Mpi26EventDataActiveCableExcept_t, 717 MPI2_POINTER pMpi26EventDataActiveCableExcept_t; 718 719 /* defines for ReasonCode field */ 720 #define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00) 721 #define MPI26_EVENT_ACTIVE_CABLE_PRESENT (0x01) 722 #define MPI26_EVENT_ACTIVE_CABLE_DEGRADED (0x02) 723 724 /* Hard Reset Received Event data */ 725 726 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED 727 { 728 U8 Reserved1; /* 0x00 */ 729 U8 Port; /* 0x01 */ 730 U16 Reserved2; /* 0x02 */ 731 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 732 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 733 Mpi2EventDataHardResetReceived_t, 734 MPI2_POINTER pMpi2EventDataHardResetReceived_t; 735 736 737 /* Task Set Full Event data */ 738 /* this event is obsolete */ 739 740 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL 741 { 742 U16 DevHandle; /* 0x00 */ 743 U16 CurrentDepth; /* 0x02 */ 744 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL, 745 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t; 746 747 748 /* SAS Device Status Change Event data */ 749 750 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE 751 { 752 U16 TaskTag; /* 0x00 */ 753 U8 ReasonCode; /* 0x02 */ 754 U8 PhysicalPort; /* 0x03 */ 755 U8 ASC; /* 0x04 */ 756 U8 ASCQ; /* 0x05 */ 757 U16 DevHandle; /* 0x06 */ 758 U32 Reserved2; /* 0x08 */ 759 U64 SASAddress; /* 0x0C */ 760 U8 LUN[8]; /* 0x14 */ 761 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 762 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 763 Mpi2EventDataSasDeviceStatusChange_t, 764 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t; 765 766 /* SAS Device Status Change Event data ReasonCode values */ 767 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 768 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 769 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 770 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 771 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 772 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 773 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 774 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 775 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 776 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 777 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) 778 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11) 779 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12) 780 781 782 /* Integrated RAID Operation Status Event data */ 783 784 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS 785 { 786 U16 VolDevHandle; /* 0x00 */ 787 U16 Reserved1; /* 0x02 */ 788 U8 RAIDOperation; /* 0x04 */ 789 U8 PercentComplete; /* 0x05 */ 790 U16 Reserved2; /* 0x06 */ 791 U32 ElapsedSeconds; /* 0x08 */ 792 } MPI2_EVENT_DATA_IR_OPERATION_STATUS, 793 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, 794 Mpi2EventDataIrOperationStatus_t, 795 MPI2_POINTER pMpi2EventDataIrOperationStatus_t; 796 797 /* Integrated RAID Operation Status Event data RAIDOperation values */ 798 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) 799 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) 800 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) 801 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) 802 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) 803 804 805 /* Integrated RAID Volume Event data */ 806 807 typedef struct _MPI2_EVENT_DATA_IR_VOLUME 808 { 809 U16 VolDevHandle; /* 0x00 */ 810 U8 ReasonCode; /* 0x02 */ 811 U8 Reserved1; /* 0x03 */ 812 U32 NewValue; /* 0x04 */ 813 U32 PreviousValue; /* 0x08 */ 814 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME, 815 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t; 816 817 /* Integrated RAID Volume Event data ReasonCode values */ 818 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) 819 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) 820 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) 821 822 823 /* Integrated RAID Physical Disk Event data */ 824 825 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK 826 { 827 U16 Reserved1; /* 0x00 */ 828 U8 ReasonCode; /* 0x02 */ 829 U8 PhysDiskNum; /* 0x03 */ 830 U16 PhysDiskDevHandle; /* 0x04 */ 831 U16 Reserved2; /* 0x06 */ 832 U16 Slot; /* 0x08 */ 833 U16 EnclosureHandle; /* 0x0A */ 834 U32 NewValue; /* 0x0C */ 835 U32 PreviousValue; /* 0x10 */ 836 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 837 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 838 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t; 839 840 /* Integrated RAID Physical Disk Event data ReasonCode values */ 841 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) 842 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) 843 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) 844 845 846 /* Integrated RAID Configuration Change List Event data */ 847 848 /* 849 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 850 * one and check NumElements at runtime. 851 */ 852 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT 853 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1) 854 #endif 855 856 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT 857 { 858 U16 ElementFlags; /* 0x00 */ 859 U16 VolDevHandle; /* 0x02 */ 860 U8 ReasonCode; /* 0x04 */ 861 U8 PhysDiskNum; /* 0x05 */ 862 U16 PhysDiskDevHandle; /* 0x06 */ 863 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, 864 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t; 865 866 /* IR Configuration Change List Event data ElementFlags values */ 867 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) 868 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) 869 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) 870 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) 871 872 /* IR Configuration Change List Event data ReasonCode values */ 873 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) 874 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) 875 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) 876 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) 877 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) 878 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) 879 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) 880 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) 881 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) 882 883 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST 884 { 885 U8 NumElements; /* 0x00 */ 886 U8 Reserved1; /* 0x01 */ 887 U8 Reserved2; /* 0x02 */ 888 U8 ConfigNum; /* 0x03 */ 889 U32 Flags; /* 0x04 */ 890 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */ 891 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 892 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 893 Mpi2EventDataIrConfigChangeList_t, 894 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t; 895 896 /* IR Configuration Change List Event data Flags values */ 897 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) 898 899 900 /* SAS Discovery Event data */ 901 902 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY 903 { 904 U8 Flags; /* 0x00 */ 905 U8 ReasonCode; /* 0x01 */ 906 U8 PhysicalPort; /* 0x02 */ 907 U8 Reserved1; /* 0x03 */ 908 U32 DiscoveryStatus; /* 0x04 */ 909 } MPI2_EVENT_DATA_SAS_DISCOVERY, 910 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, 911 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t; 912 913 /* SAS Discovery Event data Flags values */ 914 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) 915 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) 916 917 /* SAS Discovery Event data ReasonCode values */ 918 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) 919 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) 920 921 /* SAS Discovery Event data DiscoveryStatus values */ 922 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 923 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) 924 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) 925 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 926 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) 927 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 928 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 929 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) 930 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 931 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) 932 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) 933 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) 934 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) 935 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) 936 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) 937 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) 938 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) 939 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) 940 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) 941 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) 942 943 944 /* SAS Broadcast Primitive Event data */ 945 946 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE 947 { 948 U8 PhyNum; /* 0x00 */ 949 U8 Port; /* 0x01 */ 950 U8 PortWidth; /* 0x02 */ 951 U8 Primitive; /* 0x03 */ 952 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 953 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 954 Mpi2EventDataSasBroadcastPrimitive_t, 955 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t; 956 957 /* defines for the Primitive field */ 958 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) 959 #define MPI2_EVENT_PRIMITIVE_SES (0x02) 960 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) 961 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 962 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) 963 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) 964 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 965 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 966 967 968 /* SAS Notify Primitive Event data */ 969 970 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE 971 { 972 U8 PhyNum; /* 0x00 */ 973 U8 Port; /* 0x01 */ 974 U8 Reserved1; /* 0x02 */ 975 U8 Primitive; /* 0x03 */ 976 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 977 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 978 Mpi2EventDataSasNotifyPrimitive_t, 979 MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t; 980 981 /* defines for the Primitive field */ 982 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01) 983 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02) 984 #define MPI2_EVENT_NOTIFY_RESERVED1 (0x03) 985 #define MPI2_EVENT_NOTIFY_RESERVED2 (0x04) 986 987 988 /* SAS Initiator Device Status Change Event data */ 989 990 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE 991 { 992 U8 ReasonCode; /* 0x00 */ 993 U8 PhysicalPort; /* 0x01 */ 994 U16 DevHandle; /* 0x02 */ 995 U64 SASAddress; /* 0x04 */ 996 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 997 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 998 Mpi2EventDataSasInitDevStatusChange_t, 999 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t; 1000 1001 /* SAS Initiator Device Status Change event ReasonCode values */ 1002 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) 1003 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 1004 1005 1006 /* SAS Initiator Device Table Overflow Event data */ 1007 1008 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW 1009 { 1010 U16 MaxInit; /* 0x00 */ 1011 U16 CurrentInit; /* 0x02 */ 1012 U64 SASAddress; /* 0x04 */ 1013 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 1014 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 1015 Mpi2EventDataSasInitTableOverflow_t, 1016 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t; 1017 1018 1019 /* SAS Topology Change List Event data */ 1020 1021 /* 1022 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1023 * one and check NumEntries at runtime. 1024 */ 1025 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT 1026 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1) 1027 #endif 1028 1029 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY 1030 { 1031 U16 AttachedDevHandle; /* 0x00 */ 1032 U8 LinkRate; /* 0x02 */ 1033 U8 PhyStatus; /* 0x03 */ 1034 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, 1035 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t; 1036 1037 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST 1038 { 1039 U16 EnclosureHandle; /* 0x00 */ 1040 U16 ExpanderDevHandle; /* 0x02 */ 1041 U8 NumPhys; /* 0x04 */ 1042 U8 Reserved1; /* 0x05 */ 1043 U16 Reserved2; /* 0x06 */ 1044 U8 NumEntries; /* 0x08 */ 1045 U8 StartPhyNum; /* 0x09 */ 1046 U8 ExpStatus; /* 0x0A */ 1047 U8 PhysicalPort; /* 0x0B */ 1048 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/ 1049 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 1050 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 1051 Mpi2EventDataSasTopologyChangeList_t, 1052 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t; 1053 1054 /* values for the ExpStatus field */ 1055 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 1056 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) 1057 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 1058 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 1059 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 1060 1061 /* defines for the LinkRate field */ 1062 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) 1063 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 1064 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) 1065 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 1066 1067 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 1068 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 1069 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 1070 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 1071 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 1072 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 1073 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 1074 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) 1075 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) 1076 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) 1077 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B) 1078 #define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0C) 1079 1080 /* values for the PhyStatus field */ 1081 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) 1082 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) 1083 /* values for the PhyStatus ReasonCode sub-field */ 1084 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) 1085 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) 1086 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) 1087 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) 1088 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) 1089 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) 1090 1091 1092 /* SAS Enclosure Device Status Change Event data */ 1093 1094 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE 1095 { 1096 U16 EnclosureHandle; /* 0x00 */ 1097 U8 ReasonCode; /* 0x02 */ 1098 U8 PhysicalPort; /* 0x03 */ 1099 U64 EnclosureLogicalID; /* 0x04 */ 1100 U16 NumSlots; /* 0x0C */ 1101 U16 StartSlot; /* 0x0E */ 1102 U32 PhyBits; /* 0x10 */ 1103 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 1104 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 1105 Mpi2EventDataSasEnclDevStatusChange_t, 1106 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t, 1107 MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE, 1108 MPI2_POINTER PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE, 1109 Mpi26EventDataEnclDevStatusChange_t, 1110 MPI2_POINTER pMpi26EventDataEnclDevStatusChange_t; 1111 1112 /* SAS Enclosure Device Status Change event ReasonCode values */ 1113 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) 1114 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) 1115 1116 /* Enclosure Device Status Change event ReasonCode values */ 1117 #define MPI26_EVENT_ENCL_RC_ADDED (0x01) 1118 #define MPI26_EVENT_ENCL_RC_NOT_RESPONDING (0x02) 1119 1120 /* SAS PHY Counter Event data */ 1121 1122 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER 1123 { 1124 U64 TimeStamp; /* 0x00 */ 1125 U32 Reserved1; /* 0x08 */ 1126 U8 PhyEventCode; /* 0x0C */ 1127 U8 PhyNum; /* 0x0D */ 1128 U16 Reserved2; /* 0x0E */ 1129 U32 PhyEventInfo; /* 0x10 */ 1130 U8 CounterType; /* 0x14 */ 1131 U8 ThresholdWindow; /* 0x15 */ 1132 U8 TimeUnits; /* 0x16 */ 1133 U8 Reserved3; /* 0x17 */ 1134 U32 EventThreshold; /* 0x18 */ 1135 U16 ThresholdFlags; /* 0x1C */ 1136 U16 Reserved4; /* 0x1E */ 1137 } MPI2_EVENT_DATA_SAS_PHY_COUNTER, 1138 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER, 1139 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t; 1140 1141 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */ 1142 1143 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */ 1144 1145 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */ 1146 1147 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */ 1148 1149 1150 /* SAS Quiesce Event data */ 1151 1152 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE 1153 { 1154 U8 ReasonCode; /* 0x00 */ 1155 U8 Reserved1; /* 0x01 */ 1156 U16 Reserved2; /* 0x02 */ 1157 U32 Reserved3; /* 0x04 */ 1158 } MPI2_EVENT_DATA_SAS_QUIESCE, 1159 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE, 1160 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t; 1161 1162 /* SAS Quiesce Event data ReasonCode values */ 1163 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01) 1164 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02) 1165 1166 1167 /* Host Based Discovery Phy Event data */ 1168 1169 typedef struct _MPI2_EVENT_HBD_PHY_SAS 1170 { 1171 U8 Flags; /* 0x00 */ 1172 U8 NegotiatedLinkRate; /* 0x01 */ 1173 U8 PhyNum; /* 0x02 */ 1174 U8 PhysicalPort; /* 0x03 */ 1175 U32 Reserved1; /* 0x04 */ 1176 U8 InitialFrame[28]; /* 0x08 */ 1177 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS, 1178 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t; 1179 1180 /* values for the Flags field */ 1181 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02) 1182 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01) 1183 1184 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */ 1185 1186 typedef union _MPI2_EVENT_HBD_DESCRIPTOR 1187 { 1188 MPI2_EVENT_HBD_PHY_SAS Sas; 1189 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR, 1190 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t; 1191 1192 typedef struct _MPI2_EVENT_DATA_HBD_PHY 1193 { 1194 U8 DescriptorType; /* 0x00 */ 1195 U8 Reserved1; /* 0x01 */ 1196 U16 Reserved2; /* 0x02 */ 1197 U32 Reserved3; /* 0x04 */ 1198 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */ 1199 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY, 1200 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t; 1201 1202 /* values for the DescriptorType field */ 1203 #define MPI2_EVENT_HBD_DT_SAS (0x01) 1204 1205 1206 /* PCIe Device Status Change Event data (MPI v2.6 and later) */ 1207 1208 typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE 1209 { 1210 U16 TaskTag; /* 0x00 */ 1211 U8 ReasonCode; /* 0x02 */ 1212 U8 PhysicalPort; /* 0x03 */ 1213 U8 ASC; /* 0x04 */ 1214 U8 ASCQ; /* 0x05 */ 1215 U16 DevHandle; /* 0x06 */ 1216 U32 Reserved2; /* 0x08 */ 1217 U64 WWID; /* 0x0C */ 1218 U8 LUN[8]; /* 0x14 */ 1219 } MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE, 1220 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE, 1221 Mpi26EventDataPCIeDeviceStatusChange_t, 1222 MPI2_POINTER pMpi26EventDataPCIeDeviceStatusChange_t; 1223 1224 /* PCIe Device Status Change Event data ReasonCode values */ 1225 #define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA (0x05) 1226 #define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED (0x07) 1227 #define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 1228 #define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 1229 #define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 1230 #define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 1231 #define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 1232 #define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 1233 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 1234 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 1235 #define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE (0x10) 1236 1237 1238 /* PCIe Enumeration Event data (MPI v2.6 and later) */ 1239 1240 typedef struct _MPI26_EVENT_DATA_PCIE_ENUMERATION 1241 { 1242 U8 Flags; /* 0x00 */ 1243 U8 ReasonCode; /* 0x01 */ 1244 U8 PhysicalPort; /* 0x02 */ 1245 U8 Reserved1; /* 0x03 */ 1246 U32 EnumerationStatus; /* 0x04 */ 1247 } MPI26_EVENT_DATA_PCIE_ENUMERATION, 1248 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION, 1249 Mpi26EventDataPCIeEnumeration_t, 1250 MPI2_POINTER pMpi26EventDataPCIeEnumeration_t; 1251 1252 /* PCIe Enumeration Event data Flags values */ 1253 #define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE (0x02) 1254 #define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS (0x01) 1255 1256 /* PCIe Enumeration Event data ReasonCode values */ 1257 #define MPI26_EVENT_PCIE_ENUM_RC_STARTED (0x01) 1258 #define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED (0x02) 1259 1260 /* PCIe Enumeration Event data EnumerationStatus values */ 1261 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000) 1262 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000) 1263 #define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000) 1264 1265 1266 /* PCIe Topology Change List Event data (MPI v2.6 and later) */ 1267 1268 /* 1269 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1270 * one and check NumEntries at runtime. 1271 */ 1272 #ifndef MPI26_EVENT_PCIE_TOPO_PORT_COUNT 1273 #define MPI26_EVENT_PCIE_TOPO_PORT_COUNT (1) 1274 #endif 1275 1276 typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY 1277 { 1278 U16 AttachedDevHandle; /* 0x00 */ 1279 U8 PortStatus; /* 0x02 */ 1280 U8 Reserved1; /* 0x03 */ 1281 U8 CurrentPortInfo; /* 0x04 */ 1282 U8 Reserved2; /* 0x05 */ 1283 U8 PreviousPortInfo; /* 0x06 */ 1284 U8 Reserved3; /* 0x07 */ 1285 } MPI26_EVENT_PCIE_TOPO_PORT_ENTRY, 1286 MPI2_POINTER PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY, 1287 Mpi26EventPCIeTopoPortEntry_t, 1288 MPI2_POINTER pMpi26EventPCIeTopoPortEntry_t; 1289 1290 /* PCIe Topology Change List Event data PortStatus values */ 1291 #define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED (0x01) 1292 #define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02) 1293 #define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03) 1294 #define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04) 1295 #define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05) 1296 1297 /* PCIe Topology Change List Event data defines for CurrentPortInfo and PreviousPortInfo */ 1298 #define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK (0xF0) 1299 #define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00) 1300 #define MPI26_EVENT_PCIE_TOPO_PI_1_LANE (0x10) 1301 #define MPI26_EVENT_PCIE_TOPO_PI_2_LANES (0x20) 1302 #define MPI26_EVENT_PCIE_TOPO_PI_4_LANES (0x30) 1303 #define MPI26_EVENT_PCIE_TOPO_PI_8_LANES (0x40) 1304 1305 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F) 1306 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00) 1307 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01) 1308 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02) 1309 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03) 1310 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04) 1311 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05) 1312 1313 typedef struct _MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST 1314 { 1315 U16 EnclosureHandle; /* 0x00 */ 1316 U16 SwitchDevHandle; /* 0x02 */ 1317 U8 NumPorts; /* 0x04 */ 1318 U8 Reserved1; /* 0x05 */ 1319 U16 Reserved2; /* 0x06 */ 1320 U8 NumEntries; /* 0x08 */ 1321 U8 StartPortNum; /* 0x09 */ 1322 U8 SwitchStatus; /* 0x0A */ 1323 U8 PhysicalPort; /* 0x0B */ 1324 MPI26_EVENT_PCIE_TOPO_PORT_ENTRY PortEntry[MPI26_EVENT_PCIE_TOPO_PORT_COUNT]; /* 0x0C */ 1325 } MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST, 1326 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST, 1327 Mpi26EventDataPCIeTopologyChangeList_t, 1328 MPI2_POINTER pMpi26EventDataPCIeTopologyChangeList_t; 1329 1330 /* PCIe Topology Change List Event data SwitchStatus values */ 1331 #define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00) 1332 #define MPI26_EVENT_PCIE_TOPO_SS_ADDED (0x01) 1333 #define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02) 1334 #define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING (0x03) 1335 #define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04) 1336 1337 /* PCIe Link Counter Event data (MPI v2.6 and later) */ 1338 1339 typedef struct _MPI26_EVENT_DATA_PCIE_LINK_COUNTER 1340 { 1341 U64 TimeStamp; /* 0x00 */ 1342 U32 Reserved1; /* 0x08 */ 1343 U8 LinkEventCode; /* 0x0C */ 1344 U8 LinkNum; /* 0x0D */ 1345 U16 Reserved2; /* 0x0E */ 1346 U32 LinkEventInfo; /* 0x10 */ 1347 U8 CounterType; /* 0x14 */ 1348 U8 ThresholdWindow; /* 0x15 */ 1349 U8 TimeUnits; /* 0x16 */ 1350 U8 Reserved3; /* 0x17 */ 1351 U32 EventThreshold; /* 0x18 */ 1352 U16 ThresholdFlags; /* 0x1C */ 1353 U16 Reserved4; /* 0x1E */ 1354 } MPI26_EVENT_DATA_PCIE_LINK_COUNTER, 1355 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER, 1356 Mpi26EventDataPcieLinkCounter_t, MPI2_POINTER pMpi26EventDataPcieLinkCounter_t; 1357 1358 1359 /* use MPI26_PCIELINK3_EVTCODE_ values from mpi2_cnfg.h for the LinkEventCode field */ 1360 1361 /* use MPI26_PCIELINK3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */ 1362 1363 /* use MPI26_PCIELINK3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */ 1364 1365 /* use MPI26_PCIELINK3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */ 1366 1367 /**************************************************************************** 1368 * EventAck message 1369 ****************************************************************************/ 1370 1371 /* EventAck Request message */ 1372 typedef struct _MPI2_EVENT_ACK_REQUEST 1373 { 1374 U16 Reserved1; /* 0x00 */ 1375 U8 ChainOffset; /* 0x02 */ 1376 U8 Function; /* 0x03 */ 1377 U16 Reserved2; /* 0x04 */ 1378 U8 Reserved3; /* 0x06 */ 1379 U8 MsgFlags; /* 0x07 */ 1380 U8 VP_ID; /* 0x08 */ 1381 U8 VF_ID; /* 0x09 */ 1382 U16 Reserved4; /* 0x0A */ 1383 U16 Event; /* 0x0C */ 1384 U16 Reserved5; /* 0x0E */ 1385 U32 EventContext; /* 0x10 */ 1386 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST, 1387 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t; 1388 1389 1390 /* EventAck Reply message */ 1391 typedef struct _MPI2_EVENT_ACK_REPLY 1392 { 1393 U16 Reserved1; /* 0x00 */ 1394 U8 MsgLength; /* 0x02 */ 1395 U8 Function; /* 0x03 */ 1396 U16 Reserved2; /* 0x04 */ 1397 U8 Reserved3; /* 0x06 */ 1398 U8 MsgFlags; /* 0x07 */ 1399 U8 VP_ID; /* 0x08 */ 1400 U8 VF_ID; /* 0x09 */ 1401 U16 Reserved4; /* 0x0A */ 1402 U16 Reserved5; /* 0x0C */ 1403 U16 IOCStatus; /* 0x0E */ 1404 U32 IOCLogInfo; /* 0x10 */ 1405 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY, 1406 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t; 1407 1408 1409 /**************************************************************************** 1410 * SendHostMessage message 1411 ****************************************************************************/ 1412 1413 /* SendHostMessage Request message */ 1414 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST 1415 { 1416 U16 HostDataLength; /* 0x00 */ 1417 U8 ChainOffset; /* 0x02 */ 1418 U8 Function; /* 0x03 */ 1419 U16 Reserved1; /* 0x04 */ 1420 U8 Reserved2; /* 0x06 */ 1421 U8 MsgFlags; /* 0x07 */ 1422 U8 VP_ID; /* 0x08 */ 1423 U8 VF_ID; /* 0x09 */ 1424 U16 Reserved3; /* 0x0A */ 1425 U8 Reserved4; /* 0x0C */ 1426 U8 DestVF_ID; /* 0x0D */ 1427 U16 Reserved5; /* 0x0E */ 1428 U32 Reserved6; /* 0x10 */ 1429 U32 Reserved7; /* 0x14 */ 1430 U32 Reserved8; /* 0x18 */ 1431 U32 Reserved9; /* 0x1C */ 1432 U32 Reserved10; /* 0x20 */ 1433 U32 HostData[1]; /* 0x24 */ 1434 } MPI2_SEND_HOST_MESSAGE_REQUEST, 1435 MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST, 1436 Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t; 1437 1438 1439 /* SendHostMessage Reply message */ 1440 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY 1441 { 1442 U16 HostDataLength; /* 0x00 */ 1443 U8 MsgLength; /* 0x02 */ 1444 U8 Function; /* 0x03 */ 1445 U16 Reserved1; /* 0x04 */ 1446 U8 Reserved2; /* 0x06 */ 1447 U8 MsgFlags; /* 0x07 */ 1448 U8 VP_ID; /* 0x08 */ 1449 U8 VF_ID; /* 0x09 */ 1450 U16 Reserved3; /* 0x0A */ 1451 U16 Reserved4; /* 0x0C */ 1452 U16 IOCStatus; /* 0x0E */ 1453 U32 IOCLogInfo; /* 0x10 */ 1454 } MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY, 1455 Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t; 1456 1457 1458 /**************************************************************************** 1459 * FWDownload message 1460 ****************************************************************************/ 1461 1462 /* MPI v2.0 FWDownload Request message */ 1463 typedef struct _MPI2_FW_DOWNLOAD_REQUEST 1464 { 1465 U8 ImageType; /* 0x00 */ 1466 U8 Reserved1; /* 0x01 */ 1467 U8 ChainOffset; /* 0x02 */ 1468 U8 Function; /* 0x03 */ 1469 U16 Reserved2; /* 0x04 */ 1470 U8 Reserved3; /* 0x06 */ 1471 U8 MsgFlags; /* 0x07 */ 1472 U8 VP_ID; /* 0x08 */ 1473 U8 VF_ID; /* 0x09 */ 1474 U16 Reserved4; /* 0x0A */ 1475 U32 TotalImageSize; /* 0x0C */ 1476 U32 Reserved5; /* 0x10 */ 1477 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1478 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST, 1479 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest; 1480 1481 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1482 1483 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) 1484 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1485 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1486 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1487 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1488 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1489 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) 1490 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1491 #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C) /* MPI v2.5 and newer */ 1492 #define MPI2_FW_DOWNLOAD_ITYPE_SBR (0x0E) 1493 #define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP (0x0F) 1494 #define MPI2_FW_DOWNLOAD_ITYPE_HIIM (0x10) 1495 #define MPI2_FW_DOWNLOAD_ITYPE_HIIA (0x11) 1496 #define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12) 1497 #define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13) 1498 #define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14) 1499 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) 1500 1501 /* MPI v2.0 FWDownload TransactionContext Element */ 1502 typedef struct _MPI2_FW_DOWNLOAD_TCSGE 1503 { 1504 U8 Reserved1; /* 0x00 */ 1505 U8 ContextSize; /* 0x01 */ 1506 U8 DetailsLength; /* 0x02 */ 1507 U8 Flags; /* 0x03 */ 1508 U32 Reserved2; /* 0x04 */ 1509 U32 ImageOffset; /* 0x08 */ 1510 U32 ImageSize; /* 0x0C */ 1511 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE, 1512 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t; 1513 1514 1515 /* MPI v2.5 FWDownload Request message */ 1516 typedef struct _MPI25_FW_DOWNLOAD_REQUEST 1517 { 1518 U8 ImageType; /* 0x00 */ 1519 U8 Reserved1; /* 0x01 */ 1520 U8 ChainOffset; /* 0x02 */ 1521 U8 Function; /* 0x03 */ 1522 U16 Reserved2; /* 0x04 */ 1523 U8 Reserved3; /* 0x06 */ 1524 U8 MsgFlags; /* 0x07 */ 1525 U8 VP_ID; /* 0x08 */ 1526 U8 VF_ID; /* 0x09 */ 1527 U16 Reserved4; /* 0x0A */ 1528 U32 TotalImageSize; /* 0x0C */ 1529 U32 Reserved5; /* 0x10 */ 1530 U32 Reserved6; /* 0x14 */ 1531 U32 ImageOffset; /* 0x18 */ 1532 U32 ImageSize; /* 0x1C */ 1533 MPI25_SGE_IO_UNION SGL; /* 0x20 */ 1534 } MPI25_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_DOWNLOAD_REQUEST, 1535 Mpi25FWDownloadRequest, MPI2_POINTER pMpi25FWDownloadRequest; 1536 1537 1538 /* FWDownload Reply message */ 1539 typedef struct _MPI2_FW_DOWNLOAD_REPLY 1540 { 1541 U8 ImageType; /* 0x00 */ 1542 U8 Reserved1; /* 0x01 */ 1543 U8 MsgLength; /* 0x02 */ 1544 U8 Function; /* 0x03 */ 1545 U16 Reserved2; /* 0x04 */ 1546 U8 Reserved3; /* 0x06 */ 1547 U8 MsgFlags; /* 0x07 */ 1548 U8 VP_ID; /* 0x08 */ 1549 U8 VF_ID; /* 0x09 */ 1550 U16 Reserved4; /* 0x0A */ 1551 U16 Reserved5; /* 0x0C */ 1552 U16 IOCStatus; /* 0x0E */ 1553 U32 IOCLogInfo; /* 0x10 */ 1554 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY, 1555 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t; 1556 1557 1558 /**************************************************************************** 1559 * FWUpload message 1560 ****************************************************************************/ 1561 1562 /* MPI v2.0 FWUpload Request message */ 1563 typedef struct _MPI2_FW_UPLOAD_REQUEST 1564 { 1565 U8 ImageType; /* 0x00 */ 1566 U8 Reserved1; /* 0x01 */ 1567 U8 ChainOffset; /* 0x02 */ 1568 U8 Function; /* 0x03 */ 1569 U16 Reserved2; /* 0x04 */ 1570 U8 Reserved3; /* 0x06 */ 1571 U8 MsgFlags; /* 0x07 */ 1572 U8 VP_ID; /* 0x08 */ 1573 U8 VF_ID; /* 0x09 */ 1574 U16 Reserved4; /* 0x0A */ 1575 U32 Reserved5; /* 0x0C */ 1576 U32 Reserved6; /* 0x10 */ 1577 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1578 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST, 1579 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t; 1580 1581 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) 1582 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1583 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1584 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1585 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1586 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1587 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1588 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1589 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1590 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1591 #define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D) 1592 #define MPI2_FW_UPLOAD_ITYPE_SBR (0x0E) 1593 #define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP (0x0F) 1594 #define MPI2_FW_UPLOAD_ITYPE_HIIM (0x10) 1595 #define MPI2_FW_UPLOAD_ITYPE_HIIA (0x11) 1596 #define MPI2_FW_UPLOAD_ITYPE_CTLR (0x12) 1597 #define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE (0x13) 1598 #define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA (0x14) 1599 1600 /* MPI v2.0 FWUpload TransactionContext Element */ 1601 typedef struct _MPI2_FW_UPLOAD_TCSGE 1602 { 1603 U8 Reserved1; /* 0x00 */ 1604 U8 ContextSize; /* 0x01 */ 1605 U8 DetailsLength; /* 0x02 */ 1606 U8 Flags; /* 0x03 */ 1607 U32 Reserved2; /* 0x04 */ 1608 U32 ImageOffset; /* 0x08 */ 1609 U32 ImageSize; /* 0x0C */ 1610 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE, 1611 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t; 1612 1613 1614 /* MPI v2.5 FWUpload Request message */ 1615 typedef struct _MPI25_FW_UPLOAD_REQUEST 1616 { 1617 U8 ImageType; /* 0x00 */ 1618 U8 Reserved1; /* 0x01 */ 1619 U8 ChainOffset; /* 0x02 */ 1620 U8 Function; /* 0x03 */ 1621 U16 Reserved2; /* 0x04 */ 1622 U8 Reserved3; /* 0x06 */ 1623 U8 MsgFlags; /* 0x07 */ 1624 U8 VP_ID; /* 0x08 */ 1625 U8 VF_ID; /* 0x09 */ 1626 U16 Reserved4; /* 0x0A */ 1627 U32 Reserved5; /* 0x0C */ 1628 U32 Reserved6; /* 0x10 */ 1629 U32 Reserved7; /* 0x14 */ 1630 U32 ImageOffset; /* 0x18 */ 1631 U32 ImageSize; /* 0x1C */ 1632 MPI25_SGE_IO_UNION SGL; /* 0x20 */ 1633 } MPI25_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_UPLOAD_REQUEST, 1634 Mpi25FWUploadRequest_t, MPI2_POINTER pMpi25FWUploadRequest_t; 1635 1636 1637 /* FWUpload Reply message */ 1638 typedef struct _MPI2_FW_UPLOAD_REPLY 1639 { 1640 U8 ImageType; /* 0x00 */ 1641 U8 Reserved1; /* 0x01 */ 1642 U8 MsgLength; /* 0x02 */ 1643 U8 Function; /* 0x03 */ 1644 U16 Reserved2; /* 0x04 */ 1645 U8 Reserved3; /* 0x06 */ 1646 U8 MsgFlags; /* 0x07 */ 1647 U8 VP_ID; /* 0x08 */ 1648 U8 VF_ID; /* 0x09 */ 1649 U16 Reserved4; /* 0x0A */ 1650 U16 Reserved5; /* 0x0C */ 1651 U16 IOCStatus; /* 0x0E */ 1652 U32 IOCLogInfo; /* 0x10 */ 1653 U32 ActualImageSize; /* 0x14 */ 1654 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY, 1655 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t; 1656 1657 1658 /* FW Image Header */ 1659 typedef struct _MPI2_FW_IMAGE_HEADER 1660 { 1661 U32 Signature; /* 0x00 */ 1662 U32 Signature0; /* 0x04 */ 1663 U32 Signature1; /* 0x08 */ 1664 U32 Signature2; /* 0x0C */ 1665 MPI2_VERSION_UNION MPIVersion; /* 0x10 */ 1666 MPI2_VERSION_UNION FWVersion; /* 0x14 */ 1667 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */ 1668 MPI2_VERSION_UNION PackageVersion; /* 0x1C */ 1669 U16 VendorID; /* 0x20 */ 1670 U16 ProductID; /* 0x22 */ 1671 U16 ProtocolFlags; /* 0x24 */ 1672 U16 Reserved26; /* 0x26 */ 1673 U32 IOCCapabilities; /* 0x28 */ 1674 U32 ImageSize; /* 0x2C */ 1675 U32 NextImageHeaderOffset; /* 0x30 */ 1676 U32 Checksum; /* 0x34 */ 1677 U32 Reserved38; /* 0x38 */ 1678 U32 Reserved3C; /* 0x3C */ 1679 U32 Reserved40; /* 0x40 */ 1680 U32 Reserved44; /* 0x44 */ 1681 U32 Reserved48; /* 0x48 */ 1682 U32 Reserved4C; /* 0x4C */ 1683 U32 Reserved50; /* 0x50 */ 1684 U32 Reserved54; /* 0x54 */ 1685 U32 Reserved58; /* 0x58 */ 1686 U32 Reserved5C; /* 0x5C */ 1687 U32 BootFlags; /* 0x60 */ /* reserved in MPI v2.5 and earlier */ 1688 U32 FirmwareVersionNameWhat; /* 0x64 */ 1689 U8 FirmwareVersionName[32]; /* 0x68 */ 1690 U32 VendorNameWhat; /* 0x88 */ 1691 U8 VendorName[32]; /* 0x8C */ 1692 U32 PackageNameWhat; /* 0x88 */ 1693 U8 PackageName[32]; /* 0x8C */ 1694 U32 ReservedD0; /* 0xD0 */ 1695 U32 ReservedD4; /* 0xD4 */ 1696 U32 ReservedD8; /* 0xD8 */ 1697 U32 ReservedDC; /* 0xDC */ 1698 U32 ReservedE0; /* 0xE0 */ 1699 U32 ReservedE4; /* 0xE4 */ 1700 U32 ReservedE8; /* 0xE8 */ 1701 U32 ReservedEC; /* 0xEC */ 1702 U32 ReservedF0; /* 0xF0 */ 1703 U32 ReservedF4; /* 0xF4 */ 1704 U32 ReservedF8; /* 0xF8 */ 1705 U32 ReservedFC; /* 0xFC */ 1706 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER, 1707 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t; 1708 1709 /* Signature field */ 1710 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) 1711 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) 1712 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000) 1713 #define MPI26_FW_HEADER_SIGNATURE (0xEB000000) 1714 1715 /* Signature0 field */ 1716 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) 1717 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) 1718 #define MPI26_FW_HEADER_SIGNATURE0_BASE (0x5AEAA500) /* Last byte is defined by architecture */ 1719 #define MPI26_FW_HEADER_SIGNATURE0_ARC_0 (0x5A) 1720 #define MPI26_FW_HEADER_SIGNATURE0_ARC_1 (0x00) 1721 #define MPI26_FW_HEADER_SIGNATURE0_ARC_2 (0x01) 1722 #define MPI26_FW_HEADER_SIGNATURE0_ARC_3 (0x02) 1723 #define MPI26_FW_HEADER_SIGNATURE0 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_0) // legacy (0x5AEAA55A) 1724 #define MPI26_FW_HEADER_SIGNATURE0_3516 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_1) 1725 #define MPI26_FW_HEADER_SIGNATURE0_4008 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_3) 1726 1727 /* Signature1 field */ 1728 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) 1729 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) 1730 #define MPI26_FW_HEADER_SIGNATURE1 (0xA55AEAA5) 1731 1732 /* Signature2 field */ 1733 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) 1734 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) 1735 #define MPI26_FW_HEADER_SIGNATURE2 (0x5AA55AEA) 1736 1737 1738 /* defines for using the ProductID field */ 1739 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000) 1740 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000) 1741 1742 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00) 1743 #define MPI2_FW_HEADER_PID_PROD_A (0x0000) 1744 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 1745 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700) 1746 1747 1748 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1749 /* SAS ProductID Family bits */ 1750 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013) 1751 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014) 1752 #define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021) 1753 #define MPI26_FW_HEADER_PID_FAMILY_3324_SAS (0x0028) 1754 #define MPI26_FW_HEADER_PID_FAMILY_3516_SAS (0x0031) 1755 1756 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ 1757 1758 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */ 1759 1760 1761 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) 1762 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) 1763 #define MPI26_FW_HEADER_BOOTFLAGS_OFFSET (0x60) 1764 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) 1765 1766 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) 1767 1768 #define MPI2_FW_HEADER_SIZE (0x100) 1769 1770 1771 /* Extended Image Header */ 1772 typedef struct _MPI2_EXT_IMAGE_HEADER 1773 1774 { 1775 U8 ImageType; /* 0x00 */ 1776 U8 Reserved1; /* 0x01 */ 1777 U16 Reserved2; /* 0x02 */ 1778 U32 Checksum; /* 0x04 */ 1779 U32 ImageSize; /* 0x08 */ 1780 U32 NextImageHeaderOffset; /* 0x0C */ 1781 U32 PackageVersion; /* 0x10 */ 1782 U32 Reserved3; /* 0x14 */ 1783 U32 Reserved4; /* 0x18 */ 1784 U32 Reserved5; /* 0x1C */ 1785 U8 IdentifyString[32]; /* 0x20 */ 1786 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER, 1787 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t; 1788 1789 /* useful offsets */ 1790 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) 1791 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) 1792 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) 1793 1794 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40) 1795 1796 /* defines for the ImageType field */ 1797 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 1798 #define MPI2_EXT_IMAGE_TYPE_FW (0x01) 1799 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03) 1800 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04) 1801 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05) 1802 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06) 1803 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) 1804 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08) 1805 #define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09) /* MPI v2.5 and newer */ 1806 #define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80) 1807 #define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF) 1808 1809 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC) /* deprecated */ 1810 1811 1812 1813 /* FLASH Layout Extended Image Data */ 1814 1815 /* 1816 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1817 * one and check RegionsPerLayout at runtime. 1818 */ 1819 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS 1820 #define MPI2_FLASH_NUMBER_OF_REGIONS (1) 1821 #endif 1822 1823 /* 1824 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1825 * one and check NumberOfLayouts at runtime. 1826 */ 1827 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS 1828 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1) 1829 #endif 1830 1831 typedef struct _MPI2_FLASH_REGION 1832 { 1833 U8 RegionType; /* 0x00 */ 1834 U8 Reserved1; /* 0x01 */ 1835 U16 Reserved2; /* 0x02 */ 1836 U32 RegionOffset; /* 0x04 */ 1837 U32 RegionSize; /* 0x08 */ 1838 U32 Reserved3; /* 0x0C */ 1839 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION, 1840 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t; 1841 1842 typedef struct _MPI2_FLASH_LAYOUT 1843 { 1844 U32 FlashSize; /* 0x00 */ 1845 U32 Reserved1; /* 0x04 */ 1846 U32 Reserved2; /* 0x08 */ 1847 U32 Reserved3; /* 0x0C */ 1848 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */ 1849 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT, 1850 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t; 1851 1852 typedef struct _MPI2_FLASH_LAYOUT_DATA 1853 { 1854 U8 ImageRevision; /* 0x00 */ 1855 U8 Reserved1; /* 0x01 */ 1856 U8 SizeOfRegion; /* 0x02 */ 1857 U8 Reserved2; /* 0x03 */ 1858 U16 NumberOfLayouts; /* 0x04 */ 1859 U16 RegionsPerLayout; /* 0x06 */ 1860 U16 MinimumSectorAlignment; /* 0x08 */ 1861 U16 Reserved3; /* 0x0A */ 1862 U32 Reserved4; /* 0x0C */ 1863 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */ 1864 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA, 1865 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t; 1866 1867 /* defines for the RegionType field */ 1868 #define MPI2_FLASH_REGION_UNUSED (0x00) 1869 #define MPI2_FLASH_REGION_FIRMWARE (0x01) 1870 #define MPI2_FLASH_REGION_BIOS (0x02) 1871 #define MPI2_FLASH_REGION_NVDATA (0x03) 1872 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05) 1873 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06) 1874 #define MPI2_FLASH_REGION_CONFIG_1 (0x07) 1875 #define MPI2_FLASH_REGION_CONFIG_2 (0x08) 1876 #define MPI2_FLASH_REGION_MEGARAID (0x09) 1877 #define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK (0x0A) 1878 #define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK) /* older name */ 1879 #define MPI2_FLASH_REGION_CBB_BACKUP (0x0D) 1880 #define MPI2_FLASH_REGION_SBR (0x0E) 1881 #define MPI2_FLASH_REGION_SBR_BACKUP (0x0F) 1882 #define MPI2_FLASH_REGION_HIIM (0x10) 1883 #define MPI2_FLASH_REGION_HIIA (0x11) 1884 #define MPI2_FLASH_REGION_CTLR (0x12) 1885 #define MPI2_FLASH_REGION_IMR_FIRMWARE (0x13) 1886 #define MPI2_FLASH_REGION_MR_NVDATA (0x14) 1887 1888 /* ImageRevision */ 1889 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) 1890 1891 1892 1893 /* Supported Devices Extended Image Data */ 1894 1895 /* 1896 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1897 * one and check NumberOfDevices at runtime. 1898 */ 1899 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES 1900 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1) 1901 #endif 1902 1903 typedef struct _MPI2_SUPPORTED_DEVICE 1904 { 1905 U16 DeviceID; /* 0x00 */ 1906 U16 VendorID; /* 0x02 */ 1907 U16 DeviceIDMask; /* 0x04 */ 1908 U16 Reserved1; /* 0x06 */ 1909 U8 LowPCIRev; /* 0x08 */ 1910 U8 HighPCIRev; /* 0x09 */ 1911 U16 Reserved2; /* 0x0A */ 1912 U32 Reserved3; /* 0x0C */ 1913 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE, 1914 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t; 1915 1916 typedef struct _MPI2_SUPPORTED_DEVICES_DATA 1917 { 1918 U8 ImageRevision; /* 0x00 */ 1919 U8 Reserved1; /* 0x01 */ 1920 U8 NumberOfDevices; /* 0x02 */ 1921 U8 Reserved2; /* 0x03 */ 1922 U32 Reserved3; /* 0x04 */ 1923 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */ 1924 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA, 1925 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t; 1926 1927 /* ImageRevision */ 1928 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00) 1929 1930 1931 /* Init Extended Image Data */ 1932 1933 typedef struct _MPI2_INIT_IMAGE_FOOTER 1934 1935 { 1936 U32 BootFlags; /* 0x00 */ 1937 U32 ImageSize; /* 0x04 */ 1938 U32 Signature0; /* 0x08 */ 1939 U32 Signature1; /* 0x0C */ 1940 U32 Signature2; /* 0x10 */ 1941 U32 ResetVector; /* 0x14 */ 1942 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER, 1943 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t; 1944 1945 /* defines for the BootFlags field */ 1946 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00) 1947 1948 /* defines for the ImageSize field */ 1949 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04) 1950 1951 /* defines for the Signature0 field */ 1952 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08) 1953 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA) 1954 1955 /* defines for the Signature1 field */ 1956 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C) 1957 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5) 1958 1959 /* defines for the Signature2 field */ 1960 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10) 1961 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A) 1962 1963 /* Signature fields as individual bytes */ 1964 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA) 1965 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A) 1966 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5) 1967 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A) 1968 1969 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5) 1970 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA) 1971 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A) 1972 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5) 1973 1974 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A) 1975 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5) 1976 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA) 1977 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A) 1978 1979 /* defines for the ResetVector field */ 1980 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14) 1981 1982 1983 /* Encrypted Hash Extended Image Data */ 1984 1985 typedef struct _MPI25_ENCRYPTED_HASH_ENTRY 1986 { 1987 U8 HashImageType; /* 0x00 */ 1988 U8 HashAlgorithm; /* 0x01 */ 1989 U8 EncryptionAlgorithm; /* 0x02 */ 1990 U8 Reserved1; /* 0x03 */ 1991 U32 Reserved2; /* 0x04 */ 1992 U32 EncryptedHash[1]; /* 0x08 */ /* variable length */ 1993 } MPI25_ENCRYPTED_HASH_ENTRY, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_ENTRY, 1994 Mpi25EncryptedHashEntry_t, MPI2_POINTER pMpi25EncryptedHashEntry_t; 1995 1996 /* values for HashImageType */ 1997 #define MPI25_HASH_IMAGE_TYPE_UNUSED (0x00) 1998 #define MPI25_HASH_IMAGE_TYPE_FIRMWARE (0x01) 1999 #define MPI25_HASH_IMAGE_TYPE_BIOS (0x02) 2000 2001 /* values for HashAlgorithm */ 2002 #define MPI25_HASH_ALGORITHM_UNUSED (0x00) 2003 #define MPI25_HASH_ALGORITHM_SHA256 (0x01) 2004 2005 /* values for EncryptionAlgorithm */ 2006 #define MPI25_ENCRYPTION_ALG_UNUSED (0x00) 2007 #define MPI25_ENCRYPTION_ALG_RSA256 (0x01) 2008 2009 typedef struct _MPI25_ENCRYPTED_HASH_DATA 2010 { 2011 U8 ImageVersion; /* 0x00 */ 2012 U8 NumHash; /* 0x01 */ 2013 U16 Reserved1; /* 0x02 */ 2014 U32 Reserved2; /* 0x04 */ 2015 MPI25_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[1]; /* 0x08 */ /* variable number of entries */ 2016 } MPI25_ENCRYPTED_HASH_DATA, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_DATA, 2017 Mpi25EncryptedHashData_t, MPI2_POINTER pMpi25EncryptedHashData_t; 2018 2019 /**************************************************************************** 2020 * PowerManagementControl message 2021 ****************************************************************************/ 2022 2023 /* PowerManagementControl Request message */ 2024 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST 2025 { 2026 U8 Feature; /* 0x00 */ 2027 U8 Reserved1; /* 0x01 */ 2028 U8 ChainOffset; /* 0x02 */ 2029 U8 Function; /* 0x03 */ 2030 U16 Reserved2; /* 0x04 */ 2031 U8 Reserved3; /* 0x06 */ 2032 U8 MsgFlags; /* 0x07 */ 2033 U8 VP_ID; /* 0x08 */ 2034 U8 VF_ID; /* 0x09 */ 2035 U16 Reserved4; /* 0x0A */ 2036 U8 Parameter1; /* 0x0C */ 2037 U8 Parameter2; /* 0x0D */ 2038 U8 Parameter3; /* 0x0E */ 2039 U8 Parameter4; /* 0x0F */ 2040 U32 Reserved5; /* 0x10 */ 2041 U32 Reserved6; /* 0x14 */ 2042 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST, 2043 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t; 2044 2045 /* defines for the Feature field */ 2046 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01) 2047 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02) 2048 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /* obsolete */ 2049 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04) 2050 #define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05) /* reserved in MPI 2.0 */ 2051 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80) 2052 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF) 2053 2054 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */ 2055 /* Parameter1 contains a PHY number */ 2056 /* Parameter2 indicates power condition action using these defines */ 2057 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01) 2058 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02) 2059 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03) 2060 /* Parameter3 and Parameter4 are reserved */ 2061 2062 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */ 2063 /* Parameter1 contains SAS port width modulation group number */ 2064 /* Parameter2 indicates IOC action using these defines */ 2065 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01) 2066 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02) 2067 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03) 2068 /* Parameter3 indicates desired modulation level using these defines */ 2069 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00) 2070 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01) 2071 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02) 2072 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03) 2073 /* Parameter4 is reserved */ 2074 2075 /* this next set (_PCIE_LINK) is obsolete */ 2076 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */ 2077 /* Parameter1 indicates desired PCIe link speed using these defines */ 2078 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /* obsolete */ 2079 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /* obsolete */ 2080 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /* obsolete */ 2081 /* Parameter2 indicates desired PCIe link width using these defines */ 2082 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /* obsolete */ 2083 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /* obsolete */ 2084 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /* obsolete */ 2085 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /* obsolete */ 2086 /* Parameter3 and Parameter4 are reserved */ 2087 2088 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */ 2089 /* Parameter1 indicates desired IOC hardware clock speed using these defines */ 2090 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01) 2091 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02) 2092 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04) 2093 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08) 2094 /* Parameter2, Parameter3, and Parameter4 are reserved */ 2095 2096 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature */ 2097 /* Parameter1 indicates host action regarding global power management mode */ 2098 #define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01) 2099 #define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02) 2100 #define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03) 2101 /* Parameter2 indicates the requested global power management mode */ 2102 #define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01) 2103 #define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08) 2104 #define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40) 2105 /* Parameter3 and Parameter4 are reserved */ 2106 2107 2108 /* PowerManagementControl Reply message */ 2109 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY 2110 { 2111 U8 Feature; /* 0x00 */ 2112 U8 Reserved1; /* 0x01 */ 2113 U8 MsgLength; /* 0x02 */ 2114 U8 Function; /* 0x03 */ 2115 U16 Reserved2; /* 0x04 */ 2116 U8 Reserved3; /* 0x06 */ 2117 U8 MsgFlags; /* 0x07 */ 2118 U8 VP_ID; /* 0x08 */ 2119 U8 VF_ID; /* 0x09 */ 2120 U16 Reserved4; /* 0x0A */ 2121 U16 Reserved5; /* 0x0C */ 2122 U16 IOCStatus; /* 0x0E */ 2123 U32 IOCLogInfo; /* 0x10 */ 2124 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY, 2125 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t; 2126 2127 2128 /**************************************************************************** 2129 * IO Unit Control messages (MPI v2.6 and later only.) 2130 ****************************************************************************/ 2131 2132 /* IO Unit Control Request Message */ 2133 typedef struct _MPI26_IOUNIT_CONTROL_REQUEST 2134 { 2135 U8 Operation; /* 0x00 */ 2136 U8 Reserved1; /* 0x01 */ 2137 U8 ChainOffset; /* 0x02 */ 2138 U8 Function; /* 0x03 */ 2139 U16 DevHandle; /* 0x04 */ 2140 U8 IOCParameter; /* 0x06 */ 2141 U8 MsgFlags; /* 0x07 */ 2142 U8 VP_ID; /* 0x08 */ 2143 U8 VF_ID; /* 0x09 */ 2144 U16 Reserved3; /* 0x0A */ 2145 U16 Reserved4; /* 0x0C */ 2146 U8 PhyNum; /* 0x0E */ 2147 U8 PrimFlags; /* 0x0F */ 2148 U32 Primitive; /* 0x10 */ 2149 U8 LookupMethod; /* 0x14 */ 2150 U8 Reserved5; /* 0x15 */ 2151 U16 SlotNumber; /* 0x16 */ 2152 U64 LookupAddress; /* 0x18 */ 2153 U32 IOCParameterValue; /* 0x20 */ 2154 U32 Reserved7; /* 0x24 */ 2155 U32 Reserved8; /* 0x28 */ 2156 } MPI26_IOUNIT_CONTROL_REQUEST, 2157 MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REQUEST, 2158 Mpi26IoUnitControlRequest_t, MPI2_POINTER pMpi26IoUnitControlRequest_t; 2159 2160 /* values for the Operation field */ 2161 #define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02) 2162 #define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06) 2163 #define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07) 2164 #define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08) 2165 #define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09) 2166 #define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A) 2167 #define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B) 2168 #define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D) 2169 #define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E) 2170 #define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F) 2171 #define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10) 2172 #define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11) 2173 #define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12) 2174 #define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13) 2175 #define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14) 2176 #define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15) 2177 #define MPI26_CTRL_OP_SHUTDOWN (0x16) 2178 #define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17) 2179 #define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18) 2180 #define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19) 2181 #define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT (0x1A) 2182 #define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT (0x1B) 2183 #define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80) 2184 2185 /* values for the PrimFlags field */ 2186 #define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08) 2187 #define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02) 2188 #define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01) 2189 2190 /* values for the LookupMethod field */ 2191 #define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01) 2192 #define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02) 2193 #define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) 2194 2195 2196 /* IO Unit Control Reply Message */ 2197 typedef struct _MPI26_IOUNIT_CONTROL_REPLY 2198 { 2199 U8 Operation; /* 0x00 */ 2200 U8 Reserved1; /* 0x01 */ 2201 U8 MsgLength; /* 0x02 */ 2202 U8 Function; /* 0x03 */ 2203 U16 DevHandle; /* 0x04 */ 2204 U8 IOCParameter; /* 0x06 */ 2205 U8 MsgFlags; /* 0x07 */ 2206 U8 VP_ID; /* 0x08 */ 2207 U8 VF_ID; /* 0x09 */ 2208 U16 Reserved3; /* 0x0A */ 2209 U16 Reserved4; /* 0x0C */ 2210 U16 IOCStatus; /* 0x0E */ 2211 U32 IOCLogInfo; /* 0x10 */ 2212 } MPI26_IOUNIT_CONTROL_REPLY, MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REPLY, 2213 Mpi26IoUnitControlReply_t, MPI2_POINTER pMpi26IoUnitControlReply_t; 2214 2215 2216 #endif 2217 2218