xref: /linux/drivers/net/ethernet/mellanox/mlxsw/reg.h (revision ed7171ff9fabc49ae6ed42fbd082a576473836fc)
1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3 
4 #ifndef _MLXSW_REG_H
5 #define _MLXSW_REG_H
6 
7 #include <linux/kernel.h>
8 #include <linux/string.h>
9 #include <linux/bitops.h>
10 #include <linux/if_vlan.h>
11 
12 #include "item.h"
13 #include "port.h"
14 
15 struct mlxsw_reg_info {
16 	u16 id;
17 	u16 len; /* In u8 */
18 	const char *name;
19 };
20 
21 #define MLXSW_REG_DEFINE(_name, _id, _len)				\
22 static const struct mlxsw_reg_info mlxsw_reg_##_name = {		\
23 	.id = _id,							\
24 	.len = _len,							\
25 	.name = #_name,							\
26 }
27 
28 #define MLXSW_REG(type) (&mlxsw_reg_##type)
29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
31 
32 /* SGCR - Switch General Configuration Register
33  * --------------------------------------------
34  * This register is used for configuration of the switch capabilities.
35  */
36 #define MLXSW_REG_SGCR_ID 0x2000
37 #define MLXSW_REG_SGCR_LEN 0x10
38 
39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
40 
41 /* reg_sgcr_lag_lookup_pgt_base
42  * Base address used for lookup in PGT table
43  * Supported when CONFIG_PROFILE.lag_mode = 1
44  * Note: when IGCR.ddd_lag_mode=0, the address shall be aligned to 8 entries.
45  * Access: RW
46  */
47 MLXSW_ITEM32(reg, sgcr, lag_lookup_pgt_base, 0x0C, 0, 16);
48 
49 static inline void mlxsw_reg_sgcr_pack(char *payload, u16 lag_lookup_pgt_base)
50 {
51 	MLXSW_REG_ZERO(sgcr, payload);
52 	mlxsw_reg_sgcr_lag_lookup_pgt_base_set(payload, lag_lookup_pgt_base);
53 }
54 
55 /* SPAD - Switch Physical Address Register
56  * ---------------------------------------
57  * The SPAD register configures the switch physical MAC address.
58  */
59 #define MLXSW_REG_SPAD_ID 0x2002
60 #define MLXSW_REG_SPAD_LEN 0x10
61 
62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
63 
64 /* reg_spad_base_mac
65  * Base MAC address for the switch partitions.
66  * Per switch partition MAC address is equal to:
67  * base_mac + swid
68  * Access: RW
69  */
70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
71 
72 /* SSPR - Switch System Port Record Register
73  * -----------------------------------------
74  * Configures the system port to local port mapping.
75  */
76 #define MLXSW_REG_SSPR_ID 0x2008
77 #define MLXSW_REG_SSPR_LEN 0x8
78 
79 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
80 
81 /* reg_sspr_m
82  * Master - if set, then the record describes the master system port.
83  * This is needed in case a local port is mapped into several system ports
84  * (for multipathing). That number will be reported as the source system
85  * port when packets are forwarded to the CPU. Only one master port is allowed
86  * per local port.
87  *
88  * Note: Must be set for Spectrum.
89  * Access: RW
90  */
91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
92 
93 /* reg_sspr_local_port
94  * Local port number.
95  *
96  * Access: RW
97  */
98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12);
99 
100 /* reg_sspr_system_port
101  * Unique identifier within the stacking domain that represents all the ports
102  * that are available in the system (external ports).
103  *
104  * Currently, only single-ASIC configurations are supported, so we default to
105  * 1:1 mapping between system ports and local ports.
106  * Access: Index
107  */
108 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
109 
110 static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port)
111 {
112 	MLXSW_REG_ZERO(sspr, payload);
113 	mlxsw_reg_sspr_m_set(payload, 1);
114 	mlxsw_reg_sspr_local_port_set(payload, local_port);
115 	mlxsw_reg_sspr_system_port_set(payload, local_port);
116 }
117 
118 /* SFDAT - Switch Filtering Database Aging Time
119  * --------------------------------------------
120  * Controls the Switch aging time. Aging time is able to be set per Switch
121  * Partition.
122  */
123 #define MLXSW_REG_SFDAT_ID 0x2009
124 #define MLXSW_REG_SFDAT_LEN 0x8
125 
126 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
127 
128 /* reg_sfdat_swid
129  * Switch partition ID.
130  * Access: Index
131  */
132 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
133 
134 /* reg_sfdat_age_time
135  * Aging time in seconds
136  * Min - 10 seconds
137  * Max - 1,000,000 seconds
138  * Default is 300 seconds.
139  * Access: RW
140  */
141 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
142 
143 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
144 {
145 	MLXSW_REG_ZERO(sfdat, payload);
146 	mlxsw_reg_sfdat_swid_set(payload, 0);
147 	mlxsw_reg_sfdat_age_time_set(payload, age_time);
148 }
149 
150 /* SFD - Switch Filtering Database
151  * -------------------------------
152  * The following register defines the access to the filtering database.
153  * The register supports querying, adding, removing and modifying the database.
154  * The access is optimized for bulk updates in which case more than one
155  * FDB record is present in the same command.
156  */
157 #define MLXSW_REG_SFD_ID 0x200A
158 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
159 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
160 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
161 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN +	\
162 			   MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
163 
164 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
165 
166 /* reg_sfd_swid
167  * Switch partition ID for queries. Reserved on Write.
168  * Access: Index
169  */
170 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
171 
172 enum mlxsw_reg_sfd_op {
173 	/* Dump entire FDB a (process according to record_locator) */
174 	MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
175 	/* Query records by {MAC, VID/FID} value */
176 	MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
177 	/* Query and clear activity. Query records by {MAC, VID/FID} value */
178 	MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
179 	/* Test. Response indicates if each of the records could be
180 	 * added to the FDB.
181 	 */
182 	MLXSW_REG_SFD_OP_WRITE_TEST = 0,
183 	/* Add/modify. Aged-out records cannot be added. This command removes
184 	 * the learning notification of the {MAC, VID/FID}. Response includes
185 	 * the entries that were added to the FDB.
186 	 */
187 	MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
188 	/* Remove record by {MAC, VID/FID}. This command also removes
189 	 * the learning notification and aged-out notifications
190 	 * of the {MAC, VID/FID}. The response provides current (pre-removal)
191 	 * entries as non-aged-out.
192 	 */
193 	MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
194 	/* Remove learned notification by {MAC, VID/FID}. The response provides
195 	 * the removed learning notification.
196 	 */
197 	MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
198 };
199 
200 /* reg_sfd_op
201  * Operation.
202  * Access: OP
203  */
204 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
205 
206 /* reg_sfd_record_locator
207  * Used for querying the FDB. Use record_locator=0 to initiate the
208  * query. When a record is returned, a new record_locator is
209  * returned to be used in the subsequent query.
210  * Reserved for database update.
211  * Access: Index
212  */
213 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
214 
215 /* reg_sfd_num_rec
216  * Request: Number of records to read/add/modify/remove
217  * Response: Number of records read/added/replaced/removed
218  * See above description for more details.
219  * Ranges 0..64
220  * Access: RW
221  */
222 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
223 
224 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
225 				      u32 record_locator)
226 {
227 	MLXSW_REG_ZERO(sfd, payload);
228 	mlxsw_reg_sfd_op_set(payload, op);
229 	mlxsw_reg_sfd_record_locator_set(payload, record_locator);
230 }
231 
232 /* reg_sfd_rec_swid
233  * Switch partition ID.
234  * Access: Index
235  */
236 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
237 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
238 
239 enum mlxsw_reg_sfd_rec_type {
240 	MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
241 	MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
242 	MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
243 	MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
244 };
245 
246 /* reg_sfd_rec_type
247  * FDB record type.
248  * Access: RW
249  */
250 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
251 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
252 
253 enum mlxsw_reg_sfd_rec_policy {
254 	/* Replacement disabled, aging disabled. */
255 	MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
256 	/* (mlag remote): Replacement enabled, aging disabled,
257 	 * learning notification enabled on this port.
258 	 */
259 	MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
260 	/* (ingress device): Replacement enabled, aging enabled. */
261 	MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
262 };
263 
264 /* reg_sfd_rec_policy
265  * Policy.
266  * Access: RW
267  */
268 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
269 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
270 
271 /* reg_sfd_rec_a
272  * Activity. Set for new static entries. Set for static entries if a frame SMAC
273  * lookup hits on the entry.
274  * To clear the a bit, use "query and clear activity" op.
275  * Access: RO
276  */
277 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
278 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
279 
280 /* reg_sfd_rec_mac
281  * MAC address.
282  * Access: Index
283  */
284 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
285 		       MLXSW_REG_SFD_REC_LEN, 0x02);
286 
287 enum mlxsw_reg_sfd_rec_action {
288 	/* forward */
289 	MLXSW_REG_SFD_REC_ACTION_NOP = 0,
290 	/* forward and trap, trap_id is FDB_TRAP */
291 	MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
292 	/* trap and do not forward, trap_id is FDB_TRAP */
293 	MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
294 	/* forward to IP router */
295 	MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
296 	MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
297 };
298 
299 /* reg_sfd_rec_action
300  * Action to apply on the packet.
301  * Note: Dynamic entries can only be configured with NOP action.
302  * Access: RW
303  */
304 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
305 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
306 
307 /* reg_sfd_uc_sub_port
308  * VEPA channel on local port.
309  * Valid only if local port is a non-stacking port. Must be 0 if multichannel
310  * VEPA is not enabled.
311  * Access: RW
312  */
313 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
314 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
315 
316 /* reg_sfd_uc_set_vid
317  * Set VID.
318  * 0 - Do not update VID.
319  * 1 - Set VID.
320  * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid.
321  * Access: RW
322  *
323  * Note: Reserved when legacy bridge model is used.
324  */
325 MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1,
326 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
327 
328 /* reg_sfd_uc_fid_vid
329  * Filtering ID or VLAN ID
330  * For SwitchX and SwitchX-2:
331  * - Dynamic entries (policy 2,3) use FID
332  * - Static entries (policy 0) use VID
333  * - When independent learning is configured, VID=FID
334  * For Spectrum: use FID for both Dynamic and Static entries.
335  * VID should not be used.
336  * Access: Index
337  */
338 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
339 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
340 
341 /* reg_sfd_uc_vid
342  * New VID when set_vid=1.
343  * Access: RW
344  *
345  * Note: Reserved when legacy bridge model is used and when set_vid=0.
346  */
347 MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
348 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
349 
350 /* reg_sfd_uc_system_port
351  * Unique port identifier for the final destination of the packet.
352  * Access: RW
353  */
354 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
355 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
356 
357 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
358 					  enum mlxsw_reg_sfd_rec_type rec_type,
359 					  const char *mac,
360 					  enum mlxsw_reg_sfd_rec_action action)
361 {
362 	u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
363 
364 	if (rec_index >= num_rec)
365 		mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
366 	mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
367 	mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
368 	mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
369 	mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
370 }
371 
372 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
373 					 enum mlxsw_reg_sfd_rec_policy policy,
374 					 const char *mac, u16 fid_vid, u16 vid,
375 					 enum mlxsw_reg_sfd_rec_action action,
376 					 u16 local_port)
377 {
378 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
379 			       MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
380 	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
381 	mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
382 	mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
383 	mlxsw_reg_sfd_uc_set_vid_set(payload, rec_index, vid ? true : false);
384 	mlxsw_reg_sfd_uc_vid_set(payload, rec_index, vid);
385 	mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
386 }
387 
388 /* reg_sfd_uc_lag_sub_port
389  * LAG sub port.
390  * Must be 0 if multichannel VEPA is not enabled.
391  * Access: RW
392  */
393 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
394 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
395 
396 /* reg_sfd_uc_lag_set_vid
397  * Set VID.
398  * 0 - Do not update VID.
399  * 1 - Set VID.
400  * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid.
401  * Access: RW
402  *
403  * Note: Reserved when legacy bridge model is used.
404  */
405 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1,
406 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
407 
408 /* reg_sfd_uc_lag_fid_vid
409  * Filtering ID or VLAN ID
410  * For SwitchX and SwitchX-2:
411  * - Dynamic entries (policy 2,3) use FID
412  * - Static entries (policy 0) use VID
413  * - When independent learning is configured, VID=FID
414  * For Spectrum: use FID for both Dynamic and Static entries.
415  * VID should not be used.
416  * Access: Index
417  */
418 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
419 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
420 
421 /* reg_sfd_uc_lag_lag_vid
422  * New vlan ID.
423  * Access: RW
424  *
425  * Note: Reserved when legacy bridge model is used and set_vid=0.
426  */
427 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
428 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
429 
430 /* reg_sfd_uc_lag_lag_id
431  * LAG Identifier - pointer into the LAG descriptor table.
432  * Access: RW
433  */
434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
435 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
436 
437 static inline void
438 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
439 			  enum mlxsw_reg_sfd_rec_policy policy,
440 			  const char *mac, u16 fid_vid,
441 			  enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
442 			  u16 lag_id)
443 {
444 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
445 			       MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
446 			       mac, action);
447 	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
448 	mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
449 	mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
450 	mlxsw_reg_sfd_uc_lag_set_vid_set(payload, rec_index, true);
451 	mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
452 	mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
453 }
454 
455 /* reg_sfd_mc_pgi
456  *
457  * Multicast port group index - index into the port group table.
458  * Value 0x1FFF indicates the pgi should point to the MID entry.
459  * For Spectrum this value must be set to 0x1FFF
460  * Access: RW
461  */
462 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
463 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
464 
465 /* reg_sfd_mc_fid_vid
466  *
467  * Filtering ID or VLAN ID
468  * Access: Index
469  */
470 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
471 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
472 
473 /* reg_sfd_mc_mid
474  *
475  * Multicast identifier - global identifier that represents the multicast
476  * group across all devices.
477  * Access: RW
478  */
479 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
480 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
481 
482 static inline void
483 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
484 		      const char *mac, u16 fid_vid,
485 		      enum mlxsw_reg_sfd_rec_action action, u16 mid)
486 {
487 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
488 			       MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
489 	mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
490 	mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
491 	mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
492 }
493 
494 /* reg_sfd_uc_tunnel_uip_msb
495  * When protocol is IPv4, the most significant byte of the underlay IPv4
496  * destination IP.
497  * When protocol is IPv6, reserved.
498  * Access: RW
499  */
500 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
501 		     8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
502 
503 /* reg_sfd_uc_tunnel_fid
504  * Filtering ID.
505  * Access: Index
506  */
507 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
508 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
509 
510 enum mlxsw_reg_sfd_uc_tunnel_protocol {
511 	MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
512 	MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
513 };
514 
515 /* reg_sfd_uc_tunnel_protocol
516  * IP protocol.
517  * Access: RW
518  */
519 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
520 		     1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
521 
522 /* reg_sfd_uc_tunnel_uip_lsb
523  * When protocol is IPv4, the least significant bytes of the underlay
524  * IPv4 destination IP.
525  * When protocol is IPv6, pointer to the underlay IPv6 destination IP
526  * which is configured by RIPS.
527  * Access: RW
528  */
529 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
530 		     24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
531 
532 static inline void
533 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
534 			     enum mlxsw_reg_sfd_rec_policy policy,
535 			     const char *mac, u16 fid,
536 			     enum mlxsw_reg_sfd_rec_action action,
537 			     enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
538 {
539 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
540 			       MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
541 			       action);
542 	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
543 	mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
544 	mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
545 }
546 
547 static inline void
548 mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index,
549 			      enum mlxsw_reg_sfd_rec_policy policy,
550 			      const char *mac, u16 fid,
551 			      enum mlxsw_reg_sfd_rec_action action, u32 uip)
552 {
553 	mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
554 	mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
555 	mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid,
556 				     action,
557 				     MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4);
558 }
559 
560 static inline void
561 mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac,
562 			      u16 fid, enum mlxsw_reg_sfd_rec_action action,
563 			      u32 uip_ptr)
564 {
565 	mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr);
566 	/* Only static policy is supported for IPv6 unicast tunnel entry. */
567 	mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index,
568 				     MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY,
569 				     mac, fid, action,
570 				     MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6);
571 }
572 
573 enum mlxsw_reg_tunnel_port {
574 	MLXSW_REG_TUNNEL_PORT_NVE,
575 	MLXSW_REG_TUNNEL_PORT_VPLS,
576 	MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0,
577 	MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1,
578 };
579 
580 /* SFN - Switch FDB Notification Register
581  * -------------------------------------------
582  * The switch provides notifications on newly learned FDB entries and
583  * aged out entries. The notifications can be polled by software.
584  */
585 #define MLXSW_REG_SFN_ID 0x200B
586 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
587 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
588 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
589 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN +	\
590 			   MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
591 
592 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
593 
594 /* reg_sfn_swid
595  * Switch partition ID.
596  * Access: Index
597  */
598 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
599 
600 /* reg_sfn_end
601  * Forces the current session to end.
602  * Access: OP
603  */
604 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
605 
606 /* reg_sfn_num_rec
607  * Request: Number of learned notifications and aged-out notification
608  * records requested.
609  * Response: Number of notification records returned (must be smaller
610  * than or equal to the value requested)
611  * Ranges 0..64
612  * Access: OP
613  */
614 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
615 
616 static inline void mlxsw_reg_sfn_pack(char *payload)
617 {
618 	MLXSW_REG_ZERO(sfn, payload);
619 	mlxsw_reg_sfn_swid_set(payload, 0);
620 	mlxsw_reg_sfn_end_set(payload, 0);
621 	mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
622 }
623 
624 /* reg_sfn_rec_swid
625  * Switch partition ID.
626  * Access: RO
627  */
628 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
629 		     MLXSW_REG_SFN_REC_LEN, 0x00, false);
630 
631 enum mlxsw_reg_sfn_rec_type {
632 	/* MAC addresses learned on a regular port. */
633 	MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
634 	/* MAC addresses learned on a LAG port. */
635 	MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
636 	/* Aged-out MAC address on a regular port. */
637 	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
638 	/* Aged-out MAC address on a LAG port. */
639 	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
640 	/* Learned unicast tunnel record. */
641 	MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,
642 	/* Aged-out unicast tunnel record. */
643 	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
644 };
645 
646 /* reg_sfn_rec_type
647  * Notification record type.
648  * Access: RO
649  */
650 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
651 		     MLXSW_REG_SFN_REC_LEN, 0x00, false);
652 
653 /* reg_sfn_rec_mac
654  * MAC address.
655  * Access: RO
656  */
657 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
658 		       MLXSW_REG_SFN_REC_LEN, 0x02);
659 
660 /* reg_sfn_mac_sub_port
661  * VEPA channel on the local port.
662  * 0 if multichannel VEPA is not enabled.
663  * Access: RO
664  */
665 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
666 		     MLXSW_REG_SFN_REC_LEN, 0x08, false);
667 
668 /* reg_sfn_mac_fid
669  * Filtering identifier.
670  * Access: RO
671  */
672 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
673 		     MLXSW_REG_SFN_REC_LEN, 0x08, false);
674 
675 /* reg_sfn_mac_system_port
676  * Unique port identifier for the final destination of the packet.
677  * Access: RO
678  */
679 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
680 		     MLXSW_REG_SFN_REC_LEN, 0x0C, false);
681 
682 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
683 					    char *mac, u16 *p_vid,
684 					    u16 *p_local_port)
685 {
686 	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
687 	*p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
688 	*p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
689 }
690 
691 /* reg_sfn_mac_lag_lag_id
692  * LAG ID (pointer into the LAG descriptor table).
693  * Access: RO
694  */
695 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
696 		     MLXSW_REG_SFN_REC_LEN, 0x0C, false);
697 
698 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
699 						char *mac, u16 *p_vid,
700 						u16 *p_lag_id)
701 {
702 	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
703 	*p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
704 	*p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
705 }
706 
707 /* reg_sfn_uc_tunnel_uip_msb
708  * When protocol is IPv4, the most significant byte of the underlay IPv4
709  * address of the remote VTEP.
710  * When protocol is IPv6, reserved.
711  * Access: RO
712  */
713 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
714 		     8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
715 
716 enum mlxsw_reg_sfn_uc_tunnel_protocol {
717 	MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,
718 	MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,
719 };
720 
721 /* reg_sfn_uc_tunnel_protocol
722  * IP protocol.
723  * Access: RO
724  */
725 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
726 		     1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
727 
728 /* reg_sfn_uc_tunnel_uip_lsb
729  * When protocol is IPv4, the least significant bytes of the underlay
730  * IPv4 address of the remote VTEP.
731  * When protocol is IPv6, ipv6_id to be queried from TNIPSD.
732  * Access: RO
733  */
734 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
735 		     24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
736 
737 /* reg_sfn_uc_tunnel_port
738  * Tunnel port.
739  * Reserved on Spectrum.
740  * Access: RO
741  */
742 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
743 		     MLXSW_REG_SFN_REC_LEN, 0x10, false);
744 
745 static inline void
746 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac,
747 			       u16 *p_fid, u32 *p_uip,
748 			       enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)
749 {
750 	u32 uip_msb, uip_lsb;
751 
752 	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
753 	*p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
754 	uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index);
755 	uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index);
756 	*p_uip = uip_msb << 24 | uip_lsb;
757 	*p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index);
758 }
759 
760 /* SPMS - Switch Port MSTP/RSTP State Register
761  * -------------------------------------------
762  * Configures the spanning tree state of a physical port.
763  */
764 #define MLXSW_REG_SPMS_ID 0x200D
765 #define MLXSW_REG_SPMS_LEN 0x404
766 
767 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
768 
769 /* reg_spms_local_port
770  * Local port number.
771  * Access: Index
772  */
773 MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12);
774 
775 enum mlxsw_reg_spms_state {
776 	MLXSW_REG_SPMS_STATE_NO_CHANGE,
777 	MLXSW_REG_SPMS_STATE_DISCARDING,
778 	MLXSW_REG_SPMS_STATE_LEARNING,
779 	MLXSW_REG_SPMS_STATE_FORWARDING,
780 };
781 
782 /* reg_spms_state
783  * Spanning tree state of each VLAN ID (VID) of the local port.
784  * 0 - Do not change spanning tree state (used only when writing).
785  * 1 - Discarding. No learning or forwarding to/from this port (default).
786  * 2 - Learning. Port is learning, but not forwarding.
787  * 3 - Forwarding. Port is learning and forwarding.
788  * Access: RW
789  */
790 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
791 
792 static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port)
793 {
794 	MLXSW_REG_ZERO(spms, payload);
795 	mlxsw_reg_spms_local_port_set(payload, local_port);
796 }
797 
798 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
799 					   enum mlxsw_reg_spms_state state)
800 {
801 	mlxsw_reg_spms_state_set(payload, vid, state);
802 }
803 
804 /* SPVID - Switch Port VID
805  * -----------------------
806  * The switch port VID configures the default VID for a port.
807  */
808 #define MLXSW_REG_SPVID_ID 0x200E
809 #define MLXSW_REG_SPVID_LEN 0x08
810 
811 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
812 
813 /* reg_spvid_tport
814  * Port is tunnel port.
815  * Reserved when SwitchX/-2 or Spectrum-1.
816  * Access: Index
817  */
818 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1);
819 
820 /* reg_spvid_local_port
821  * When tport = 0: Local port number. Not supported for CPU port.
822  * When tport = 1: Tunnel port.
823  * Access: Index
824  */
825 MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12);
826 
827 /* reg_spvid_sub_port
828  * Virtual port within the physical port.
829  * Should be set to 0 when virtual ports are not enabled on the port.
830  * Access: Index
831  */
832 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
833 
834 /* reg_spvid_egr_et_set
835  * When VLAN is pushed at ingress (for untagged packets or for
836  * QinQ push mode) then the EtherType is decided at the egress port.
837  * Reserved when Spectrum-1.
838  * Access: RW
839  */
840 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1);
841 
842 /* reg_spvid_et_vlan
843  * EtherType used for when VLAN is pushed at ingress (for untagged
844  * packets or for QinQ push mode).
845  * 0: ether_type0 - (default)
846  * 1: ether_type1
847  * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2
848  * Ethertype IDs are configured by SVER.
849  * Reserved when egr_et_set = 1.
850  * Access: RW
851  */
852 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2);
853 
854 /* reg_spvid_pvid
855  * Port default VID
856  * Access: RW
857  */
858 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
859 
860 static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid,
861 					u8 et_vlan)
862 {
863 	MLXSW_REG_ZERO(spvid, payload);
864 	mlxsw_reg_spvid_local_port_set(payload, local_port);
865 	mlxsw_reg_spvid_pvid_set(payload, pvid);
866 	mlxsw_reg_spvid_et_vlan_set(payload, et_vlan);
867 }
868 
869 /* SPVM - Switch Port VLAN Membership
870  * ----------------------------------
871  * The Switch Port VLAN Membership register configures the VLAN membership
872  * of a port in a VLAN denoted by VID. VLAN membership is managed per
873  * virtual port. The register can be used to add and remove VID(s) from a port.
874  */
875 #define MLXSW_REG_SPVM_ID 0x200F
876 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
877 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
878 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255
879 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN +	\
880 		    MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
881 
882 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
883 
884 /* reg_spvm_pt
885  * Priority tagged. If this bit is set, packets forwarded to the port with
886  * untagged VLAN membership (u bit is set) will be tagged with priority tag
887  * (VID=0)
888  * Access: RW
889  */
890 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
891 
892 /* reg_spvm_pte
893  * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
894  * the pt bit will NOT be updated. To update the pt bit, pte must be set.
895  * Access: WO
896  */
897 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
898 
899 /* reg_spvm_local_port
900  * Local port number.
901  * Access: Index
902  */
903 MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12);
904 
905 /* reg_spvm_sub_port
906  * Virtual port within the physical port.
907  * Should be set to 0 when virtual ports are not enabled on the port.
908  * Access: Index
909  */
910 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
911 
912 /* reg_spvm_num_rec
913  * Number of records to update. Each record contains: i, e, u, vid.
914  * Access: OP
915  */
916 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
917 
918 /* reg_spvm_rec_i
919  * Ingress membership in VLAN ID.
920  * Access: Index
921  */
922 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
923 		     MLXSW_REG_SPVM_BASE_LEN, 14, 1,
924 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
925 
926 /* reg_spvm_rec_e
927  * Egress membership in VLAN ID.
928  * Access: Index
929  */
930 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
931 		     MLXSW_REG_SPVM_BASE_LEN, 13, 1,
932 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
933 
934 /* reg_spvm_rec_u
935  * Untagged - port is an untagged member - egress transmission uses untagged
936  * frames on VID<n>
937  * Access: Index
938  */
939 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
940 		     MLXSW_REG_SPVM_BASE_LEN, 12, 1,
941 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
942 
943 /* reg_spvm_rec_vid
944  * Egress membership in VLAN ID.
945  * Access: Index
946  */
947 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
948 		     MLXSW_REG_SPVM_BASE_LEN, 0, 12,
949 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
950 
951 static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port,
952 				       u16 vid_begin, u16 vid_end,
953 				       bool is_member, bool untagged)
954 {
955 	int size = vid_end - vid_begin + 1;
956 	int i;
957 
958 	MLXSW_REG_ZERO(spvm, payload);
959 	mlxsw_reg_spvm_local_port_set(payload, local_port);
960 	mlxsw_reg_spvm_num_rec_set(payload, size);
961 
962 	for (i = 0; i < size; i++) {
963 		mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
964 		mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
965 		mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
966 		mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
967 	}
968 }
969 
970 /* SPAFT - Switch Port Acceptable Frame Types
971  * ------------------------------------------
972  * The Switch Port Acceptable Frame Types register configures the frame
973  * admittance of the port.
974  */
975 #define MLXSW_REG_SPAFT_ID 0x2010
976 #define MLXSW_REG_SPAFT_LEN 0x08
977 
978 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
979 
980 /* reg_spaft_local_port
981  * Local port number.
982  * Access: Index
983  *
984  * Note: CPU port is not supported (all tag types are allowed).
985  */
986 MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12);
987 
988 /* reg_spaft_sub_port
989  * Virtual port within the physical port.
990  * Should be set to 0 when virtual ports are not enabled on the port.
991  * Access: RW
992  */
993 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
994 
995 /* reg_spaft_allow_untagged
996  * When set, untagged frames on the ingress are allowed (default).
997  * Access: RW
998  */
999 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
1000 
1001 /* reg_spaft_allow_prio_tagged
1002  * When set, priority tagged frames on the ingress are allowed (default).
1003  * Access: RW
1004  */
1005 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
1006 
1007 /* reg_spaft_allow_tagged
1008  * When set, tagged frames on the ingress are allowed (default).
1009  * Access: RW
1010  */
1011 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
1012 
1013 static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port,
1014 					bool allow_untagged)
1015 {
1016 	MLXSW_REG_ZERO(spaft, payload);
1017 	mlxsw_reg_spaft_local_port_set(payload, local_port);
1018 	mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
1019 	mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged);
1020 	mlxsw_reg_spaft_allow_tagged_set(payload, true);
1021 }
1022 
1023 /* SFGC - Switch Flooding Group Configuration
1024  * ------------------------------------------
1025  * The following register controls the association of flooding tables and MIDs
1026  * to packet types used for flooding.
1027  *
1028  * Reserved when CONFIG_PROFILE.flood_mode = CFF.
1029  */
1030 #define MLXSW_REG_SFGC_ID 0x2011
1031 #define MLXSW_REG_SFGC_LEN 0x14
1032 
1033 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
1034 
1035 enum mlxsw_reg_sfgc_type {
1036 	MLXSW_REG_SFGC_TYPE_BROADCAST,
1037 	MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1038 	MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1039 	MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1040 	MLXSW_REG_SFGC_TYPE_RESERVED,
1041 	MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1042 	MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
1043 	MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
1044 	MLXSW_REG_SFGC_TYPE_MAX,
1045 };
1046 
1047 /* reg_sfgc_type
1048  * The traffic type to reach the flooding table.
1049  * Access: Index
1050  */
1051 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
1052 
1053 /* bridge_type is used in SFGC and SFMR. */
1054 enum mlxsw_reg_bridge_type {
1055 	MLXSW_REG_BRIDGE_TYPE_0 = 0, /* Used for .1q FIDs. */
1056 	MLXSW_REG_BRIDGE_TYPE_1 = 1, /* Used for .1d FIDs. */
1057 };
1058 
1059 /* reg_sfgc_bridge_type
1060  * Access: Index
1061  *
1062  * Note: SwitchX-2 only supports 802.1Q mode.
1063  */
1064 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
1065 
1066 enum mlxsw_flood_table_type {
1067 	MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
1068 	MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
1069 	MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
1070 	MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
1071 	MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
1072 };
1073 
1074 /* reg_sfgc_table_type
1075  * See mlxsw_flood_table_type
1076  * Access: RW
1077  *
1078  * Note: FID offset and FID types are not supported in SwitchX-2.
1079  */
1080 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1081 
1082 /* reg_sfgc_flood_table
1083  * Flooding table index to associate with the specific type on the specific
1084  * switch partition.
1085  * Access: RW
1086  */
1087 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1088 
1089 /* reg_sfgc_counter_set_type
1090  * Counter Set Type for flow counters.
1091  * Access: RW
1092  */
1093 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1094 
1095 /* reg_sfgc_counter_index
1096  * Counter Index for flow counters.
1097  * Access: RW
1098  */
1099 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1100 
1101 /* reg_sfgc_mid_base
1102  * MID Base.
1103  * Access: RW
1104  *
1105  * Note: Reserved when legacy bridge model is used.
1106  */
1107 MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16);
1108 
1109 static inline void
1110 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1111 		    enum mlxsw_reg_bridge_type bridge_type,
1112 		    enum mlxsw_flood_table_type table_type,
1113 		    unsigned int flood_table, u16 mid_base)
1114 {
1115 	MLXSW_REG_ZERO(sfgc, payload);
1116 	mlxsw_reg_sfgc_type_set(payload, type);
1117 	mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1118 	mlxsw_reg_sfgc_table_type_set(payload, table_type);
1119 	mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1120 	mlxsw_reg_sfgc_mid_base_set(payload, mid_base);
1121 }
1122 
1123 /* SFDF - Switch Filtering DB Flush
1124  * --------------------------------
1125  * The switch filtering DB flush register is used to flush the FDB.
1126  * Note that FDB notifications are flushed as well.
1127  */
1128 #define MLXSW_REG_SFDF_ID 0x2013
1129 #define MLXSW_REG_SFDF_LEN 0x14
1130 
1131 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1132 
1133 /* reg_sfdf_swid
1134  * Switch partition ID.
1135  * Access: Index
1136  */
1137 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1138 
1139 enum mlxsw_reg_sfdf_flush_type {
1140 	MLXSW_REG_SFDF_FLUSH_PER_SWID,
1141 	MLXSW_REG_SFDF_FLUSH_PER_FID,
1142 	MLXSW_REG_SFDF_FLUSH_PER_PORT,
1143 	MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1144 	MLXSW_REG_SFDF_FLUSH_PER_LAG,
1145 	MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1146 	MLXSW_REG_SFDF_FLUSH_PER_NVE,
1147 	MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1148 };
1149 
1150 /* reg_sfdf_flush_type
1151  * Flush type.
1152  * 0 - All SWID dynamic entries are flushed.
1153  * 1 - All FID dynamic entries are flushed.
1154  * 2 - All dynamic entries pointing to port are flushed.
1155  * 3 - All FID dynamic entries pointing to port are flushed.
1156  * 4 - All dynamic entries pointing to LAG are flushed.
1157  * 5 - All FID dynamic entries pointing to LAG are flushed.
1158  * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1159  *     flushed.
1160  * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1161  *     flushed, per FID.
1162  * Access: RW
1163  */
1164 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1165 
1166 /* reg_sfdf_flush_static
1167  * Static.
1168  * 0 - Flush only dynamic entries.
1169  * 1 - Flush both dynamic and static entries.
1170  * Access: RW
1171  */
1172 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1173 
1174 static inline void mlxsw_reg_sfdf_pack(char *payload,
1175 				       enum mlxsw_reg_sfdf_flush_type type)
1176 {
1177 	MLXSW_REG_ZERO(sfdf, payload);
1178 	mlxsw_reg_sfdf_flush_type_set(payload, type);
1179 	mlxsw_reg_sfdf_flush_static_set(payload, true);
1180 }
1181 
1182 /* reg_sfdf_fid
1183  * FID to flush.
1184  * Access: RW
1185  */
1186 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1187 
1188 /* reg_sfdf_system_port
1189  * Port to flush.
1190  * Access: RW
1191  */
1192 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1193 
1194 /* reg_sfdf_port_fid_system_port
1195  * Port to flush, pointed to by FID.
1196  * Access: RW
1197  */
1198 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1199 
1200 /* reg_sfdf_lag_id
1201  * LAG ID to flush.
1202  * Access: RW
1203  */
1204 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1205 
1206 /* reg_sfdf_lag_fid_lag_id
1207  * LAG ID to flush, pointed to by FID.
1208  * Access: RW
1209  */
1210 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1211 
1212 /* SLDR - Switch LAG Descriptor Register
1213  * -----------------------------------------
1214  * The switch LAG descriptor register is populated by LAG descriptors.
1215  * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1216  * max_lag-1.
1217  */
1218 #define MLXSW_REG_SLDR_ID 0x2014
1219 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1220 
1221 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1222 
1223 enum mlxsw_reg_sldr_op {
1224 	/* Indicates a creation of a new LAG-ID, lag_id must be valid */
1225 	MLXSW_REG_SLDR_OP_LAG_CREATE,
1226 	MLXSW_REG_SLDR_OP_LAG_DESTROY,
1227 	/* Ports that appear in the list have the Distributor enabled */
1228 	MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1229 	/* Removes ports from the disributor list */
1230 	MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1231 };
1232 
1233 /* reg_sldr_op
1234  * Operation.
1235  * Access: RW
1236  */
1237 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1238 
1239 /* reg_sldr_lag_id
1240  * LAG identifier. The lag_id is the index into the LAG descriptor table.
1241  * Access: Index
1242  */
1243 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1244 
1245 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1246 {
1247 	MLXSW_REG_ZERO(sldr, payload);
1248 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1249 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1250 }
1251 
1252 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1253 {
1254 	MLXSW_REG_ZERO(sldr, payload);
1255 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1256 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1257 }
1258 
1259 /* reg_sldr_num_ports
1260  * The number of member ports of the LAG.
1261  * Reserved for Create / Destroy operations
1262  * For Add / Remove operations - indicates the number of ports in the list.
1263  * Access: RW
1264  */
1265 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1266 
1267 /* reg_sldr_system_port
1268  * System port.
1269  * Access: RW
1270  */
1271 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1272 
1273 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1274 						    u16 local_port)
1275 {
1276 	MLXSW_REG_ZERO(sldr, payload);
1277 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1278 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1279 	mlxsw_reg_sldr_num_ports_set(payload, 1);
1280 	mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1281 }
1282 
1283 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1284 						       u16 local_port)
1285 {
1286 	MLXSW_REG_ZERO(sldr, payload);
1287 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1288 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1289 	mlxsw_reg_sldr_num_ports_set(payload, 1);
1290 	mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1291 }
1292 
1293 /* SLCR - Switch LAG Configuration 2 Register
1294  * -------------------------------------------
1295  * The Switch LAG Configuration register is used for configuring the
1296  * LAG properties of the switch.
1297  */
1298 #define MLXSW_REG_SLCR_ID 0x2015
1299 #define MLXSW_REG_SLCR_LEN 0x10
1300 
1301 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1302 
1303 enum mlxsw_reg_slcr_pp {
1304 	/* Global Configuration (for all ports) */
1305 	MLXSW_REG_SLCR_PP_GLOBAL,
1306 	/* Per port configuration, based on local_port field */
1307 	MLXSW_REG_SLCR_PP_PER_PORT,
1308 };
1309 
1310 /* reg_slcr_pp
1311  * Per Port Configuration
1312  * Note: Reading at Global mode results in reading port 1 configuration.
1313  * Access: Index
1314  */
1315 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1316 
1317 /* reg_slcr_local_port
1318  * Local port number
1319  * Supported from CPU port
1320  * Not supported from router port
1321  * Reserved when pp = Global Configuration
1322  * Access: Index
1323  */
1324 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12);
1325 
1326 enum mlxsw_reg_slcr_type {
1327 	MLXSW_REG_SLCR_TYPE_CRC, /* default */
1328 	MLXSW_REG_SLCR_TYPE_XOR,
1329 	MLXSW_REG_SLCR_TYPE_RANDOM,
1330 };
1331 
1332 /* reg_slcr_type
1333  * Hash type
1334  * Access: RW
1335  */
1336 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1337 
1338 /* Ingress port */
1339 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT		BIT(0)
1340 /* SMAC - for IPv4 and IPv6 packets */
1341 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP		BIT(1)
1342 /* SMAC - for non-IP packets */
1343 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP	BIT(2)
1344 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1345 	(MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1346 	 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1347 /* DMAC - for IPv4 and IPv6 packets */
1348 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP		BIT(3)
1349 /* DMAC - for non-IP packets */
1350 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP	BIT(4)
1351 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1352 	(MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1353 	 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1354 /* Ethertype - for IPv4 and IPv6 packets */
1355 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP	BIT(5)
1356 /* Ethertype - for non-IP packets */
1357 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP	BIT(6)
1358 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1359 	(MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1360 	 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1361 /* VLAN ID - for IPv4 and IPv6 packets */
1362 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP	BIT(7)
1363 /* VLAN ID - for non-IP packets */
1364 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP	BIT(8)
1365 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1366 	(MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1367 	 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1368 /* Source IP address (can be IPv4 or IPv6) */
1369 #define MLXSW_REG_SLCR_LAG_HASH_SIP		BIT(9)
1370 /* Destination IP address (can be IPv4 or IPv6) */
1371 #define MLXSW_REG_SLCR_LAG_HASH_DIP		BIT(10)
1372 /* TCP/UDP source port */
1373 #define MLXSW_REG_SLCR_LAG_HASH_SPORT		BIT(11)
1374 /* TCP/UDP destination port*/
1375 #define MLXSW_REG_SLCR_LAG_HASH_DPORT		BIT(12)
1376 /* IPv4 Protocol/IPv6 Next Header */
1377 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO		BIT(13)
1378 /* IPv6 Flow label */
1379 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL	BIT(14)
1380 /* SID - FCoE source ID */
1381 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID	BIT(15)
1382 /* DID - FCoE destination ID */
1383 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID	BIT(16)
1384 /* OXID - FCoE originator exchange ID */
1385 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID	BIT(17)
1386 /* Destination QP number - for RoCE packets */
1387 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP	BIT(19)
1388 
1389 /* reg_slcr_lag_hash
1390  * LAG hashing configuration. This is a bitmask, in which each set
1391  * bit includes the corresponding item in the LAG hash calculation.
1392  * The default lag_hash contains SMAC, DMAC, VLANID and
1393  * Ethertype (for all packet types).
1394  * Access: RW
1395  */
1396 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1397 
1398 /* reg_slcr_seed
1399  * LAG seed value. The seed is the same for all ports.
1400  * Access: RW
1401  */
1402 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1403 
1404 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1405 {
1406 	MLXSW_REG_ZERO(slcr, payload);
1407 	mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1408 	mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1409 	mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1410 	mlxsw_reg_slcr_seed_set(payload, seed);
1411 }
1412 
1413 /* SLCOR - Switch LAG Collector Register
1414  * -------------------------------------
1415  * The Switch LAG Collector register controls the Local Port membership
1416  * in a LAG and enablement of the collector.
1417  */
1418 #define MLXSW_REG_SLCOR_ID 0x2016
1419 #define MLXSW_REG_SLCOR_LEN 0x10
1420 
1421 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1422 
1423 enum mlxsw_reg_slcor_col {
1424 	/* Port is added with collector disabled */
1425 	MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1426 	MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1427 	MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1428 	MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1429 };
1430 
1431 /* reg_slcor_col
1432  * Collector configuration
1433  * Access: RW
1434  */
1435 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1436 
1437 /* reg_slcor_local_port
1438  * Local port number
1439  * Not supported for CPU port
1440  * Access: Index
1441  */
1442 MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12);
1443 
1444 /* reg_slcor_lag_id
1445  * LAG Identifier. Index into the LAG descriptor table.
1446  * Access: Index
1447  */
1448 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1449 
1450 /* reg_slcor_port_index
1451  * Port index in the LAG list. Only valid on Add Port to LAG col.
1452  * Valid range is from 0 to cap_max_lag_members-1
1453  * Access: RW
1454  */
1455 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1456 
1457 static inline void mlxsw_reg_slcor_pack(char *payload,
1458 					u16 local_port, u16 lag_id,
1459 					enum mlxsw_reg_slcor_col col)
1460 {
1461 	MLXSW_REG_ZERO(slcor, payload);
1462 	mlxsw_reg_slcor_col_set(payload, col);
1463 	mlxsw_reg_slcor_local_port_set(payload, local_port);
1464 	mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1465 }
1466 
1467 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1468 						 u16 local_port, u16 lag_id,
1469 						 u8 port_index)
1470 {
1471 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1472 			     MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1473 	mlxsw_reg_slcor_port_index_set(payload, port_index);
1474 }
1475 
1476 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1477 						    u16 local_port, u16 lag_id)
1478 {
1479 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1480 			     MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1481 }
1482 
1483 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1484 						   u16 local_port, u16 lag_id)
1485 {
1486 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1487 			     MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1488 }
1489 
1490 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1491 						    u16 local_port, u16 lag_id)
1492 {
1493 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1494 			     MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1495 }
1496 
1497 /* SPMLR - Switch Port MAC Learning Register
1498  * -----------------------------------------
1499  * Controls the Switch MAC learning policy per port.
1500  */
1501 #define MLXSW_REG_SPMLR_ID 0x2018
1502 #define MLXSW_REG_SPMLR_LEN 0x8
1503 
1504 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1505 
1506 /* reg_spmlr_local_port
1507  * Local port number.
1508  * Access: Index
1509  */
1510 MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12);
1511 
1512 /* reg_spmlr_sub_port
1513  * Virtual port within the physical port.
1514  * Should be set to 0 when virtual ports are not enabled on the port.
1515  * Access: Index
1516  */
1517 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1518 
1519 enum mlxsw_reg_spmlr_learn_mode {
1520 	MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1521 	MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1522 	MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1523 };
1524 
1525 /* reg_spmlr_learn_mode
1526  * Learning mode on the port.
1527  * 0 - Learning disabled.
1528  * 2 - Learning enabled.
1529  * 3 - Security mode.
1530  *
1531  * In security mode the switch does not learn MACs on the port, but uses the
1532  * SMAC to see if it exists on another ingress port. If so, the packet is
1533  * classified as a bad packet and is discarded unless the software registers
1534  * to receive port security error packets usign HPKT.
1535  */
1536 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1537 
1538 static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port,
1539 					enum mlxsw_reg_spmlr_learn_mode mode)
1540 {
1541 	MLXSW_REG_ZERO(spmlr, payload);
1542 	mlxsw_reg_spmlr_local_port_set(payload, local_port);
1543 	mlxsw_reg_spmlr_sub_port_set(payload, 0);
1544 	mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1545 }
1546 
1547 /* SVFA - Switch VID to FID Allocation Register
1548  * --------------------------------------------
1549  * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1550  * virtualized ports.
1551  */
1552 #define MLXSW_REG_SVFA_ID 0x201C
1553 #define MLXSW_REG_SVFA_LEN 0x18
1554 
1555 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1556 
1557 /* reg_svfa_swid
1558  * Switch partition ID.
1559  * Access: Index
1560  */
1561 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1562 
1563 /* reg_svfa_local_port
1564  * Local port number.
1565  * Access: Index
1566  *
1567  * Note: Reserved for 802.1Q FIDs.
1568  */
1569 MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12);
1570 
1571 enum mlxsw_reg_svfa_mt {
1572 	MLXSW_REG_SVFA_MT_VID_TO_FID,
1573 	MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1574 	MLXSW_REG_SVFA_MT_VNI_TO_FID,
1575 };
1576 
1577 /* reg_svfa_mapping_table
1578  * Mapping table:
1579  * 0 - VID to FID
1580  * 1 - {Port, VID} to FID
1581  * Access: Index
1582  *
1583  * Note: Reserved for SwitchX-2.
1584  */
1585 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1586 
1587 /* reg_svfa_v
1588  * Valid.
1589  * Valid if set.
1590  * Access: RW
1591  *
1592  * Note: Reserved for SwitchX-2.
1593  */
1594 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1595 
1596 /* reg_svfa_fid
1597  * Filtering ID.
1598  * Access: RW
1599  */
1600 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1601 
1602 /* reg_svfa_vid
1603  * VLAN ID.
1604  * Access: Index
1605  */
1606 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1607 
1608 /* reg_svfa_counter_set_type
1609  * Counter set type for flow counters.
1610  * Access: RW
1611  *
1612  * Note: Reserved for SwitchX-2.
1613  */
1614 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1615 
1616 /* reg_svfa_counter_index
1617  * Counter index for flow counters.
1618  * Access: RW
1619  *
1620  * Note: Reserved for SwitchX-2.
1621  */
1622 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1623 
1624 /* reg_svfa_vni
1625  * Virtual Network Identifier.
1626  * Access: Index
1627  *
1628  * Note: Reserved when mapping_table is not 2 (VNI mapping table).
1629  */
1630 MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24);
1631 
1632 /* reg_svfa_irif_v
1633  * Ingress RIF valid.
1634  * 0 - Ingress RIF is not valid, no ingress RIF assigned.
1635  * 1 - Ingress RIF valid.
1636  * Must not be set for a non enabled RIF.
1637  * Access: RW
1638  *
1639  * Note: Reserved when legacy bridge model is used.
1640  */
1641 MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1);
1642 
1643 /* reg_svfa_irif
1644  * Ingress RIF (Router Interface).
1645  * Range is 0..cap_max_router_interfaces-1.
1646  * Access: RW
1647  *
1648  * Note: Reserved when legacy bridge model is used and when irif_v=0.
1649  */
1650 MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16);
1651 
1652 static inline void __mlxsw_reg_svfa_pack(char *payload,
1653 					 enum mlxsw_reg_svfa_mt mt, bool valid,
1654 					 u16 fid, bool irif_v, u16 irif)
1655 {
1656 	MLXSW_REG_ZERO(svfa, payload);
1657 	mlxsw_reg_svfa_swid_set(payload, 0);
1658 	mlxsw_reg_svfa_mapping_table_set(payload, mt);
1659 	mlxsw_reg_svfa_v_set(payload, valid);
1660 	mlxsw_reg_svfa_fid_set(payload, fid);
1661 	mlxsw_reg_svfa_irif_v_set(payload, irif_v);
1662 	mlxsw_reg_svfa_irif_set(payload, irif_v ? irif : 0);
1663 }
1664 
1665 static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port,
1666 						bool valid, u16 fid, u16 vid,
1667 						bool irif_v, u16 irif)
1668 {
1669 	enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1670 
1671 	__mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif);
1672 	mlxsw_reg_svfa_local_port_set(payload, local_port);
1673 	mlxsw_reg_svfa_vid_set(payload, vid);
1674 }
1675 
1676 static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid,
1677 					   u16 vid, bool irif_v, u16 irif)
1678 {
1679 	enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID;
1680 
1681 	__mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif);
1682 	mlxsw_reg_svfa_vid_set(payload, vid);
1683 }
1684 
1685 static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid,
1686 					   u32 vni, bool irif_v, u16 irif)
1687 {
1688 	enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID;
1689 
1690 	__mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif);
1691 	mlxsw_reg_svfa_vni_set(payload, vni);
1692 }
1693 
1694 /*  SPVTR - Switch Port VLAN Stacking Register
1695  *  ------------------------------------------
1696  *  The Switch Port VLAN Stacking register configures the VLAN mode of the port
1697  *  to enable VLAN stacking.
1698  */
1699 #define MLXSW_REG_SPVTR_ID 0x201D
1700 #define MLXSW_REG_SPVTR_LEN 0x10
1701 
1702 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN);
1703 
1704 /* reg_spvtr_tport
1705  * Port is tunnel port.
1706  * Access: Index
1707  *
1708  * Note: Reserved when SwitchX/-2 or Spectrum-1.
1709  */
1710 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1);
1711 
1712 /* reg_spvtr_local_port
1713  * When tport = 0: local port number (Not supported from/to CPU).
1714  * When tport = 1: tunnel port.
1715  * Access: Index
1716  */
1717 MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12);
1718 
1719 /* reg_spvtr_ippe
1720  * Ingress Port Prio Mode Update Enable.
1721  * When set, the Port Prio Mode is updated with the provided ipprio_mode field.
1722  * Reserved on Get operations.
1723  * Access: OP
1724  */
1725 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1);
1726 
1727 /* reg_spvtr_ipve
1728  * Ingress Port VID Mode Update Enable.
1729  * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode
1730  * field.
1731  * Reserved on Get operations.
1732  * Access: OP
1733  */
1734 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1);
1735 
1736 /* reg_spvtr_epve
1737  * Egress Port VID Mode Update Enable.
1738  * When set, the Egress Port VID Mode is updated with the provided epvid_mode
1739  * field.
1740  * Access: OP
1741  */
1742 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1);
1743 
1744 /* reg_spvtr_ipprio_mode
1745  * Ingress Port Priority Mode.
1746  * This controls the PCP and DEI of the new outer VLAN
1747  * Note: for SwitchX/-2 the DEI is not affected.
1748  * 0: use port default PCP and DEI (configured by QPDPC).
1749  * 1: use C-VLAN PCP and DEI.
1750  * Has no effect when ipvid_mode = 0.
1751  * Reserved when tport = 1.
1752  * Access: RW
1753  */
1754 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4);
1755 
1756 enum mlxsw_reg_spvtr_ipvid_mode {
1757 	/* IEEE Compliant PVID (default) */
1758 	MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID,
1759 	/* Push VLAN (for VLAN stacking, except prio tagged packets) */
1760 	MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET,
1761 	/* Always push VLAN (also for prio tagged packets) */
1762 	MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN,
1763 };
1764 
1765 /* reg_spvtr_ipvid_mode
1766  * Ingress Port VLAN-ID Mode.
1767  * For Spectrum family, this affects the values of SPVM.i
1768  * Access: RW
1769  */
1770 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4);
1771 
1772 enum mlxsw_reg_spvtr_epvid_mode {
1773 	/* IEEE Compliant VLAN membership */
1774 	MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP,
1775 	/* Pop VLAN (for VLAN stacking) */
1776 	MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN,
1777 };
1778 
1779 /* reg_spvtr_epvid_mode
1780  * Egress Port VLAN-ID Mode.
1781  * For Spectrum family, this affects the values of SPVM.e,u,pt.
1782  * Access: WO
1783  */
1784 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4);
1785 
1786 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport,
1787 					u16 local_port,
1788 					enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode)
1789 {
1790 	MLXSW_REG_ZERO(spvtr, payload);
1791 	mlxsw_reg_spvtr_tport_set(payload, tport);
1792 	mlxsw_reg_spvtr_local_port_set(payload, local_port);
1793 	mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode);
1794 	mlxsw_reg_spvtr_ipve_set(payload, true);
1795 }
1796 
1797 /* SVPE - Switch Virtual-Port Enabling Register
1798  * --------------------------------------------
1799  * Enables port virtualization.
1800  */
1801 #define MLXSW_REG_SVPE_ID 0x201E
1802 #define MLXSW_REG_SVPE_LEN 0x4
1803 
1804 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1805 
1806 /* reg_svpe_local_port
1807  * Local port number
1808  * Access: Index
1809  *
1810  * Note: CPU port is not supported (uses VLAN mode only).
1811  */
1812 MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12);
1813 
1814 /* reg_svpe_vp_en
1815  * Virtual port enable.
1816  * 0 - Disable, VLAN mode (VID to FID).
1817  * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1818  * Access: RW
1819  */
1820 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1821 
1822 static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port,
1823 				       bool enable)
1824 {
1825 	MLXSW_REG_ZERO(svpe, payload);
1826 	mlxsw_reg_svpe_local_port_set(payload, local_port);
1827 	mlxsw_reg_svpe_vp_en_set(payload, enable);
1828 }
1829 
1830 /* SFMR - Switch FID Management Register
1831  * -------------------------------------
1832  * Creates and configures FIDs.
1833  */
1834 #define MLXSW_REG_SFMR_ID 0x201F
1835 #define MLXSW_REG_SFMR_LEN 0x30
1836 
1837 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1838 
1839 enum mlxsw_reg_sfmr_op {
1840 	MLXSW_REG_SFMR_OP_CREATE_FID,
1841 	MLXSW_REG_SFMR_OP_DESTROY_FID,
1842 };
1843 
1844 /* reg_sfmr_op
1845  * Operation.
1846  * 0 - Create or edit FID.
1847  * 1 - Destroy FID.
1848  * Access: WO
1849  */
1850 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1851 
1852 /* reg_sfmr_fid
1853  * Filtering ID.
1854  * Access: Index
1855  */
1856 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1857 
1858 /* reg_sfmr_flood_rsp
1859  * Router sub-port flooding table.
1860  * 0 - Regular flooding table.
1861  * 1 - Router sub-port flooding table. For this FID the flooding is per
1862  * router-sub-port local_port. Must not be set for a FID which is not a
1863  * router-sub-port and must be set prior to enabling the relevant RIF.
1864  * Access: RW
1865  *
1866  * Note: Reserved when legacy bridge model is used.
1867  * Reserved when CONFIG_PROFILE.flood_mode = CFF.
1868  */
1869 MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1);
1870 
1871 /* reg_sfmr_flood_bridge_type
1872  * Flood bridge type (see SFGC.bridge_type).
1873  * 0 - type_0.
1874  * 1 - type_1.
1875  * Access: RW
1876  *
1877  * Note: Reserved when legacy bridge model is used and when flood_rsp=1.
1878  * Reserved when CONFIG_PROFILE.flood_mode = CFF
1879  */
1880 MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1);
1881 
1882 /* reg_sfmr_fid_offset
1883  * FID offset.
1884  * Used to point into the flooding table selected by SFGC register if
1885  * the table is of type FID-Offset. Otherwise, this field is reserved.
1886  * Access: RW
1887  *
1888  * Note: Reserved when CONFIG_PROFILE.flood_mode = CFF
1889  */
1890 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1891 
1892 /* reg_sfmr_vtfp
1893  * Valid Tunnel Flood Pointer.
1894  * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1895  * Access: RW
1896  *
1897  * Note: Reserved for 802.1Q FIDs.
1898  */
1899 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1900 
1901 /* reg_sfmr_nve_tunnel_flood_ptr
1902  * Underlay Flooding and BC Pointer.
1903  * Used as a pointer to the first entry of the group based link lists of
1904  * flooding or BC entries (for NVE tunnels).
1905  * Access: RW
1906  */
1907 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1908 
1909 /* reg_sfmr_vv
1910  * VNI Valid.
1911  * If not set, then vni is reserved.
1912  * Access: RW
1913  *
1914  * Note: Reserved for 802.1Q FIDs.
1915  */
1916 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1917 
1918 /* reg_sfmr_vni
1919  * Virtual Network Identifier.
1920  * When legacy bridge model is used, a given VNI can only be assigned to one
1921  * FID. When unified bridge model is used, it configures only the FID->VNI,
1922  * the VNI->FID is done by SVFA.
1923  * Access: RW
1924  */
1925 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1926 
1927 /* reg_sfmr_irif_v
1928  * Ingress RIF valid.
1929  * 0 - Ingress RIF is not valid, no ingress RIF assigned.
1930  * 1 - Ingress RIF valid.
1931  * Must not be set for a non valid RIF.
1932  * Access: RW
1933  *
1934  * Note: Reserved when legacy bridge model is used.
1935  */
1936 MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1);
1937 
1938 /* reg_sfmr_irif
1939  * Ingress RIF (Router Interface).
1940  * Range is 0..cap_max_router_interfaces-1.
1941  * Access: RW
1942  *
1943  * Note: Reserved when legacy bridge model is used and when irif_v=0.
1944  */
1945 MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16);
1946 
1947 /* reg_sfmr_cff_mid_base
1948  * Pointer to PGT table.
1949  * Range: 0..(cap_max_pgt-1)
1950  * Access: RW
1951  *
1952  * Note: Reserved when SwitchX/-2 and Spectrum-1.
1953  * Supported when CONFIG_PROFILE.flood_mode = CFF.
1954  */
1955 MLXSW_ITEM32(reg, sfmr, cff_mid_base, 0x20, 0, 16);
1956 
1957 /* reg_sfmr_nve_flood_prf_id
1958  * FID flooding profile_id for NVE Encap
1959  * Range 0..(max_cap_nve_flood_prf-1)
1960  * Access: RW
1961  *
1962  * Note: Reserved when SwitchX/-2 and Spectrum-1
1963  */
1964 MLXSW_ITEM32(reg, sfmr, nve_flood_prf_id, 0x24, 8, 2);
1965 
1966 /* reg_sfmr_cff_prf_id
1967  * Compressed Fid Flooding profile_id
1968  * Range 0..(max_cap_nve_flood_prf-1)
1969  * Access: RW
1970  *
1971  * Note: Reserved when SwitchX/-2 and Spectrum-1
1972  * Supported only when CONFIG_PROFLE.flood_mode = CFF.
1973  */
1974 MLXSW_ITEM32(reg, sfmr, cff_prf_id, 0x24, 0, 2);
1975 
1976 /* reg_sfmr_smpe_valid
1977  * SMPE is valid.
1978  * Access: RW
1979  *
1980  * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on
1981  * Spectrum-1.
1982  */
1983 MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1);
1984 
1985 /* reg_sfmr_smpe
1986  * Switch multicast port to egress VID.
1987  * Range is 0..cap_max_rmpe-1
1988  * Access: RW
1989  *
1990  * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on
1991  * Spectrum-1.
1992  */
1993 MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16);
1994 
1995 static inline void mlxsw_reg_sfmr_pack(char *payload,
1996 				       enum mlxsw_reg_sfmr_op op, u16 fid,
1997 				       bool smpe_valid, u16 smpe)
1998 {
1999 	MLXSW_REG_ZERO(sfmr, payload);
2000 	mlxsw_reg_sfmr_op_set(payload, op);
2001 	mlxsw_reg_sfmr_fid_set(payload, fid);
2002 	mlxsw_reg_sfmr_smpe_valid_set(payload, smpe_valid);
2003 	mlxsw_reg_sfmr_smpe_set(payload, smpe);
2004 }
2005 
2006 /* SPVMLR - Switch Port VLAN MAC Learning Register
2007  * -----------------------------------------------
2008  * Controls the switch MAC learning policy per {Port, VID}.
2009  */
2010 #define MLXSW_REG_SPVMLR_ID 0x2020
2011 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
2012 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
2013 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
2014 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
2015 			      MLXSW_REG_SPVMLR_REC_LEN * \
2016 			      MLXSW_REG_SPVMLR_REC_MAX_COUNT)
2017 
2018 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
2019 
2020 /* reg_spvmlr_local_port
2021  * Local ingress port.
2022  * Access: Index
2023  *
2024  * Note: CPU port is not supported.
2025  */
2026 MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12);
2027 
2028 /* reg_spvmlr_num_rec
2029  * Number of records to update.
2030  * Access: OP
2031  */
2032 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
2033 
2034 /* reg_spvmlr_rec_learn_enable
2035  * 0 - Disable learning for {Port, VID}.
2036  * 1 - Enable learning for {Port, VID}.
2037  * Access: RW
2038  */
2039 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
2040 		     31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
2041 
2042 /* reg_spvmlr_rec_vid
2043  * VLAN ID to be added/removed from port or for querying.
2044  * Access: Index
2045  */
2046 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
2047 		     MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
2048 
2049 static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port,
2050 					 u16 vid_begin, u16 vid_end,
2051 					 bool learn_enable)
2052 {
2053 	int num_rec = vid_end - vid_begin + 1;
2054 	int i;
2055 
2056 	WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
2057 
2058 	MLXSW_REG_ZERO(spvmlr, payload);
2059 	mlxsw_reg_spvmlr_local_port_set(payload, local_port);
2060 	mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
2061 
2062 	for (i = 0; i < num_rec; i++) {
2063 		mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
2064 		mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
2065 	}
2066 }
2067 
2068 /* SPFSR - Switch Port FDB Security Register
2069  * -----------------------------------------
2070  * Configures the security mode per port.
2071  */
2072 #define MLXSW_REG_SPFSR_ID 0x2023
2073 #define MLXSW_REG_SPFSR_LEN 0x08
2074 
2075 MLXSW_REG_DEFINE(spfsr, MLXSW_REG_SPFSR_ID, MLXSW_REG_SPFSR_LEN);
2076 
2077 /* reg_spfsr_local_port
2078  * Local port.
2079  * Access: Index
2080  *
2081  * Note: not supported for CPU port.
2082  */
2083 MLXSW_ITEM32_LP(reg, spfsr, 0x00, 16, 0x00, 12);
2084 
2085 /* reg_spfsr_security
2086  * Security checks.
2087  * 0: disabled (default)
2088  * 1: enabled
2089  * Access: RW
2090  */
2091 MLXSW_ITEM32(reg, spfsr, security, 0x04, 31, 1);
2092 
2093 static inline void mlxsw_reg_spfsr_pack(char *payload, u16 local_port,
2094 					bool security)
2095 {
2096 	MLXSW_REG_ZERO(spfsr, payload);
2097 	mlxsw_reg_spfsr_local_port_set(payload, local_port);
2098 	mlxsw_reg_spfsr_security_set(payload, security);
2099 }
2100 
2101 /* SPVC - Switch Port VLAN Classification Register
2102  * -----------------------------------------------
2103  * Configures the port to identify packets as untagged / single tagged /
2104  * double packets based on the packet EtherTypes.
2105  * Ethertype IDs are configured by SVER.
2106  */
2107 #define MLXSW_REG_SPVC_ID 0x2026
2108 #define MLXSW_REG_SPVC_LEN 0x0C
2109 
2110 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN);
2111 
2112 /* reg_spvc_local_port
2113  * Local port.
2114  * Access: Index
2115  *
2116  * Note: applies both to Rx port and Tx port, so if a packet traverses
2117  * through Rx port i and a Tx port j then port i and port j must have the
2118  * same configuration.
2119  */
2120 MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12);
2121 
2122 /* reg_spvc_inner_et2
2123  * Vlan Tag1 EtherType2 enable.
2124  * Packet is initially classified as double VLAN Tag if in addition to
2125  * being classified with a tag0 VLAN Tag its tag1 EtherType value is
2126  * equal to ether_type2.
2127  * 0: disable (default)
2128  * 1: enable
2129  * Access: RW
2130  */
2131 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1);
2132 
2133 /* reg_spvc_et2
2134  * Vlan Tag0 EtherType2 enable.
2135  * Packet is initially classified as VLAN Tag if its tag0 EtherType is
2136  * equal to ether_type2.
2137  * 0: disable (default)
2138  * 1: enable
2139  * Access: RW
2140  */
2141 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1);
2142 
2143 /* reg_spvc_inner_et1
2144  * Vlan Tag1 EtherType1 enable.
2145  * Packet is initially classified as double VLAN Tag if in addition to
2146  * being classified with a tag0 VLAN Tag its tag1 EtherType value is
2147  * equal to ether_type1.
2148  * 0: disable
2149  * 1: enable (default)
2150  * Access: RW
2151  */
2152 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1);
2153 
2154 /* reg_spvc_et1
2155  * Vlan Tag0 EtherType1 enable.
2156  * Packet is initially classified as VLAN Tag if its tag0 EtherType is
2157  * equal to ether_type1.
2158  * 0: disable
2159  * 1: enable (default)
2160  * Access: RW
2161  */
2162 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1);
2163 
2164 /* reg_inner_et0
2165  * Vlan Tag1 EtherType0 enable.
2166  * Packet is initially classified as double VLAN Tag if in addition to
2167  * being classified with a tag0 VLAN Tag its tag1 EtherType value is
2168  * equal to ether_type0.
2169  * 0: disable
2170  * 1: enable (default)
2171  * Access: RW
2172  */
2173 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1);
2174 
2175 /* reg_et0
2176  * Vlan Tag0 EtherType0 enable.
2177  * Packet is initially classified as VLAN Tag if its tag0 EtherType is
2178  * equal to ether_type0.
2179  * 0: disable
2180  * 1: enable (default)
2181  * Access: RW
2182  */
2183 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1);
2184 
2185 static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1,
2186 				       bool et0)
2187 {
2188 	MLXSW_REG_ZERO(spvc, payload);
2189 	mlxsw_reg_spvc_local_port_set(payload, local_port);
2190 	/* Enable inner_et1 and inner_et0 to enable identification of double
2191 	 * tagged packets.
2192 	 */
2193 	mlxsw_reg_spvc_inner_et1_set(payload, 1);
2194 	mlxsw_reg_spvc_inner_et0_set(payload, 1);
2195 	mlxsw_reg_spvc_et1_set(payload, et1);
2196 	mlxsw_reg_spvc_et0_set(payload, et0);
2197 }
2198 
2199 /* SFFP - Switch FID Flooding Profiles Register
2200  * --------------------------------------------
2201  * The SFFP register populates the fid flooding profile tables used for the NVE
2202  * flooding and Compressed-FID Flooding (CFF).
2203  *
2204  * Reserved on Spectrum-1.
2205  */
2206 #define MLXSW_REG_SFFP_ID 0x2029
2207 #define MLXSW_REG_SFFP_LEN 0x0C
2208 
2209 MLXSW_REG_DEFINE(sffp, MLXSW_REG_SFFP_ID, MLXSW_REG_SFFP_LEN);
2210 
2211 /* reg_sffp_profile_id
2212  * Profile ID a.k.a. SFMR.nve_flood_prf_id or SFMR.cff_prf_id
2213  * Range 0..max_cap_nve_flood_prf-1
2214  * Access: Index
2215  */
2216 MLXSW_ITEM32(reg, sffp, profile_id, 0x00, 16, 2);
2217 
2218 /* reg_sffp_type
2219  * The traffic type to reach the flooding table.
2220  * Same as SFGC.type
2221  * Access: Index
2222  */
2223 MLXSW_ITEM32(reg, sffp, type, 0x00, 0, 4);
2224 
2225 /* reg_sffp_flood_offset
2226  * Flood offset. Offset to add to SFMR.cff_mid_base to get the final PGT address
2227  * for FID flood; or offset to add to SFMR.nve_tunnel_flood_ptr to get KVD
2228  * pointer for NVE underlay.
2229  * Access: RW
2230  */
2231 MLXSW_ITEM32(reg, sffp, flood_offset, 0x04, 0, 3);
2232 
2233 static inline void mlxsw_reg_sffp_pack(char *payload, u8 profile_id,
2234 				       enum mlxsw_reg_sfgc_type type,
2235 				       u8 flood_offset)
2236 {
2237 	MLXSW_REG_ZERO(sffp, payload);
2238 	mlxsw_reg_sffp_profile_id_set(payload, profile_id);
2239 	mlxsw_reg_sffp_type_set(payload, type);
2240 	mlxsw_reg_sffp_flood_offset_set(payload, flood_offset);
2241 }
2242 
2243 /* SPEVET - Switch Port Egress VLAN EtherType
2244  * ------------------------------------------
2245  * The switch port egress VLAN EtherType configures which EtherType to push at
2246  * egress for packets incoming through a local port for which 'SPVID.egr_et_set'
2247  * is set.
2248  */
2249 #define MLXSW_REG_SPEVET_ID 0x202A
2250 #define MLXSW_REG_SPEVET_LEN 0x08
2251 
2252 MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN);
2253 
2254 /* reg_spevet_local_port
2255  * Egress Local port number.
2256  * Not supported to CPU port.
2257  * Access: Index
2258  */
2259 MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12);
2260 
2261 /* reg_spevet_et_vlan
2262  * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet:
2263  * 0: ether_type0 - (default)
2264  * 1: ether_type1
2265  * 2: ether_type2
2266  * Access: RW
2267  */
2268 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2);
2269 
2270 static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port,
2271 					 u8 et_vlan)
2272 {
2273 	MLXSW_REG_ZERO(spevet, payload);
2274 	mlxsw_reg_spevet_local_port_set(payload, local_port);
2275 	mlxsw_reg_spevet_et_vlan_set(payload, et_vlan);
2276 }
2277 
2278 /* SMPE - Switch Multicast Port to Egress VID
2279  * ------------------------------------------
2280  * The switch multicast port to egress VID maps
2281  * {egress_port, SMPE index} -> {VID}.
2282  */
2283 #define MLXSW_REG_SMPE_ID 0x202B
2284 #define MLXSW_REG_SMPE_LEN 0x0C
2285 
2286 MLXSW_REG_DEFINE(smpe, MLXSW_REG_SMPE_ID, MLXSW_REG_SMPE_LEN);
2287 
2288 /* reg_smpe_local_port
2289  * Local port number.
2290  * CPU port is not supported.
2291  * Access: Index
2292  */
2293 MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12);
2294 
2295 /* reg_smpe_smpe_index
2296  * Switch multicast port to egress VID.
2297  * Range is 0..cap_max_rmpe-1.
2298  * Access: Index
2299  */
2300 MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16);
2301 
2302 /* reg_smpe_evid
2303  * Egress VID.
2304  * Access: RW
2305  */
2306 MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12);
2307 
2308 static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port,
2309 				       u16 smpe_index, u16 evid)
2310 {
2311 	MLXSW_REG_ZERO(smpe, payload);
2312 	mlxsw_reg_smpe_local_port_set(payload, local_port);
2313 	mlxsw_reg_smpe_smpe_index_set(payload, smpe_index);
2314 	mlxsw_reg_smpe_evid_set(payload, evid);
2315 }
2316 
2317 /* SMID-V2 - Switch Multicast ID Version 2 Register
2318  * ------------------------------------------------
2319  * The MID record maps from a MID (Multicast ID), which is a unique identifier
2320  * of the multicast group within the stacking domain, into a list of local
2321  * ports into which the packet is replicated.
2322  */
2323 #define MLXSW_REG_SMID2_ID 0x2034
2324 #define MLXSW_REG_SMID2_LEN 0x120
2325 
2326 MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN);
2327 
2328 /* reg_smid2_swid
2329  * Switch partition ID.
2330  * Access: Index
2331  */
2332 MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8);
2333 
2334 /* reg_smid2_mid
2335  * Multicast identifier - global identifier that represents the multicast group
2336  * across all devices.
2337  * Access: Index
2338  */
2339 MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16);
2340 
2341 /* reg_smid2_smpe_valid
2342  * SMPE is valid.
2343  * When not valid, the egress VID will not be modified by the SMPE table.
2344  * Access: RW
2345  *
2346  * Note: Reserved when legacy bridge model is used and on Spectrum-2.
2347  */
2348 MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1);
2349 
2350 /* reg_smid2_smpe
2351  * Switch multicast port to egress VID.
2352  * Access: RW
2353  *
2354  * Note: Reserved when legacy bridge model is used and on Spectrum-2.
2355  */
2356 MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16);
2357 
2358 /* reg_smid2_port
2359  * Local port memebership (1 bit per port).
2360  * Access: RW
2361  */
2362 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1);
2363 
2364 /* reg_smid2_port_mask
2365  * Local port mask (1 bit per port).
2366  * Access: WO
2367  */
2368 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1);
2369 
2370 static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port,
2371 					bool set, bool smpe_valid, u16 smpe)
2372 {
2373 	MLXSW_REG_ZERO(smid2, payload);
2374 	mlxsw_reg_smid2_swid_set(payload, 0);
2375 	mlxsw_reg_smid2_mid_set(payload, mid);
2376 	mlxsw_reg_smid2_port_set(payload, port, set);
2377 	mlxsw_reg_smid2_port_mask_set(payload, port, 1);
2378 	mlxsw_reg_smid2_smpe_valid_set(payload, smpe_valid);
2379 	mlxsw_reg_smid2_smpe_set(payload, smpe_valid ? smpe : 0);
2380 }
2381 
2382 /* CWTP - Congetion WRED ECN TClass Profile
2383  * ----------------------------------------
2384  * Configures the profiles for queues of egress port and traffic class
2385  */
2386 #define MLXSW_REG_CWTP_ID 0x2802
2387 #define MLXSW_REG_CWTP_BASE_LEN 0x28
2388 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
2389 #define MLXSW_REG_CWTP_LEN 0x40
2390 
2391 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
2392 
2393 /* reg_cwtp_local_port
2394  * Local port number
2395  * Not supported for CPU port
2396  * Access: Index
2397  */
2398 MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12);
2399 
2400 /* reg_cwtp_traffic_class
2401  * Traffic Class to configure
2402  * Access: Index
2403  */
2404 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
2405 
2406 /* reg_cwtp_profile_min
2407  * Minimum Average Queue Size of the profile in cells.
2408  * Access: RW
2409  */
2410 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
2411 		     0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
2412 
2413 /* reg_cwtp_profile_percent
2414  * Percentage of WRED and ECN marking for maximum Average Queue size
2415  * Range is 0 to 100, units of integer percentage
2416  * Access: RW
2417  */
2418 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
2419 		     24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
2420 
2421 /* reg_cwtp_profile_max
2422  * Maximum Average Queue size of the profile in cells
2423  * Access: RW
2424  */
2425 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
2426 		     0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
2427 
2428 #define MLXSW_REG_CWTP_MIN_VALUE 64
2429 #define MLXSW_REG_CWTP_MAX_PROFILE 2
2430 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
2431 
2432 static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port,
2433 				       u8 traffic_class)
2434 {
2435 	int i;
2436 
2437 	MLXSW_REG_ZERO(cwtp, payload);
2438 	mlxsw_reg_cwtp_local_port_set(payload, local_port);
2439 	mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
2440 
2441 	for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
2442 		mlxsw_reg_cwtp_profile_min_set(payload, i,
2443 					       MLXSW_REG_CWTP_MIN_VALUE);
2444 		mlxsw_reg_cwtp_profile_max_set(payload, i,
2445 					       MLXSW_REG_CWTP_MIN_VALUE);
2446 	}
2447 }
2448 
2449 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
2450 
2451 static inline void
2452 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
2453 			    u32 probability)
2454 {
2455 	u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
2456 
2457 	mlxsw_reg_cwtp_profile_min_set(payload, index, min);
2458 	mlxsw_reg_cwtp_profile_max_set(payload, index, max);
2459 	mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
2460 }
2461 
2462 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping
2463  * ---------------------------------------------------
2464  * The CWTPM register maps each egress port and traffic class to profile num.
2465  */
2466 #define MLXSW_REG_CWTPM_ID 0x2803
2467 #define MLXSW_REG_CWTPM_LEN 0x44
2468 
2469 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
2470 
2471 /* reg_cwtpm_local_port
2472  * Local port number
2473  * Not supported for CPU port
2474  * Access: Index
2475  */
2476 MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12);
2477 
2478 /* reg_cwtpm_traffic_class
2479  * Traffic Class to configure
2480  * Access: Index
2481  */
2482 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
2483 
2484 /* reg_cwtpm_ew
2485  * Control enablement of WRED for traffic class:
2486  * 0 - Disable
2487  * 1 - Enable
2488  * Access: RW
2489  */
2490 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
2491 
2492 /* reg_cwtpm_ee
2493  * Control enablement of ECN for traffic class:
2494  * 0 - Disable
2495  * 1 - Enable
2496  * Access: RW
2497  */
2498 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
2499 
2500 /* reg_cwtpm_tcp_g
2501  * TCP Green Profile.
2502  * Index of the profile within {port, traffic class} to use.
2503  * 0 for disabling both WRED and ECN for this type of traffic.
2504  * Access: RW
2505  */
2506 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
2507 
2508 /* reg_cwtpm_tcp_y
2509  * TCP Yellow Profile.
2510  * Index of the profile within {port, traffic class} to use.
2511  * 0 for disabling both WRED and ECN for this type of traffic.
2512  * Access: RW
2513  */
2514 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
2515 
2516 /* reg_cwtpm_tcp_r
2517  * TCP Red Profile.
2518  * Index of the profile within {port, traffic class} to use.
2519  * 0 for disabling both WRED and ECN for this type of traffic.
2520  * Access: RW
2521  */
2522 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
2523 
2524 /* reg_cwtpm_ntcp_g
2525  * Non-TCP Green Profile.
2526  * Index of the profile within {port, traffic class} to use.
2527  * 0 for disabling both WRED and ECN for this type of traffic.
2528  * Access: RW
2529  */
2530 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
2531 
2532 /* reg_cwtpm_ntcp_y
2533  * Non-TCP Yellow Profile.
2534  * Index of the profile within {port, traffic class} to use.
2535  * 0 for disabling both WRED and ECN for this type of traffic.
2536  * Access: RW
2537  */
2538 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
2539 
2540 /* reg_cwtpm_ntcp_r
2541  * Non-TCP Red Profile.
2542  * Index of the profile within {port, traffic class} to use.
2543  * 0 for disabling both WRED and ECN for this type of traffic.
2544  * Access: RW
2545  */
2546 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2547 
2548 #define MLXSW_REG_CWTPM_RESET_PROFILE 0
2549 
2550 static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port,
2551 					u8 traffic_class, u8 profile,
2552 					bool wred, bool ecn)
2553 {
2554 	MLXSW_REG_ZERO(cwtpm, payload);
2555 	mlxsw_reg_cwtpm_local_port_set(payload, local_port);
2556 	mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
2557 	mlxsw_reg_cwtpm_ew_set(payload, wred);
2558 	mlxsw_reg_cwtpm_ee_set(payload, ecn);
2559 	mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
2560 	mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
2561 	mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
2562 	mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
2563 	mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
2564 	mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
2565 }
2566 
2567 /* PGCR - Policy-Engine General Configuration Register
2568  * ---------------------------------------------------
2569  * This register configures general Policy-Engine settings.
2570  */
2571 #define MLXSW_REG_PGCR_ID 0x3001
2572 #define MLXSW_REG_PGCR_LEN 0x20
2573 
2574 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
2575 
2576 /* reg_pgcr_default_action_pointer_base
2577  * Default action pointer base. Each region has a default action pointer
2578  * which is equal to default_action_pointer_base + region_id.
2579  * Access: RW
2580  */
2581 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
2582 
2583 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
2584 {
2585 	MLXSW_REG_ZERO(pgcr, payload);
2586 	mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
2587 }
2588 
2589 /* PPBT - Policy-Engine Port Binding Table
2590  * ---------------------------------------
2591  * This register is used for configuration of the Port Binding Table.
2592  */
2593 #define MLXSW_REG_PPBT_ID 0x3002
2594 #define MLXSW_REG_PPBT_LEN 0x14
2595 
2596 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2597 
2598 enum mlxsw_reg_pxbt_e {
2599 	MLXSW_REG_PXBT_E_IACL,
2600 	MLXSW_REG_PXBT_E_EACL,
2601 };
2602 
2603 /* reg_ppbt_e
2604  * Access: Index
2605  */
2606 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2607 
2608 enum mlxsw_reg_pxbt_op {
2609 	MLXSW_REG_PXBT_OP_BIND,
2610 	MLXSW_REG_PXBT_OP_UNBIND,
2611 };
2612 
2613 /* reg_ppbt_op
2614  * Access: RW
2615  */
2616 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2617 
2618 /* reg_ppbt_local_port
2619  * Local port. Not including CPU port.
2620  * Access: Index
2621  */
2622 MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12);
2623 
2624 /* reg_ppbt_g
2625  * group - When set, the binding is of an ACL group. When cleared,
2626  * the binding is of an ACL.
2627  * Must be set to 1 for Spectrum.
2628  * Access: RW
2629  */
2630 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2631 
2632 /* reg_ppbt_acl_info
2633  * ACL/ACL group identifier. If the g bit is set, this field should hold
2634  * the acl_group_id, else it should hold the acl_id.
2635  * Access: RW
2636  */
2637 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2638 
2639 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2640 				       enum mlxsw_reg_pxbt_op op,
2641 				       u16 local_port, u16 acl_info)
2642 {
2643 	MLXSW_REG_ZERO(ppbt, payload);
2644 	mlxsw_reg_ppbt_e_set(payload, e);
2645 	mlxsw_reg_ppbt_op_set(payload, op);
2646 	mlxsw_reg_ppbt_local_port_set(payload, local_port);
2647 	mlxsw_reg_ppbt_g_set(payload, true);
2648 	mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2649 }
2650 
2651 /* PACL - Policy-Engine ACL Register
2652  * ---------------------------------
2653  * This register is used for configuration of the ACL.
2654  */
2655 #define MLXSW_REG_PACL_ID 0x3004
2656 #define MLXSW_REG_PACL_LEN 0x70
2657 
2658 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2659 
2660 /* reg_pacl_v
2661  * Valid. Setting the v bit makes the ACL valid. It should not be cleared
2662  * while the ACL is bounded to either a port, VLAN or ACL rule.
2663  * Access: RW
2664  */
2665 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2666 
2667 /* reg_pacl_acl_id
2668  * An identifier representing the ACL (managed by software)
2669  * Range 0 .. cap_max_acl_regions - 1
2670  * Access: Index
2671  */
2672 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2673 
2674 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2675 
2676 /* reg_pacl_tcam_region_info
2677  * Opaque object that represents a TCAM region.
2678  * Obtained through PTAR register.
2679  * Access: RW
2680  */
2681 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2682 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2683 
2684 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2685 				       bool valid, const char *tcam_region_info)
2686 {
2687 	MLXSW_REG_ZERO(pacl, payload);
2688 	mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2689 	mlxsw_reg_pacl_v_set(payload, valid);
2690 	mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2691 }
2692 
2693 /* PAGT - Policy-Engine ACL Group Table
2694  * ------------------------------------
2695  * This register is used for configuration of the ACL Group Table.
2696  */
2697 #define MLXSW_REG_PAGT_ID 0x3005
2698 #define MLXSW_REG_PAGT_BASE_LEN 0x30
2699 #define MLXSW_REG_PAGT_ACL_LEN 4
2700 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2701 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2702 		MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2703 
2704 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2705 
2706 /* reg_pagt_size
2707  * Number of ACLs in the group.
2708  * Size 0 invalidates a group.
2709  * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now)
2710  * Total number of ACLs in all groups must be lower or equal
2711  * to cap_max_acl_tot_groups
2712  * Note: a group which is binded must not be invalidated
2713  * Access: Index
2714  */
2715 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2716 
2717 /* reg_pagt_acl_group_id
2718  * An identifier (numbered from 0..cap_max_acl_groups-1) representing
2719  * the ACL Group identifier (managed by software).
2720  * Access: Index
2721  */
2722 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2723 
2724 /* reg_pagt_multi
2725  * Multi-ACL
2726  * 0 - This ACL is the last ACL in the multi-ACL
2727  * 1 - This ACL is part of a multi-ACL
2728  * Access: RW
2729  */
2730 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
2731 
2732 /* reg_pagt_acl_id
2733  * ACL identifier
2734  * Access: RW
2735  */
2736 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2737 
2738 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2739 {
2740 	MLXSW_REG_ZERO(pagt, payload);
2741 	mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2742 }
2743 
2744 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2745 					      u16 acl_id, bool multi)
2746 {
2747 	u8 size = mlxsw_reg_pagt_size_get(payload);
2748 
2749 	if (index >= size)
2750 		mlxsw_reg_pagt_size_set(payload, index + 1);
2751 	mlxsw_reg_pagt_multi_set(payload, index, multi);
2752 	mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2753 }
2754 
2755 /* PTAR - Policy-Engine TCAM Allocation Register
2756  * ---------------------------------------------
2757  * This register is used for allocation of regions in the TCAM.
2758  * Note: Query method is not supported on this register.
2759  */
2760 #define MLXSW_REG_PTAR_ID 0x3006
2761 #define MLXSW_REG_PTAR_BASE_LEN 0x20
2762 #define MLXSW_REG_PTAR_KEY_ID_LEN 1
2763 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2764 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2765 		MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2766 
2767 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2768 
2769 enum mlxsw_reg_ptar_op {
2770 	/* allocate a TCAM region */
2771 	MLXSW_REG_PTAR_OP_ALLOC,
2772 	/* resize a TCAM region */
2773 	MLXSW_REG_PTAR_OP_RESIZE,
2774 	/* deallocate TCAM region */
2775 	MLXSW_REG_PTAR_OP_FREE,
2776 	/* test allocation */
2777 	MLXSW_REG_PTAR_OP_TEST,
2778 };
2779 
2780 /* reg_ptar_op
2781  * Access: OP
2782  */
2783 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2784 
2785 /* reg_ptar_action_set_type
2786  * Type of action set to be used on this region.
2787  * For Spectrum and Spectrum-2, this is always type 2 - "flexible"
2788  * Access: WO
2789  */
2790 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2791 
2792 enum mlxsw_reg_ptar_key_type {
2793 	MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */
2794 	MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */
2795 };
2796 
2797 /* reg_ptar_key_type
2798  * TCAM key type for the region.
2799  * Access: WO
2800  */
2801 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2802 
2803 /* reg_ptar_region_size
2804  * TCAM region size. When allocating/resizing this is the requested size,
2805  * the response is the actual size. Note that actual size may be
2806  * larger than requested.
2807  * Allowed range 1 .. cap_max_rules-1
2808  * Reserved during op deallocate.
2809  * Access: WO
2810  */
2811 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2812 
2813 /* reg_ptar_region_id
2814  * Region identifier
2815  * Range 0 .. cap_max_regions-1
2816  * Access: Index
2817  */
2818 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2819 
2820 /* reg_ptar_tcam_region_info
2821  * Opaque object that represents the TCAM region.
2822  * Returned when allocating a region.
2823  * Provided by software for ACL generation and region deallocation and resize.
2824  * Access: RW
2825  */
2826 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2827 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2828 
2829 /* reg_ptar_flexible_key_id
2830  * Identifier of the Flexible Key.
2831  * Only valid if key_type == "FLEX_KEY"
2832  * The key size will be rounded up to one of the following values:
2833  * 9B, 18B, 36B, 54B.
2834  * This field is reserved for in resize operation.
2835  * Access: WO
2836  */
2837 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2838 		    MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2839 
2840 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2841 				       enum mlxsw_reg_ptar_key_type key_type,
2842 				       u16 region_size, u16 region_id,
2843 				       const char *tcam_region_info)
2844 {
2845 	MLXSW_REG_ZERO(ptar, payload);
2846 	mlxsw_reg_ptar_op_set(payload, op);
2847 	mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */
2848 	mlxsw_reg_ptar_key_type_set(payload, key_type);
2849 	mlxsw_reg_ptar_region_size_set(payload, region_size);
2850 	mlxsw_reg_ptar_region_id_set(payload, region_id);
2851 	mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2852 }
2853 
2854 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2855 					      u16 key_id)
2856 {
2857 	mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2858 }
2859 
2860 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2861 {
2862 	mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2863 }
2864 
2865 /* PPRR - Policy-Engine Port Range Register
2866  * ----------------------------------------
2867  * This register is used for configuring port range identification.
2868  */
2869 #define MLXSW_REG_PPRR_ID 0x3008
2870 #define MLXSW_REG_PPRR_LEN 0x14
2871 
2872 MLXSW_REG_DEFINE(pprr, MLXSW_REG_PPRR_ID, MLXSW_REG_PPRR_LEN);
2873 
2874 /* reg_pprr_ipv4
2875  * Apply port range register to IPv4 packets.
2876  * Access: RW
2877  */
2878 MLXSW_ITEM32(reg, pprr, ipv4, 0x00, 31, 1);
2879 
2880 /* reg_pprr_ipv6
2881  * Apply port range register to IPv6 packets.
2882  * Access: RW
2883  */
2884 MLXSW_ITEM32(reg, pprr, ipv6, 0x00, 30, 1);
2885 
2886 /* reg_pprr_src
2887  * Apply port range register to source L4 ports.
2888  * Access: RW
2889  */
2890 MLXSW_ITEM32(reg, pprr, src, 0x00, 29, 1);
2891 
2892 /* reg_pprr_dst
2893  * Apply port range register to destination L4 ports.
2894  * Access: RW
2895  */
2896 MLXSW_ITEM32(reg, pprr, dst, 0x00, 28, 1);
2897 
2898 /* reg_pprr_tcp
2899  * Apply port range register to TCP packets.
2900  * Access: RW
2901  */
2902 MLXSW_ITEM32(reg, pprr, tcp, 0x00, 27, 1);
2903 
2904 /* reg_pprr_udp
2905  * Apply port range register to UDP packets.
2906  * Access: RW
2907  */
2908 MLXSW_ITEM32(reg, pprr, udp, 0x00, 26, 1);
2909 
2910 /* reg_pprr_register_index
2911  * Index of Port Range Register being accessed.
2912  * Range is 0..cap_max_acl_l4_port_range-1.
2913  * Access: Index
2914  */
2915 MLXSW_ITEM32(reg, pprr, register_index, 0x00, 0, 8);
2916 
2917 /* reg_prrr_port_range_min
2918  * Minimum port range for comparison.
2919  * Match is defined as:
2920  * port_range_min <= packet_port <= port_range_max.
2921  * Access: RW
2922  */
2923 MLXSW_ITEM32(reg, pprr, port_range_min, 0x04, 16, 16);
2924 
2925 /* reg_prrr_port_range_max
2926  * Maximum port range for comparison.
2927  * Access: RW
2928  */
2929 MLXSW_ITEM32(reg, pprr, port_range_max, 0x04, 0, 16);
2930 
2931 static inline void mlxsw_reg_pprr_pack(char *payload, u8 register_index)
2932 {
2933 	MLXSW_REG_ZERO(pprr, payload);
2934 	mlxsw_reg_pprr_register_index_set(payload, register_index);
2935 }
2936 
2937 /* PPBS - Policy-Engine Policy Based Switching Register
2938  * ----------------------------------------------------
2939  * This register retrieves and sets Policy Based Switching Table entries.
2940  */
2941 #define MLXSW_REG_PPBS_ID 0x300C
2942 #define MLXSW_REG_PPBS_LEN 0x14
2943 
2944 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2945 
2946 /* reg_ppbs_pbs_ptr
2947  * Index into the PBS table.
2948  * For Spectrum, the index points to the KVD Linear.
2949  * Access: Index
2950  */
2951 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2952 
2953 /* reg_ppbs_system_port
2954  * Unique port identifier for the final destination of the packet.
2955  * Access: RW
2956  */
2957 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2958 
2959 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2960 				       u16 system_port)
2961 {
2962 	MLXSW_REG_ZERO(ppbs, payload);
2963 	mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2964 	mlxsw_reg_ppbs_system_port_set(payload, system_port);
2965 }
2966 
2967 /* PRCR - Policy-Engine Rules Copy Register
2968  * ----------------------------------------
2969  * This register is used for accessing rules within a TCAM region.
2970  */
2971 #define MLXSW_REG_PRCR_ID 0x300D
2972 #define MLXSW_REG_PRCR_LEN 0x40
2973 
2974 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2975 
2976 enum mlxsw_reg_prcr_op {
2977 	/* Move rules. Moves the rules from "tcam_region_info" starting
2978 	 * at offset "offset" to "dest_tcam_region_info"
2979 	 * at offset "dest_offset."
2980 	 */
2981 	MLXSW_REG_PRCR_OP_MOVE,
2982 	/* Copy rules. Copies the rules from "tcam_region_info" starting
2983 	 * at offset "offset" to "dest_tcam_region_info"
2984 	 * at offset "dest_offset."
2985 	 */
2986 	MLXSW_REG_PRCR_OP_COPY,
2987 };
2988 
2989 /* reg_prcr_op
2990  * Access: OP
2991  */
2992 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2993 
2994 /* reg_prcr_offset
2995  * Offset within the source region to copy/move from.
2996  * Access: Index
2997  */
2998 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2999 
3000 /* reg_prcr_size
3001  * The number of rules to copy/move.
3002  * Access: WO
3003  */
3004 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
3005 
3006 /* reg_prcr_tcam_region_info
3007  * Opaque object that represents the source TCAM region.
3008  * Access: Index
3009  */
3010 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
3011 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
3012 
3013 /* reg_prcr_dest_offset
3014  * Offset within the source region to copy/move to.
3015  * Access: Index
3016  */
3017 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
3018 
3019 /* reg_prcr_dest_tcam_region_info
3020  * Opaque object that represents the destination TCAM region.
3021  * Access: Index
3022  */
3023 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
3024 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
3025 
3026 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
3027 				       const char *src_tcam_region_info,
3028 				       u16 src_offset,
3029 				       const char *dest_tcam_region_info,
3030 				       u16 dest_offset, u16 size)
3031 {
3032 	MLXSW_REG_ZERO(prcr, payload);
3033 	mlxsw_reg_prcr_op_set(payload, op);
3034 	mlxsw_reg_prcr_offset_set(payload, src_offset);
3035 	mlxsw_reg_prcr_size_set(payload, size);
3036 	mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
3037 						  src_tcam_region_info);
3038 	mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
3039 	mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
3040 						       dest_tcam_region_info);
3041 }
3042 
3043 /* PEFA - Policy-Engine Extended Flexible Action Register
3044  * ------------------------------------------------------
3045  * This register is used for accessing an extended flexible action entry
3046  * in the central KVD Linear Database.
3047  */
3048 #define MLXSW_REG_PEFA_ID 0x300F
3049 #define MLXSW_REG_PEFA_LEN 0xB0
3050 
3051 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
3052 
3053 /* reg_pefa_index
3054  * Index in the KVD Linear Centralized Database.
3055  * Access: Index
3056  */
3057 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
3058 
3059 /* reg_pefa_a
3060  * Index in the KVD Linear Centralized Database.
3061  * Activity
3062  * For a new entry: set if ca=0, clear if ca=1
3063  * Set if a packet lookup has hit on the specific entry
3064  * Access: RO
3065  */
3066 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
3067 
3068 /* reg_pefa_ca
3069  * Clear activity
3070  * When write: activity is according to this field
3071  * When read: after reading the activity is cleared according to ca
3072  * Access: OP
3073  */
3074 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
3075 
3076 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
3077 
3078 /* reg_pefa_flex_action_set
3079  * Action-set to perform when rule is matched.
3080  * Must be zero padded if action set is shorter.
3081  * Access: RW
3082  */
3083 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
3084 
3085 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
3086 				       const char *flex_action_set)
3087 {
3088 	MLXSW_REG_ZERO(pefa, payload);
3089 	mlxsw_reg_pefa_index_set(payload, index);
3090 	mlxsw_reg_pefa_ca_set(payload, ca);
3091 	if (flex_action_set)
3092 		mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
3093 							 flex_action_set);
3094 }
3095 
3096 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
3097 {
3098 	*p_a = mlxsw_reg_pefa_a_get(payload);
3099 }
3100 
3101 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register
3102  * --------------------------------------------------------------
3103  * This register is used for binding Multicast router to an ACL group
3104  * that serves the MC router.
3105  * This register is not supported by SwitchX/-2 and Spectrum.
3106  */
3107 #define MLXSW_REG_PEMRBT_ID 0x3014
3108 #define MLXSW_REG_PEMRBT_LEN 0x14
3109 
3110 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);
3111 
3112 enum mlxsw_reg_pemrbt_protocol {
3113 	MLXSW_REG_PEMRBT_PROTO_IPV4,
3114 	MLXSW_REG_PEMRBT_PROTO_IPV6,
3115 };
3116 
3117 /* reg_pemrbt_protocol
3118  * Access: Index
3119  */
3120 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
3121 
3122 /* reg_pemrbt_group_id
3123  * ACL group identifier.
3124  * Range 0..cap_max_acl_groups-1
3125  * Access: RW
3126  */
3127 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
3128 
3129 static inline void
3130 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,
3131 		      u16 group_id)
3132 {
3133 	MLXSW_REG_ZERO(pemrbt, payload);
3134 	mlxsw_reg_pemrbt_protocol_set(payload, protocol);
3135 	mlxsw_reg_pemrbt_group_id_set(payload, group_id);
3136 }
3137 
3138 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2
3139  * -----------------------------------------------------
3140  * This register is used for accessing rules within a TCAM region.
3141  * It is a new version of PTCE in order to support wider key,
3142  * mask and action within a TCAM region. This register is not supported
3143  * by SwitchX and SwitchX-2.
3144  */
3145 #define MLXSW_REG_PTCE2_ID 0x3017
3146 #define MLXSW_REG_PTCE2_LEN 0x1D8
3147 
3148 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
3149 
3150 /* reg_ptce2_v
3151  * Valid.
3152  * Access: RW
3153  */
3154 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
3155 
3156 /* reg_ptce2_a
3157  * Activity. Set if a packet lookup has hit on the specific entry.
3158  * To clear the "a" bit, use "clear activity" op or "clear on read" op.
3159  * Access: RO
3160  */
3161 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
3162 
3163 enum mlxsw_reg_ptce2_op {
3164 	/* Read operation. */
3165 	MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
3166 	/* clear on read operation. Used to read entry
3167 	 * and clear Activity bit.
3168 	 */
3169 	MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
3170 	/* Write operation. Used to write a new entry to the table.
3171 	 * All R/W fields are relevant for new entry. Activity bit is set
3172 	 * for new entries - Note write with v = 0 will delete the entry.
3173 	 */
3174 	MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
3175 	/* Update action. Only action set will be updated. */
3176 	MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
3177 	/* Clear activity. A bit is cleared for the entry. */
3178 	MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
3179 };
3180 
3181 /* reg_ptce2_op
3182  * Access: OP
3183  */
3184 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
3185 
3186 /* reg_ptce2_offset
3187  * Access: Index
3188  */
3189 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
3190 
3191 /* reg_ptce2_priority
3192  * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1.
3193  * Note: priority does not have to be unique per rule.
3194  * Within a region, higher priority should have lower offset (no limitation
3195  * between regions in a multi-region).
3196  * Access: RW
3197  */
3198 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
3199 
3200 /* reg_ptce2_tcam_region_info
3201  * Opaque object that represents the TCAM region.
3202  * Access: Index
3203  */
3204 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
3205 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
3206 
3207 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
3208 
3209 /* reg_ptce2_flex_key_blocks
3210  * ACL Key.
3211  * Access: RW
3212  */
3213 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
3214 	       MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3215 
3216 /* reg_ptce2_mask
3217  * mask- in the same size as key. A bit that is set directs the TCAM
3218  * to compare the corresponding bit in key. A bit that is clear directs
3219  * the TCAM to ignore the corresponding bit in key.
3220  * Access: RW
3221  */
3222 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
3223 	       MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3224 
3225 /* reg_ptce2_flex_action_set
3226  * ACL action set.
3227  * Access: RW
3228  */
3229 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
3230 	       MLXSW_REG_FLEX_ACTION_SET_LEN);
3231 
3232 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
3233 					enum mlxsw_reg_ptce2_op op,
3234 					const char *tcam_region_info,
3235 					u16 offset, u32 priority)
3236 {
3237 	MLXSW_REG_ZERO(ptce2, payload);
3238 	mlxsw_reg_ptce2_v_set(payload, valid);
3239 	mlxsw_reg_ptce2_op_set(payload, op);
3240 	mlxsw_reg_ptce2_offset_set(payload, offset);
3241 	mlxsw_reg_ptce2_priority_set(payload, priority);
3242 	mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
3243 }
3244 
3245 /* PERPT - Policy-Engine ERP Table Register
3246  * ----------------------------------------
3247  * This register adds and removes eRPs from the eRP table.
3248  */
3249 #define MLXSW_REG_PERPT_ID 0x3021
3250 #define MLXSW_REG_PERPT_LEN 0x80
3251 
3252 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
3253 
3254 /* reg_perpt_erpt_bank
3255  * eRP table bank.
3256  * Range 0 .. cap_max_erp_table_banks - 1
3257  * Access: Index
3258  */
3259 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
3260 
3261 /* reg_perpt_erpt_index
3262  * Index to eRP table within the eRP bank.
3263  * Range is 0 .. cap_max_erp_table_bank_size - 1
3264  * Access: Index
3265  */
3266 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
3267 
3268 enum mlxsw_reg_perpt_key_size {
3269 	MLXSW_REG_PERPT_KEY_SIZE_2KB,
3270 	MLXSW_REG_PERPT_KEY_SIZE_4KB,
3271 	MLXSW_REG_PERPT_KEY_SIZE_8KB,
3272 	MLXSW_REG_PERPT_KEY_SIZE_12KB,
3273 };
3274 
3275 /* reg_perpt_key_size
3276  * Access: OP
3277  */
3278 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
3279 
3280 /* reg_perpt_bf_bypass
3281  * 0 - The eRP is used only if bloom filter state is set for the given
3282  * rule.
3283  * 1 - The eRP is used regardless of bloom filter state.
3284  * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass
3285  * Access: RW
3286  */
3287 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
3288 
3289 /* reg_perpt_erp_id
3290  * eRP ID for use by the rules.
3291  * Access: RW
3292  */
3293 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
3294 
3295 /* reg_perpt_erpt_base_bank
3296  * Base eRP table bank, points to head of erp_vector
3297  * Range is 0 .. cap_max_erp_table_banks - 1
3298  * Access: OP
3299  */
3300 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
3301 
3302 /* reg_perpt_erpt_base_index
3303  * Base index to eRP table within the eRP bank
3304  * Range is 0 .. cap_max_erp_table_bank_size - 1
3305  * Access: OP
3306  */
3307 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
3308 
3309 /* reg_perpt_erp_index_in_vector
3310  * eRP index in the vector.
3311  * Access: OP
3312  */
3313 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
3314 
3315 /* reg_perpt_erp_vector
3316  * eRP vector.
3317  * Access: OP
3318  */
3319 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
3320 
3321 /* reg_perpt_mask
3322  * Mask
3323  * 0 - A-TCAM will ignore the bit in key
3324  * 1 - A-TCAM will compare the bit in key
3325  * Access: RW
3326  */
3327 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3328 
3329 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
3330 						   unsigned long *erp_vector,
3331 						   unsigned long size)
3332 {
3333 	unsigned long bit;
3334 
3335 	for_each_set_bit(bit, erp_vector, size)
3336 		mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
3337 }
3338 
3339 static inline void
3340 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
3341 		     enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
3342 		     u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
3343 		     char *mask)
3344 {
3345 	MLXSW_REG_ZERO(perpt, payload);
3346 	mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
3347 	mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
3348 	mlxsw_reg_perpt_key_size_set(payload, key_size);
3349 	mlxsw_reg_perpt_bf_bypass_set(payload, false);
3350 	mlxsw_reg_perpt_erp_id_set(payload, erp_id);
3351 	mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
3352 	mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
3353 	mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
3354 	mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
3355 }
3356 
3357 /* PERAR - Policy-Engine Region Association Register
3358  * -------------------------------------------------
3359  * This register associates a hw region for region_id's. Changing on the fly
3360  * is supported by the device.
3361  */
3362 #define MLXSW_REG_PERAR_ID 0x3026
3363 #define MLXSW_REG_PERAR_LEN 0x08
3364 
3365 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
3366 
3367 /* reg_perar_region_id
3368  * Region identifier
3369  * Range 0 .. cap_max_regions-1
3370  * Access: Index
3371  */
3372 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
3373 
3374 static inline unsigned int
3375 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
3376 {
3377 	return DIV_ROUND_UP(block_num, 4);
3378 }
3379 
3380 /* reg_perar_hw_region
3381  * HW Region
3382  * Range 0 .. cap_max_regions-1
3383  * Default: hw_region = region_id
3384  * For a 8 key block region, 2 consecutive regions are used
3385  * For a 12 key block region, 3 consecutive regions are used
3386  * Access: RW
3387  */
3388 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
3389 
3390 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
3391 					u16 hw_region)
3392 {
3393 	MLXSW_REG_ZERO(perar, payload);
3394 	mlxsw_reg_perar_region_id_set(payload, region_id);
3395 	mlxsw_reg_perar_hw_region_set(payload, hw_region);
3396 }
3397 
3398 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3
3399  * -----------------------------------------------------
3400  * This register is a new version of PTCE-V2 in order to support the
3401  * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum.
3402  */
3403 #define MLXSW_REG_PTCE3_ID 0x3027
3404 #define MLXSW_REG_PTCE3_LEN 0xF0
3405 
3406 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
3407 
3408 /* reg_ptce3_v
3409  * Valid.
3410  * Access: RW
3411  */
3412 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
3413 
3414 enum mlxsw_reg_ptce3_op {
3415 	/* Write operation. Used to write a new entry to the table.
3416 	 * All R/W fields are relevant for new entry. Activity bit is set
3417 	 * for new entries. Write with v = 0 will delete the entry. Must
3418 	 * not be used if an entry exists.
3419 	 */
3420 	 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
3421 	 /* Update operation */
3422 	 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
3423 	 /* Read operation */
3424 	 MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
3425 };
3426 
3427 /* reg_ptce3_op
3428  * Access: OP
3429  */
3430 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
3431 
3432 /* reg_ptce3_priority
3433  * Priority of the rule. Higher values win.
3434  * For Spectrum-2 range is 1..cap_kvd_size - 1
3435  * Note: Priority does not have to be unique per rule.
3436  * Access: RW
3437  */
3438 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
3439 
3440 /* reg_ptce3_tcam_region_info
3441  * Opaque object that represents the TCAM region.
3442  * Access: Index
3443  */
3444 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
3445 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
3446 
3447 /* reg_ptce3_flex2_key_blocks
3448  * ACL key. The key must be masked according to eRP (if exists) or
3449  * according to master mask.
3450  * Access: Index
3451  */
3452 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
3453 	       MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3454 
3455 /* reg_ptce3_erp_id
3456  * eRP ID.
3457  * Access: Index
3458  */
3459 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
3460 
3461 /* reg_ptce3_delta_start
3462  * Start point of delta_value and delta_mask, in bits. Must not exceed
3463  * num_key_blocks * 36 - 8. Reserved when delta_mask = 0.
3464  * Access: Index
3465  */
3466 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
3467 
3468 /* reg_ptce3_delta_mask
3469  * Delta mask.
3470  * 0 - Ignore relevant bit in delta_value
3471  * 1 - Compare relevant bit in delta_value
3472  * Delta mask must not be set for reserved fields in the key blocks.
3473  * Note: No delta when no eRPs. Thus, for regions with
3474  * PERERP.erpt_pointer_valid = 0 the delta mask must be 0.
3475  * Access: Index
3476  */
3477 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
3478 
3479 /* reg_ptce3_delta_value
3480  * Delta value.
3481  * Bits which are masked by delta_mask must be 0.
3482  * Access: Index
3483  */
3484 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
3485 
3486 /* reg_ptce3_prune_vector
3487  * Pruning vector relative to the PERPT.erp_id.
3488  * Used for reducing lookups.
3489  * 0 - NEED: Do a lookup using the eRP.
3490  * 1 - PRUNE: Do not perform a lookup using the eRP.
3491  * Maybe be modified by PEAPBL and PEAPBM.
3492  * Note: In Spectrum-2, a region of 8 key blocks must be set to either
3493  * all 1's or all 0's.
3494  * Access: RW
3495  */
3496 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
3497 
3498 /* reg_ptce3_prune_ctcam
3499  * Pruning on C-TCAM. Used for reducing lookups.
3500  * 0 - NEED: Do a lookup in the C-TCAM.
3501  * 1 - PRUNE: Do not perform a lookup in the C-TCAM.
3502  * Access: RW
3503  */
3504 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
3505 
3506 /* reg_ptce3_large_exists
3507  * Large entry key ID exists.
3508  * Within the region:
3509  * 0 - SINGLE: The large_entry_key_id is not currently in use.
3510  * For rule insert: The MSB of the key (blocks 6..11) will be added.
3511  * For rule delete: The MSB of the key will be removed.
3512  * 1 - NON_SINGLE: The large_entry_key_id is currently in use.
3513  * For rule insert: The MSB of the key (blocks 6..11) will not be added.
3514  * For rule delete: The MSB of the key will not be removed.
3515  * Access: WO
3516  */
3517 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
3518 
3519 /* reg_ptce3_large_entry_key_id
3520  * Large entry key ID.
3521  * A key for 12 key blocks rules. Reserved when region has less than 12 key
3522  * blocks. Must be different for different keys which have the same common
3523  * 6 key blocks (MSB, blocks 6..11) key within a region.
3524  * Range is 0..cap_max_pe_large_key_id - 1
3525  * Access: RW
3526  */
3527 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
3528 
3529 /* reg_ptce3_action_pointer
3530  * Pointer to action.
3531  * Range is 0..cap_max_kvd_action_sets - 1
3532  * Access: RW
3533  */
3534 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
3535 
3536 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
3537 					enum mlxsw_reg_ptce3_op op,
3538 					u32 priority,
3539 					const char *tcam_region_info,
3540 					const char *key, u8 erp_id,
3541 					u16 delta_start, u8 delta_mask,
3542 					u8 delta_value, bool large_exists,
3543 					u32 lkey_id, u32 action_pointer)
3544 {
3545 	MLXSW_REG_ZERO(ptce3, payload);
3546 	mlxsw_reg_ptce3_v_set(payload, valid);
3547 	mlxsw_reg_ptce3_op_set(payload, op);
3548 	mlxsw_reg_ptce3_priority_set(payload, priority);
3549 	mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
3550 	mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
3551 	mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
3552 	mlxsw_reg_ptce3_delta_start_set(payload, delta_start);
3553 	mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask);
3554 	mlxsw_reg_ptce3_delta_value_set(payload, delta_value);
3555 	mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
3556 	mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
3557 	mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
3558 }
3559 
3560 /* PERCR - Policy-Engine Region Configuration Register
3561  * ---------------------------------------------------
3562  * This register configures the region parameters. The region_id must be
3563  * allocated.
3564  */
3565 #define MLXSW_REG_PERCR_ID 0x302A
3566 #define MLXSW_REG_PERCR_LEN 0x80
3567 
3568 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
3569 
3570 /* reg_percr_region_id
3571  * Region identifier.
3572  * Range 0..cap_max_regions-1
3573  * Access: Index
3574  */
3575 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
3576 
3577 /* reg_percr_atcam_ignore_prune
3578  * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule.
3579  * Access: RW
3580  */
3581 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
3582 
3583 /* reg_percr_ctcam_ignore_prune
3584  * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule.
3585  * Access: RW
3586  */
3587 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
3588 
3589 /* reg_percr_bf_bypass
3590  * Bloom filter bypass.
3591  * 0 - Bloom filter is used (default)
3592  * 1 - Bloom filter is bypassed. The bypass is an OR condition of
3593  * region_id or eRP. See PERPT.bf_bypass
3594  * Access: RW
3595  */
3596 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
3597 
3598 /* reg_percr_master_mask
3599  * Master mask. Logical OR mask of all masks of all rules of a region
3600  * (both A-TCAM and C-TCAM). When there are no eRPs
3601  * (erpt_pointer_valid = 0), then this provides the mask.
3602  * Access: RW
3603  */
3604 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
3605 
3606 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
3607 {
3608 	MLXSW_REG_ZERO(percr, payload);
3609 	mlxsw_reg_percr_region_id_set(payload, region_id);
3610 	mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
3611 	mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
3612 	mlxsw_reg_percr_bf_bypass_set(payload, false);
3613 }
3614 
3615 /* PERERP - Policy-Engine Region eRP Register
3616  * ------------------------------------------
3617  * This register configures the region eRP. The region_id must be
3618  * allocated.
3619  */
3620 #define MLXSW_REG_PERERP_ID 0x302B
3621 #define MLXSW_REG_PERERP_LEN 0x1C
3622 
3623 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
3624 
3625 /* reg_pererp_region_id
3626  * Region identifier.
3627  * Range 0..cap_max_regions-1
3628  * Access: Index
3629  */
3630 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
3631 
3632 /* reg_pererp_ctcam_le
3633  * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0.
3634  * Access: RW
3635  */
3636 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
3637 
3638 /* reg_pererp_erpt_pointer_valid
3639  * erpt_pointer is valid.
3640  * Access: RW
3641  */
3642 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
3643 
3644 /* reg_pererp_erpt_bank_pointer
3645  * Pointer to eRP table bank. May be modified at any time.
3646  * Range 0..cap_max_erp_table_banks-1
3647  * Reserved when erpt_pointer_valid = 0
3648  */
3649 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
3650 
3651 /* reg_pererp_erpt_pointer
3652  * Pointer to eRP table within the eRP bank. Can be changed for an
3653  * existing region.
3654  * Range 0..cap_max_erp_table_size-1
3655  * Reserved when erpt_pointer_valid = 0
3656  * Access: RW
3657  */
3658 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
3659 
3660 /* reg_pererp_erpt_vector
3661  * Vector of allowed eRP indexes starting from erpt_pointer within the
3662  * erpt_bank_pointer. Next entries will be in next bank.
3663  * Note that eRP index is used and not eRP ID.
3664  * Reserved when erpt_pointer_valid = 0
3665  * Access: RW
3666  */
3667 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
3668 
3669 /* reg_pererp_master_rp_id
3670  * Master RP ID. When there are no eRPs, then this provides the eRP ID
3671  * for the lookup. Can be changed for an existing region.
3672  * Reserved when erpt_pointer_valid = 1
3673  * Access: RW
3674  */
3675 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
3676 
3677 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
3678 						    unsigned long *erp_vector,
3679 						    unsigned long size)
3680 {
3681 	unsigned long bit;
3682 
3683 	for_each_set_bit(bit, erp_vector, size)
3684 		mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
3685 }
3686 
3687 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
3688 					 bool ctcam_le, bool erpt_pointer_valid,
3689 					 u8 erpt_bank_pointer, u8 erpt_pointer,
3690 					 u8 master_rp_id)
3691 {
3692 	MLXSW_REG_ZERO(pererp, payload);
3693 	mlxsw_reg_pererp_region_id_set(payload, region_id);
3694 	mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
3695 	mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
3696 	mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
3697 	mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
3698 	mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
3699 }
3700 
3701 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register
3702  * ----------------------------------------------------------------
3703  * This register configures the Bloom filter entries.
3704  */
3705 #define MLXSW_REG_PEABFE_ID 0x3022
3706 #define MLXSW_REG_PEABFE_BASE_LEN 0x10
3707 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4
3708 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256
3709 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \
3710 			      MLXSW_REG_PEABFE_BF_REC_LEN * \
3711 			      MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)
3712 
3713 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);
3714 
3715 /* reg_peabfe_size
3716  * Number of BF entries to be updated.
3717  * Range 1..256
3718  * Access: Op
3719  */
3720 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
3721 
3722 /* reg_peabfe_bf_entry_state
3723  * Bloom filter state
3724  * 0 - Clear
3725  * 1 - Set
3726  * Access: RW
3727  */
3728 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
3729 		     MLXSW_REG_PEABFE_BASE_LEN,	31, 1,
3730 		     MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3731 
3732 /* reg_peabfe_bf_entry_bank
3733  * Bloom filter bank ID
3734  * Range 0..cap_max_erp_table_banks-1
3735  * Access: Index
3736  */
3737 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
3738 		     MLXSW_REG_PEABFE_BASE_LEN,	24, 4,
3739 		     MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3740 
3741 /* reg_peabfe_bf_entry_index
3742  * Bloom filter entry index
3743  * Range 0..2^cap_max_bf_log-1
3744  * Access: Index
3745  */
3746 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
3747 		     MLXSW_REG_PEABFE_BASE_LEN,	0, 24,
3748 		     MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3749 
3750 static inline void mlxsw_reg_peabfe_pack(char *payload)
3751 {
3752 	MLXSW_REG_ZERO(peabfe, payload);
3753 }
3754 
3755 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,
3756 					     u8 state, u8 bank, u32 bf_index)
3757 {
3758 	u8 num_rec = mlxsw_reg_peabfe_size_get(payload);
3759 
3760 	if (rec_index >= num_rec)
3761 		mlxsw_reg_peabfe_size_set(payload, rec_index + 1);
3762 	mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state);
3763 	mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);
3764 	mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index);
3765 }
3766 
3767 /* IEDR - Infrastructure Entry Delete Register
3768  * ----------------------------------------------------
3769  * This register is used for deleting entries from the entry tables.
3770  * It is legitimate to attempt to delete a nonexisting entry (the device will
3771  * respond as a good flow).
3772  */
3773 #define MLXSW_REG_IEDR_ID 0x3804
3774 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */
3775 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */
3776 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3777 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN +	\
3778 			    MLXSW_REG_IEDR_REC_LEN *	\
3779 			    MLXSW_REG_IEDR_REC_MAX_COUNT)
3780 
3781 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3782 
3783 /* reg_iedr_num_rec
3784  * Number of records.
3785  * Access: OP
3786  */
3787 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3788 
3789 /* reg_iedr_rec_type
3790  * Resource type.
3791  * Access: OP
3792  */
3793 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3794 		     MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3795 
3796 /* reg_iedr_rec_size
3797  * Size of entries do be deleted. The unit is 1 entry, regardless of entry type.
3798  * Access: OP
3799  */
3800 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13,
3801 		     MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3802 
3803 /* reg_iedr_rec_index_start
3804  * Resource index start.
3805  * Access: OP
3806  */
3807 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3808 		     MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3809 
3810 static inline void mlxsw_reg_iedr_pack(char *payload)
3811 {
3812 	MLXSW_REG_ZERO(iedr, payload);
3813 }
3814 
3815 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3816 					   u8 rec_type, u16 rec_size,
3817 					   u32 rec_index_start)
3818 {
3819 	u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
3820 
3821 	if (rec_index >= num_rec)
3822 		mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
3823 	mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
3824 	mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
3825 	mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
3826 }
3827 
3828 /* QPTS - QoS Priority Trust State Register
3829  * ----------------------------------------
3830  * This register controls the port policy to calculate the switch priority and
3831  * packet color based on incoming packet fields.
3832  */
3833 #define MLXSW_REG_QPTS_ID 0x4002
3834 #define MLXSW_REG_QPTS_LEN 0x8
3835 
3836 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3837 
3838 /* reg_qpts_local_port
3839  * Local port number.
3840  * Access: Index
3841  *
3842  * Note: CPU port is supported.
3843  */
3844 MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12);
3845 
3846 enum mlxsw_reg_qpts_trust_state {
3847 	MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3848 	MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */
3849 };
3850 
3851 /* reg_qpts_trust_state
3852  * Trust state for a given port.
3853  * Access: RW
3854  */
3855 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3856 
3857 static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port,
3858 				       enum mlxsw_reg_qpts_trust_state ts)
3859 {
3860 	MLXSW_REG_ZERO(qpts, payload);
3861 
3862 	mlxsw_reg_qpts_local_port_set(payload, local_port);
3863 	mlxsw_reg_qpts_trust_state_set(payload, ts);
3864 }
3865 
3866 /* QPCR - QoS Policer Configuration Register
3867  * -----------------------------------------
3868  * The QPCR register is used to create policers - that limit
3869  * the rate of bytes or packets via some trap group.
3870  */
3871 #define MLXSW_REG_QPCR_ID 0x4004
3872 #define MLXSW_REG_QPCR_LEN 0x28
3873 
3874 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3875 
3876 enum mlxsw_reg_qpcr_g {
3877 	MLXSW_REG_QPCR_G_GLOBAL = 2,
3878 	MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3879 };
3880 
3881 /* reg_qpcr_g
3882  * The policer type.
3883  * Access: Index
3884  */
3885 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3886 
3887 /* reg_qpcr_pid
3888  * Policer ID.
3889  * Access: Index
3890  */
3891 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3892 
3893 /* reg_qpcr_clear_counter
3894  * Clear counters.
3895  * Access: OP
3896  */
3897 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1);
3898 
3899 /* reg_qpcr_color_aware
3900  * Is the policer aware of colors.
3901  * Must be 0 (unaware) for cpu port.
3902  * Access: RW for unbounded policer. RO for bounded policer.
3903  */
3904 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3905 
3906 /* reg_qpcr_bytes
3907  * Is policer limit is for bytes per sec or packets per sec.
3908  * 0 - packets
3909  * 1 - bytes
3910  * Access: RW for unbounded policer. RO for bounded policer.
3911  */
3912 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3913 
3914 enum mlxsw_reg_qpcr_ir_units {
3915 	MLXSW_REG_QPCR_IR_UNITS_M,
3916 	MLXSW_REG_QPCR_IR_UNITS_K,
3917 };
3918 
3919 /* reg_qpcr_ir_units
3920  * Policer's units for cir and eir fields (for bytes limits only)
3921  * 1 - 10^3
3922  * 0 - 10^6
3923  * Access: OP
3924  */
3925 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3926 
3927 enum mlxsw_reg_qpcr_rate_type {
3928 	MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3929 	MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3930 };
3931 
3932 /* reg_qpcr_rate_type
3933  * Policer can have one limit (single rate) or 2 limits with specific operation
3934  * for packets that exceed the lower rate but not the upper one.
3935  * (For cpu port must be single rate)
3936  * Access: RW for unbounded policer. RO for bounded policer.
3937  */
3938 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3939 
3940 /* reg_qpc_cbs
3941  * Policer's committed burst size.
3942  * The policer is working with time slices of 50 nano sec. By default every
3943  * slice is granted the proportionate share of the committed rate. If we want to
3944  * allow a slice to exceed that share (while still keeping the rate per sec) we
3945  * can allow burst. The burst size is between the default proportionate share
3946  * (and no lower than 8) to 32Gb. (Even though giving a number higher than the
3947  * committed rate will result in exceeding the rate). The burst size must be a
3948  * log of 2 and will be determined by 2^cbs.
3949  * Access: RW
3950  */
3951 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3952 
3953 /* reg_qpcr_cir
3954  * Policer's committed rate.
3955  * The rate used for sungle rate, the lower rate for double rate.
3956  * For bytes limits, the rate will be this value * the unit from ir_units.
3957  * (Resolution error is up to 1%).
3958  * Access: RW
3959  */
3960 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3961 
3962 /* reg_qpcr_eir
3963  * Policer's exceed rate.
3964  * The higher rate for double rate, reserved for single rate.
3965  * Lower rate for double rate policer.
3966  * For bytes limits, the rate will be this value * the unit from ir_units.
3967  * (Resolution error is up to 1%).
3968  * Access: RW
3969  */
3970 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3971 
3972 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3973 
3974 /* reg_qpcr_exceed_action.
3975  * What to do with packets between the 2 limits for double rate.
3976  * Access: RW for unbounded policer. RO for bounded policer.
3977  */
3978 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3979 
3980 enum mlxsw_reg_qpcr_action {
3981 	/* Discard */
3982 	MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3983 	/* Forward and set color to red.
3984 	 * If the packet is intended to cpu port, it will be dropped.
3985 	 */
3986 	MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3987 };
3988 
3989 /* reg_qpcr_violate_action
3990  * What to do with packets that cross the cir limit (for single rate) or the eir
3991  * limit (for double rate).
3992  * Access: RW for unbounded policer. RO for bounded policer.
3993  */
3994 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3995 
3996 /* reg_qpcr_violate_count
3997  * Counts the number of times violate_action happened on this PID.
3998  * Access: RW
3999  */
4000 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64);
4001 
4002 /* Packets */
4003 #define MLXSW_REG_QPCR_LOWEST_CIR	1
4004 #define MLXSW_REG_QPCR_HIGHEST_CIR	(2 * 1000 * 1000 * 1000) /* 2Gpps */
4005 #define MLXSW_REG_QPCR_LOWEST_CBS	4
4006 #define MLXSW_REG_QPCR_HIGHEST_CBS	24
4007 
4008 /* Bandwidth */
4009 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS		1024 /* bps */
4010 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS		2000000000000ULL /* 2Tbps */
4011 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1	4
4012 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2	4
4013 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1	25
4014 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2	31
4015 
4016 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
4017 				       enum mlxsw_reg_qpcr_ir_units ir_units,
4018 				       bool bytes, u32 cir, u16 cbs)
4019 {
4020 	MLXSW_REG_ZERO(qpcr, payload);
4021 	mlxsw_reg_qpcr_pid_set(payload, pid);
4022 	mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
4023 	mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
4024 	mlxsw_reg_qpcr_violate_action_set(payload,
4025 					  MLXSW_REG_QPCR_ACTION_DISCARD);
4026 	mlxsw_reg_qpcr_cir_set(payload, cir);
4027 	mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
4028 	mlxsw_reg_qpcr_bytes_set(payload, bytes);
4029 	mlxsw_reg_qpcr_cbs_set(payload, cbs);
4030 }
4031 
4032 /* QTCT - QoS Switch Traffic Class Table
4033  * -------------------------------------
4034  * Configures the mapping between the packet switch priority and the
4035  * traffic class on the transmit port.
4036  */
4037 #define MLXSW_REG_QTCT_ID 0x400A
4038 #define MLXSW_REG_QTCT_LEN 0x08
4039 
4040 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
4041 
4042 /* reg_qtct_local_port
4043  * Local port number.
4044  * Access: Index
4045  *
4046  * Note: CPU port is not supported.
4047  */
4048 MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12);
4049 
4050 /* reg_qtct_sub_port
4051  * Virtual port within the physical port.
4052  * Should be set to 0 when virtual ports are not enabled on the port.
4053  * Access: Index
4054  */
4055 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
4056 
4057 /* reg_qtct_switch_prio
4058  * Switch priority.
4059  * Access: Index
4060  */
4061 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
4062 
4063 /* reg_qtct_tclass
4064  * Traffic class.
4065  * Default values:
4066  * switch_prio 0 : tclass 1
4067  * switch_prio 1 : tclass 0
4068  * switch_prio i : tclass i, for i > 1
4069  * Access: RW
4070  */
4071 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
4072 
4073 static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port,
4074 				       u8 switch_prio, u8 tclass)
4075 {
4076 	MLXSW_REG_ZERO(qtct, payload);
4077 	mlxsw_reg_qtct_local_port_set(payload, local_port);
4078 	mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
4079 	mlxsw_reg_qtct_tclass_set(payload, tclass);
4080 }
4081 
4082 /* QEEC - QoS ETS Element Configuration Register
4083  * ---------------------------------------------
4084  * Configures the ETS elements.
4085  */
4086 #define MLXSW_REG_QEEC_ID 0x400D
4087 #define MLXSW_REG_QEEC_LEN 0x20
4088 
4089 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
4090 
4091 /* reg_qeec_local_port
4092  * Local port number.
4093  * Access: Index
4094  *
4095  * Note: CPU port is supported.
4096  */
4097 MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12);
4098 
4099 enum mlxsw_reg_qeec_hr {
4100 	MLXSW_REG_QEEC_HR_PORT,
4101 	MLXSW_REG_QEEC_HR_GROUP,
4102 	MLXSW_REG_QEEC_HR_SUBGROUP,
4103 	MLXSW_REG_QEEC_HR_TC,
4104 };
4105 
4106 /* reg_qeec_element_hierarchy
4107  * 0 - Port
4108  * 1 - Group
4109  * 2 - Subgroup
4110  * 3 - Traffic Class
4111  * Access: Index
4112  */
4113 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
4114 
4115 /* reg_qeec_element_index
4116  * The index of the element in the hierarchy.
4117  * Access: Index
4118  */
4119 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
4120 
4121 /* reg_qeec_next_element_index
4122  * The index of the next (lower) element in the hierarchy.
4123  * Access: RW
4124  *
4125  * Note: Reserved for element_hierarchy 0.
4126  */
4127 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
4128 
4129 /* reg_qeec_mise
4130  * Min shaper configuration enable. Enables configuration of the min
4131  * shaper on this ETS element
4132  * 0 - Disable
4133  * 1 - Enable
4134  * Access: RW
4135  */
4136 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
4137 
4138 /* reg_qeec_ptps
4139  * PTP shaper
4140  * 0: regular shaper mode
4141  * 1: PTP oriented shaper
4142  * Allowed only for hierarchy 0
4143  * Not supported for CPU port
4144  * Note that ptps mode may affect the shaper rates of all hierarchies
4145  * Supported only on Spectrum-1
4146  * Access: RW
4147  */
4148 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);
4149 
4150 enum {
4151 	MLXSW_REG_QEEC_BYTES_MODE,
4152 	MLXSW_REG_QEEC_PACKETS_MODE,
4153 };
4154 
4155 /* reg_qeec_pb
4156  * Packets or bytes mode.
4157  * 0 - Bytes mode
4158  * 1 - Packets mode
4159  * Access: RW
4160  *
4161  * Note: Used for max shaper configuration. For Spectrum, packets mode
4162  * is supported only for traffic classes of CPU port.
4163  */
4164 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
4165 
4166 /* The smallest permitted min shaper rate. */
4167 #define MLXSW_REG_QEEC_MIS_MIN	200000		/* Kbps */
4168 
4169 /* reg_qeec_min_shaper_rate
4170  * Min shaper information rate.
4171  * For CPU port, can only be configured for port hierarchy.
4172  * When in bytes mode, value is specified in units of 1000bps.
4173  * Access: RW
4174  */
4175 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
4176 
4177 /* reg_qeec_mase
4178  * Max shaper configuration enable. Enables configuration of the max
4179  * shaper on this ETS element.
4180  * 0 - Disable
4181  * 1 - Enable
4182  * Access: RW
4183  */
4184 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
4185 
4186 /* The largest max shaper value possible to disable the shaper. */
4187 #define MLXSW_REG_QEEC_MAS_DIS	((1u << 31) - 1)	/* Kbps */
4188 
4189 /* reg_qeec_max_shaper_rate
4190  * Max shaper information rate.
4191  * For CPU port, can only be configured for port hierarchy.
4192  * When in bytes mode, value is specified in units of 1000bps.
4193  * Access: RW
4194  */
4195 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31);
4196 
4197 /* reg_qeec_de
4198  * DWRR configuration enable. Enables configuration of the dwrr and
4199  * dwrr_weight.
4200  * 0 - Disable
4201  * 1 - Enable
4202  * Access: RW
4203  */
4204 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
4205 
4206 /* reg_qeec_dwrr
4207  * Transmission selection algorithm to use on the link going down from
4208  * the ETS element.
4209  * 0 - Strict priority
4210  * 1 - DWRR
4211  * Access: RW
4212  */
4213 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
4214 
4215 /* reg_qeec_dwrr_weight
4216  * DWRR weight on the link going down from the ETS element. The
4217  * percentage of bandwidth guaranteed to an ETS element within
4218  * its hierarchy. The sum of all weights across all ETS elements
4219  * within one hierarchy should be equal to 100. Reserved when
4220  * transmission selection algorithm is strict priority.
4221  * Access: RW
4222  */
4223 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
4224 
4225 /* reg_qeec_max_shaper_bs
4226  * Max shaper burst size
4227  * Burst size is 2^max_shaper_bs * 512 bits
4228  * For Spectrum-1: Range is: 5..25
4229  * For Spectrum-2: Range is: 11..25
4230  * Reserved when ptps = 1
4231  * Access: RW
4232  */
4233 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6);
4234 
4235 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS	25
4236 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1	5
4237 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2	11
4238 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3	11
4239 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4	11
4240 
4241 static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port,
4242 				       enum mlxsw_reg_qeec_hr hr, u8 index,
4243 				       u8 next_index)
4244 {
4245 	MLXSW_REG_ZERO(qeec, payload);
4246 	mlxsw_reg_qeec_local_port_set(payload, local_port);
4247 	mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
4248 	mlxsw_reg_qeec_element_index_set(payload, index);
4249 	mlxsw_reg_qeec_next_element_index_set(payload, next_index);
4250 }
4251 
4252 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port,
4253 					    bool ptps)
4254 {
4255 	MLXSW_REG_ZERO(qeec, payload);
4256 	mlxsw_reg_qeec_local_port_set(payload, local_port);
4257 	mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT);
4258 	mlxsw_reg_qeec_ptps_set(payload, ptps);
4259 }
4260 
4261 /* QRWE - QoS ReWrite Enable
4262  * -------------------------
4263  * This register configures the rewrite enable per receive port.
4264  */
4265 #define MLXSW_REG_QRWE_ID 0x400F
4266 #define MLXSW_REG_QRWE_LEN 0x08
4267 
4268 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
4269 
4270 /* reg_qrwe_local_port
4271  * Local port number.
4272  * Access: Index
4273  *
4274  * Note: CPU port is supported. No support for router port.
4275  */
4276 MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12);
4277 
4278 /* reg_qrwe_dscp
4279  * Whether to enable DSCP rewrite (default is 0, don't rewrite).
4280  * Access: RW
4281  */
4282 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
4283 
4284 /* reg_qrwe_pcp
4285  * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
4286  * Access: RW
4287  */
4288 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
4289 
4290 static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port,
4291 				       bool rewrite_pcp, bool rewrite_dscp)
4292 {
4293 	MLXSW_REG_ZERO(qrwe, payload);
4294 	mlxsw_reg_qrwe_local_port_set(payload, local_port);
4295 	mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
4296 	mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
4297 }
4298 
4299 /* QPDSM - QoS Priority to DSCP Mapping
4300  * ------------------------------------
4301  * QoS Priority to DSCP Mapping Register
4302  */
4303 #define MLXSW_REG_QPDSM_ID 0x4011
4304 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */
4305 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */
4306 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
4307 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN +			\
4308 			     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN *	\
4309 			     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
4310 
4311 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
4312 
4313 /* reg_qpdsm_local_port
4314  * Local Port. Supported for data packets from CPU port.
4315  * Access: Index
4316  */
4317 MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12);
4318 
4319 /* reg_qpdsm_prio_entry_color0_e
4320  * Enable update of the entry for color 0 and a given port.
4321  * Access: WO
4322  */
4323 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
4324 		     MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
4325 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4326 
4327 /* reg_qpdsm_prio_entry_color0_dscp
4328  * DSCP field in the outer label of the packet for color 0 and a given port.
4329  * Reserved when e=0.
4330  * Access: RW
4331  */
4332 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
4333 		     MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
4334 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4335 
4336 /* reg_qpdsm_prio_entry_color1_e
4337  * Enable update of the entry for color 1 and a given port.
4338  * Access: WO
4339  */
4340 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
4341 		     MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
4342 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4343 
4344 /* reg_qpdsm_prio_entry_color1_dscp
4345  * DSCP field in the outer label of the packet for color 1 and a given port.
4346  * Reserved when e=0.
4347  * Access: RW
4348  */
4349 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
4350 		     MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
4351 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4352 
4353 /* reg_qpdsm_prio_entry_color2_e
4354  * Enable update of the entry for color 2 and a given port.
4355  * Access: WO
4356  */
4357 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
4358 		     MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
4359 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4360 
4361 /* reg_qpdsm_prio_entry_color2_dscp
4362  * DSCP field in the outer label of the packet for color 2 and a given port.
4363  * Reserved when e=0.
4364  * Access: RW
4365  */
4366 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
4367 		     MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
4368 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4369 
4370 static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port)
4371 {
4372 	MLXSW_REG_ZERO(qpdsm, payload);
4373 	mlxsw_reg_qpdsm_local_port_set(payload, local_port);
4374 }
4375 
4376 static inline void
4377 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
4378 {
4379 	mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
4380 	mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
4381 	mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
4382 	mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
4383 	mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
4384 	mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
4385 }
4386 
4387 /* QPDP - QoS Port DSCP to Priority Mapping Register
4388  * -------------------------------------------------
4389  * This register controls the port default Switch Priority and Color. The
4390  * default Switch Priority and Color are used for frames where the trust state
4391  * uses default values. All member ports of a LAG should be configured with the
4392  * same default values.
4393  */
4394 #define MLXSW_REG_QPDP_ID 0x4007
4395 #define MLXSW_REG_QPDP_LEN 0x8
4396 
4397 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN);
4398 
4399 /* reg_qpdp_local_port
4400  * Local Port. Supported for data packets from CPU port.
4401  * Access: Index
4402  */
4403 MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12);
4404 
4405 /* reg_qpdp_switch_prio
4406  * Default port Switch Priority (default 0)
4407  * Access: RW
4408  */
4409 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4);
4410 
4411 static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port,
4412 				       u8 switch_prio)
4413 {
4414 	MLXSW_REG_ZERO(qpdp, payload);
4415 	mlxsw_reg_qpdp_local_port_set(payload, local_port);
4416 	mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio);
4417 }
4418 
4419 /* QPDPM - QoS Port DSCP to Priority Mapping Register
4420  * --------------------------------------------------
4421  * This register controls the mapping from DSCP field to
4422  * Switch Priority for IP packets.
4423  */
4424 #define MLXSW_REG_QPDPM_ID 0x4013
4425 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */
4426 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */
4427 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
4428 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN +			\
4429 			     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN *	\
4430 			     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
4431 
4432 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
4433 
4434 /* reg_qpdpm_local_port
4435  * Local Port. Supported for data packets from CPU port.
4436  * Access: Index
4437  */
4438 MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12);
4439 
4440 /* reg_qpdpm_dscp_e
4441  * Enable update of the specific entry. When cleared, the switch_prio and color
4442  * fields are ignored and the previous switch_prio and color values are
4443  * preserved.
4444  * Access: WO
4445  */
4446 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
4447 		     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4448 
4449 /* reg_qpdpm_dscp_prio
4450  * The new Switch Priority value for the relevant DSCP value.
4451  * Access: RW
4452  */
4453 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
4454 		     MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
4455 		     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4456 
4457 static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port)
4458 {
4459 	MLXSW_REG_ZERO(qpdpm, payload);
4460 	mlxsw_reg_qpdpm_local_port_set(payload, local_port);
4461 }
4462 
4463 static inline void
4464 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
4465 {
4466 	mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
4467 	mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
4468 }
4469 
4470 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register
4471  * ------------------------------------------------------------------
4472  * This register configures if the Switch Priority to Traffic Class mapping is
4473  * based on Multicast packet indication. If so, then multicast packets will get
4474  * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by
4475  * QTCT.
4476  * By default, Switch Priority to Traffic Class mapping is not based on
4477  * Multicast packet indication.
4478  */
4479 #define MLXSW_REG_QTCTM_ID 0x401A
4480 #define MLXSW_REG_QTCTM_LEN 0x08
4481 
4482 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
4483 
4484 /* reg_qtctm_local_port
4485  * Local port number.
4486  * No support for CPU port.
4487  * Access: Index
4488  */
4489 MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12);
4490 
4491 /* reg_qtctm_mc
4492  * Multicast Mode
4493  * Whether Switch Priority to Traffic Class mapping is based on Multicast packet
4494  * indication (default is 0, not based on Multicast packet indication).
4495  */
4496 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
4497 
4498 static inline void
4499 mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc)
4500 {
4501 	MLXSW_REG_ZERO(qtctm, payload);
4502 	mlxsw_reg_qtctm_local_port_set(payload, local_port);
4503 	mlxsw_reg_qtctm_mc_set(payload, mc);
4504 }
4505 
4506 /* QPSC - QoS PTP Shaper Configuration Register
4507  * --------------------------------------------
4508  * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1.
4509  * Supported only on Spectrum-1.
4510  */
4511 #define MLXSW_REG_QPSC_ID 0x401B
4512 #define MLXSW_REG_QPSC_LEN 0x28
4513 
4514 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN);
4515 
4516 enum mlxsw_reg_qpsc_port_speed {
4517 	MLXSW_REG_QPSC_PORT_SPEED_100M,
4518 	MLXSW_REG_QPSC_PORT_SPEED_1G,
4519 	MLXSW_REG_QPSC_PORT_SPEED_10G,
4520 	MLXSW_REG_QPSC_PORT_SPEED_25G,
4521 };
4522 
4523 /* reg_qpsc_port_speed
4524  * Port speed.
4525  * Access: Index
4526  */
4527 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4);
4528 
4529 /* reg_qpsc_shaper_time_exp
4530  * The base-time-interval for updating the shapers tokens (for all hierarchies).
4531  * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
4532  * shaper_rate = 64bit * shaper_inc / shaper_update_rate
4533  * Access: RW
4534  */
4535 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4);
4536 
4537 /* reg_qpsc_shaper_time_mantissa
4538  * The base-time-interval for updating the shapers tokens (for all hierarchies).
4539  * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
4540  * shaper_rate = 64bit * shaper_inc / shaper_update_rate
4541  * Access: RW
4542  */
4543 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5);
4544 
4545 /* reg_qpsc_shaper_inc
4546  * Number of tokens added to shaper on each update.
4547  * Units of 8B.
4548  * Access: RW
4549  */
4550 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5);
4551 
4552 /* reg_qpsc_shaper_bs
4553  * Max shaper Burst size.
4554  * Burst size is 2 ^ max_shaper_bs * 512 [bits]
4555  * Range is: 5..25 (from 2KB..2GB)
4556  * Access: RW
4557  */
4558 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6);
4559 
4560 /* reg_qpsc_ptsc_we
4561  * Write enable to port_to_shaper_credits.
4562  * Access: WO
4563  */
4564 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1);
4565 
4566 /* reg_qpsc_port_to_shaper_credits
4567  * For split ports: range 1..57
4568  * For non-split ports: range 1..112
4569  * Written only when ptsc_we is set.
4570  * Access: RW
4571  */
4572 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8);
4573 
4574 /* reg_qpsc_ing_timestamp_inc
4575  * Ingress timestamp increment.
4576  * 2's complement.
4577  * The timestamp of MTPPTR at ingress will be incremented by this value. Global
4578  * value for all ports.
4579  * Same units as used by MTPPTR.
4580  * Access: RW
4581  */
4582 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32);
4583 
4584 /* reg_qpsc_egr_timestamp_inc
4585  * Egress timestamp increment.
4586  * 2's complement.
4587  * The timestamp of MTPPTR at egress will be incremented by this value. Global
4588  * value for all ports.
4589  * Same units as used by MTPPTR.
4590  * Access: RW
4591  */
4592 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32);
4593 
4594 static inline void
4595 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed,
4596 		    u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc,
4597 		    u8 shaper_bs, u8 port_to_shaper_credits,
4598 		    int ing_timestamp_inc, int egr_timestamp_inc)
4599 {
4600 	MLXSW_REG_ZERO(qpsc, payload);
4601 	mlxsw_reg_qpsc_port_speed_set(payload, port_speed);
4602 	mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp);
4603 	mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa);
4604 	mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc);
4605 	mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs);
4606 	mlxsw_reg_qpsc_ptsc_we_set(payload, true);
4607 	mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits);
4608 	mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc);
4609 	mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc);
4610 }
4611 
4612 /* PMLP - Ports Module to Local Port Register
4613  * ------------------------------------------
4614  * Configures the assignment of modules to local ports.
4615  */
4616 #define MLXSW_REG_PMLP_ID 0x5002
4617 #define MLXSW_REG_PMLP_LEN 0x40
4618 
4619 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
4620 
4621 /* reg_pmlp_rxtx
4622  * 0 - Tx value is used for both Tx and Rx.
4623  * 1 - Rx value is taken from a separte field.
4624  * Access: RW
4625  */
4626 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
4627 
4628 /* reg_pmlp_local_port
4629  * Local port number.
4630  * Access: Index
4631  */
4632 MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12);
4633 
4634 /* reg_pmlp_width
4635  * 0 - Unmap local port.
4636  * 1 - Lane 0 is used.
4637  * 2 - Lanes 0 and 1 are used.
4638  * 4 - Lanes 0, 1, 2 and 3 are used.
4639  * 8 - Lanes 0-7 are used.
4640  * Access: RW
4641  */
4642 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
4643 
4644 /* reg_pmlp_module
4645  * Module number.
4646  * Access: RW
4647  */
4648 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
4649 
4650 /* reg_pmlp_slot_index
4651  * Module number.
4652  * Slot_index
4653  * Slot_index = 0 represent the onboard (motherboard).
4654  * In case of non-modular system only slot_index = 0 is available.
4655  * Access: RW
4656  */
4657 MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false);
4658 
4659 /* reg_pmlp_tx_lane
4660  * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
4661  * Access: RW
4662  */
4663 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false);
4664 
4665 /* reg_pmlp_rx_lane
4666  * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
4667  * equal to Tx lane.
4668  * Access: RW
4669  */
4670 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false);
4671 
4672 static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port)
4673 {
4674 	MLXSW_REG_ZERO(pmlp, payload);
4675 	mlxsw_reg_pmlp_local_port_set(payload, local_port);
4676 }
4677 
4678 /* PMTU - Port MTU Register
4679  * ------------------------
4680  * Configures and reports the port MTU.
4681  */
4682 #define MLXSW_REG_PMTU_ID 0x5003
4683 #define MLXSW_REG_PMTU_LEN 0x10
4684 
4685 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
4686 
4687 /* reg_pmtu_local_port
4688  * Local port number.
4689  * Access: Index
4690  */
4691 MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12);
4692 
4693 /* reg_pmtu_max_mtu
4694  * Maximum MTU.
4695  * When port type (e.g. Ethernet) is configured, the relevant MTU is
4696  * reported, otherwise the minimum between the max_mtu of the different
4697  * types is reported.
4698  * Access: RO
4699  */
4700 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
4701 
4702 /* reg_pmtu_admin_mtu
4703  * MTU value to set port to. Must be smaller or equal to max_mtu.
4704  * Note: If port type is Infiniband, then port must be disabled, when its
4705  * MTU is set.
4706  * Access: RW
4707  */
4708 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
4709 
4710 /* reg_pmtu_oper_mtu
4711  * The actual MTU configured on the port. Packets exceeding this size
4712  * will be dropped.
4713  * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
4714  * oper_mtu might be smaller than admin_mtu.
4715  * Access: RO
4716  */
4717 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
4718 
4719 static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port,
4720 				       u16 new_mtu)
4721 {
4722 	MLXSW_REG_ZERO(pmtu, payload);
4723 	mlxsw_reg_pmtu_local_port_set(payload, local_port);
4724 	mlxsw_reg_pmtu_max_mtu_set(payload, 0);
4725 	mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
4726 	mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
4727 }
4728 
4729 /* PTYS - Port Type and Speed Register
4730  * -----------------------------------
4731  * Configures and reports the port speed type.
4732  *
4733  * Note: When set while the link is up, the changes will not take effect
4734  * until the port transitions from down to up state.
4735  */
4736 #define MLXSW_REG_PTYS_ID 0x5004
4737 #define MLXSW_REG_PTYS_LEN 0x40
4738 
4739 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
4740 
4741 /* an_disable_admin
4742  * Auto negotiation disable administrative configuration
4743  * 0 - Device doesn't support AN disable.
4744  * 1 - Device supports AN disable.
4745  * Access: RW
4746  */
4747 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
4748 
4749 /* reg_ptys_local_port
4750  * Local port number.
4751  * Access: Index
4752  */
4753 MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12);
4754 
4755 #define MLXSW_REG_PTYS_PROTO_MASK_IB	BIT(0)
4756 #define MLXSW_REG_PTYS_PROTO_MASK_ETH	BIT(2)
4757 
4758 /* reg_ptys_proto_mask
4759  * Protocol mask. Indicates which protocol is used.
4760  * 0 - Infiniband.
4761  * 1 - Fibre Channel.
4762  * 2 - Ethernet.
4763  * Access: Index
4764  */
4765 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
4766 
4767 enum {
4768 	MLXSW_REG_PTYS_AN_STATUS_NA,
4769 	MLXSW_REG_PTYS_AN_STATUS_OK,
4770 	MLXSW_REG_PTYS_AN_STATUS_FAIL,
4771 };
4772 
4773 /* reg_ptys_an_status
4774  * Autonegotiation status.
4775  * Access: RO
4776  */
4777 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
4778 
4779 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M				BIT(0)
4780 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII			BIT(1)
4781 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R				BIT(3)
4782 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G			BIT(4)
4783 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G		BIT(5)
4784 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR		BIT(6)
4785 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2	BIT(7)
4786 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR	BIT(8)
4787 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4		BIT(9)
4788 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2		BIT(10)
4789 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_1_100GBASE_CR_KR		BIT(11)
4790 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4		BIT(12)
4791 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_2_200GBASE_CR2_KR2		BIT(13)
4792 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8				BIT(15)
4793 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_4_400GBASE_CR4_KR4		BIT(16)
4794 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8				BIT(19)
4795 
4796 /* reg_ptys_ext_eth_proto_cap
4797  * Extended Ethernet port supported speeds and protocols.
4798  * Access: RO
4799  */
4800 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
4801 
4802 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII			BIT(0)
4803 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX		BIT(1)
4804 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4		BIT(2)
4805 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4		BIT(3)
4806 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR		BIT(4)
4807 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4		BIT(6)
4808 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4		BIT(7)
4809 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR		BIT(12)
4810 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR		BIT(13)
4811 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR		BIT(14)
4812 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4		BIT(15)
4813 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4	BIT(16)
4814 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2		BIT(18)
4815 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4		BIT(19)
4816 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4		BIT(20)
4817 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4		BIT(21)
4818 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4		BIT(22)
4819 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4	BIT(23)
4820 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T		BIT(24)
4821 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T		BIT(25)
4822 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR		BIT(27)
4823 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR		BIT(28)
4824 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR		BIT(29)
4825 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2		BIT(30)
4826 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2		BIT(31)
4827 
4828 /* reg_ptys_eth_proto_cap
4829  * Ethernet port supported speeds and protocols.
4830  * Access: RO
4831  */
4832 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
4833 
4834 /* reg_ptys_ext_eth_proto_admin
4835  * Extended speed and protocol to set port to.
4836  * Access: RW
4837  */
4838 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
4839 
4840 /* reg_ptys_eth_proto_admin
4841  * Speed and protocol to set port to.
4842  * Access: RW
4843  */
4844 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
4845 
4846 /* reg_ptys_ext_eth_proto_oper
4847  * The extended current speed and protocol configured for the port.
4848  * Access: RO
4849  */
4850 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
4851 
4852 /* reg_ptys_eth_proto_oper
4853  * The current speed and protocol configured for the port.
4854  * Access: RO
4855  */
4856 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
4857 
4858 enum mlxsw_reg_ptys_connector_type {
4859 	MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
4860 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
4861 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,
4862 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,
4863 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,
4864 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,
4865 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,
4866 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,
4867 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,
4868 };
4869 
4870 /* reg_ptys_connector_type
4871  * Connector type indication.
4872  * Access: RO
4873  */
4874 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4875 
4876 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port,
4877 					   u32 proto_admin, bool autoneg)
4878 {
4879 	MLXSW_REG_ZERO(ptys, payload);
4880 	mlxsw_reg_ptys_local_port_set(payload, local_port);
4881 	mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4882 	mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
4883 	mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4884 }
4885 
4886 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port,
4887 					       u32 proto_admin, bool autoneg)
4888 {
4889 	MLXSW_REG_ZERO(ptys, payload);
4890 	mlxsw_reg_ptys_local_port_set(payload, local_port);
4891 	mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4892 	mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4893 	mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4894 }
4895 
4896 static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
4897 					     u32 *p_eth_proto_cap,
4898 					     u32 *p_eth_proto_admin,
4899 					     u32 *p_eth_proto_oper)
4900 {
4901 	if (p_eth_proto_cap)
4902 		*p_eth_proto_cap =
4903 			mlxsw_reg_ptys_eth_proto_cap_get(payload);
4904 	if (p_eth_proto_admin)
4905 		*p_eth_proto_admin =
4906 			mlxsw_reg_ptys_eth_proto_admin_get(payload);
4907 	if (p_eth_proto_oper)
4908 		*p_eth_proto_oper =
4909 			mlxsw_reg_ptys_eth_proto_oper_get(payload);
4910 }
4911 
4912 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
4913 						 u32 *p_eth_proto_cap,
4914 						 u32 *p_eth_proto_admin,
4915 						 u32 *p_eth_proto_oper)
4916 {
4917 	if (p_eth_proto_cap)
4918 		*p_eth_proto_cap =
4919 			mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);
4920 	if (p_eth_proto_admin)
4921 		*p_eth_proto_admin =
4922 			mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
4923 	if (p_eth_proto_oper)
4924 		*p_eth_proto_oper =
4925 			mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
4926 }
4927 
4928 /* PPAD - Port Physical Address Register
4929  * -------------------------------------
4930  * The PPAD register configures the per port physical MAC address.
4931  */
4932 #define MLXSW_REG_PPAD_ID 0x5005
4933 #define MLXSW_REG_PPAD_LEN 0x10
4934 
4935 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
4936 
4937 /* reg_ppad_single_base_mac
4938  * 0: base_mac, local port should be 0 and mac[7:0] is
4939  * reserved. HW will set incremental
4940  * 1: single_mac - mac of the local_port
4941  * Access: RW
4942  */
4943 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
4944 
4945 /* reg_ppad_local_port
4946  * port number, if single_base_mac = 0 then local_port is reserved
4947  * Access: RW
4948  */
4949 MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24);
4950 
4951 /* reg_ppad_mac
4952  * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
4953  * If single_base_mac = 1 - the per port MAC address
4954  * Access: RW
4955  */
4956 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4957 
4958 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
4959 				       u16 local_port)
4960 {
4961 	MLXSW_REG_ZERO(ppad, payload);
4962 	mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
4963 	mlxsw_reg_ppad_local_port_set(payload, local_port);
4964 }
4965 
4966 /* PAOS - Ports Administrative and Operational Status Register
4967  * -----------------------------------------------------------
4968  * Configures and retrieves per port administrative and operational status.
4969  */
4970 #define MLXSW_REG_PAOS_ID 0x5006
4971 #define MLXSW_REG_PAOS_LEN 0x10
4972 
4973 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
4974 
4975 /* reg_paos_swid
4976  * Switch partition ID with which to associate the port.
4977  * Note: while external ports uses unique local port numbers (and thus swid is
4978  * redundant), router ports use the same local port number where swid is the
4979  * only indication for the relevant port.
4980  * Access: Index
4981  */
4982 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
4983 
4984 /* reg_paos_local_port
4985  * Local port number.
4986  * Access: Index
4987  */
4988 MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12);
4989 
4990 /* reg_paos_admin_status
4991  * Port administrative state (the desired state of the port):
4992  * 1 - Up.
4993  * 2 - Down.
4994  * 3 - Up once. This means that in case of link failure, the port won't go
4995  *     into polling mode, but will wait to be re-enabled by software.
4996  * 4 - Disabled by system. Can only be set by hardware.
4997  * Access: RW
4998  */
4999 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
5000 
5001 /* reg_paos_oper_status
5002  * Port operational state (the current state):
5003  * 1 - Up.
5004  * 2 - Down.
5005  * 3 - Down by port failure. This means that the device will not let the
5006  *     port up again until explicitly specified by software.
5007  * Access: RO
5008  */
5009 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
5010 
5011 /* reg_paos_ase
5012  * Admin state update enabled.
5013  * Access: WO
5014  */
5015 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
5016 
5017 /* reg_paos_ee
5018  * Event update enable. If this bit is set, event generation will be
5019  * updated based on the e field.
5020  * Access: WO
5021  */
5022 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
5023 
5024 /* reg_paos_e
5025  * Event generation on operational state change:
5026  * 0 - Do not generate event.
5027  * 1 - Generate Event.
5028  * 2 - Generate Single Event.
5029  * Access: RW
5030  */
5031 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
5032 
5033 static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port,
5034 				       enum mlxsw_port_admin_status status)
5035 {
5036 	MLXSW_REG_ZERO(paos, payload);
5037 	mlxsw_reg_paos_swid_set(payload, 0);
5038 	mlxsw_reg_paos_local_port_set(payload, local_port);
5039 	mlxsw_reg_paos_admin_status_set(payload, status);
5040 	mlxsw_reg_paos_oper_status_set(payload, 0);
5041 	mlxsw_reg_paos_ase_set(payload, 1);
5042 	mlxsw_reg_paos_ee_set(payload, 1);
5043 	mlxsw_reg_paos_e_set(payload, 1);
5044 }
5045 
5046 /* PFCC - Ports Flow Control Configuration Register
5047  * ------------------------------------------------
5048  * Configures and retrieves the per port flow control configuration.
5049  */
5050 #define MLXSW_REG_PFCC_ID 0x5007
5051 #define MLXSW_REG_PFCC_LEN 0x20
5052 
5053 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
5054 
5055 /* reg_pfcc_local_port
5056  * Local port number.
5057  * Access: Index
5058  */
5059 MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12);
5060 
5061 /* reg_pfcc_pnat
5062  * Port number access type. Determines the way local_port is interpreted:
5063  * 0 - Local port number.
5064  * 1 - IB / label port number.
5065  * Access: Index
5066  */
5067 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
5068 
5069 /* reg_pfcc_shl_cap
5070  * Send to higher layers capabilities:
5071  * 0 - No capability of sending Pause and PFC frames to higher layers.
5072  * 1 - Device has capability of sending Pause and PFC frames to higher
5073  *     layers.
5074  * Access: RO
5075  */
5076 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
5077 
5078 /* reg_pfcc_shl_opr
5079  * Send to higher layers operation:
5080  * 0 - Pause and PFC frames are handled by the port (default).
5081  * 1 - Pause and PFC frames are handled by the port and also sent to
5082  *     higher layers. Only valid if shl_cap = 1.
5083  * Access: RW
5084  */
5085 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
5086 
5087 /* reg_pfcc_ppan
5088  * Pause policy auto negotiation.
5089  * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
5090  * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
5091  *     based on the auto-negotiation resolution.
5092  * Access: RW
5093  *
5094  * Note: The auto-negotiation advertisement is set according to pptx and
5095  * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
5096  */
5097 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
5098 
5099 /* reg_pfcc_prio_mask_tx
5100  * Bit per priority indicating if Tx flow control policy should be
5101  * updated based on bit pfctx.
5102  * Access: WO
5103  */
5104 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
5105 
5106 /* reg_pfcc_prio_mask_rx
5107  * Bit per priority indicating if Rx flow control policy should be
5108  * updated based on bit pfcrx.
5109  * Access: WO
5110  */
5111 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
5112 
5113 /* reg_pfcc_pptx
5114  * Admin Pause policy on Tx.
5115  * 0 - Never generate Pause frames (default).
5116  * 1 - Generate Pause frames according to Rx buffer threshold.
5117  * Access: RW
5118  */
5119 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
5120 
5121 /* reg_pfcc_aptx
5122  * Active (operational) Pause policy on Tx.
5123  * 0 - Never generate Pause frames.
5124  * 1 - Generate Pause frames according to Rx buffer threshold.
5125  * Access: RO
5126  */
5127 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
5128 
5129 /* reg_pfcc_pfctx
5130  * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
5131  * 0 - Never generate priority Pause frames on the specified priority
5132  *     (default).
5133  * 1 - Generate priority Pause frames according to Rx buffer threshold on
5134  *     the specified priority.
5135  * Access: RW
5136  *
5137  * Note: pfctx and pptx must be mutually exclusive.
5138  */
5139 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
5140 
5141 /* reg_pfcc_pprx
5142  * Admin Pause policy on Rx.
5143  * 0 - Ignore received Pause frames (default).
5144  * 1 - Respect received Pause frames.
5145  * Access: RW
5146  */
5147 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
5148 
5149 /* reg_pfcc_aprx
5150  * Active (operational) Pause policy on Rx.
5151  * 0 - Ignore received Pause frames.
5152  * 1 - Respect received Pause frames.
5153  * Access: RO
5154  */
5155 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
5156 
5157 /* reg_pfcc_pfcrx
5158  * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
5159  * 0 - Ignore incoming priority Pause frames on the specified priority
5160  *     (default).
5161  * 1 - Respect incoming priority Pause frames on the specified priority.
5162  * Access: RW
5163  */
5164 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
5165 
5166 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
5167 
5168 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
5169 {
5170 	mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
5171 	mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
5172 	mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
5173 	mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
5174 }
5175 
5176 static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port)
5177 {
5178 	MLXSW_REG_ZERO(pfcc, payload);
5179 	mlxsw_reg_pfcc_local_port_set(payload, local_port);
5180 }
5181 
5182 /* PPCNT - Ports Performance Counters Register
5183  * -------------------------------------------
5184  * The PPCNT register retrieves per port performance counters.
5185  */
5186 #define MLXSW_REG_PPCNT_ID 0x5008
5187 #define MLXSW_REG_PPCNT_LEN 0x100
5188 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
5189 
5190 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
5191 
5192 /* reg_ppcnt_swid
5193  * For HCA: must be always 0.
5194  * Switch partition ID to associate port with.
5195  * Switch partitions are numbered from 0 to 7 inclusively.
5196  * Switch partition 254 indicates stacking ports.
5197  * Switch partition 255 indicates all switch partitions.
5198  * Only valid on Set() operation with local_port=255.
5199  * Access: Index
5200  */
5201 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
5202 
5203 /* reg_ppcnt_local_port
5204  * Local port number.
5205  * Access: Index
5206  */
5207 MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12);
5208 
5209 /* reg_ppcnt_pnat
5210  * Port number access type:
5211  * 0 - Local port number
5212  * 1 - IB port number
5213  * Access: Index
5214  */
5215 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
5216 
5217 enum mlxsw_reg_ppcnt_grp {
5218 	MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
5219 	MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1,
5220 	MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
5221 	MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3,
5222 	MLXSW_REG_PPCNT_EXT_CNT = 0x5,
5223 	MLXSW_REG_PPCNT_DISCARD_CNT = 0x6,
5224 	MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
5225 	MLXSW_REG_PPCNT_TC_CNT = 0x11,
5226 	MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13,
5227 };
5228 
5229 /* reg_ppcnt_grp
5230  * Performance counter group.
5231  * Group 63 indicates all groups. Only valid on Set() operation with
5232  * clr bit set.
5233  * 0x0: IEEE 802.3 Counters
5234  * 0x1: RFC 2863 Counters
5235  * 0x2: RFC 2819 Counters
5236  * 0x3: RFC 3635 Counters
5237  * 0x5: Ethernet Extended Counters
5238  * 0x6: Ethernet Discard Counters
5239  * 0x8: Link Level Retransmission Counters
5240  * 0x10: Per Priority Counters
5241  * 0x11: Per Traffic Class Counters
5242  * 0x12: Physical Layer Counters
5243  * 0x13: Per Traffic Class Congestion Counters
5244  * Access: Index
5245  */
5246 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
5247 
5248 /* reg_ppcnt_clr
5249  * Clear counters. Setting the clr bit will reset the counter value
5250  * for all counters in the counter group. This bit can be set
5251  * for both Set() and Get() operation.
5252  * Access: OP
5253  */
5254 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
5255 
5256 /* reg_ppcnt_lp_gl
5257  * Local port global variable.
5258  * 0: local_port 255 = all ports of the device.
5259  * 1: local_port indicates local port number for all ports.
5260  * Access: OP
5261  */
5262 MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1);
5263 
5264 /* reg_ppcnt_prio_tc
5265  * Priority for counter set that support per priority, valid values: 0-7.
5266  * Traffic class for counter set that support per traffic class,
5267  * valid values: 0- cap_max_tclass-1 .
5268  * For HCA: cap_max_tclass is always 8.
5269  * Otherwise must be 0.
5270  * Access: Index
5271  */
5272 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
5273 
5274 /* Ethernet IEEE 802.3 Counter Group */
5275 
5276 /* reg_ppcnt_a_frames_transmitted_ok
5277  * Access: RO
5278  */
5279 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
5280 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5281 
5282 /* reg_ppcnt_a_frames_received_ok
5283  * Access: RO
5284  */
5285 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
5286 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5287 
5288 /* reg_ppcnt_a_frame_check_sequence_errors
5289  * Access: RO
5290  */
5291 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
5292 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
5293 
5294 /* reg_ppcnt_a_alignment_errors
5295  * Access: RO
5296  */
5297 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
5298 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
5299 
5300 /* reg_ppcnt_a_octets_transmitted_ok
5301  * Access: RO
5302  */
5303 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
5304 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5305 
5306 /* reg_ppcnt_a_octets_received_ok
5307  * Access: RO
5308  */
5309 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
5310 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5311 
5312 /* reg_ppcnt_a_multicast_frames_xmitted_ok
5313  * Access: RO
5314  */
5315 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
5316 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5317 
5318 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
5319  * Access: RO
5320  */
5321 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
5322 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
5323 
5324 /* reg_ppcnt_a_multicast_frames_received_ok
5325  * Access: RO
5326  */
5327 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
5328 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5329 
5330 /* reg_ppcnt_a_broadcast_frames_received_ok
5331  * Access: RO
5332  */
5333 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
5334 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
5335 
5336 /* reg_ppcnt_a_in_range_length_errors
5337  * Access: RO
5338  */
5339 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
5340 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5341 
5342 /* reg_ppcnt_a_out_of_range_length_field
5343  * Access: RO
5344  */
5345 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
5346 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5347 
5348 /* reg_ppcnt_a_frame_too_long_errors
5349  * Access: RO
5350  */
5351 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
5352 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5353 
5354 /* reg_ppcnt_a_symbol_error_during_carrier
5355  * Access: RO
5356  */
5357 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
5358 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5359 
5360 /* reg_ppcnt_a_mac_control_frames_transmitted
5361  * Access: RO
5362  */
5363 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
5364 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5365 
5366 /* reg_ppcnt_a_mac_control_frames_received
5367  * Access: RO
5368  */
5369 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
5370 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
5371 
5372 /* reg_ppcnt_a_unsupported_opcodes_received
5373  * Access: RO
5374  */
5375 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
5376 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
5377 
5378 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
5379  * Access: RO
5380  */
5381 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
5382 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
5383 
5384 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
5385  * Access: RO
5386  */
5387 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
5388 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
5389 
5390 /* Ethernet RFC 2863 Counter Group */
5391 
5392 /* reg_ppcnt_if_in_discards
5393  * Access: RO
5394  */
5395 MLXSW_ITEM64(reg, ppcnt, if_in_discards,
5396 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
5397 
5398 /* reg_ppcnt_if_out_discards
5399  * Access: RO
5400  */
5401 MLXSW_ITEM64(reg, ppcnt, if_out_discards,
5402 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
5403 
5404 /* reg_ppcnt_if_out_errors
5405  * Access: RO
5406  */
5407 MLXSW_ITEM64(reg, ppcnt, if_out_errors,
5408 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5409 
5410 /* Ethernet RFC 2819 Counter Group */
5411 
5412 /* reg_ppcnt_ether_stats_undersize_pkts
5413  * Access: RO
5414  */
5415 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,
5416 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5417 
5418 /* reg_ppcnt_ether_stats_oversize_pkts
5419  * Access: RO
5420  */
5421 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,
5422 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
5423 
5424 /* reg_ppcnt_ether_stats_fragments
5425  * Access: RO
5426  */
5427 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,
5428 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5429 
5430 /* reg_ppcnt_ether_stats_pkts64octets
5431  * Access: RO
5432  */
5433 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
5434 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5435 
5436 /* reg_ppcnt_ether_stats_pkts65to127octets
5437  * Access: RO
5438  */
5439 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
5440 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5441 
5442 /* reg_ppcnt_ether_stats_pkts128to255octets
5443  * Access: RO
5444  */
5445 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
5446 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5447 
5448 /* reg_ppcnt_ether_stats_pkts256to511octets
5449  * Access: RO
5450  */
5451 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
5452 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5453 
5454 /* reg_ppcnt_ether_stats_pkts512to1023octets
5455  * Access: RO
5456  */
5457 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
5458 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
5459 
5460 /* reg_ppcnt_ether_stats_pkts1024to1518octets
5461  * Access: RO
5462  */
5463 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
5464 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
5465 
5466 /* reg_ppcnt_ether_stats_pkts1519to2047octets
5467  * Access: RO
5468  */
5469 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
5470 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
5471 
5472 /* reg_ppcnt_ether_stats_pkts2048to4095octets
5473  * Access: RO
5474  */
5475 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
5476 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
5477 
5478 /* reg_ppcnt_ether_stats_pkts4096to8191octets
5479  * Access: RO
5480  */
5481 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
5482 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
5483 
5484 /* reg_ppcnt_ether_stats_pkts8192to10239octets
5485  * Access: RO
5486  */
5487 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
5488 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
5489 
5490 /* Ethernet RFC 3635 Counter Group */
5491 
5492 /* reg_ppcnt_dot3stats_fcs_errors
5493  * Access: RO
5494  */
5495 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,
5496 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5497 
5498 /* reg_ppcnt_dot3stats_symbol_errors
5499  * Access: RO
5500  */
5501 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors,
5502 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5503 
5504 /* reg_ppcnt_dot3control_in_unknown_opcodes
5505  * Access: RO
5506  */
5507 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes,
5508 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5509 
5510 /* reg_ppcnt_dot3in_pause_frames
5511  * Access: RO
5512  */
5513 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames,
5514 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5515 
5516 /* Ethernet Extended Counter Group Counters */
5517 
5518 /* reg_ppcnt_ecn_marked
5519  * Access: RO
5520  */
5521 MLXSW_ITEM64(reg, ppcnt, ecn_marked,
5522 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5523 
5524 /* Ethernet Discard Counter Group Counters */
5525 
5526 /* reg_ppcnt_ingress_general
5527  * Access: RO
5528  */
5529 MLXSW_ITEM64(reg, ppcnt, ingress_general,
5530 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5531 
5532 /* reg_ppcnt_ingress_policy_engine
5533  * Access: RO
5534  */
5535 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine,
5536 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5537 
5538 /* reg_ppcnt_ingress_vlan_membership
5539  * Access: RO
5540  */
5541 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership,
5542 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
5543 
5544 /* reg_ppcnt_ingress_tag_frame_type
5545  * Access: RO
5546  */
5547 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type,
5548 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
5549 
5550 /* reg_ppcnt_egress_vlan_membership
5551  * Access: RO
5552  */
5553 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership,
5554 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5555 
5556 /* reg_ppcnt_loopback_filter
5557  * Access: RO
5558  */
5559 MLXSW_ITEM64(reg, ppcnt, loopback_filter,
5560 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5561 
5562 /* reg_ppcnt_egress_general
5563  * Access: RO
5564  */
5565 MLXSW_ITEM64(reg, ppcnt, egress_general,
5566 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5567 
5568 /* reg_ppcnt_egress_hoq
5569  * Access: RO
5570  */
5571 MLXSW_ITEM64(reg, ppcnt, egress_hoq,
5572 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5573 
5574 /* reg_ppcnt_egress_policy_engine
5575  * Access: RO
5576  */
5577 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine,
5578 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5579 
5580 /* reg_ppcnt_ingress_tx_link_down
5581  * Access: RO
5582  */
5583 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down,
5584 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5585 
5586 /* reg_ppcnt_egress_stp_filter
5587  * Access: RO
5588  */
5589 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter,
5590 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5591 
5592 /* reg_ppcnt_egress_sll
5593  * Access: RO
5594  */
5595 MLXSW_ITEM64(reg, ppcnt, egress_sll,
5596 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5597 
5598 /* Ethernet Per Priority Group Counters */
5599 
5600 /* reg_ppcnt_rx_octets
5601  * Access: RO
5602  */
5603 MLXSW_ITEM64(reg, ppcnt, rx_octets,
5604 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5605 
5606 /* reg_ppcnt_rx_frames
5607  * Access: RO
5608  */
5609 MLXSW_ITEM64(reg, ppcnt, rx_frames,
5610 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5611 
5612 /* reg_ppcnt_tx_octets
5613  * Access: RO
5614  */
5615 MLXSW_ITEM64(reg, ppcnt, tx_octets,
5616 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5617 
5618 /* reg_ppcnt_tx_frames
5619  * Access: RO
5620  */
5621 MLXSW_ITEM64(reg, ppcnt, tx_frames,
5622 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
5623 
5624 /* reg_ppcnt_rx_pause
5625  * Access: RO
5626  */
5627 MLXSW_ITEM64(reg, ppcnt, rx_pause,
5628 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5629 
5630 /* reg_ppcnt_rx_pause_duration
5631  * Access: RO
5632  */
5633 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
5634 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5635 
5636 /* reg_ppcnt_tx_pause
5637  * Access: RO
5638  */
5639 MLXSW_ITEM64(reg, ppcnt, tx_pause,
5640 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5641 
5642 /* reg_ppcnt_tx_pause_duration
5643  * Access: RO
5644  */
5645 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
5646 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5647 
5648 /* reg_ppcnt_rx_pause_transition
5649  * Access: RO
5650  */
5651 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
5652 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5653 
5654 /* Ethernet Per Traffic Class Counters */
5655 
5656 /* reg_ppcnt_tc_transmit_queue
5657  * Contains the transmit queue depth in cells of traffic class
5658  * selected by prio_tc and the port selected by local_port.
5659  * The field cannot be cleared.
5660  * Access: RO
5661  */
5662 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
5663 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5664 
5665 /* reg_ppcnt_tc_no_buffer_discard_uc
5666  * The number of unicast packets dropped due to lack of shared
5667  * buffer resources.
5668  * Access: RO
5669  */
5670 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
5671 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5672 
5673 /* Ethernet Per Traffic Class Congestion Group Counters */
5674 
5675 /* reg_ppcnt_wred_discard
5676  * Access: RO
5677  */
5678 MLXSW_ITEM64(reg, ppcnt, wred_discard,
5679 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5680 
5681 /* reg_ppcnt_ecn_marked_tc
5682  * Access: RO
5683  */
5684 MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc,
5685 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5686 
5687 static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port,
5688 					enum mlxsw_reg_ppcnt_grp grp,
5689 					u8 prio_tc)
5690 {
5691 	MLXSW_REG_ZERO(ppcnt, payload);
5692 	mlxsw_reg_ppcnt_swid_set(payload, 0);
5693 	mlxsw_reg_ppcnt_local_port_set(payload, local_port);
5694 	mlxsw_reg_ppcnt_pnat_set(payload, 0);
5695 	mlxsw_reg_ppcnt_grp_set(payload, grp);
5696 	mlxsw_reg_ppcnt_clr_set(payload, 0);
5697 	mlxsw_reg_ppcnt_lp_gl_set(payload, 1);
5698 	mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
5699 }
5700 
5701 /* PPTB - Port Prio To Buffer Register
5702  * -----------------------------------
5703  * Configures the switch priority to buffer table.
5704  */
5705 #define MLXSW_REG_PPTB_ID 0x500B
5706 #define MLXSW_REG_PPTB_LEN 0x10
5707 
5708 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
5709 
5710 enum {
5711 	MLXSW_REG_PPTB_MM_UM,
5712 	MLXSW_REG_PPTB_MM_UNICAST,
5713 	MLXSW_REG_PPTB_MM_MULTICAST,
5714 };
5715 
5716 /* reg_pptb_mm
5717  * Mapping mode.
5718  * 0 - Map both unicast and multicast packets to the same buffer.
5719  * 1 - Map only unicast packets.
5720  * 2 - Map only multicast packets.
5721  * Access: Index
5722  *
5723  * Note: SwitchX-2 only supports the first option.
5724  */
5725 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
5726 
5727 /* reg_pptb_local_port
5728  * Local port number.
5729  * Access: Index
5730  */
5731 MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12);
5732 
5733 /* reg_pptb_um
5734  * Enables the update of the untagged_buf field.
5735  * Access: RW
5736  */
5737 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
5738 
5739 /* reg_pptb_pm
5740  * Enables the update of the prio_to_buff field.
5741  * Bit <i> is a flag for updating the mapping for switch priority <i>.
5742  * Access: RW
5743  */
5744 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
5745 
5746 /* reg_pptb_prio_to_buff
5747  * Mapping of switch priority <i> to one of the allocated receive port
5748  * buffers.
5749  * Access: RW
5750  */
5751 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
5752 
5753 /* reg_pptb_pm_msb
5754  * Enables the update of the prio_to_buff field.
5755  * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
5756  * Access: RW
5757  */
5758 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
5759 
5760 /* reg_pptb_untagged_buff
5761  * Mapping of untagged frames to one of the allocated receive port buffers.
5762  * Access: RW
5763  *
5764  * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
5765  * Spectrum, as it maps untagged packets based on the default switch priority.
5766  */
5767 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
5768 
5769 /* reg_pptb_prio_to_buff_msb
5770  * Mapping of switch priority <i+8> to one of the allocated receive port
5771  * buffers.
5772  * Access: RW
5773  */
5774 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
5775 
5776 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
5777 
5778 static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port)
5779 {
5780 	MLXSW_REG_ZERO(pptb, payload);
5781 	mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
5782 	mlxsw_reg_pptb_local_port_set(payload, local_port);
5783 	mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5784 	mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5785 }
5786 
5787 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
5788 						    u8 buff)
5789 {
5790 	mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
5791 	mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
5792 }
5793 
5794 /* PBMC - Port Buffer Management Control Register
5795  * ----------------------------------------------
5796  * The PBMC register configures and retrieves the port packet buffer
5797  * allocation for different Prios, and the Pause threshold management.
5798  */
5799 #define MLXSW_REG_PBMC_ID 0x500C
5800 #define MLXSW_REG_PBMC_LEN 0x6C
5801 
5802 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
5803 
5804 /* reg_pbmc_local_port
5805  * Local port number.
5806  * Access: Index
5807  */
5808 MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12);
5809 
5810 /* reg_pbmc_xoff_timer_value
5811  * When device generates a pause frame, it uses this value as the pause
5812  * timer (time for the peer port to pause in quota-512 bit time).
5813  * Access: RW
5814  */
5815 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
5816 
5817 /* reg_pbmc_xoff_refresh
5818  * The time before a new pause frame should be sent to refresh the pause RW
5819  * state. Using the same units as xoff_timer_value above (in quota-512 bit
5820  * time).
5821  * Access: RW
5822  */
5823 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
5824 
5825 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
5826 
5827 /* reg_pbmc_buf_lossy
5828  * The field indicates if the buffer is lossy.
5829  * 0 - Lossless
5830  * 1 - Lossy
5831  * Access: RW
5832  */
5833 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
5834 
5835 /* reg_pbmc_buf_epsb
5836  * Eligible for Port Shared buffer.
5837  * If epsb is set, packets assigned to buffer are allowed to insert the port
5838  * shared buffer.
5839  * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
5840  * Access: RW
5841  */
5842 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
5843 
5844 /* reg_pbmc_buf_size
5845  * The part of the packet buffer array is allocated for the specific buffer.
5846  * Units are represented in cells.
5847  * Access: RW
5848  */
5849 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
5850 
5851 /* reg_pbmc_buf_xoff_threshold
5852  * Once the amount of data in the buffer goes above this value, device
5853  * starts sending PFC frames for all priorities associated with the
5854  * buffer. Units are represented in cells. Reserved in case of lossy
5855  * buffer.
5856  * Access: RW
5857  *
5858  * Note: In Spectrum, reserved for buffer[9].
5859  */
5860 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
5861 		     0x08, 0x04, false);
5862 
5863 /* reg_pbmc_buf_xon_threshold
5864  * When the amount of data in the buffer goes below this value, device
5865  * stops sending PFC frames for the priorities associated with the
5866  * buffer. Units are represented in cells. Reserved in case of lossy
5867  * buffer.
5868  * Access: RW
5869  *
5870  * Note: In Spectrum, reserved for buffer[9].
5871  */
5872 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
5873 		     0x08, 0x04, false);
5874 
5875 static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port,
5876 				       u16 xoff_timer_value, u16 xoff_refresh)
5877 {
5878 	MLXSW_REG_ZERO(pbmc, payload);
5879 	mlxsw_reg_pbmc_local_port_set(payload, local_port);
5880 	mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
5881 	mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
5882 }
5883 
5884 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
5885 						    int buf_index,
5886 						    u16 size)
5887 {
5888 	mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
5889 	mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5890 	mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5891 }
5892 
5893 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
5894 						       int buf_index, u16 size,
5895 						       u16 threshold)
5896 {
5897 	mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
5898 	mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5899 	mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5900 	mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
5901 	mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
5902 }
5903 
5904 /* PSPA - Port Switch Partition Allocation
5905  * ---------------------------------------
5906  * Controls the association of a port with a switch partition and enables
5907  * configuring ports as stacking ports.
5908  */
5909 #define MLXSW_REG_PSPA_ID 0x500D
5910 #define MLXSW_REG_PSPA_LEN 0x8
5911 
5912 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
5913 
5914 /* reg_pspa_swid
5915  * Switch partition ID.
5916  * Access: RW
5917  */
5918 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
5919 
5920 /* reg_pspa_local_port
5921  * Local port number.
5922  * Access: Index
5923  */
5924 MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0);
5925 
5926 /* reg_pspa_sub_port
5927  * Virtual port within the local port. Set to 0 when virtual ports are
5928  * disabled on the local port.
5929  * Access: Index
5930  */
5931 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
5932 
5933 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port)
5934 {
5935 	MLXSW_REG_ZERO(pspa, payload);
5936 	mlxsw_reg_pspa_swid_set(payload, swid);
5937 	mlxsw_reg_pspa_local_port_set(payload, local_port);
5938 	mlxsw_reg_pspa_sub_port_set(payload, 0);
5939 }
5940 
5941 /* PMAOS - Ports Module Administrative and Operational Status
5942  * ----------------------------------------------------------
5943  * This register configures and retrieves the per module status.
5944  */
5945 #define MLXSW_REG_PMAOS_ID 0x5012
5946 #define MLXSW_REG_PMAOS_LEN 0x10
5947 
5948 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN);
5949 
5950 /* reg_pmaos_rst
5951  * Module reset toggle.
5952  * Note: Setting reset while module is plugged-in will result in transition to
5953  * "initializing" operational state.
5954  * Access: OP
5955  */
5956 MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1);
5957 
5958 /* reg_pmaos_slot_index
5959  * Slot index.
5960  * Access: Index
5961  */
5962 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4);
5963 
5964 /* reg_pmaos_module
5965  * Module number.
5966  * Access: Index
5967  */
5968 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8);
5969 
5970 enum mlxsw_reg_pmaos_admin_status {
5971 	MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1,
5972 	MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2,
5973 	/* If the module is active and then unplugged, or experienced an error
5974 	 * event, the operational status should go to "disabled" and can only
5975 	 * be enabled upon explicit enable command.
5976 	 */
5977 	MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3,
5978 };
5979 
5980 /* reg_pmaos_admin_status
5981  * Module administrative state (the desired state of the module).
5982  * Note: To disable a module, all ports associated with the port must be
5983  * administatively down first.
5984  * Access: RW
5985  */
5986 MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4);
5987 
5988 /* reg_pmaos_ase
5989  * Admin state update enable.
5990  * If this bit is set, admin state will be updated based on admin_state field.
5991  * Only relevant on Set() operations.
5992  * Access: WO
5993  */
5994 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1);
5995 
5996 /* reg_pmaos_ee
5997  * Event update enable.
5998  * If this bit is set, event generation will be updated based on the e field.
5999  * Only relevant on Set operations.
6000  * Access: WO
6001  */
6002 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1);
6003 
6004 enum mlxsw_reg_pmaos_e {
6005 	MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT,
6006 	MLXSW_REG_PMAOS_E_GENERATE_EVENT,
6007 	MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT,
6008 };
6009 
6010 /* reg_pmaos_e
6011  * Event Generation on operational state change.
6012  * Access: RW
6013  */
6014 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2);
6015 
6016 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 slot_index, u8 module)
6017 {
6018 	MLXSW_REG_ZERO(pmaos, payload);
6019 	mlxsw_reg_pmaos_slot_index_set(payload, slot_index);
6020 	mlxsw_reg_pmaos_module_set(payload, module);
6021 }
6022 
6023 /* PPLR - Port Physical Loopback Register
6024  * --------------------------------------
6025  * This register allows configuration of the port's loopback mode.
6026  */
6027 #define MLXSW_REG_PPLR_ID 0x5018
6028 #define MLXSW_REG_PPLR_LEN 0x8
6029 
6030 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN);
6031 
6032 /* reg_pplr_local_port
6033  * Local port number.
6034  * Access: Index
6035  */
6036 MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12);
6037 
6038 /* Phy local loopback. When set the port's egress traffic is looped back
6039  * to the receiver and the port transmitter is disabled.
6040  */
6041 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
6042 
6043 /* reg_pplr_lb_en
6044  * Loopback enable.
6045  * Access: RW
6046  */
6047 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
6048 
6049 static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port,
6050 				       bool phy_local)
6051 {
6052 	MLXSW_REG_ZERO(pplr, payload);
6053 	mlxsw_reg_pplr_local_port_set(payload, local_port);
6054 	mlxsw_reg_pplr_lb_en_set(payload,
6055 				 phy_local ?
6056 				 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
6057 }
6058 
6059 /* PMTDB - Port Module To local DataBase Register
6060  * ----------------------------------------------
6061  * The PMTDB register allows to query the possible module<->local port
6062  * mapping than can be used in PMLP. It does not represent the actual/current
6063  * mapping of the local to module. Actual mapping is only defined by PMLP.
6064  */
6065 #define MLXSW_REG_PMTDB_ID 0x501A
6066 #define MLXSW_REG_PMTDB_LEN 0x40
6067 
6068 MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN);
6069 
6070 /* reg_pmtdb_slot_index
6071  * Slot index (0: Main board).
6072  * Access: Index
6073  */
6074 MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4);
6075 
6076 /* reg_pmtdb_module
6077  * Module number.
6078  * Access: Index
6079  */
6080 MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8);
6081 
6082 /* reg_pmtdb_ports_width
6083  * Port's width
6084  * Access: Index
6085  */
6086 MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4);
6087 
6088 /* reg_pmtdb_num_ports
6089  * Number of ports in a single module (split/breakout)
6090  * Access: Index
6091  */
6092 MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4);
6093 
6094 enum mlxsw_reg_pmtdb_status {
6095 	MLXSW_REG_PMTDB_STATUS_SUCCESS,
6096 };
6097 
6098 /* reg_pmtdb_status
6099  * Status
6100  * Access: RO
6101  */
6102 MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4);
6103 
6104 /* reg_pmtdb_port_num
6105  * The local_port value which can be assigned to the module.
6106  * In case of more than one port, port<x> represent the /<x> port of
6107  * the module.
6108  * Access: RO
6109  */
6110 MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false);
6111 
6112 static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module,
6113 					u8 ports_width, u8 num_ports)
6114 {
6115 	MLXSW_REG_ZERO(pmtdb, payload);
6116 	mlxsw_reg_pmtdb_slot_index_set(payload, slot_index);
6117 	mlxsw_reg_pmtdb_module_set(payload, module);
6118 	mlxsw_reg_pmtdb_ports_width_set(payload, ports_width);
6119 	mlxsw_reg_pmtdb_num_ports_set(payload, num_ports);
6120 }
6121 
6122 /* PMECR - Ports Mapping Event Configuration Register
6123  * --------------------------------------------------
6124  * The PMECR register is used to enable/disable event triggering
6125  * in case of local port mapping change.
6126  */
6127 #define MLXSW_REG_PMECR_ID 0x501B
6128 #define MLXSW_REG_PMECR_LEN 0x20
6129 
6130 MLXSW_REG_DEFINE(pmecr, MLXSW_REG_PMECR_ID, MLXSW_REG_PMECR_LEN);
6131 
6132 /* reg_pmecr_local_port
6133  * Local port number.
6134  * Access: Index
6135  */
6136 MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12);
6137 
6138 /* reg_pmecr_ee
6139  * Event update enable. If this bit is set, event generation will be updated
6140  * based on the e field. Only relevant on Set operations.
6141  * Access: WO
6142  */
6143 MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1);
6144 
6145 /* reg_pmecr_eswi
6146  * Software ignore enable bit. If this bit is set, the value of swi is used.
6147  * If this bit is clear, the value of swi is ignored.
6148  * Only relevant on Set operations.
6149  * Access: WO
6150  */
6151 MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1);
6152 
6153 /* reg_pmecr_swi
6154  * Software ignore. If this bit is set, the device shouldn't generate events
6155  * in case of PMLP SET operation but only upon self local port mapping change
6156  * (if applicable according to e configuration). This is supplementary
6157  * configuration on top of e value.
6158  * Access: RW
6159  */
6160 MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1);
6161 
6162 enum mlxsw_reg_pmecr_e {
6163 	MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT,
6164 	MLXSW_REG_PMECR_E_GENERATE_EVENT,
6165 	MLXSW_REG_PMECR_E_GENERATE_SINGLE_EVENT,
6166 };
6167 
6168 /* reg_pmecr_e
6169  * Event generation on local port mapping change.
6170  * Access: RW
6171  */
6172 MLXSW_ITEM32(reg, pmecr, e, 0x04, 0, 2);
6173 
6174 static inline void mlxsw_reg_pmecr_pack(char *payload, u16 local_port,
6175 					enum mlxsw_reg_pmecr_e e)
6176 {
6177 	MLXSW_REG_ZERO(pmecr, payload);
6178 	mlxsw_reg_pmecr_local_port_set(payload, local_port);
6179 	mlxsw_reg_pmecr_e_set(payload, e);
6180 	mlxsw_reg_pmecr_ee_set(payload, true);
6181 	mlxsw_reg_pmecr_swi_set(payload, true);
6182 	mlxsw_reg_pmecr_eswi_set(payload, true);
6183 }
6184 
6185 /* PMPE - Port Module Plug/Unplug Event Register
6186  * ---------------------------------------------
6187  * This register reports any operational status change of a module.
6188  * A change in the module’s state will generate an event only if the change
6189  * happens after arming the event mechanism. Any changes to the module state
6190  * while the event mechanism is not armed will not be reported. Software can
6191  * query the PMPE register for module status.
6192  */
6193 #define MLXSW_REG_PMPE_ID 0x5024
6194 #define MLXSW_REG_PMPE_LEN 0x10
6195 
6196 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN);
6197 
6198 /* reg_pmpe_slot_index
6199  * Slot index.
6200  * Access: Index
6201  */
6202 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4);
6203 
6204 /* reg_pmpe_module
6205  * Module number.
6206  * Access: Index
6207  */
6208 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8);
6209 
6210 enum mlxsw_reg_pmpe_module_status {
6211 	MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1,
6212 	MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED,
6213 	MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR,
6214 	MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED,
6215 };
6216 
6217 /* reg_pmpe_module_status
6218  * Module status.
6219  * Access: RO
6220  */
6221 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4);
6222 
6223 /* reg_pmpe_error_type
6224  * Module error details.
6225  * Access: RO
6226  */
6227 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4);
6228 
6229 /* PDDR - Port Diagnostics Database Register
6230  * -----------------------------------------
6231  * The PDDR enables to read the Phy debug database
6232  */
6233 #define MLXSW_REG_PDDR_ID 0x5031
6234 #define MLXSW_REG_PDDR_LEN 0x100
6235 
6236 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN);
6237 
6238 /* reg_pddr_local_port
6239  * Local port number.
6240  * Access: Index
6241  */
6242 MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12);
6243 
6244 enum mlxsw_reg_pddr_page_select {
6245 	MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1,
6246 };
6247 
6248 /* reg_pddr_page_select
6249  * Page select index.
6250  * Access: Index
6251  */
6252 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8);
6253 
6254 enum mlxsw_reg_pddr_trblsh_group_opcode {
6255 	/* Monitor opcodes */
6256 	MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR,
6257 };
6258 
6259 /* reg_pddr_group_opcode
6260  * Group selector.
6261  * Access: Index
6262  */
6263 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16);
6264 
6265 /* reg_pddr_status_opcode
6266  * Group selector.
6267  * Access: RO
6268  */
6269 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16);
6270 
6271 static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port,
6272 				       u8 page_select)
6273 {
6274 	MLXSW_REG_ZERO(pddr, payload);
6275 	mlxsw_reg_pddr_local_port_set(payload, local_port);
6276 	mlxsw_reg_pddr_page_select_set(payload, page_select);
6277 }
6278 
6279 /* PMMP - Port Module Memory Map Properties Register
6280  * -------------------------------------------------
6281  * The PMMP register allows to override the module memory map advertisement.
6282  * The register can only be set when the module is disabled by PMAOS register.
6283  */
6284 #define MLXSW_REG_PMMP_ID 0x5044
6285 #define MLXSW_REG_PMMP_LEN 0x2C
6286 
6287 MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN);
6288 
6289 /* reg_pmmp_module
6290  * Module number.
6291  * Access: Index
6292  */
6293 MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8);
6294 
6295 /* reg_pmmp_slot_index
6296  * Slot index.
6297  * Access: Index
6298  */
6299 MLXSW_ITEM32(reg, pmmp, slot_index, 0x00, 24, 4);
6300 
6301 /* reg_pmmp_sticky
6302  * When set, will keep eeprom_override values after plug-out event.
6303  * Access: OP
6304  */
6305 MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1);
6306 
6307 /* reg_pmmp_eeprom_override_mask
6308  * Write mask bit (negative polarity).
6309  * 0 - Allow write
6310  * 1 - Ignore write
6311  * On write, indicates which of the bits from eeprom_override field are
6312  * updated.
6313  * Access: WO
6314  */
6315 MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16);
6316 
6317 enum {
6318 	/* Set module to low power mode */
6319 	MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8),
6320 };
6321 
6322 /* reg_pmmp_eeprom_override
6323  * Override / ignore EEPROM advertisement properties bitmask
6324  * Access: RW
6325  */
6326 MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16);
6327 
6328 static inline void mlxsw_reg_pmmp_pack(char *payload, u8 slot_index, u8 module)
6329 {
6330 	MLXSW_REG_ZERO(pmmp, payload);
6331 	mlxsw_reg_pmmp_slot_index_set(payload, slot_index);
6332 	mlxsw_reg_pmmp_module_set(payload, module);
6333 }
6334 
6335 /* PLLP - Port Local port to Label Port mapping Register
6336  * -----------------------------------------------------
6337  * The PLLP register returns the mapping from Local Port into Label Port.
6338  */
6339 #define MLXSW_REG_PLLP_ID 0x504A
6340 #define MLXSW_REG_PLLP_LEN 0x10
6341 
6342 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN);
6343 
6344 /* reg_pllp_local_port
6345  * Local port number.
6346  * Access: Index
6347  */
6348 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12);
6349 
6350 /* reg_pllp_label_port
6351  * Front panel label of the port.
6352  * Access: RO
6353  */
6354 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8);
6355 
6356 /* reg_pllp_split_num
6357  * Label split mapping for local_port.
6358  * Access: RO
6359  */
6360 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4);
6361 
6362 /* reg_pllp_slot_index
6363  * Slot index (0: Main board).
6364  * Access: RO
6365  */
6366 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4);
6367 
6368 static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port)
6369 {
6370 	MLXSW_REG_ZERO(pllp, payload);
6371 	mlxsw_reg_pllp_local_port_set(payload, local_port);
6372 }
6373 
6374 static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port,
6375 					 u8 *split_num, u8 *slot_index)
6376 {
6377 	*label_port = mlxsw_reg_pllp_label_port_get(payload);
6378 	*split_num = mlxsw_reg_pllp_split_num_get(payload);
6379 	*slot_index = mlxsw_reg_pllp_slot_index_get(payload);
6380 }
6381 
6382 /* PMTM - Port Module Type Mapping Register
6383  * ----------------------------------------
6384  * The PMTM register allows query or configuration of module types.
6385  * The register can only be set when the module is disabled by PMAOS register
6386  */
6387 #define MLXSW_REG_PMTM_ID 0x5067
6388 #define MLXSW_REG_PMTM_LEN 0x10
6389 
6390 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN);
6391 
6392 /* reg_pmtm_slot_index
6393  * Slot index.
6394  * Access: Index
6395  */
6396 MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4);
6397 
6398 /* reg_pmtm_module
6399  * Module number.
6400  * Access: Index
6401  */
6402 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8);
6403 
6404 enum mlxsw_reg_pmtm_module_type {
6405 	MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0,
6406 	MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1,
6407 	MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2,
6408 	MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4,
6409 	MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8,
6410 	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10,
6411 	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11,
6412 	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12,
6413 	MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14,
6414 	MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15,
6415 	MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16,
6416 	MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17,
6417 	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18,
6418 	MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19,
6419 };
6420 
6421 /* reg_pmtm_module_type
6422  * Module type.
6423  * Access: RW
6424  */
6425 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5);
6426 
6427 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module)
6428 {
6429 	MLXSW_REG_ZERO(pmtm, payload);
6430 	mlxsw_reg_pmtm_slot_index_set(payload, slot_index);
6431 	mlxsw_reg_pmtm_module_set(payload, module);
6432 }
6433 
6434 /* HTGT - Host Trap Group Table
6435  * ----------------------------
6436  * Configures the properties for forwarding to CPU.
6437  */
6438 #define MLXSW_REG_HTGT_ID 0x7002
6439 #define MLXSW_REG_HTGT_LEN 0x20
6440 
6441 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
6442 
6443 /* reg_htgt_swid
6444  * Switch partition ID.
6445  * Access: Index
6446  */
6447 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
6448 
6449 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0	/* For locally attached CPU */
6450 
6451 /* reg_htgt_type
6452  * CPU path type.
6453  * Access: RW
6454  */
6455 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
6456 
6457 enum mlxsw_reg_htgt_trap_group {
6458 	MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
6459 	MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT,
6460 	MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
6461 	MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
6462 	MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
6463 	MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING,
6464 	MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
6465 	MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
6466 	MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
6467 	MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
6468 	MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY,
6469 	MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
6470 	MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE,
6471 	MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
6472 	MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
6473 	MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
6474 	MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6,
6475 	MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,
6476 	MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0,
6477 	MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1,
6478 	MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP,
6479 	MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE,
6480 	MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING,
6481 	MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS,
6482 	MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD,
6483 	MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY,
6484 	MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS,
6485 	MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS,
6486 	MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS,
6487 	MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS,
6488 	MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS,
6489 	MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS,
6490 	MLXSW_REG_HTGT_TRAP_GROUP_SP_EAPOL,
6491 
6492 	__MLXSW_REG_HTGT_TRAP_GROUP_MAX,
6493 	MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1
6494 };
6495 
6496 /* reg_htgt_trap_group
6497  * Trap group number. User defined number specifying which trap groups
6498  * should be forwarded to the CPU. The mapping between trap IDs and trap
6499  * groups is configured using HPKT register.
6500  * Access: Index
6501  */
6502 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
6503 
6504 enum {
6505 	MLXSW_REG_HTGT_POLICER_DISABLE,
6506 	MLXSW_REG_HTGT_POLICER_ENABLE,
6507 };
6508 
6509 /* reg_htgt_pide
6510  * Enable policer ID specified using 'pid' field.
6511  * Access: RW
6512  */
6513 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
6514 
6515 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff
6516 
6517 /* reg_htgt_pid
6518  * Policer ID for the trap group.
6519  * Access: RW
6520  */
6521 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
6522 
6523 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
6524 
6525 /* reg_htgt_mirror_action
6526  * Mirror action to use.
6527  * 0 - Trap to CPU.
6528  * 1 - Trap to CPU and mirror to a mirroring agent.
6529  * 2 - Mirror to a mirroring agent and do not trap to CPU.
6530  * Access: RW
6531  *
6532  * Note: Mirroring to a mirroring agent is only supported in Spectrum.
6533  */
6534 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
6535 
6536 /* reg_htgt_mirroring_agent
6537  * Mirroring agent.
6538  * Access: RW
6539  */
6540 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
6541 
6542 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
6543 
6544 /* reg_htgt_priority
6545  * Trap group priority.
6546  * In case a packet matches multiple classification rules, the packet will
6547  * only be trapped once, based on the trap ID associated with the group (via
6548  * register HPKT) with the highest priority.
6549  * Supported values are 0-7, with 7 represnting the highest priority.
6550  * Access: RW
6551  *
6552  * Note: In SwitchX-2 this field is ignored and the priority value is replaced
6553  * by the 'trap_group' field.
6554  */
6555 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
6556 
6557 #define MLXSW_REG_HTGT_DEFAULT_TC 7
6558 
6559 /* reg_htgt_local_path_cpu_tclass
6560  * CPU ingress traffic class for the trap group.
6561  * Access: RW
6562  */
6563 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
6564 
6565 enum mlxsw_reg_htgt_local_path_rdq {
6566 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
6567 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
6568 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
6569 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
6570 };
6571 /* reg_htgt_local_path_rdq
6572  * Receive descriptor queue (RDQ) to use for the trap group.
6573  * Access: RW
6574  */
6575 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
6576 
6577 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
6578 				       u8 priority, u8 tc)
6579 {
6580 	MLXSW_REG_ZERO(htgt, payload);
6581 
6582 	if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
6583 		mlxsw_reg_htgt_pide_set(payload,
6584 					MLXSW_REG_HTGT_POLICER_DISABLE);
6585 	} else {
6586 		mlxsw_reg_htgt_pide_set(payload,
6587 					MLXSW_REG_HTGT_POLICER_ENABLE);
6588 		mlxsw_reg_htgt_pid_set(payload, policer_id);
6589 	}
6590 
6591 	mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
6592 	mlxsw_reg_htgt_trap_group_set(payload, group);
6593 	mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
6594 	mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
6595 	mlxsw_reg_htgt_priority_set(payload, priority);
6596 	mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
6597 	mlxsw_reg_htgt_local_path_rdq_set(payload, group);
6598 }
6599 
6600 /* HPKT - Host Packet Trap
6601  * -----------------------
6602  * Configures trap IDs inside trap groups.
6603  */
6604 #define MLXSW_REG_HPKT_ID 0x7003
6605 #define MLXSW_REG_HPKT_LEN 0x10
6606 
6607 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
6608 
6609 enum {
6610 	MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
6611 	MLXSW_REG_HPKT_ACK_REQUIRED,
6612 };
6613 
6614 /* reg_hpkt_ack
6615  * Require acknowledgements from the host for events.
6616  * If set, then the device will wait for the event it sent to be acknowledged
6617  * by the host. This option is only relevant for event trap IDs.
6618  * Access: RW
6619  *
6620  * Note: Currently not supported by firmware.
6621  */
6622 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
6623 
6624 enum mlxsw_reg_hpkt_action {
6625 	MLXSW_REG_HPKT_ACTION_FORWARD,
6626 	MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
6627 	MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
6628 	MLXSW_REG_HPKT_ACTION_DISCARD,
6629 	MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
6630 	MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
6631 	MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU,
6632 	MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15,
6633 };
6634 
6635 /* reg_hpkt_action
6636  * Action to perform on packet when trapped.
6637  * 0 - No action. Forward to CPU based on switching rules.
6638  * 1 - Trap to CPU (CPU receives sole copy).
6639  * 2 - Mirror to CPU (CPU receives a replica of the packet).
6640  * 3 - Discard.
6641  * 4 - Soft discard (allow other traps to act on the packet).
6642  * 5 - Trap and soft discard (allow other traps to overwrite this trap).
6643  * 6 - Trap to CPU (CPU receives sole copy) and count it as error.
6644  * 15 - Restore the firmware's default action.
6645  * Access: RW
6646  *
6647  * Note: Must be set to 0 (forward) for event trap IDs, as they are already
6648  * addressed to the CPU.
6649  */
6650 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
6651 
6652 /* reg_hpkt_trap_group
6653  * Trap group to associate the trap with.
6654  * Access: RW
6655  */
6656 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
6657 
6658 /* reg_hpkt_trap_id
6659  * Trap ID.
6660  * Access: Index
6661  *
6662  * Note: A trap ID can only be associated with a single trap group. The device
6663  * will associate the trap ID with the last trap group configured.
6664  */
6665 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10);
6666 
6667 enum {
6668 	MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
6669 	MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
6670 	MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
6671 };
6672 
6673 /* reg_hpkt_ctrl
6674  * Configure dedicated buffer resources for control packets.
6675  * Ignored by SwitchX-2.
6676  * 0 - Keep factory defaults.
6677  * 1 - Do not use control buffer for this trap ID.
6678  * 2 - Use control buffer for this trap ID.
6679  * Access: RW
6680  */
6681 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
6682 
6683 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
6684 				       enum mlxsw_reg_htgt_trap_group trap_group,
6685 				       bool is_ctrl)
6686 {
6687 	MLXSW_REG_ZERO(hpkt, payload);
6688 	mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
6689 	mlxsw_reg_hpkt_action_set(payload, action);
6690 	mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
6691 	mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
6692 	mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
6693 				MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
6694 				MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
6695 }
6696 
6697 /* RGCR - Router General Configuration Register
6698  * --------------------------------------------
6699  * The register is used for setting up the router configuration.
6700  */
6701 #define MLXSW_REG_RGCR_ID 0x8001
6702 #define MLXSW_REG_RGCR_LEN 0x28
6703 
6704 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
6705 
6706 /* reg_rgcr_ipv4_en
6707  * IPv4 router enable.
6708  * Access: RW
6709  */
6710 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
6711 
6712 /* reg_rgcr_ipv6_en
6713  * IPv6 router enable.
6714  * Access: RW
6715  */
6716 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
6717 
6718 /* reg_rgcr_max_router_interfaces
6719  * Defines the maximum number of active router interfaces for all virtual
6720  * routers.
6721  * Access: RW
6722  */
6723 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
6724 
6725 /* reg_rgcr_usp
6726  * Update switch priority and packet color.
6727  * 0 - Preserve the value of Switch Priority and packet color.
6728  * 1 - Recalculate the value of Switch Priority and packet color.
6729  * Access: RW
6730  *
6731  * Note: Not supported by SwitchX and SwitchX-2.
6732  */
6733 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
6734 
6735 /* reg_rgcr_pcp_rw
6736  * Indicates how to handle the pcp_rewrite_en value:
6737  * 0 - Preserve the value of pcp_rewrite_en.
6738  * 2 - Disable PCP rewrite.
6739  * 3 - Enable PCP rewrite.
6740  * Access: RW
6741  *
6742  * Note: Not supported by SwitchX and SwitchX-2.
6743  */
6744 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
6745 
6746 /* reg_rgcr_activity_dis
6747  * Activity disable:
6748  * 0 - Activity will be set when an entry is hit (default).
6749  * 1 - Activity will not be set when an entry is hit.
6750  *
6751  * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
6752  * (RALUE).
6753  * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
6754  * Entry (RAUHT).
6755  * Bits 2:7 are reserved.
6756  * Access: RW
6757  *
6758  * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
6759  */
6760 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
6761 
6762 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
6763 				       bool ipv6_en)
6764 {
6765 	MLXSW_REG_ZERO(rgcr, payload);
6766 	mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
6767 	mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
6768 }
6769 
6770 /* RITR - Router Interface Table Register
6771  * --------------------------------------
6772  * The register is used to configure the router interface table.
6773  */
6774 #define MLXSW_REG_RITR_ID 0x8002
6775 #define MLXSW_REG_RITR_LEN 0x40
6776 
6777 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
6778 
6779 /* reg_ritr_enable
6780  * Enables routing on the router interface.
6781  * Access: RW
6782  */
6783 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
6784 
6785 /* reg_ritr_ipv4
6786  * IPv4 routing enable. Enables routing of IPv4 traffic on the router
6787  * interface.
6788  * Access: RW
6789  */
6790 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
6791 
6792 /* reg_ritr_ipv6
6793  * IPv6 routing enable. Enables routing of IPv6 traffic on the router
6794  * interface.
6795  * Access: RW
6796  */
6797 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
6798 
6799 /* reg_ritr_ipv4_mc
6800  * IPv4 multicast routing enable.
6801  * Access: RW
6802  */
6803 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
6804 
6805 /* reg_ritr_ipv6_mc
6806  * IPv6 multicast routing enable.
6807  * Access: RW
6808  */
6809 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
6810 
6811 enum mlxsw_reg_ritr_if_type {
6812 	/* VLAN interface. */
6813 	MLXSW_REG_RITR_VLAN_IF,
6814 	/* FID interface. */
6815 	MLXSW_REG_RITR_FID_IF,
6816 	/* Sub-port interface. */
6817 	MLXSW_REG_RITR_SP_IF,
6818 	/* Loopback Interface. */
6819 	MLXSW_REG_RITR_LOOPBACK_IF,
6820 };
6821 
6822 /* reg_ritr_type
6823  * Router interface type as per enum mlxsw_reg_ritr_if_type.
6824  * Access: RW
6825  */
6826 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
6827 
6828 enum {
6829 	MLXSW_REG_RITR_RIF_CREATE,
6830 	MLXSW_REG_RITR_RIF_DEL,
6831 };
6832 
6833 /* reg_ritr_op
6834  * Opcode:
6835  * 0 - Create or edit RIF.
6836  * 1 - Delete RIF.
6837  * Reserved for SwitchX-2. For Spectrum, editing of interface properties
6838  * is not supported. An interface must be deleted and re-created in order
6839  * to update properties.
6840  * Access: WO
6841  */
6842 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
6843 
6844 /* reg_ritr_rif
6845  * Router interface index. A pointer to the Router Interface Table.
6846  * Access: Index
6847  */
6848 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
6849 
6850 /* reg_ritr_ipv4_fe
6851  * IPv4 Forwarding Enable.
6852  * Enables routing of IPv4 traffic on the router interface. When disabled,
6853  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
6854  * Not supported in SwitchX-2.
6855  * Access: RW
6856  */
6857 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
6858 
6859 /* reg_ritr_ipv6_fe
6860  * IPv6 Forwarding Enable.
6861  * Enables routing of IPv6 traffic on the router interface. When disabled,
6862  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
6863  * Not supported in SwitchX-2.
6864  * Access: RW
6865  */
6866 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
6867 
6868 /* reg_ritr_ipv4_mc_fe
6869  * IPv4 Multicast Forwarding Enable.
6870  * When disabled, forwarding is blocked but local traffic (traps and IP to me)
6871  * will be enabled.
6872  * Access: RW
6873  */
6874 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
6875 
6876 /* reg_ritr_ipv6_mc_fe
6877  * IPv6 Multicast Forwarding Enable.
6878  * When disabled, forwarding is blocked but local traffic (traps and IP to me)
6879  * will be enabled.
6880  * Access: RW
6881  */
6882 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
6883 
6884 /* reg_ritr_lb_en
6885  * Loop-back filter enable for unicast packets.
6886  * If the flag is set then loop-back filter for unicast packets is
6887  * implemented on the RIF. Multicast packets are always subject to
6888  * loop-back filtering.
6889  * Access: RW
6890  */
6891 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
6892 
6893 /* reg_ritr_virtual_router
6894  * Virtual router ID associated with the router interface.
6895  * Access: RW
6896  */
6897 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
6898 
6899 /* reg_ritr_mtu
6900  * Router interface MTU.
6901  * Access: RW
6902  */
6903 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
6904 
6905 /* reg_ritr_if_swid
6906  * Switch partition ID.
6907  * Access: RW
6908  */
6909 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
6910 
6911 /* reg_ritr_if_mac_profile_id
6912  * MAC msb profile ID.
6913  * Access: RW
6914  */
6915 MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4);
6916 
6917 /* reg_ritr_if_mac
6918  * Router interface MAC address.
6919  * In Spectrum, all MAC addresses must have the same 38 MSBits.
6920  * Access: RW
6921  */
6922 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
6923 
6924 /* reg_ritr_if_vrrp_id_ipv6
6925  * VRRP ID for IPv6
6926  * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
6927  * Access: RW
6928  */
6929 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
6930 
6931 /* reg_ritr_if_vrrp_id_ipv4
6932  * VRRP ID for IPv4
6933  * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
6934  * Access: RW
6935  */
6936 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
6937 
6938 /* VLAN Interface */
6939 
6940 /* reg_ritr_vlan_if_vlan_id
6941  * VLAN ID.
6942  * Access: RW
6943  */
6944 MLXSW_ITEM32(reg, ritr, vlan_if_vlan_id, 0x08, 0, 12);
6945 
6946 /* reg_ritr_vlan_if_efid
6947  * Egress FID.
6948  * Used to connect the RIF to a bridge.
6949  * Access: RW
6950  *
6951  * Note: Reserved when legacy bridge model is used and on Spectrum-1.
6952  */
6953 MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16);
6954 
6955 /* FID Interface */
6956 
6957 /* reg_ritr_fid_if_fid
6958  * Filtering ID. Used to connect a bridge to the router.
6959  * When legacy bridge model is used, only FIDs from the vFID range are
6960  * supported. When unified bridge model is used, this is the egress FID for
6961  * router to bridge.
6962  * Access: RW
6963  */
6964 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
6965 
6966 /* Sub-port Interface */
6967 
6968 /* reg_ritr_sp_if_lag
6969  * LAG indication. When this bit is set the system_port field holds the
6970  * LAG identifier.
6971  * Access: RW
6972  */
6973 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
6974 
6975 /* reg_ritr_sp_system_port
6976  * Port unique indentifier. When lag bit is set, this field holds the
6977  * lag_id in bits 0:9.
6978  * Access: RW
6979  */
6980 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
6981 
6982 /* reg_ritr_sp_if_efid
6983  * Egress filtering ID.
6984  * Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or
6985  * the VID.
6986  * Access: RW
6987  *
6988  * Note: Reserved when legacy bridge model is used.
6989  */
6990 MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16);
6991 
6992 /* reg_ritr_sp_if_vid
6993  * VLAN ID.
6994  * Access: RW
6995  */
6996 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
6997 
6998 /* Loopback Interface */
6999 
7000 enum mlxsw_reg_ritr_loopback_protocol {
7001 	/* IPinIP IPv4 underlay Unicast */
7002 	MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
7003 	/* IPinIP IPv6 underlay Unicast */
7004 	MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
7005 	/* IPinIP generic - used for Spectrum-2 underlay RIF */
7006 	MLXSW_REG_RITR_LOOPBACK_GENERIC,
7007 };
7008 
7009 /* reg_ritr_loopback_protocol
7010  * Access: RW
7011  */
7012 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
7013 
7014 enum mlxsw_reg_ritr_loopback_ipip_type {
7015 	/* Tunnel is IPinIP. */
7016 	MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
7017 	/* Tunnel is GRE, no key. */
7018 	MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
7019 	/* Tunnel is GRE, with a key. */
7020 	MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
7021 };
7022 
7023 /* reg_ritr_loopback_ipip_type
7024  * Encapsulation type.
7025  * Access: RW
7026  */
7027 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
7028 
7029 enum mlxsw_reg_ritr_loopback_ipip_options {
7030 	/* The key is defined by gre_key. */
7031 	MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
7032 };
7033 
7034 /* reg_ritr_loopback_ipip_options
7035  * Access: RW
7036  */
7037 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
7038 
7039 /* reg_ritr_loopback_ipip_uvr
7040  * Underlay Virtual Router ID.
7041  * Range is 0..cap_max_virtual_routers-1.
7042  * Reserved for Spectrum-2.
7043  * Access: RW
7044  */
7045 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
7046 
7047 /* reg_ritr_loopback_ipip_underlay_rif
7048  * Underlay ingress router interface.
7049  * Reserved for Spectrum.
7050  * Access: RW
7051  */
7052 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16);
7053 
7054 /* reg_ritr_loopback_ipip_usip*
7055  * Encapsulation Underlay source IP.
7056  * Access: RW
7057  */
7058 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
7059 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
7060 
7061 /* reg_ritr_loopback_ipip_gre_key
7062  * GRE Key.
7063  * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP.
7064  * Access: RW
7065  */
7066 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
7067 
7068 /* Shared between ingress/egress */
7069 enum mlxsw_reg_ritr_counter_set_type {
7070 	/* No Count. */
7071 	MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
7072 	/* Basic. Used for router interfaces, counting the following:
7073 	 *	- Error and Discard counters.
7074 	 *	- Unicast, Multicast and Broadcast counters. Sharing the
7075 	 *	  same set of counters for the different type of traffic
7076 	 *	  (IPv4, IPv6 and mpls).
7077 	 */
7078 	MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
7079 };
7080 
7081 /* reg_ritr_ingress_counter_index
7082  * Counter Index for flow counter.
7083  * Access: RW
7084  */
7085 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
7086 
7087 /* reg_ritr_ingress_counter_set_type
7088  * Igress Counter Set Type for router interface counter.
7089  * Access: RW
7090  */
7091 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
7092 
7093 /* reg_ritr_egress_counter_index
7094  * Counter Index for flow counter.
7095  * Access: RW
7096  */
7097 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
7098 
7099 /* reg_ritr_egress_counter_set_type
7100  * Egress Counter Set Type for router interface counter.
7101  * Access: RW
7102  */
7103 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
7104 
7105 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
7106 					       bool enable, bool egress)
7107 {
7108 	enum mlxsw_reg_ritr_counter_set_type set_type;
7109 
7110 	if (enable)
7111 		set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
7112 	else
7113 		set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
7114 
7115 	if (egress) {
7116 		mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
7117 		mlxsw_reg_ritr_egress_counter_index_set(payload, index);
7118 	} else {
7119 		mlxsw_reg_ritr_ingress_counter_set_type_set(payload, set_type);
7120 		mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
7121 	}
7122 }
7123 
7124 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
7125 {
7126 	MLXSW_REG_ZERO(ritr, payload);
7127 	mlxsw_reg_ritr_rif_set(payload, rif);
7128 }
7129 
7130 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
7131 					     u16 system_port, u16 efid, u16 vid)
7132 {
7133 	mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
7134 	mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
7135 	mlxsw_reg_ritr_sp_if_efid_set(payload, efid);
7136 	mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
7137 }
7138 
7139 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
7140 				       enum mlxsw_reg_ritr_if_type type,
7141 				       u16 rif, u16 vr_id, u16 mtu)
7142 {
7143 	bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
7144 
7145 	MLXSW_REG_ZERO(ritr, payload);
7146 	mlxsw_reg_ritr_enable_set(payload, enable);
7147 	mlxsw_reg_ritr_ipv4_set(payload, 1);
7148 	mlxsw_reg_ritr_ipv6_set(payload, 1);
7149 	mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
7150 	mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
7151 	mlxsw_reg_ritr_type_set(payload, type);
7152 	mlxsw_reg_ritr_op_set(payload, op);
7153 	mlxsw_reg_ritr_rif_set(payload, rif);
7154 	mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
7155 	mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
7156 	mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
7157 	mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
7158 	mlxsw_reg_ritr_lb_en_set(payload, 1);
7159 	mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
7160 	mlxsw_reg_ritr_mtu_set(payload, mtu);
7161 }
7162 
7163 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
7164 {
7165 	mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
7166 }
7167 
7168 static inline void
7169 mlxsw_reg_ritr_vlan_if_pack(char *payload, bool enable, u16 rif, u16 vr_id,
7170 			    u16 mtu, const char *mac, u8 mac_profile_id,
7171 			    u16 vlan_id, u16 efid)
7172 {
7173 	enum mlxsw_reg_ritr_if_type type = MLXSW_REG_RITR_VLAN_IF;
7174 
7175 	mlxsw_reg_ritr_pack(payload, enable, type, rif, vr_id, mtu);
7176 	mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
7177 	mlxsw_reg_ritr_if_mac_profile_id_set(payload, mac_profile_id);
7178 	mlxsw_reg_ritr_vlan_if_vlan_id_set(payload, vlan_id);
7179 	mlxsw_reg_ritr_vlan_if_efid_set(payload, efid);
7180 }
7181 
7182 static inline void
7183 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
7184 			    enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
7185 			    enum mlxsw_reg_ritr_loopback_ipip_options options,
7186 			    u16 uvr_id, u16 underlay_rif, u32 gre_key)
7187 {
7188 	mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
7189 	mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
7190 	mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
7191 	mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif);
7192 	mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
7193 }
7194 
7195 static inline void
7196 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
7197 			    enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
7198 			    enum mlxsw_reg_ritr_loopback_ipip_options options,
7199 			    u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key)
7200 {
7201 	mlxsw_reg_ritr_loopback_protocol_set(payload,
7202 				    MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
7203 	mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
7204 						 uvr_id, underlay_rif, gre_key);
7205 	mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
7206 }
7207 
7208 static inline void
7209 mlxsw_reg_ritr_loopback_ipip6_pack(char *payload,
7210 				   enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
7211 				   enum mlxsw_reg_ritr_loopback_ipip_options options,
7212 				   u16 uvr_id, u16 underlay_rif,
7213 				   const struct in6_addr *usip, u32 gre_key)
7214 {
7215 	enum mlxsw_reg_ritr_loopback_protocol protocol =
7216 		MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6;
7217 
7218 	mlxsw_reg_ritr_loopback_protocol_set(payload, protocol);
7219 	mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
7220 						 uvr_id, underlay_rif, gre_key);
7221 	mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload,
7222 						     (const char *)usip);
7223 }
7224 
7225 /* RTAR - Router TCAM Allocation Register
7226  * --------------------------------------
7227  * This register is used for allocation of regions in the TCAM table.
7228  */
7229 #define MLXSW_REG_RTAR_ID 0x8004
7230 #define MLXSW_REG_RTAR_LEN 0x20
7231 
7232 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
7233 
7234 enum mlxsw_reg_rtar_op {
7235 	MLXSW_REG_RTAR_OP_ALLOCATE,
7236 	MLXSW_REG_RTAR_OP_RESIZE,
7237 	MLXSW_REG_RTAR_OP_DEALLOCATE,
7238 };
7239 
7240 /* reg_rtar_op
7241  * Access: WO
7242  */
7243 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
7244 
7245 enum mlxsw_reg_rtar_key_type {
7246 	MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
7247 	MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
7248 };
7249 
7250 /* reg_rtar_key_type
7251  * TCAM key type for the region.
7252  * Access: WO
7253  */
7254 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
7255 
7256 /* reg_rtar_region_size
7257  * TCAM region size. When allocating/resizing this is the requested
7258  * size, the response is the actual size.
7259  * Note: Actual size may be larger than requested.
7260  * Reserved for op = Deallocate
7261  * Access: WO
7262  */
7263 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
7264 
7265 static inline void mlxsw_reg_rtar_pack(char *payload,
7266 				       enum mlxsw_reg_rtar_op op,
7267 				       enum mlxsw_reg_rtar_key_type key_type,
7268 				       u16 region_size)
7269 {
7270 	MLXSW_REG_ZERO(rtar, payload);
7271 	mlxsw_reg_rtar_op_set(payload, op);
7272 	mlxsw_reg_rtar_key_type_set(payload, key_type);
7273 	mlxsw_reg_rtar_region_size_set(payload, region_size);
7274 }
7275 
7276 /* RATR - Router Adjacency Table Register
7277  * --------------------------------------
7278  * The RATR register is used to configure the Router Adjacency (next-hop)
7279  * Table.
7280  */
7281 #define MLXSW_REG_RATR_ID 0x8008
7282 #define MLXSW_REG_RATR_LEN 0x2C
7283 
7284 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
7285 
7286 enum mlxsw_reg_ratr_op {
7287 	/* Read */
7288 	MLXSW_REG_RATR_OP_QUERY_READ = 0,
7289 	/* Read and clear activity */
7290 	MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
7291 	/* Write Adjacency entry */
7292 	MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
7293 	/* Write Adjacency entry only if the activity is cleared.
7294 	 * The write may not succeed if the activity is set. There is not
7295 	 * direct feedback if the write has succeeded or not, however
7296 	 * the get will reveal the actual entry (SW can compare the get
7297 	 * response to the set command).
7298 	 */
7299 	MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
7300 };
7301 
7302 /* reg_ratr_op
7303  * Note that Write operation may also be used for updating
7304  * counter_set_type and counter_index. In this case all other
7305  * fields must not be updated.
7306  * Access: OP
7307  */
7308 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
7309 
7310 /* reg_ratr_v
7311  * Valid bit. Indicates if the adjacency entry is valid.
7312  * Note: the device may need some time before reusing an invalidated
7313  * entry. During this time the entry can not be reused. It is
7314  * recommended to use another entry before reusing an invalidated
7315  * entry (e.g. software can put it at the end of the list for
7316  * reusing). Trying to access an invalidated entry not yet cleared
7317  * by the device results with failure indicating "Try Again" status.
7318  * When valid is '0' then egress_router_interface,trap_action,
7319  * adjacency_parameters and counters are reserved
7320  * Access: RW
7321  */
7322 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
7323 
7324 /* reg_ratr_a
7325  * Activity. Set for new entries. Set if a packet lookup has hit on
7326  * the specific entry. To clear the a bit, use "clear activity".
7327  * Access: RO
7328  */
7329 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
7330 
7331 enum mlxsw_reg_ratr_type {
7332 	/* Ethernet */
7333 	MLXSW_REG_RATR_TYPE_ETHERNET,
7334 	/* IPoIB Unicast without GRH.
7335 	 * Reserved for Spectrum.
7336 	 */
7337 	MLXSW_REG_RATR_TYPE_IPOIB_UC,
7338 	/* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast
7339 	 * adjacency).
7340 	 * Reserved for Spectrum.
7341 	 */
7342 	MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
7343 	/* IPoIB Multicast.
7344 	 * Reserved for Spectrum.
7345 	 */
7346 	MLXSW_REG_RATR_TYPE_IPOIB_MC,
7347 	/* MPLS.
7348 	 * Reserved for SwitchX/-2.
7349 	 */
7350 	MLXSW_REG_RATR_TYPE_MPLS,
7351 	/* IPinIP Encap.
7352 	 * Reserved for SwitchX/-2.
7353 	 */
7354 	MLXSW_REG_RATR_TYPE_IPIP,
7355 };
7356 
7357 /* reg_ratr_type
7358  * Adjacency entry type.
7359  * Access: RW
7360  */
7361 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
7362 
7363 /* reg_ratr_adjacency_index_low
7364  * Bits 15:0 of index into the adjacency table.
7365  * For SwitchX and SwitchX-2, the adjacency table is linear and
7366  * used for adjacency entries only.
7367  * For Spectrum, the index is to the KVD linear.
7368  * Access: Index
7369  */
7370 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
7371 
7372 /* reg_ratr_egress_router_interface
7373  * Range is 0 .. cap_max_router_interfaces - 1
7374  * Access: RW
7375  */
7376 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
7377 
7378 enum mlxsw_reg_ratr_trap_action {
7379 	MLXSW_REG_RATR_TRAP_ACTION_NOP,
7380 	MLXSW_REG_RATR_TRAP_ACTION_TRAP,
7381 	MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
7382 	MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
7383 	MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
7384 };
7385 
7386 /* reg_ratr_trap_action
7387  * see mlxsw_reg_ratr_trap_action
7388  * Access: RW
7389  */
7390 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
7391 
7392 /* reg_ratr_adjacency_index_high
7393  * Bits 23:16 of the adjacency_index.
7394  * Access: Index
7395  */
7396 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
7397 
7398 enum mlxsw_reg_ratr_trap_id {
7399 	MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
7400 	MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
7401 };
7402 
7403 /* reg_ratr_trap_id
7404  * Trap ID to be reported to CPU.
7405  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
7406  * For trap_action of NOP, MIRROR and DISCARD_ERROR
7407  * Access: RW
7408  */
7409 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
7410 
7411 /* reg_ratr_eth_destination_mac
7412  * MAC address of the destination next-hop.
7413  * Access: RW
7414  */
7415 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
7416 
7417 enum mlxsw_reg_ratr_ipip_type {
7418 	/* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */
7419 	MLXSW_REG_RATR_IPIP_TYPE_IPV4,
7420 	/* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */
7421 	MLXSW_REG_RATR_IPIP_TYPE_IPV6,
7422 };
7423 
7424 /* reg_ratr_ipip_type
7425  * Underlay destination ip type.
7426  * Note: the type field must match the protocol of the router interface.
7427  * Access: RW
7428  */
7429 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
7430 
7431 /* reg_ratr_ipip_ipv4_udip
7432  * Underlay ipv4 dip.
7433  * Reserved when ipip_type is IPv6.
7434  * Access: RW
7435  */
7436 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
7437 
7438 /* reg_ratr_ipip_ipv6_ptr
7439  * Pointer to IPv6 underlay destination ip address.
7440  * For Spectrum: Pointer to KVD linear space.
7441  * Access: RW
7442  */
7443 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
7444 
7445 enum mlxsw_reg_flow_counter_set_type {
7446 	/* No count */
7447 	MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
7448 	/* Count packets and bytes */
7449 	MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
7450 	/* Count only packets */
7451 	MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
7452 };
7453 
7454 /* reg_ratr_counter_set_type
7455  * Counter set type for flow counters
7456  * Access: RW
7457  */
7458 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
7459 
7460 /* reg_ratr_counter_index
7461  * Counter index for flow counters
7462  * Access: RW
7463  */
7464 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
7465 
7466 static inline void
7467 mlxsw_reg_ratr_pack(char *payload,
7468 		    enum mlxsw_reg_ratr_op op, bool valid,
7469 		    enum mlxsw_reg_ratr_type type,
7470 		    u32 adjacency_index, u16 egress_rif)
7471 {
7472 	MLXSW_REG_ZERO(ratr, payload);
7473 	mlxsw_reg_ratr_op_set(payload, op);
7474 	mlxsw_reg_ratr_v_set(payload, valid);
7475 	mlxsw_reg_ratr_type_set(payload, type);
7476 	mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
7477 	mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
7478 	mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
7479 }
7480 
7481 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
7482 						 const char *dest_mac)
7483 {
7484 	mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
7485 }
7486 
7487 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
7488 {
7489 	mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
7490 	mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
7491 }
7492 
7493 static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr)
7494 {
7495 	mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6);
7496 	mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr);
7497 }
7498 
7499 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
7500 					       bool counter_enable)
7501 {
7502 	enum mlxsw_reg_flow_counter_set_type set_type;
7503 
7504 	if (counter_enable)
7505 		set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
7506 	else
7507 		set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
7508 
7509 	mlxsw_reg_ratr_counter_index_set(payload, counter_index);
7510 	mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
7511 }
7512 
7513 /* RDPM - Router DSCP to Priority Mapping
7514  * --------------------------------------
7515  * Controls the mapping from DSCP field to switch priority on routed packets
7516  */
7517 #define MLXSW_REG_RDPM_ID 0x8009
7518 #define MLXSW_REG_RDPM_BASE_LEN 0x00
7519 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
7520 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
7521 #define MLXSW_REG_RDPM_LEN 0x40
7522 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
7523 				   MLXSW_REG_RDPM_LEN - \
7524 				   MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
7525 
7526 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
7527 
7528 /* reg_dscp_entry_e
7529  * Enable update of the specific entry
7530  * Access: Index
7531  */
7532 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
7533 		    -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
7534 
7535 /* reg_dscp_entry_prio
7536  * Switch Priority
7537  * Access: RW
7538  */
7539 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
7540 		    -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
7541 
7542 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
7543 				       u8 prio)
7544 {
7545 	mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
7546 	mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
7547 }
7548 
7549 /* RICNT - Router Interface Counter Register
7550  * -----------------------------------------
7551  * The RICNT register retrieves per port performance counters
7552  */
7553 #define MLXSW_REG_RICNT_ID 0x800B
7554 #define MLXSW_REG_RICNT_LEN 0x100
7555 
7556 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
7557 
7558 /* reg_ricnt_counter_index
7559  * Counter index
7560  * Access: RW
7561  */
7562 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
7563 
7564 enum mlxsw_reg_ricnt_counter_set_type {
7565 	/* No Count. */
7566 	MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
7567 	/* Basic. Used for router interfaces, counting the following:
7568 	 *	- Error and Discard counters.
7569 	 *	- Unicast, Multicast and Broadcast counters. Sharing the
7570 	 *	  same set of counters for the different type of traffic
7571 	 *	  (IPv4, IPv6 and mpls).
7572 	 */
7573 	MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
7574 };
7575 
7576 /* reg_ricnt_counter_set_type
7577  * Counter Set Type for router interface counter
7578  * Access: RW
7579  */
7580 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
7581 
7582 enum mlxsw_reg_ricnt_opcode {
7583 	/* Nop. Supported only for read access*/
7584 	MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
7585 	/* Clear. Setting the clr bit will reset the counter value for
7586 	 * all counters of the specified Router Interface.
7587 	 */
7588 	MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
7589 };
7590 
7591 /* reg_ricnt_opcode
7592  * Opcode
7593  * Access: RW
7594  */
7595 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
7596 
7597 /* reg_ricnt_good_unicast_packets
7598  * good unicast packets.
7599  * Access: RW
7600  */
7601 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
7602 
7603 /* reg_ricnt_good_multicast_packets
7604  * good multicast packets.
7605  * Access: RW
7606  */
7607 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
7608 
7609 /* reg_ricnt_good_broadcast_packets
7610  * good broadcast packets
7611  * Access: RW
7612  */
7613 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
7614 
7615 /* reg_ricnt_good_unicast_bytes
7616  * A count of L3 data and padding octets not including L2 headers
7617  * for good unicast frames.
7618  * Access: RW
7619  */
7620 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
7621 
7622 /* reg_ricnt_good_multicast_bytes
7623  * A count of L3 data and padding octets not including L2 headers
7624  * for good multicast frames.
7625  * Access: RW
7626  */
7627 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
7628 
7629 /* reg_ritr_good_broadcast_bytes
7630  * A count of L3 data and padding octets not including L2 headers
7631  * for good broadcast frames.
7632  * Access: RW
7633  */
7634 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
7635 
7636 /* reg_ricnt_error_packets
7637  * A count of errored frames that do not pass the router checks.
7638  * Access: RW
7639  */
7640 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
7641 
7642 /* reg_ricnt_discrad_packets
7643  * A count of non-errored frames that do not pass the router checks.
7644  * Access: RW
7645  */
7646 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
7647 
7648 /* reg_ricnt_error_bytes
7649  * A count of L3 data and padding octets not including L2 headers
7650  * for errored frames.
7651  * Access: RW
7652  */
7653 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
7654 
7655 /* reg_ricnt_discard_bytes
7656  * A count of L3 data and padding octets not including L2 headers
7657  * for non-errored frames that do not pass the router checks.
7658  * Access: RW
7659  */
7660 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
7661 
7662 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
7663 					enum mlxsw_reg_ricnt_opcode op)
7664 {
7665 	MLXSW_REG_ZERO(ricnt, payload);
7666 	mlxsw_reg_ricnt_op_set(payload, op);
7667 	mlxsw_reg_ricnt_counter_index_set(payload, index);
7668 	mlxsw_reg_ricnt_counter_set_type_set(payload,
7669 					     MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
7670 }
7671 
7672 /* RRCR - Router Rules Copy Register Layout
7673  * ----------------------------------------
7674  * This register is used for moving and copying route entry rules.
7675  */
7676 #define MLXSW_REG_RRCR_ID 0x800F
7677 #define MLXSW_REG_RRCR_LEN 0x24
7678 
7679 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
7680 
7681 enum mlxsw_reg_rrcr_op {
7682 	/* Move rules */
7683 	MLXSW_REG_RRCR_OP_MOVE,
7684 	/* Copy rules */
7685 	MLXSW_REG_RRCR_OP_COPY,
7686 };
7687 
7688 /* reg_rrcr_op
7689  * Access: WO
7690  */
7691 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
7692 
7693 /* reg_rrcr_offset
7694  * Offset within the region from which to copy/move.
7695  * Access: Index
7696  */
7697 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
7698 
7699 /* reg_rrcr_size
7700  * The number of rules to copy/move.
7701  * Access: WO
7702  */
7703 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
7704 
7705 /* reg_rrcr_table_id
7706  * Identifier of the table on which to perform the operation. Encoding is the
7707  * same as in RTAR.key_type
7708  * Access: Index
7709  */
7710 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
7711 
7712 /* reg_rrcr_dest_offset
7713  * Offset within the region to which to copy/move
7714  * Access: Index
7715  */
7716 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
7717 
7718 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
7719 				       u16 offset, u16 size,
7720 				       enum mlxsw_reg_rtar_key_type table_id,
7721 				       u16 dest_offset)
7722 {
7723 	MLXSW_REG_ZERO(rrcr, payload);
7724 	mlxsw_reg_rrcr_op_set(payload, op);
7725 	mlxsw_reg_rrcr_offset_set(payload, offset);
7726 	mlxsw_reg_rrcr_size_set(payload, size);
7727 	mlxsw_reg_rrcr_table_id_set(payload, table_id);
7728 	mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
7729 }
7730 
7731 /* RALTA - Router Algorithmic LPM Tree Allocation Register
7732  * -------------------------------------------------------
7733  * RALTA is used to allocate the LPM trees of the SHSPM method.
7734  */
7735 #define MLXSW_REG_RALTA_ID 0x8010
7736 #define MLXSW_REG_RALTA_LEN 0x04
7737 
7738 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
7739 
7740 /* reg_ralta_op
7741  * opcode (valid for Write, must be 0 on Read)
7742  * 0 - allocate a tree
7743  * 1 - deallocate a tree
7744  * Access: OP
7745  */
7746 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
7747 
7748 enum mlxsw_reg_ralxx_protocol {
7749 	MLXSW_REG_RALXX_PROTOCOL_IPV4,
7750 	MLXSW_REG_RALXX_PROTOCOL_IPV6,
7751 };
7752 
7753 /* reg_ralta_protocol
7754  * Protocol.
7755  * Deallocation opcode: Reserved.
7756  * Access: RW
7757  */
7758 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
7759 
7760 /* reg_ralta_tree_id
7761  * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
7762  * the tree identifier (managed by software).
7763  * Note that tree_id 0 is allocated for a default-route tree.
7764  * Access: Index
7765  */
7766 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
7767 
7768 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
7769 					enum mlxsw_reg_ralxx_protocol protocol,
7770 					u8 tree_id)
7771 {
7772 	MLXSW_REG_ZERO(ralta, payload);
7773 	mlxsw_reg_ralta_op_set(payload, !alloc);
7774 	mlxsw_reg_ralta_protocol_set(payload, protocol);
7775 	mlxsw_reg_ralta_tree_id_set(payload, tree_id);
7776 }
7777 
7778 /* RALST - Router Algorithmic LPM Structure Tree Register
7779  * ------------------------------------------------------
7780  * RALST is used to set and query the structure of an LPM tree.
7781  * The structure of the tree must be sorted as a sorted binary tree, while
7782  * each node is a bin that is tagged as the length of the prefixes the lookup
7783  * will refer to. Therefore, bin X refers to a set of entries with prefixes
7784  * of X bits to match with the destination address. The bin 0 indicates
7785  * the default action, when there is no match of any prefix.
7786  */
7787 #define MLXSW_REG_RALST_ID 0x8011
7788 #define MLXSW_REG_RALST_LEN 0x104
7789 
7790 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
7791 
7792 /* reg_ralst_root_bin
7793  * The bin number of the root bin.
7794  * 0<root_bin=<(length of IP address)
7795  * For a default-route tree configure 0xff
7796  * Access: RW
7797  */
7798 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
7799 
7800 /* reg_ralst_tree_id
7801  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
7802  * Access: Index
7803  */
7804 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
7805 
7806 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
7807 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
7808 #define MLXSW_REG_RALST_BIN_COUNT 128
7809 
7810 /* reg_ralst_left_child_bin
7811  * Holding the children of the bin according to the stored tree's structure.
7812  * For trees composed of less than 4 blocks, the bins in excess are reserved.
7813  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
7814  * Access: RW
7815  */
7816 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
7817 
7818 /* reg_ralst_right_child_bin
7819  * Holding the children of the bin according to the stored tree's structure.
7820  * For trees composed of less than 4 blocks, the bins in excess are reserved.
7821  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
7822  * Access: RW
7823  */
7824 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
7825 		     false);
7826 
7827 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
7828 {
7829 	MLXSW_REG_ZERO(ralst, payload);
7830 
7831 	/* Initialize all bins to have no left or right child */
7832 	memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
7833 	       MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
7834 
7835 	mlxsw_reg_ralst_root_bin_set(payload, root_bin);
7836 	mlxsw_reg_ralst_tree_id_set(payload, tree_id);
7837 }
7838 
7839 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
7840 					    u8 left_child_bin,
7841 					    u8 right_child_bin)
7842 {
7843 	int bin_index = bin_number - 1;
7844 
7845 	mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
7846 	mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
7847 					    right_child_bin);
7848 }
7849 
7850 /* RALTB - Router Algorithmic LPM Tree Binding Register
7851  * ----------------------------------------------------
7852  * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
7853  */
7854 #define MLXSW_REG_RALTB_ID 0x8012
7855 #define MLXSW_REG_RALTB_LEN 0x04
7856 
7857 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
7858 
7859 /* reg_raltb_virtual_router
7860  * Virtual Router ID
7861  * Range is 0..cap_max_virtual_routers-1
7862  * Access: Index
7863  */
7864 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
7865 
7866 /* reg_raltb_protocol
7867  * Protocol.
7868  * Access: Index
7869  */
7870 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
7871 
7872 /* reg_raltb_tree_id
7873  * Tree to be used for the {virtual_router, protocol}
7874  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
7875  * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
7876  * Access: RW
7877  */
7878 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
7879 
7880 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
7881 					enum mlxsw_reg_ralxx_protocol protocol,
7882 					u8 tree_id)
7883 {
7884 	MLXSW_REG_ZERO(raltb, payload);
7885 	mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
7886 	mlxsw_reg_raltb_protocol_set(payload, protocol);
7887 	mlxsw_reg_raltb_tree_id_set(payload, tree_id);
7888 }
7889 
7890 /* RALUE - Router Algorithmic LPM Unicast Entry Register
7891  * -----------------------------------------------------
7892  * RALUE is used to configure and query LPM entries that serve
7893  * the Unicast protocols.
7894  */
7895 #define MLXSW_REG_RALUE_ID 0x8013
7896 #define MLXSW_REG_RALUE_LEN 0x38
7897 
7898 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
7899 
7900 /* reg_ralue_protocol
7901  * Protocol.
7902  * Access: Index
7903  */
7904 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
7905 
7906 enum mlxsw_reg_ralue_op {
7907 	/* Read operation. If entry doesn't exist, the operation fails. */
7908 	MLXSW_REG_RALUE_OP_QUERY_READ = 0,
7909 	/* Clear on read operation. Used to read entry and
7910 	 * clear Activity bit.
7911 	 */
7912 	MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
7913 	/* Write operation. Used to write a new entry to the table. All RW
7914 	 * fields are written for new entry. Activity bit is set
7915 	 * for new entries.
7916 	 */
7917 	MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
7918 	/* Update operation. Used to update an existing route entry and
7919 	 * only update the RW fields that are detailed in the field
7920 	 * op_u_mask. If entry doesn't exist, the operation fails.
7921 	 */
7922 	MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
7923 	/* Clear activity. The Activity bit (the field a) is cleared
7924 	 * for the entry.
7925 	 */
7926 	MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
7927 	/* Delete operation. Used to delete an existing entry. If entry
7928 	 * doesn't exist, the operation fails.
7929 	 */
7930 	MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
7931 };
7932 
7933 /* reg_ralue_op
7934  * Operation.
7935  * Access: OP
7936  */
7937 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
7938 
7939 /* reg_ralue_a
7940  * Activity. Set for new entries. Set if a packet lookup has hit on the
7941  * specific entry, only if the entry is a route. To clear the a bit, use
7942  * "clear activity" op.
7943  * Enabled by activity_dis in RGCR
7944  * Access: RO
7945  */
7946 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
7947 
7948 /* reg_ralue_virtual_router
7949  * Virtual Router ID
7950  * Range is 0..cap_max_virtual_routers-1
7951  * Access: Index
7952  */
7953 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
7954 
7955 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE	BIT(0)
7956 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN	BIT(1)
7957 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION	BIT(2)
7958 
7959 /* reg_ralue_op_u_mask
7960  * opcode update mask.
7961  * On read operation, this field is reserved.
7962  * This field is valid for update opcode, otherwise - reserved.
7963  * This field is a bitmask of the fields that should be updated.
7964  * Access: WO
7965  */
7966 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
7967 
7968 /* reg_ralue_prefix_len
7969  * Number of bits in the prefix of the LPM route.
7970  * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
7971  * two entries in the physical HW table.
7972  * Access: Index
7973  */
7974 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
7975 
7976 /* reg_ralue_dip*
7977  * The prefix of the route or of the marker that the object of the LPM
7978  * is compared with. The most significant bits of the dip are the prefix.
7979  * The least significant bits must be '0' if the prefix_len is smaller
7980  * than 128 for IPv6 or smaller than 32 for IPv4.
7981  * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
7982  * Access: Index
7983  */
7984 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
7985 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
7986 
7987 enum mlxsw_reg_ralue_entry_type {
7988 	MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
7989 	MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
7990 	MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
7991 };
7992 
7993 /* reg_ralue_entry_type
7994  * Entry type.
7995  * Note - for Marker entries, the action_type and action fields are reserved.
7996  * Access: RW
7997  */
7998 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
7999 
8000 /* reg_ralue_bmp_len
8001  * The best match prefix length in the case that there is no match for
8002  * longer prefixes.
8003  * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
8004  * Note for any update operation with entry_type modification this
8005  * field must be set.
8006  * Access: RW
8007  */
8008 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
8009 
8010 enum mlxsw_reg_ralue_action_type {
8011 	MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
8012 	MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
8013 	MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
8014 };
8015 
8016 /* reg_ralue_action_type
8017  * Action Type
8018  * Indicates how the IP address is connected.
8019  * It can be connected to a local subnet through local_erif or can be
8020  * on a remote subnet connected through a next-hop router,
8021  * or transmitted to the CPU.
8022  * Reserved when entry_type = MARKER_ENTRY
8023  * Access: RW
8024  */
8025 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
8026 
8027 enum mlxsw_reg_ralue_trap_action {
8028 	MLXSW_REG_RALUE_TRAP_ACTION_NOP,
8029 	MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
8030 	MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
8031 	MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
8032 	MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
8033 };
8034 
8035 /* reg_ralue_trap_action
8036  * Trap action.
8037  * For IP2ME action, only NOP and MIRROR are possible.
8038  * Access: RW
8039  */
8040 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
8041 
8042 /* reg_ralue_trap_id
8043  * Trap ID to be reported to CPU.
8044  * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
8045  * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
8046  * Access: RW
8047  */
8048 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
8049 
8050 /* reg_ralue_adjacency_index
8051  * Points to the first entry of the group-based ECMP.
8052  * Only relevant in case of REMOTE action.
8053  * Access: RW
8054  */
8055 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
8056 
8057 /* reg_ralue_ecmp_size
8058  * Amount of sequential entries starting
8059  * from the adjacency_index (the number of ECMPs).
8060  * The valid range is 1-64, 512, 1024, 2048 and 4096.
8061  * Reserved when trap_action is TRAP or DISCARD_ERROR.
8062  * Only relevant in case of REMOTE action.
8063  * Access: RW
8064  */
8065 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
8066 
8067 /* reg_ralue_local_erif
8068  * Egress Router Interface.
8069  * Only relevant in case of LOCAL action.
8070  * Access: RW
8071  */
8072 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
8073 
8074 /* reg_ralue_ip2me_v
8075  * Valid bit for the tunnel_ptr field.
8076  * If valid = 0 then trap to CPU as IP2ME trap ID.
8077  * If valid = 1 and the packet format allows NVE or IPinIP tunnel
8078  * decapsulation then tunnel decapsulation is done.
8079  * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
8080  * decapsulation then trap as IP2ME trap ID.
8081  * Only relevant in case of IP2ME action.
8082  * Access: RW
8083  */
8084 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
8085 
8086 /* reg_ralue_ip2me_tunnel_ptr
8087  * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
8088  * For Spectrum, pointer to KVD Linear.
8089  * Only relevant in case of IP2ME action.
8090  * Access: RW
8091  */
8092 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
8093 
8094 static inline void mlxsw_reg_ralue_pack(char *payload,
8095 					enum mlxsw_reg_ralxx_protocol protocol,
8096 					enum mlxsw_reg_ralue_op op,
8097 					u16 virtual_router, u8 prefix_len)
8098 {
8099 	MLXSW_REG_ZERO(ralue, payload);
8100 	mlxsw_reg_ralue_protocol_set(payload, protocol);
8101 	mlxsw_reg_ralue_op_set(payload, op);
8102 	mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
8103 	mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
8104 	mlxsw_reg_ralue_entry_type_set(payload,
8105 				       MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
8106 	mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
8107 }
8108 
8109 static inline void mlxsw_reg_ralue_pack4(char *payload,
8110 					 enum mlxsw_reg_ralxx_protocol protocol,
8111 					 enum mlxsw_reg_ralue_op op,
8112 					 u16 virtual_router, u8 prefix_len,
8113 					 u32 dip)
8114 {
8115 	mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
8116 	mlxsw_reg_ralue_dip4_set(payload, dip);
8117 }
8118 
8119 static inline void mlxsw_reg_ralue_pack6(char *payload,
8120 					 enum mlxsw_reg_ralxx_protocol protocol,
8121 					 enum mlxsw_reg_ralue_op op,
8122 					 u16 virtual_router, u8 prefix_len,
8123 					 const void *dip)
8124 {
8125 	mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
8126 	mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
8127 }
8128 
8129 static inline void
8130 mlxsw_reg_ralue_act_remote_pack(char *payload,
8131 				enum mlxsw_reg_ralue_trap_action trap_action,
8132 				u16 trap_id, u32 adjacency_index, u16 ecmp_size)
8133 {
8134 	mlxsw_reg_ralue_action_type_set(payload,
8135 					MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
8136 	mlxsw_reg_ralue_trap_action_set(payload, trap_action);
8137 	mlxsw_reg_ralue_trap_id_set(payload, trap_id);
8138 	mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
8139 	mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
8140 }
8141 
8142 static inline void
8143 mlxsw_reg_ralue_act_local_pack(char *payload,
8144 			       enum mlxsw_reg_ralue_trap_action trap_action,
8145 			       u16 trap_id, u16 local_erif)
8146 {
8147 	mlxsw_reg_ralue_action_type_set(payload,
8148 					MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
8149 	mlxsw_reg_ralue_trap_action_set(payload, trap_action);
8150 	mlxsw_reg_ralue_trap_id_set(payload, trap_id);
8151 	mlxsw_reg_ralue_local_erif_set(payload, local_erif);
8152 }
8153 
8154 static inline void
8155 mlxsw_reg_ralue_act_ip2me_pack(char *payload)
8156 {
8157 	mlxsw_reg_ralue_action_type_set(payload,
8158 					MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
8159 }
8160 
8161 static inline void
8162 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
8163 {
8164 	mlxsw_reg_ralue_action_type_set(payload,
8165 					MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
8166 	mlxsw_reg_ralue_ip2me_v_set(payload, 1);
8167 	mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
8168 }
8169 
8170 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
8171  * ----------------------------------------------------------
8172  * The RAUHT register is used to configure and query the Unicast Host table in
8173  * devices that implement the Algorithmic LPM.
8174  */
8175 #define MLXSW_REG_RAUHT_ID 0x8014
8176 #define MLXSW_REG_RAUHT_LEN 0x74
8177 
8178 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
8179 
8180 enum mlxsw_reg_rauht_type {
8181 	MLXSW_REG_RAUHT_TYPE_IPV4,
8182 	MLXSW_REG_RAUHT_TYPE_IPV6,
8183 };
8184 
8185 /* reg_rauht_type
8186  * Access: Index
8187  */
8188 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
8189 
8190 enum mlxsw_reg_rauht_op {
8191 	MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
8192 	/* Read operation */
8193 	MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
8194 	/* Clear on read operation. Used to read entry and clear
8195 	 * activity bit.
8196 	 */
8197 	MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
8198 	/* Add. Used to write a new entry to the table. All R/W fields are
8199 	 * relevant for new entry. Activity bit is set for new entries.
8200 	 */
8201 	MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
8202 	/* Update action. Used to update an existing route entry and
8203 	 * only update the following fields:
8204 	 * trap_action, trap_id, mac, counter_set_type, counter_index
8205 	 */
8206 	MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
8207 	/* Clear activity. A bit is cleared for the entry. */
8208 	MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
8209 	/* Delete entry */
8210 	MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
8211 	/* Delete all host entries on a RIF. In this command, dip
8212 	 * field is reserved.
8213 	 */
8214 };
8215 
8216 /* reg_rauht_op
8217  * Access: OP
8218  */
8219 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
8220 
8221 /* reg_rauht_a
8222  * Activity. Set for new entries. Set if a packet lookup has hit on
8223  * the specific entry.
8224  * To clear the a bit, use "clear activity" op.
8225  * Enabled by activity_dis in RGCR
8226  * Access: RO
8227  */
8228 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
8229 
8230 /* reg_rauht_rif
8231  * Router Interface
8232  * Access: Index
8233  */
8234 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
8235 
8236 /* reg_rauht_dip*
8237  * Destination address.
8238  * Access: Index
8239  */
8240 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
8241 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
8242 
8243 enum mlxsw_reg_rauht_trap_action {
8244 	MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
8245 	MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
8246 	MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
8247 	MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
8248 	MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
8249 };
8250 
8251 /* reg_rauht_trap_action
8252  * Access: RW
8253  */
8254 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
8255 
8256 enum mlxsw_reg_rauht_trap_id {
8257 	MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
8258 	MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
8259 };
8260 
8261 /* reg_rauht_trap_id
8262  * Trap ID to be reported to CPU.
8263  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
8264  * For trap_action of NOP, MIRROR and DISCARD_ERROR,
8265  * trap_id is reserved.
8266  * Access: RW
8267  */
8268 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
8269 
8270 /* reg_rauht_counter_set_type
8271  * Counter set type for flow counters
8272  * Access: RW
8273  */
8274 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
8275 
8276 /* reg_rauht_counter_index
8277  * Counter index for flow counters
8278  * Access: RW
8279  */
8280 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
8281 
8282 /* reg_rauht_mac
8283  * MAC address.
8284  * Access: RW
8285  */
8286 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
8287 
8288 static inline void mlxsw_reg_rauht_pack(char *payload,
8289 					enum mlxsw_reg_rauht_op op, u16 rif,
8290 					const char *mac)
8291 {
8292 	MLXSW_REG_ZERO(rauht, payload);
8293 	mlxsw_reg_rauht_op_set(payload, op);
8294 	mlxsw_reg_rauht_rif_set(payload, rif);
8295 	mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
8296 }
8297 
8298 static inline void mlxsw_reg_rauht_pack4(char *payload,
8299 					 enum mlxsw_reg_rauht_op op, u16 rif,
8300 					 const char *mac, u32 dip)
8301 {
8302 	mlxsw_reg_rauht_pack(payload, op, rif, mac);
8303 	mlxsw_reg_rauht_dip4_set(payload, dip);
8304 }
8305 
8306 static inline void mlxsw_reg_rauht_pack6(char *payload,
8307 					 enum mlxsw_reg_rauht_op op, u16 rif,
8308 					 const char *mac, const char *dip)
8309 {
8310 	mlxsw_reg_rauht_pack(payload, op, rif, mac);
8311 	mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
8312 	mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
8313 }
8314 
8315 static inline void mlxsw_reg_rauht_pack_counter(char *payload,
8316 						u64 counter_index)
8317 {
8318 	mlxsw_reg_rauht_counter_index_set(payload, counter_index);
8319 	mlxsw_reg_rauht_counter_set_type_set(payload,
8320 					     MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
8321 }
8322 
8323 /* RALEU - Router Algorithmic LPM ECMP Update Register
8324  * ---------------------------------------------------
8325  * The register enables updating the ECMP section in the action for multiple
8326  * LPM Unicast entries in a single operation. The update is executed to
8327  * all entries of a {virtual router, protocol} tuple using the same ECMP group.
8328  */
8329 #define MLXSW_REG_RALEU_ID 0x8015
8330 #define MLXSW_REG_RALEU_LEN 0x28
8331 
8332 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
8333 
8334 /* reg_raleu_protocol
8335  * Protocol.
8336  * Access: Index
8337  */
8338 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
8339 
8340 /* reg_raleu_virtual_router
8341  * Virtual Router ID
8342  * Range is 0..cap_max_virtual_routers-1
8343  * Access: Index
8344  */
8345 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
8346 
8347 /* reg_raleu_adjacency_index
8348  * Adjacency Index used for matching on the existing entries.
8349  * Access: Index
8350  */
8351 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
8352 
8353 /* reg_raleu_ecmp_size
8354  * ECMP Size used for matching on the existing entries.
8355  * Access: Index
8356  */
8357 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
8358 
8359 /* reg_raleu_new_adjacency_index
8360  * New Adjacency Index.
8361  * Access: WO
8362  */
8363 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
8364 
8365 /* reg_raleu_new_ecmp_size
8366  * New ECMP Size.
8367  * Access: WO
8368  */
8369 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
8370 
8371 static inline void mlxsw_reg_raleu_pack(char *payload,
8372 					enum mlxsw_reg_ralxx_protocol protocol,
8373 					u16 virtual_router,
8374 					u32 adjacency_index, u16 ecmp_size,
8375 					u32 new_adjacency_index,
8376 					u16 new_ecmp_size)
8377 {
8378 	MLXSW_REG_ZERO(raleu, payload);
8379 	mlxsw_reg_raleu_protocol_set(payload, protocol);
8380 	mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
8381 	mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
8382 	mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
8383 	mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
8384 	mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
8385 }
8386 
8387 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
8388  * ----------------------------------------------------------------
8389  * The RAUHTD register allows dumping entries from the Router Unicast Host
8390  * Table. For a given session an entry is dumped no more than one time. The
8391  * first RAUHTD access after reset is a new session. A session ends when the
8392  * num_rec response is smaller than num_rec request or for IPv4 when the
8393  * num_entries is smaller than 4. The clear activity affect the current session
8394  * or the last session if a new session has not started.
8395  */
8396 #define MLXSW_REG_RAUHTD_ID 0x8018
8397 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
8398 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
8399 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
8400 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
8401 		MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
8402 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
8403 
8404 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
8405 
8406 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
8407 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
8408 
8409 /* reg_rauhtd_filter_fields
8410  * if a bit is '0' then the relevant field is ignored and dump is done
8411  * regardless of the field value
8412  * Bit0 - filter by activity: entry_a
8413  * Bit3 - filter by entry rip: entry_rif
8414  * Access: Index
8415  */
8416 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
8417 
8418 enum mlxsw_reg_rauhtd_op {
8419 	MLXSW_REG_RAUHTD_OP_DUMP,
8420 	MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
8421 };
8422 
8423 /* reg_rauhtd_op
8424  * Access: OP
8425  */
8426 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
8427 
8428 /* reg_rauhtd_num_rec
8429  * At request: number of records requested
8430  * At response: number of records dumped
8431  * For IPv4, each record has 4 entries at request and up to 4 entries
8432  * at response
8433  * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
8434  * Access: Index
8435  */
8436 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
8437 
8438 /* reg_rauhtd_entry_a
8439  * Dump only if activity has value of entry_a
8440  * Reserved if filter_fields bit0 is '0'
8441  * Access: Index
8442  */
8443 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
8444 
8445 enum mlxsw_reg_rauhtd_type {
8446 	MLXSW_REG_RAUHTD_TYPE_IPV4,
8447 	MLXSW_REG_RAUHTD_TYPE_IPV6,
8448 };
8449 
8450 /* reg_rauhtd_type
8451  * Dump only if record type is:
8452  * 0 - IPv4
8453  * 1 - IPv6
8454  * Access: Index
8455  */
8456 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
8457 
8458 /* reg_rauhtd_entry_rif
8459  * Dump only if RIF has value of entry_rif
8460  * Reserved if filter_fields bit3 is '0'
8461  * Access: Index
8462  */
8463 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
8464 
8465 static inline void mlxsw_reg_rauhtd_pack(char *payload,
8466 					 enum mlxsw_reg_rauhtd_type type)
8467 {
8468 	MLXSW_REG_ZERO(rauhtd, payload);
8469 	mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
8470 	mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
8471 	mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
8472 	mlxsw_reg_rauhtd_entry_a_set(payload, 1);
8473 	mlxsw_reg_rauhtd_type_set(payload, type);
8474 }
8475 
8476 /* reg_rauhtd_ipv4_rec_num_entries
8477  * Number of valid entries in this record:
8478  * 0 - 1 valid entry
8479  * 1 - 2 valid entries
8480  * 2 - 3 valid entries
8481  * 3 - 4 valid entries
8482  * Access: RO
8483  */
8484 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
8485 		     MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
8486 		     MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
8487 
8488 /* reg_rauhtd_rec_type
8489  * Record type.
8490  * 0 - IPv4
8491  * 1 - IPv6
8492  * Access: RO
8493  */
8494 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
8495 		     MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
8496 
8497 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
8498 
8499 /* reg_rauhtd_ipv4_ent_a
8500  * Activity. Set for new entries. Set if a packet lookup has hit on the
8501  * specific entry.
8502  * Access: RO
8503  */
8504 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
8505 		     MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
8506 
8507 /* reg_rauhtd_ipv4_ent_rif
8508  * Router interface.
8509  * Access: RO
8510  */
8511 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
8512 		     16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
8513 
8514 /* reg_rauhtd_ipv4_ent_dip
8515  * Destination IPv4 address.
8516  * Access: RO
8517  */
8518 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
8519 		     32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
8520 
8521 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
8522 
8523 /* reg_rauhtd_ipv6_ent_a
8524  * Activity. Set for new entries. Set if a packet lookup has hit on the
8525  * specific entry.
8526  * Access: RO
8527  */
8528 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
8529 		     MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
8530 
8531 /* reg_rauhtd_ipv6_ent_rif
8532  * Router interface.
8533  * Access: RO
8534  */
8535 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
8536 		     16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
8537 
8538 /* reg_rauhtd_ipv6_ent_dip
8539  * Destination IPv6 address.
8540  * Access: RO
8541  */
8542 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
8543 		       16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
8544 
8545 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
8546 						    int ent_index, u16 *p_rif,
8547 						    u32 *p_dip)
8548 {
8549 	*p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
8550 	*p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
8551 }
8552 
8553 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
8554 						    int rec_index, u16 *p_rif,
8555 						    char *p_dip)
8556 {
8557 	*p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
8558 	mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
8559 }
8560 
8561 /* RTDP - Routing Tunnel Decap Properties Register
8562  * -----------------------------------------------
8563  * The RTDP register is used for configuring the tunnel decap properties of NVE
8564  * and IPinIP.
8565  */
8566 #define MLXSW_REG_RTDP_ID 0x8020
8567 #define MLXSW_REG_RTDP_LEN 0x44
8568 
8569 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
8570 
8571 enum mlxsw_reg_rtdp_type {
8572 	MLXSW_REG_RTDP_TYPE_NVE,
8573 	MLXSW_REG_RTDP_TYPE_IPIP,
8574 };
8575 
8576 /* reg_rtdp_type
8577  * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type.
8578  * Access: RW
8579  */
8580 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
8581 
8582 /* reg_rtdp_tunnel_index
8583  * Index to the Decap entry.
8584  * For Spectrum, Index to KVD Linear.
8585  * Access: Index
8586  */
8587 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
8588 
8589 /* reg_rtdp_egress_router_interface
8590  * Underlay egress router interface.
8591  * Valid range is from 0 to cap_max_router_interfaces - 1
8592  * Access: RW
8593  */
8594 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);
8595 
8596 /* IPinIP */
8597 
8598 /* reg_rtdp_ipip_irif
8599  * Ingress Router Interface for the overlay router
8600  * Access: RW
8601  */
8602 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
8603 
8604 enum mlxsw_reg_rtdp_ipip_sip_check {
8605 	/* No sip checks. */
8606 	MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
8607 	/* Filter packet if underlay is not IPv4 or if underlay SIP does not
8608 	 * equal ipv4_usip.
8609 	 */
8610 	MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
8611 	/* Filter packet if underlay is not IPv6 or if underlay SIP does not
8612 	 * equal ipv6_usip.
8613 	 */
8614 	MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
8615 };
8616 
8617 /* reg_rtdp_ipip_sip_check
8618  * SIP check to perform. If decapsulation failed due to these configurations
8619  * then trap_id is IPIP_DECAP_ERROR.
8620  * Access: RW
8621  */
8622 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
8623 
8624 /* If set, allow decapsulation of IPinIP (without GRE). */
8625 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP	BIT(0)
8626 /* If set, allow decapsulation of IPinGREinIP without a key. */
8627 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE	BIT(1)
8628 /* If set, allow decapsulation of IPinGREinIP with a key. */
8629 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY	BIT(2)
8630 
8631 /* reg_rtdp_ipip_type_check
8632  * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to
8633  * these configurations then trap_id is IPIP_DECAP_ERROR.
8634  * Access: RW
8635  */
8636 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
8637 
8638 /* reg_rtdp_ipip_gre_key_check
8639  * Whether GRE key should be checked. When check is enabled:
8640  * - A packet received as IPinIP (without GRE) will always pass.
8641  * - A packet received as IPinGREinIP without a key will not pass the check.
8642  * - A packet received as IPinGREinIP with a key will pass the check only if the
8643  *   key in the packet is equal to expected_gre_key.
8644  * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR.
8645  * Access: RW
8646  */
8647 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
8648 
8649 /* reg_rtdp_ipip_ipv4_usip
8650  * Underlay IPv4 address for ipv4 source address check.
8651  * Reserved when sip_check is not '1'.
8652  * Access: RW
8653  */
8654 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
8655 
8656 /* reg_rtdp_ipip_ipv6_usip_ptr
8657  * This field is valid when sip_check is "sipv6 check explicitly". This is a
8658  * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index
8659  * is to the KVD linear.
8660  * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6.
8661  * Access: RW
8662  */
8663 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
8664 
8665 /* reg_rtdp_ipip_expected_gre_key
8666  * GRE key for checking.
8667  * Reserved when gre_key_check is '0'.
8668  * Access: RW
8669  */
8670 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
8671 
8672 static inline void mlxsw_reg_rtdp_pack(char *payload,
8673 				       enum mlxsw_reg_rtdp_type type,
8674 				       u32 tunnel_index)
8675 {
8676 	MLXSW_REG_ZERO(rtdp, payload);
8677 	mlxsw_reg_rtdp_type_set(payload, type);
8678 	mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
8679 }
8680 
8681 static inline void
8682 mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif,
8683 			 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
8684 			 unsigned int type_check, bool gre_key_check,
8685 			 u32 expected_gre_key)
8686 {
8687 	mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
8688 	mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
8689 	mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
8690 	mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
8691 	mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
8692 }
8693 
8694 static inline void
8695 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
8696 			  enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
8697 			  unsigned int type_check, bool gre_key_check,
8698 			  u32 ipv4_usip, u32 expected_gre_key)
8699 {
8700 	mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check,
8701 				 gre_key_check, expected_gre_key);
8702 	mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
8703 }
8704 
8705 static inline void
8706 mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif,
8707 			  enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
8708 			  unsigned int type_check, bool gre_key_check,
8709 			  u32 ipv6_usip_ptr, u32 expected_gre_key)
8710 {
8711 	mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check,
8712 				 gre_key_check, expected_gre_key);
8713 	mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr);
8714 }
8715 
8716 /* RIPS - Router IP version Six Register
8717  * -------------------------------------
8718  * The RIPS register is used to store IPv6 addresses for use by the NVE and
8719  * IPinIP
8720  */
8721 #define MLXSW_REG_RIPS_ID 0x8021
8722 #define MLXSW_REG_RIPS_LEN 0x14
8723 
8724 MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN);
8725 
8726 /* reg_rips_index
8727  * Index to IPv6 address.
8728  * For Spectrum, the index is to the KVD linear.
8729  * Access: Index
8730  */
8731 MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24);
8732 
8733 /* reg_rips_ipv6
8734  * IPv6 address
8735  * Access: RW
8736  */
8737 MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16);
8738 
8739 static inline void mlxsw_reg_rips_pack(char *payload, u32 index,
8740 				       const struct in6_addr *ipv6)
8741 {
8742 	MLXSW_REG_ZERO(rips, payload);
8743 	mlxsw_reg_rips_index_set(payload, index);
8744 	mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6);
8745 }
8746 
8747 /* RATRAD - Router Adjacency Table Activity Dump Register
8748  * ------------------------------------------------------
8749  * The RATRAD register is used to dump and optionally clear activity bits of
8750  * router adjacency table entries.
8751  */
8752 #define MLXSW_REG_RATRAD_ID 0x8022
8753 #define MLXSW_REG_RATRAD_LEN 0x210
8754 
8755 MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN);
8756 
8757 enum {
8758 	/* Read activity */
8759 	MLXSW_REG_RATRAD_OP_READ_ACTIVITY,
8760 	/* Read and clear activity */
8761 	MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY,
8762 };
8763 
8764 /* reg_ratrad_op
8765  * Access: Operation
8766  */
8767 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2);
8768 
8769 /* reg_ratrad_ecmp_size
8770  * ecmp_size is the amount of sequential entries from adjacency_index. Valid
8771  * ranges:
8772  * Spectrum-1: 32-64, 512, 1024, 2048, 4096
8773  * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 4096
8774  * Access: Index
8775  */
8776 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13);
8777 
8778 /* reg_ratrad_adjacency_index
8779  * Index into the adjacency table.
8780  * Access: Index
8781  */
8782 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24);
8783 
8784 /* reg_ratrad_activity_vector
8785  * Activity bit per adjacency index.
8786  * Bits higher than ecmp_size are reserved.
8787  * Access: RO
8788  */
8789 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1);
8790 
8791 static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index,
8792 					 u16 ecmp_size)
8793 {
8794 	MLXSW_REG_ZERO(ratrad, payload);
8795 	mlxsw_reg_ratrad_op_set(payload,
8796 				MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY);
8797 	mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size);
8798 	mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index);
8799 }
8800 
8801 /* RIGR-V2 - Router Interface Group Register Version 2
8802  * ---------------------------------------------------
8803  * The RIGR_V2 register is used to add, remove and query egress interface list
8804  * of a multicast forwarding entry.
8805  */
8806 #define MLXSW_REG_RIGR2_ID 0x8023
8807 #define MLXSW_REG_RIGR2_LEN 0xB0
8808 
8809 #define MLXSW_REG_RIGR2_MAX_ERIFS 32
8810 
8811 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
8812 
8813 /* reg_rigr2_rigr_index
8814  * KVD Linear index.
8815  * Access: Index
8816  */
8817 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
8818 
8819 /* reg_rigr2_vnext
8820  * Next RIGR Index is valid.
8821  * Access: RW
8822  */
8823 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
8824 
8825 /* reg_rigr2_next_rigr_index
8826  * Next RIGR Index. The index is to the KVD linear.
8827  * Reserved when vnxet = '0'.
8828  * Access: RW
8829  */
8830 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
8831 
8832 /* reg_rigr2_vrmid
8833  * RMID Index is valid.
8834  * Access: RW
8835  */
8836 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
8837 
8838 /* reg_rigr2_rmid_index
8839  * RMID Index.
8840  * Range 0 .. max_mid - 1
8841  * Reserved when vrmid = '0'.
8842  * The index is to the Port Group Table (PGT)
8843  * Access: RW
8844  */
8845 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
8846 
8847 /* reg_rigr2_erif_entry_v
8848  * Egress Router Interface is valid.
8849  * Note that low-entries must be set if high-entries are set. For
8850  * example: if erif_entry[2].v is set then erif_entry[1].v and
8851  * erif_entry[0].v must be set.
8852  * Index can be from 0 to cap_mc_erif_list_entries-1
8853  * Access: RW
8854  */
8855 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
8856 
8857 /* reg_rigr2_erif_entry_erif
8858  * Egress Router Interface.
8859  * Valid range is from 0 to cap_max_router_interfaces - 1
8860  * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1
8861  * Access: RW
8862  */
8863 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
8864 
8865 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
8866 					bool vnext, u32 next_rigr_index)
8867 {
8868 	MLXSW_REG_ZERO(rigr2, payload);
8869 	mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
8870 	mlxsw_reg_rigr2_vnext_set(payload, vnext);
8871 	mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
8872 	mlxsw_reg_rigr2_vrmid_set(payload, 0);
8873 	mlxsw_reg_rigr2_rmid_index_set(payload, 0);
8874 }
8875 
8876 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
8877 						   bool v, u16 erif)
8878 {
8879 	mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
8880 	mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
8881 }
8882 
8883 /* RECR-V2 - Router ECMP Configuration Version 2 Register
8884  * ------------------------------------------------------
8885  */
8886 #define MLXSW_REG_RECR2_ID 0x8025
8887 #define MLXSW_REG_RECR2_LEN 0x38
8888 
8889 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
8890 
8891 /* reg_recr2_pp
8892  * Per-port configuration
8893  * Access: Index
8894  */
8895 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
8896 
8897 /* reg_recr2_sh
8898  * Symmetric hash
8899  * Access: RW
8900  */
8901 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
8902 
8903 /* reg_recr2_seed
8904  * Seed
8905  * Access: RW
8906  */
8907 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
8908 
8909 enum {
8910 	/* Enable IPv4 fields if packet is not TCP and not UDP */
8911 	MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP	= 3,
8912 	/* Enable IPv4 fields if packet is TCP or UDP */
8913 	MLXSW_REG_RECR2_IPV4_EN_TCP_UDP		= 4,
8914 	/* Enable IPv6 fields if packet is not TCP and not UDP */
8915 	MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP	= 5,
8916 	/* Enable IPv6 fields if packet is TCP or UDP */
8917 	MLXSW_REG_RECR2_IPV6_EN_TCP_UDP		= 6,
8918 	/* Enable TCP/UDP header fields if packet is IPv4 */
8919 	MLXSW_REG_RECR2_TCP_UDP_EN_IPV4		= 7,
8920 	/* Enable TCP/UDP header fields if packet is IPv6 */
8921 	MLXSW_REG_RECR2_TCP_UDP_EN_IPV6		= 8,
8922 
8923 	__MLXSW_REG_RECR2_HEADER_CNT,
8924 };
8925 
8926 /* reg_recr2_outer_header_enables
8927  * Bit mask where each bit enables a specific layer to be included in
8928  * the hash calculation.
8929  * Access: RW
8930  */
8931 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
8932 
8933 enum {
8934 	/* IPv4 Source IP */
8935 	MLXSW_REG_RECR2_IPV4_SIP0			= 9,
8936 	MLXSW_REG_RECR2_IPV4_SIP3			= 12,
8937 	/* IPv4 Destination IP */
8938 	MLXSW_REG_RECR2_IPV4_DIP0			= 13,
8939 	MLXSW_REG_RECR2_IPV4_DIP3			= 16,
8940 	/* IP Protocol */
8941 	MLXSW_REG_RECR2_IPV4_PROTOCOL			= 17,
8942 	/* IPv6 Source IP */
8943 	MLXSW_REG_RECR2_IPV6_SIP0_7			= 21,
8944 	MLXSW_REG_RECR2_IPV6_SIP8			= 29,
8945 	MLXSW_REG_RECR2_IPV6_SIP15			= 36,
8946 	/* IPv6 Destination IP */
8947 	MLXSW_REG_RECR2_IPV6_DIP0_7			= 37,
8948 	MLXSW_REG_RECR2_IPV6_DIP8			= 45,
8949 	MLXSW_REG_RECR2_IPV6_DIP15			= 52,
8950 	/* IPv6 Next Header */
8951 	MLXSW_REG_RECR2_IPV6_NEXT_HEADER		= 53,
8952 	/* IPv6 Flow Label */
8953 	MLXSW_REG_RECR2_IPV6_FLOW_LABEL			= 57,
8954 	/* TCP/UDP Source Port */
8955 	MLXSW_REG_RECR2_TCP_UDP_SPORT			= 74,
8956 	/* TCP/UDP Destination Port */
8957 	MLXSW_REG_RECR2_TCP_UDP_DPORT			= 75,
8958 
8959 	__MLXSW_REG_RECR2_FIELD_CNT,
8960 };
8961 
8962 /* reg_recr2_outer_header_fields_enable
8963  * Packet fields to enable for ECMP hash subject to outer_header_enable.
8964  * Access: RW
8965  */
8966 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
8967 
8968 /* reg_recr2_inner_header_enables
8969  * Bit mask where each bit enables a specific inner layer to be included in the
8970  * hash calculation. Same values as reg_recr2_outer_header_enables.
8971  * Access: RW
8972  */
8973 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1);
8974 
8975 enum {
8976 	/* Inner IPv4 Source IP */
8977 	MLXSW_REG_RECR2_INNER_IPV4_SIP0			= 3,
8978 	MLXSW_REG_RECR2_INNER_IPV4_SIP3			= 6,
8979 	/* Inner IPv4 Destination IP */
8980 	MLXSW_REG_RECR2_INNER_IPV4_DIP0			= 7,
8981 	MLXSW_REG_RECR2_INNER_IPV4_DIP3			= 10,
8982 	/* Inner IP Protocol */
8983 	MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL		= 11,
8984 	/* Inner IPv6 Source IP */
8985 	MLXSW_REG_RECR2_INNER_IPV6_SIP0_7		= 12,
8986 	MLXSW_REG_RECR2_INNER_IPV6_SIP8			= 20,
8987 	MLXSW_REG_RECR2_INNER_IPV6_SIP15		= 27,
8988 	/* Inner IPv6 Destination IP */
8989 	MLXSW_REG_RECR2_INNER_IPV6_DIP0_7		= 28,
8990 	MLXSW_REG_RECR2_INNER_IPV6_DIP8			= 36,
8991 	MLXSW_REG_RECR2_INNER_IPV6_DIP15		= 43,
8992 	/* Inner IPv6 Next Header */
8993 	MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER		= 44,
8994 	/* Inner IPv6 Flow Label */
8995 	MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL		= 45,
8996 	/* Inner TCP/UDP Source Port */
8997 	MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT		= 46,
8998 	/* Inner TCP/UDP Destination Port */
8999 	MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT		= 47,
9000 
9001 	__MLXSW_REG_RECR2_INNER_FIELD_CNT,
9002 };
9003 
9004 /* reg_recr2_inner_header_fields_enable
9005  * Inner packet fields to enable for ECMP hash subject to inner_header_enables.
9006  * Access: RW
9007  */
9008 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1);
9009 
9010 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
9011 {
9012 	MLXSW_REG_ZERO(recr2, payload);
9013 	mlxsw_reg_recr2_pp_set(payload, false);
9014 	mlxsw_reg_recr2_sh_set(payload, true);
9015 	mlxsw_reg_recr2_seed_set(payload, seed);
9016 }
9017 
9018 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register
9019  * --------------------------------------------------------------
9020  * The RMFT_V2 register is used to configure and query the multicast table.
9021  */
9022 #define MLXSW_REG_RMFT2_ID 0x8027
9023 #define MLXSW_REG_RMFT2_LEN 0x174
9024 
9025 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
9026 
9027 /* reg_rmft2_v
9028  * Valid
9029  * Access: RW
9030  */
9031 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
9032 
9033 enum mlxsw_reg_rmft2_type {
9034 	MLXSW_REG_RMFT2_TYPE_IPV4,
9035 	MLXSW_REG_RMFT2_TYPE_IPV6
9036 };
9037 
9038 /* reg_rmft2_type
9039  * Access: Index
9040  */
9041 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
9042 
9043 enum mlxsw_sp_reg_rmft2_op {
9044 	/* For Write:
9045 	 * Write operation. Used to write a new entry to the table. All RW
9046 	 * fields are relevant for new entry. Activity bit is set for new
9047 	 * entries - Note write with v (Valid) 0 will delete the entry.
9048 	 * For Query:
9049 	 * Read operation
9050 	 */
9051 	MLXSW_REG_RMFT2_OP_READ_WRITE,
9052 };
9053 
9054 /* reg_rmft2_op
9055  * Operation.
9056  * Access: OP
9057  */
9058 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
9059 
9060 /* reg_rmft2_a
9061  * Activity. Set for new entries. Set if a packet lookup has hit on the specific
9062  * entry.
9063  * Access: RO
9064  */
9065 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
9066 
9067 /* reg_rmft2_offset
9068  * Offset within the multicast forwarding table to write to.
9069  * Access: Index
9070  */
9071 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
9072 
9073 /* reg_rmft2_virtual_router
9074  * Virtual Router ID. Range from 0..cap_max_virtual_routers-1
9075  * Access: RW
9076  */
9077 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
9078 
9079 enum mlxsw_reg_rmft2_irif_mask {
9080 	MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
9081 	MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
9082 };
9083 
9084 /* reg_rmft2_irif_mask
9085  * Ingress RIF mask.
9086  * Access: RW
9087  */
9088 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
9089 
9090 /* reg_rmft2_irif
9091  * Ingress RIF index.
9092  * Access: RW
9093  */
9094 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
9095 
9096 /* reg_rmft2_dip{4,6}
9097  * Destination IPv4/6 address
9098  * Access: RW
9099  */
9100 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
9101 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
9102 
9103 /* reg_rmft2_dip{4,6}_mask
9104  * A bit that is set directs the TCAM to compare the corresponding bit in key. A
9105  * bit that is clear directs the TCAM to ignore the corresponding bit in key.
9106  * Access: RW
9107  */
9108 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
9109 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
9110 
9111 /* reg_rmft2_sip{4,6}
9112  * Source IPv4/6 address
9113  * Access: RW
9114  */
9115 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
9116 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
9117 
9118 /* reg_rmft2_sip{4,6}_mask
9119  * A bit that is set directs the TCAM to compare the corresponding bit in key. A
9120  * bit that is clear directs the TCAM to ignore the corresponding bit in key.
9121  * Access: RW
9122  */
9123 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
9124 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
9125 
9126 /* reg_rmft2_flexible_action_set
9127  * ACL action set. The only supported action types in this field and in any
9128  * action-set pointed from here are as follows:
9129  * 00h: ACTION_NULL
9130  * 01h: ACTION_MAC_TTL, only TTL configuration is supported.
9131  * 03h: ACTION_TRAP
9132  * 06h: ACTION_QOS
9133  * 08h: ACTION_POLICING_MONITORING
9134  * 10h: ACTION_ROUTER_MC
9135  * Access: RW
9136  */
9137 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
9138 	       MLXSW_REG_FLEX_ACTION_SET_LEN);
9139 
9140 static inline void
9141 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
9142 			    u16 virtual_router,
9143 			    enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
9144 			    const char *flex_action_set)
9145 {
9146 	MLXSW_REG_ZERO(rmft2, payload);
9147 	mlxsw_reg_rmft2_v_set(payload, v);
9148 	mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
9149 	mlxsw_reg_rmft2_offset_set(payload, offset);
9150 	mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
9151 	mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
9152 	mlxsw_reg_rmft2_irif_set(payload, irif);
9153 	if (flex_action_set)
9154 		mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
9155 							      flex_action_set);
9156 }
9157 
9158 static inline void
9159 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
9160 			  enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
9161 			  u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
9162 			  const char *flexible_action_set)
9163 {
9164 	mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
9165 				    irif_mask, irif, flexible_action_set);
9166 	mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
9167 	mlxsw_reg_rmft2_dip4_set(payload, dip4);
9168 	mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
9169 	mlxsw_reg_rmft2_sip4_set(payload, sip4);
9170 	mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
9171 }
9172 
9173 static inline void
9174 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
9175 			  enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
9176 			  struct in6_addr dip6, struct in6_addr dip6_mask,
9177 			  struct in6_addr sip6, struct in6_addr sip6_mask,
9178 			  const char *flexible_action_set)
9179 {
9180 	mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
9181 				    irif_mask, irif, flexible_action_set);
9182 	mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
9183 	mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
9184 	mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
9185 	mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
9186 	mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
9187 }
9188 
9189 /* REIV - Router Egress Interface to VID Register
9190  * ----------------------------------------------
9191  * The REIV register maps {eRIF, egress_port} -> VID.
9192  * This mapping is done at the egress, after the ACLs.
9193  * This mapping always takes effect after router, regardless of cast
9194  * (for unicast/multicast/port-base multicast), regardless of eRIF type and
9195  * regardless of bridge decisions (e.g. SFD for unicast or SMPE).
9196  * Reserved when the RIF is a loopback RIF.
9197  *
9198  * Note: Reserved when legacy bridge model is used.
9199  */
9200 #define MLXSW_REG_REIV_ID 0x8034
9201 #define MLXSW_REG_REIV_BASE_LEN 0x20 /* base length, without records */
9202 #define MLXSW_REG_REIV_REC_LEN 0x04 /* record length */
9203 #define MLXSW_REG_REIV_REC_MAX_COUNT 256 /* firmware limitation */
9204 #define MLXSW_REG_REIV_LEN (MLXSW_REG_REIV_BASE_LEN +	\
9205 			    MLXSW_REG_REIV_REC_LEN *	\
9206 			    MLXSW_REG_REIV_REC_MAX_COUNT)
9207 
9208 MLXSW_REG_DEFINE(reiv, MLXSW_REG_REIV_ID, MLXSW_REG_REIV_LEN);
9209 
9210 /* reg_reiv_port_page
9211  * Port page - elport_record[0] is 256*port_page.
9212  * Access: Index
9213  */
9214 MLXSW_ITEM32(reg, reiv, port_page, 0x00, 0, 4);
9215 
9216 /* reg_reiv_erif
9217  * Egress RIF.
9218  * Range is 0..cap_max_router_interfaces-1.
9219  * Access: Index
9220  */
9221 MLXSW_ITEM32(reg, reiv, erif, 0x04, 0, 16);
9222 
9223 /* reg_reiv_rec_update
9224  * Update enable (when write):
9225  * 0 - Do not update the entry.
9226  * 1 - Update the entry.
9227  * Access: OP
9228  */
9229 MLXSW_ITEM32_INDEXED(reg, reiv, rec_update, MLXSW_REG_REIV_BASE_LEN, 31, 1,
9230 		     MLXSW_REG_REIV_REC_LEN, 0x00, false);
9231 
9232 /* reg_reiv_rec_evid
9233  * Egress VID.
9234  * Range is 0..4095.
9235  * Access: RW
9236  */
9237 MLXSW_ITEM32_INDEXED(reg, reiv, rec_evid, MLXSW_REG_REIV_BASE_LEN, 0, 12,
9238 		     MLXSW_REG_REIV_REC_LEN, 0x00, false);
9239 
9240 static inline void mlxsw_reg_reiv_pack(char *payload, u8 port_page, u16 erif)
9241 {
9242 	MLXSW_REG_ZERO(reiv, payload);
9243 	mlxsw_reg_reiv_port_page_set(payload, port_page);
9244 	mlxsw_reg_reiv_erif_set(payload, erif);
9245 }
9246 
9247 /* MFCR - Management Fan Control Register
9248  * --------------------------------------
9249  * This register controls the settings of the Fan Speed PWM mechanism.
9250  */
9251 #define MLXSW_REG_MFCR_ID 0x9001
9252 #define MLXSW_REG_MFCR_LEN 0x08
9253 
9254 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
9255 
9256 enum mlxsw_reg_mfcr_pwm_frequency {
9257 	MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
9258 	MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
9259 	MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
9260 	MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
9261 	MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
9262 	MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
9263 	MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
9264 	MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
9265 };
9266 
9267 /* reg_mfcr_pwm_frequency
9268  * Controls the frequency of the PWM signal.
9269  * Access: RW
9270  */
9271 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
9272 
9273 #define MLXSW_MFCR_TACHOS_MAX 10
9274 
9275 /* reg_mfcr_tacho_active
9276  * Indicates which of the tachometer is active (bit per tachometer).
9277  * Access: RO
9278  */
9279 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
9280 
9281 #define MLXSW_MFCR_PWMS_MAX 5
9282 
9283 /* reg_mfcr_pwm_active
9284  * Indicates which of the PWM control is active (bit per PWM).
9285  * Access: RO
9286  */
9287 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
9288 
9289 static inline void
9290 mlxsw_reg_mfcr_pack(char *payload,
9291 		    enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
9292 {
9293 	MLXSW_REG_ZERO(mfcr, payload);
9294 	mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
9295 }
9296 
9297 static inline void
9298 mlxsw_reg_mfcr_unpack(char *payload,
9299 		      enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
9300 		      u16 *p_tacho_active, u8 *p_pwm_active)
9301 {
9302 	*p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
9303 	*p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
9304 	*p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
9305 }
9306 
9307 /* MFSC - Management Fan Speed Control Register
9308  * --------------------------------------------
9309  * This register controls the settings of the Fan Speed PWM mechanism.
9310  */
9311 #define MLXSW_REG_MFSC_ID 0x9002
9312 #define MLXSW_REG_MFSC_LEN 0x08
9313 
9314 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
9315 
9316 /* reg_mfsc_pwm
9317  * Fan pwm to control / monitor.
9318  * Access: Index
9319  */
9320 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
9321 
9322 /* reg_mfsc_pwm_duty_cycle
9323  * Controls the duty cycle of the PWM. Value range from 0..255 to
9324  * represent duty cycle of 0%...100%.
9325  * Access: RW
9326  */
9327 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
9328 
9329 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
9330 				       u8 pwm_duty_cycle)
9331 {
9332 	MLXSW_REG_ZERO(mfsc, payload);
9333 	mlxsw_reg_mfsc_pwm_set(payload, pwm);
9334 	mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
9335 }
9336 
9337 /* MFSM - Management Fan Speed Measurement
9338  * ---------------------------------------
9339  * This register controls the settings of the Tacho measurements and
9340  * enables reading the Tachometer measurements.
9341  */
9342 #define MLXSW_REG_MFSM_ID 0x9003
9343 #define MLXSW_REG_MFSM_LEN 0x08
9344 
9345 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
9346 
9347 /* reg_mfsm_tacho
9348  * Fan tachometer index.
9349  * Access: Index
9350  */
9351 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
9352 
9353 /* reg_mfsm_rpm
9354  * Fan speed (round per minute).
9355  * Access: RO
9356  */
9357 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
9358 
9359 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
9360 {
9361 	MLXSW_REG_ZERO(mfsm, payload);
9362 	mlxsw_reg_mfsm_tacho_set(payload, tacho);
9363 }
9364 
9365 /* MFSL - Management Fan Speed Limit Register
9366  * ------------------------------------------
9367  * The Fan Speed Limit register is used to configure the fan speed
9368  * event / interrupt notification mechanism. Fan speed threshold are
9369  * defined for both under-speed and over-speed.
9370  */
9371 #define MLXSW_REG_MFSL_ID 0x9004
9372 #define MLXSW_REG_MFSL_LEN 0x0C
9373 
9374 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
9375 
9376 /* reg_mfsl_tacho
9377  * Fan tachometer index.
9378  * Access: Index
9379  */
9380 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
9381 
9382 /* reg_mfsl_tach_min
9383  * Tachometer minimum value (minimum RPM).
9384  * Access: RW
9385  */
9386 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
9387 
9388 /* reg_mfsl_tach_max
9389  * Tachometer maximum value (maximum RPM).
9390  * Access: RW
9391  */
9392 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
9393 
9394 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
9395 				       u16 tach_min, u16 tach_max)
9396 {
9397 	MLXSW_REG_ZERO(mfsl, payload);
9398 	mlxsw_reg_mfsl_tacho_set(payload, tacho);
9399 	mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
9400 	mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
9401 }
9402 
9403 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
9404 					 u16 *p_tach_min, u16 *p_tach_max)
9405 {
9406 	if (p_tach_min)
9407 		*p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
9408 
9409 	if (p_tach_max)
9410 		*p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
9411 }
9412 
9413 /* FORE - Fan Out of Range Event Register
9414  * --------------------------------------
9415  * This register reports the status of the controlled fans compared to the
9416  * range defined by the MFSL register.
9417  */
9418 #define MLXSW_REG_FORE_ID 0x9007
9419 #define MLXSW_REG_FORE_LEN 0x0C
9420 
9421 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN);
9422 
9423 /* fan_under_limit
9424  * Fan speed is below the low limit defined in MFSL register. Each bit relates
9425  * to a single tachometer and indicates the specific tachometer reading is
9426  * below the threshold.
9427  * Access: RO
9428  */
9429 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);
9430 
9431 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho,
9432 					 bool *fault)
9433 {
9434 	u16 limit;
9435 
9436 	if (fault) {
9437 		limit = mlxsw_reg_fore_fan_under_limit_get(payload);
9438 		*fault = limit & BIT(tacho);
9439 	}
9440 }
9441 
9442 /* MTCAP - Management Temperature Capabilities
9443  * -------------------------------------------
9444  * This register exposes the capabilities of the device and
9445  * system temperature sensing.
9446  */
9447 #define MLXSW_REG_MTCAP_ID 0x9009
9448 #define MLXSW_REG_MTCAP_LEN 0x08
9449 
9450 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
9451 
9452 /* reg_mtcap_sensor_count
9453  * Number of sensors supported by the device.
9454  * This includes the QSFP module sensors (if exists in the QSFP module).
9455  * Access: RO
9456  */
9457 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
9458 
9459 /* MTMP - Management Temperature
9460  * -----------------------------
9461  * This register controls the settings of the temperature measurements
9462  * and enables reading the temperature measurements. Note that temperature
9463  * is in 0.125 degrees Celsius.
9464  */
9465 #define MLXSW_REG_MTMP_ID 0x900A
9466 #define MLXSW_REG_MTMP_LEN 0x20
9467 
9468 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
9469 
9470 /* reg_mtmp_slot_index
9471  * Slot index (0: Main board).
9472  * Access: Index
9473  */
9474 MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4);
9475 
9476 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64
9477 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256
9478 /* reg_mtmp_sensor_index
9479  * Sensors index to access.
9480  * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
9481  * (module 0 is mapped to sensor_index 64).
9482  * Access: Index
9483  */
9484 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12);
9485 
9486 /* Convert to milli degrees Celsius */
9487 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \
9488 					  ((v_) >= 0) ? ((v_) * 125) : \
9489 					  ((s16)((GENMASK(15, 0) + (v_) + 1) \
9490 					   * 125)); })
9491 
9492 /* reg_mtmp_max_operational_temperature
9493  * The highest temperature in the nominal operational range. Reading is in
9494  * 0.125 Celsius degrees units.
9495  * In case of module this is SFF critical temperature threshold.
9496  * Access: RO
9497  */
9498 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16);
9499 
9500 /* reg_mtmp_temperature
9501  * Temperature reading from the sensor. Reading is in 0.125 Celsius
9502  * degrees units.
9503  * Access: RO
9504  */
9505 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
9506 
9507 /* reg_mtmp_mte
9508  * Max Temperature Enable - enables measuring the max temperature on a sensor.
9509  * Access: RW
9510  */
9511 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
9512 
9513 /* reg_mtmp_mtr
9514  * Max Temperature Reset - clears the value of the max temperature register.
9515  * Access: WO
9516  */
9517 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
9518 
9519 /* reg_mtmp_max_temperature
9520  * The highest measured temperature from the sensor.
9521  * When the bit mte is cleared, the field max_temperature is reserved.
9522  * Access: RO
9523  */
9524 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
9525 
9526 /* reg_mtmp_tee
9527  * Temperature Event Enable.
9528  * 0 - Do not generate event
9529  * 1 - Generate event
9530  * 2 - Generate single event
9531  * Access: RW
9532  */
9533 
9534 enum mlxsw_reg_mtmp_tee {
9535 	MLXSW_REG_MTMP_TEE_NO_EVENT,
9536 	MLXSW_REG_MTMP_TEE_GENERATE_EVENT,
9537 	MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT,
9538 };
9539 
9540 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
9541 
9542 #define MLXSW_REG_MTMP_THRESH_HI 0x348	/* 105 Celsius */
9543 
9544 /* reg_mtmp_temperature_threshold_hi
9545  * High threshold for Temperature Warning Event. In 0.125 Celsius.
9546  * Access: RW
9547  */
9548 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
9549 
9550 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */
9551 /* reg_mtmp_temperature_threshold_lo
9552  * Low threshold for Temperature Warning Event. In 0.125 Celsius.
9553  * Access: RW
9554  */
9555 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
9556 
9557 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
9558 
9559 /* reg_mtmp_sensor_name
9560  * Sensor Name
9561  * Access: RO
9562  */
9563 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
9564 
9565 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 slot_index,
9566 				       u16 sensor_index, bool max_temp_enable,
9567 				       bool max_temp_reset)
9568 {
9569 	MLXSW_REG_ZERO(mtmp, payload);
9570 	mlxsw_reg_mtmp_slot_index_set(payload, slot_index);
9571 	mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
9572 	mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
9573 	mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
9574 	mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
9575 						    MLXSW_REG_MTMP_THRESH_HI);
9576 }
9577 
9578 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp,
9579 					 int *p_max_temp, int *p_temp_hi,
9580 					 int *p_max_oper_temp,
9581 					 char *sensor_name)
9582 {
9583 	s16 temp;
9584 
9585 	if (p_temp) {
9586 		temp = mlxsw_reg_mtmp_temperature_get(payload);
9587 		*p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9588 	}
9589 	if (p_max_temp) {
9590 		temp = mlxsw_reg_mtmp_max_temperature_get(payload);
9591 		*p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9592 	}
9593 	if (p_temp_hi) {
9594 		temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload);
9595 		*p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9596 	}
9597 	if (p_max_oper_temp) {
9598 		temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload);
9599 		*p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9600 	}
9601 	if (sensor_name)
9602 		mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
9603 }
9604 
9605 /* MTWE - Management Temperature Warning Event
9606  * -------------------------------------------
9607  * This register is used for over temperature warning.
9608  */
9609 #define MLXSW_REG_MTWE_ID 0x900B
9610 #define MLXSW_REG_MTWE_LEN 0x10
9611 
9612 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN);
9613 
9614 /* reg_mtwe_sensor_warning
9615  * Bit vector indicating which of the sensor reading is above threshold.
9616  * Address 00h bit31 is sensor_warning[127].
9617  * Address 0Ch bit0 is sensor_warning[0].
9618  * Access: RO
9619  */
9620 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1);
9621 
9622 /* MTBR - Management Temperature Bulk Register
9623  * -------------------------------------------
9624  * This register is used for bulk temperature reading.
9625  */
9626 #define MLXSW_REG_MTBR_ID 0x900F
9627 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */
9628 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */
9629 #define MLXSW_REG_MTBR_REC_MAX_COUNT 1
9630 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN +	\
9631 			    MLXSW_REG_MTBR_REC_LEN *	\
9632 			    MLXSW_REG_MTBR_REC_MAX_COUNT)
9633 
9634 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN);
9635 
9636 /* reg_mtbr_slot_index
9637  * Slot index (0: Main board).
9638  * Access: Index
9639  */
9640 MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4);
9641 
9642 /* reg_mtbr_base_sensor_index
9643  * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors,
9644  * 64-127 are mapped to the SFP+/QSFP modules sequentially).
9645  * Access: Index
9646  */
9647 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12);
9648 
9649 /* reg_mtbr_num_rec
9650  * Request: Number of records to read
9651  * Response: Number of records read
9652  * See above description for more details.
9653  * Range 1..255
9654  * Access: RW
9655  */
9656 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);
9657 
9658 /* reg_mtbr_rec_max_temp
9659  * The highest measured temperature from the sensor.
9660  * When the bit mte is cleared, the field max_temperature is reserved.
9661  * Access: RO
9662  */
9663 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,
9664 		     16, MLXSW_REG_MTBR_REC_LEN, 0x00, false);
9665 
9666 /* reg_mtbr_rec_temp
9667  * Temperature reading from the sensor. Reading is in 0..125 Celsius
9668  * degrees units.
9669  * Access: RO
9670  */
9671 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,
9672 		     MLXSW_REG_MTBR_REC_LEN, 0x00, false);
9673 
9674 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 slot_index,
9675 				       u16 base_sensor_index)
9676 {
9677 	MLXSW_REG_ZERO(mtbr, payload);
9678 	mlxsw_reg_mtbr_slot_index_set(payload, slot_index);
9679 	mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index);
9680 	mlxsw_reg_mtbr_num_rec_set(payload, 1);
9681 }
9682 
9683 /* Error codes from temperatute reading */
9684 enum mlxsw_reg_mtbr_temp_status {
9685 	MLXSW_REG_MTBR_NO_CONN		= 0x8000,
9686 	MLXSW_REG_MTBR_NO_TEMP_SENS	= 0x8001,
9687 	MLXSW_REG_MTBR_INDEX_NA		= 0x8002,
9688 	MLXSW_REG_MTBR_BAD_SENS_INFO	= 0x8003,
9689 };
9690 
9691 /* Base index for reading modules temperature */
9692 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64
9693 
9694 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind,
9695 					      u16 *p_temp, u16 *p_max_temp)
9696 {
9697 	if (p_temp)
9698 		*p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind);
9699 	if (p_max_temp)
9700 		*p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind);
9701 }
9702 
9703 /* MCIA - Management Cable Info Access
9704  * -----------------------------------
9705  * MCIA register is used to access the SFP+ and QSFP connector's EPROM.
9706  */
9707 
9708 #define MLXSW_REG_MCIA_ID 0x9014
9709 #define MLXSW_REG_MCIA_LEN 0x94
9710 
9711 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
9712 
9713 /* reg_mcia_module
9714  * Module number.
9715  * Access: Index
9716  */
9717 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
9718 
9719 /* reg_mcia_slot_index
9720  * Slot index (0: Main board)
9721  * Access: Index
9722  */
9723 MLXSW_ITEM32(reg, mcia, slot, 0x00, 12, 4);
9724 
9725 enum {
9726 	MLXSW_REG_MCIA_STATUS_GOOD = 0,
9727 	/* No response from module's EEPROM. */
9728 	MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1,
9729 	/* Module type not supported by the device. */
9730 	MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2,
9731 	/* No module present indication. */
9732 	MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3,
9733 	/* Error occurred while trying to access module's EEPROM using I2C. */
9734 	MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9,
9735 	/* Module is disabled. */
9736 	MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16,
9737 };
9738 
9739 /* reg_mcia_status
9740  * Module status.
9741  * Access: RO
9742  */
9743 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
9744 
9745 /* reg_mcia_i2c_device_address
9746  * I2C device address.
9747  * Access: RW
9748  */
9749 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
9750 
9751 /* reg_mcia_page_number
9752  * Page number.
9753  * Access: RW
9754  */
9755 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
9756 
9757 /* reg_mcia_device_address
9758  * Device address.
9759  * Access: RW
9760  */
9761 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
9762 
9763 /* reg_mcia_bank_number
9764  * Bank number.
9765  * Access: Index
9766  */
9767 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8);
9768 
9769 /* reg_mcia_size
9770  * Number of bytes to read/write (up to 48 bytes).
9771  * Access: RW
9772  */
9773 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
9774 
9775 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH	256
9776 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH	128
9777 #define MLXSW_REG_MCIA_I2C_ADDR_LOW		0x50
9778 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH		0x51
9779 #define MLXSW_REG_MCIA_PAGE0_LO_OFF		0xa0
9780 #define MLXSW_REG_MCIA_TH_ITEM_SIZE		2
9781 #define MLXSW_REG_MCIA_TH_PAGE_NUM		3
9782 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM		2
9783 #define MLXSW_REG_MCIA_PAGE0_LO			0
9784 #define MLXSW_REG_MCIA_TH_PAGE_OFF		0x80
9785 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY	BIT(7)
9786 
9787 enum mlxsw_reg_mcia_eeprom_module_info_rev_id {
9788 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC	= 0x00,
9789 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436	= 0x01,
9790 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636	= 0x03,
9791 };
9792 
9793 enum mlxsw_reg_mcia_eeprom_module_info_id {
9794 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP	= 0x03,
9795 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP	= 0x0C,
9796 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS	= 0x0D,
9797 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28	= 0x11,
9798 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD	= 0x18,
9799 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP	= 0x19,
9800 };
9801 
9802 enum mlxsw_reg_mcia_eeprom_module_info {
9803 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID,
9804 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID,
9805 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID,
9806 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE,
9807 };
9808 
9809 /* reg_mcia_eeprom
9810  * Bytes to read/write.
9811  * Access: RW
9812  */
9813 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, 128);
9814 
9815 /* This is used to access the optional upper pages (1-3) in the QSFP+
9816  * memory map. Page 1 is available on offset 256 through 383, page 2 -
9817  * on offset 384 through 511, page 3 - on offset 512 through 639.
9818  */
9819 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \
9820 				MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \
9821 				MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1)
9822 
9823 static inline void mlxsw_reg_mcia_pack(char *payload, u8 slot_index, u8 module,
9824 				       u8 page_number, u16 device_addr, u8 size,
9825 				       u8 i2c_device_addr)
9826 {
9827 	MLXSW_REG_ZERO(mcia, payload);
9828 	mlxsw_reg_mcia_slot_set(payload, slot_index);
9829 	mlxsw_reg_mcia_module_set(payload, module);
9830 	mlxsw_reg_mcia_page_number_set(payload, page_number);
9831 	mlxsw_reg_mcia_device_address_set(payload, device_addr);
9832 	mlxsw_reg_mcia_size_set(payload, size);
9833 	mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
9834 }
9835 
9836 /* MPAT - Monitoring Port Analyzer Table
9837  * -------------------------------------
9838  * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
9839  * For an enabled analyzer, all fields except e (enable) cannot be modified.
9840  */
9841 #define MLXSW_REG_MPAT_ID 0x901A
9842 #define MLXSW_REG_MPAT_LEN 0x78
9843 
9844 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
9845 
9846 /* reg_mpat_pa_id
9847  * Port Analyzer ID.
9848  * Access: Index
9849  */
9850 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
9851 
9852 /* reg_mpat_session_id
9853  * Mirror Session ID.
9854  * Used for MIRROR_SESSION<i> trap.
9855  * Access: RW
9856  */
9857 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4);
9858 
9859 /* reg_mpat_system_port
9860  * A unique port identifier for the final destination of the packet.
9861  * Access: RW
9862  */
9863 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
9864 
9865 /* reg_mpat_e
9866  * Enable. Indicating the Port Analyzer is enabled.
9867  * Access: RW
9868  */
9869 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
9870 
9871 /* reg_mpat_qos
9872  * Quality Of Service Mode.
9873  * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
9874  * PCP, DEI, DSCP or VL) are configured.
9875  * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
9876  * same as in the original packet that has triggered the mirroring. For
9877  * SPAN also the pcp,dei are maintained.
9878  * Access: RW
9879  */
9880 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
9881 
9882 /* reg_mpat_be
9883  * Best effort mode. Indicates mirroring traffic should not cause packet
9884  * drop or back pressure, but will discard the mirrored packets. Mirrored
9885  * packets will be forwarded on a best effort manner.
9886  * 0: Do not discard mirrored packets
9887  * 1: Discard mirrored packets if causing congestion
9888  * Access: RW
9889  */
9890 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
9891 
9892 enum mlxsw_reg_mpat_span_type {
9893 	/* Local SPAN Ethernet.
9894 	 * The original packet is not encapsulated.
9895 	 */
9896 	MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
9897 
9898 	/* Remote SPAN Ethernet VLAN.
9899 	 * The packet is forwarded to the monitoring port on the monitoring
9900 	 * VLAN.
9901 	 */
9902 	MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
9903 
9904 	/* Encapsulated Remote SPAN Ethernet L3 GRE.
9905 	 * The packet is encapsulated with GRE header.
9906 	 */
9907 	MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
9908 };
9909 
9910 /* reg_mpat_span_type
9911  * SPAN type.
9912  * Access: RW
9913  */
9914 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
9915 
9916 /* reg_mpat_pide
9917  * Policer enable.
9918  * Access: RW
9919  */
9920 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1);
9921 
9922 /* reg_mpat_pid
9923  * Policer ID.
9924  * Access: RW
9925  */
9926 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14);
9927 
9928 /* Remote SPAN - Ethernet VLAN
9929  * - - - - - - - - - - - - - -
9930  */
9931 
9932 /* reg_mpat_eth_rspan_vid
9933  * Encapsulation header VLAN ID.
9934  * Access: RW
9935  */
9936 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
9937 
9938 /* Encapsulated Remote SPAN - Ethernet L2
9939  * - - - - - - - - - - - - - - - - - - -
9940  */
9941 
9942 enum mlxsw_reg_mpat_eth_rspan_version {
9943 	MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
9944 };
9945 
9946 /* reg_mpat_eth_rspan_version
9947  * RSPAN mirror header version.
9948  * Access: RW
9949  */
9950 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
9951 
9952 /* reg_mpat_eth_rspan_mac
9953  * Destination MAC address.
9954  * Access: RW
9955  */
9956 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
9957 
9958 /* reg_mpat_eth_rspan_tp
9959  * Tag Packet. Indicates whether the mirroring header should be VLAN tagged.
9960  * Access: RW
9961  */
9962 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
9963 
9964 /* Encapsulated Remote SPAN - Ethernet L3
9965  * - - - - - - - - - - - - - - - - - - -
9966  */
9967 
9968 enum mlxsw_reg_mpat_eth_rspan_protocol {
9969 	MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
9970 	MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
9971 };
9972 
9973 /* reg_mpat_eth_rspan_protocol
9974  * SPAN encapsulation protocol.
9975  * Access: RW
9976  */
9977 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
9978 
9979 /* reg_mpat_eth_rspan_ttl
9980  * Encapsulation header Time-to-Live/HopLimit.
9981  * Access: RW
9982  */
9983 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
9984 
9985 /* reg_mpat_eth_rspan_smac
9986  * Source MAC address
9987  * Access: RW
9988  */
9989 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
9990 
9991 /* reg_mpat_eth_rspan_dip*
9992  * Destination IP address. The IP version is configured by protocol.
9993  * Access: RW
9994  */
9995 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
9996 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
9997 
9998 /* reg_mpat_eth_rspan_sip*
9999  * Source IP address. The IP version is configured by protocol.
10000  * Access: RW
10001  */
10002 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
10003 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
10004 
10005 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
10006 				       u16 system_port, bool e,
10007 				       enum mlxsw_reg_mpat_span_type span_type)
10008 {
10009 	MLXSW_REG_ZERO(mpat, payload);
10010 	mlxsw_reg_mpat_pa_id_set(payload, pa_id);
10011 	mlxsw_reg_mpat_system_port_set(payload, system_port);
10012 	mlxsw_reg_mpat_e_set(payload, e);
10013 	mlxsw_reg_mpat_qos_set(payload, 1);
10014 	mlxsw_reg_mpat_be_set(payload, 1);
10015 	mlxsw_reg_mpat_span_type_set(payload, span_type);
10016 }
10017 
10018 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
10019 {
10020 	mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
10021 }
10022 
10023 static inline void
10024 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
10025 				 enum mlxsw_reg_mpat_eth_rspan_version version,
10026 				 const char *mac,
10027 				 bool tp)
10028 {
10029 	mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
10030 	mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
10031 	mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
10032 }
10033 
10034 static inline void
10035 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
10036 				      const char *smac,
10037 				      u32 sip, u32 dip)
10038 {
10039 	mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
10040 	mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
10041 	mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
10042 				    MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
10043 	mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
10044 	mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
10045 }
10046 
10047 static inline void
10048 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
10049 				      const char *smac,
10050 				      struct in6_addr sip, struct in6_addr dip)
10051 {
10052 	mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
10053 	mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
10054 	mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
10055 				    MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
10056 	mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
10057 	mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
10058 }
10059 
10060 /* MPAR - Monitoring Port Analyzer Register
10061  * ----------------------------------------
10062  * MPAR register is used to query and configure the port analyzer port mirroring
10063  * properties.
10064  */
10065 #define MLXSW_REG_MPAR_ID 0x901B
10066 #define MLXSW_REG_MPAR_LEN 0x0C
10067 
10068 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
10069 
10070 /* reg_mpar_local_port
10071  * The local port to mirror the packets from.
10072  * Access: Index
10073  */
10074 MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4);
10075 
10076 enum mlxsw_reg_mpar_i_e {
10077 	MLXSW_REG_MPAR_TYPE_EGRESS,
10078 	MLXSW_REG_MPAR_TYPE_INGRESS,
10079 };
10080 
10081 /* reg_mpar_i_e
10082  * Ingress/Egress
10083  * Access: Index
10084  */
10085 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
10086 
10087 /* reg_mpar_enable
10088  * Enable mirroring
10089  * By default, port mirroring is disabled for all ports.
10090  * Access: RW
10091  */
10092 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
10093 
10094 /* reg_mpar_pa_id
10095  * Port Analyzer ID.
10096  * Access: RW
10097  */
10098 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
10099 
10100 #define MLXSW_REG_MPAR_RATE_MAX 3500000000UL
10101 
10102 /* reg_mpar_probability_rate
10103  * Sampling rate.
10104  * Valid values are: 1 to 3.5*10^9
10105  * Value of 1 means "sample all". Default is 1.
10106  * Reserved when Spectrum-1.
10107  * Access: RW
10108  */
10109 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32);
10110 
10111 static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port,
10112 				       enum mlxsw_reg_mpar_i_e i_e,
10113 				       bool enable, u8 pa_id,
10114 				       u32 probability_rate)
10115 {
10116 	MLXSW_REG_ZERO(mpar, payload);
10117 	mlxsw_reg_mpar_local_port_set(payload, local_port);
10118 	mlxsw_reg_mpar_enable_set(payload, enable);
10119 	mlxsw_reg_mpar_i_e_set(payload, i_e);
10120 	mlxsw_reg_mpar_pa_id_set(payload, pa_id);
10121 	mlxsw_reg_mpar_probability_rate_set(payload, probability_rate);
10122 }
10123 
10124 /* MGIR - Management General Information Register
10125  * ----------------------------------------------
10126  * MGIR register allows software to query the hardware and firmware general
10127  * information.
10128  */
10129 #define MLXSW_REG_MGIR_ID 0x9020
10130 #define MLXSW_REG_MGIR_LEN 0x9C
10131 
10132 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN);
10133 
10134 /* reg_mgir_hw_info_device_hw_revision
10135  * Access: RO
10136  */
10137 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16);
10138 
10139 /* reg_mgir_fw_info_latency_tlv
10140  * When set, latency-TLV is supported.
10141  * Access: RO
10142  */
10143 MLXSW_ITEM32(reg, mgir, fw_info_latency_tlv, 0x20, 29, 1);
10144 
10145 /* reg_mgir_fw_info_string_tlv
10146  * When set, string-TLV is supported.
10147  * Access: RO
10148  */
10149 MLXSW_ITEM32(reg, mgir, fw_info_string_tlv, 0x20, 28, 1);
10150 
10151 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16
10152 
10153 /* reg_mgir_fw_info_psid
10154  * PSID (ASCII string).
10155  * Access: RO
10156  */
10157 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE);
10158 
10159 /* reg_mgir_fw_info_extended_major
10160  * Access: RO
10161  */
10162 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32);
10163 
10164 /* reg_mgir_fw_info_extended_minor
10165  * Access: RO
10166  */
10167 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32);
10168 
10169 /* reg_mgir_fw_info_extended_sub_minor
10170  * Access: RO
10171  */
10172 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32);
10173 
10174 static inline void mlxsw_reg_mgir_pack(char *payload)
10175 {
10176 	MLXSW_REG_ZERO(mgir, payload);
10177 }
10178 
10179 static inline void
10180 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid,
10181 		      u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor)
10182 {
10183 	*hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload);
10184 	mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid);
10185 	*fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload);
10186 	*fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload);
10187 	*fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload);
10188 }
10189 
10190 /* MRSR - Management Reset and Shutdown Register
10191  * ---------------------------------------------
10192  * MRSR register is used to reset or shutdown the switch or
10193  * the entire system (when applicable).
10194  */
10195 #define MLXSW_REG_MRSR_ID 0x9023
10196 #define MLXSW_REG_MRSR_LEN 0x08
10197 
10198 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);
10199 
10200 enum mlxsw_reg_mrsr_command {
10201 	/* Switch soft reset, does not reset PCI firmware. */
10202 	MLXSW_REG_MRSR_COMMAND_SOFTWARE_RESET = 1,
10203 	/* Reset will be done when PCI link will be disabled.
10204 	 * This command will reset PCI firmware also.
10205 	 */
10206 	MLXSW_REG_MRSR_COMMAND_RESET_AT_PCI_DISABLE = 6,
10207 };
10208 
10209 /* reg_mrsr_command
10210  * Reset/shutdown command
10211  * 0 - do nothing
10212  * 1 - software reset
10213  * Access: WO
10214  */
10215 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
10216 
10217 static inline void mlxsw_reg_mrsr_pack(char *payload,
10218 				       enum mlxsw_reg_mrsr_command command)
10219 {
10220 	MLXSW_REG_ZERO(mrsr, payload);
10221 	mlxsw_reg_mrsr_command_set(payload, command);
10222 }
10223 
10224 /* MLCR - Management LED Control Register
10225  * --------------------------------------
10226  * Controls the system LEDs.
10227  */
10228 #define MLXSW_REG_MLCR_ID 0x902B
10229 #define MLXSW_REG_MLCR_LEN 0x0C
10230 
10231 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
10232 
10233 /* reg_mlcr_local_port
10234  * Local port number.
10235  * Access: RW
10236  */
10237 MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24);
10238 
10239 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
10240 
10241 /* reg_mlcr_beacon_duration
10242  * Duration of the beacon to be active, in seconds.
10243  * 0x0 - Will turn off the beacon.
10244  * 0xFFFF - Will turn on the beacon until explicitly turned off.
10245  * Access: RW
10246  */
10247 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
10248 
10249 /* reg_mlcr_beacon_remain
10250  * Remaining duration of the beacon, in seconds.
10251  * 0xFFFF indicates an infinite amount of time.
10252  * Access: RO
10253  */
10254 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
10255 
10256 static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port,
10257 				       bool active)
10258 {
10259 	MLXSW_REG_ZERO(mlcr, payload);
10260 	mlxsw_reg_mlcr_local_port_set(payload, local_port);
10261 	mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
10262 					   MLXSW_REG_MLCR_DURATION_MAX : 0);
10263 }
10264 
10265 /* MCION - Management Cable IO and Notifications Register
10266  * ------------------------------------------------------
10267  * The MCION register is used to query transceiver modules' IO pins and other
10268  * notifications.
10269  */
10270 #define MLXSW_REG_MCION_ID 0x9052
10271 #define MLXSW_REG_MCION_LEN 0x18
10272 
10273 MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN);
10274 
10275 /* reg_mcion_module
10276  * Module number.
10277  * Access: Index
10278  */
10279 MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8);
10280 
10281 /* reg_mcion_slot_index
10282  * Slot index.
10283  * Access: Index
10284  */
10285 MLXSW_ITEM32(reg, mcion, slot_index, 0x00, 12, 4);
10286 
10287 enum {
10288 	MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0),
10289 	MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8),
10290 };
10291 
10292 /* reg_mcion_module_status_bits
10293  * Module IO status as defined by SFF.
10294  * Access: RO
10295  */
10296 MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16);
10297 
10298 static inline void mlxsw_reg_mcion_pack(char *payload, u8 slot_index, u8 module)
10299 {
10300 	MLXSW_REG_ZERO(mcion, payload);
10301 	mlxsw_reg_mcion_slot_index_set(payload, slot_index);
10302 	mlxsw_reg_mcion_module_set(payload, module);
10303 }
10304 
10305 /* MTPPS - Management Pulse Per Second Register
10306  * --------------------------------------------
10307  * This register provides the device PPS capabilities, configure the PPS in and
10308  * out modules and holds the PPS in time stamp.
10309  */
10310 #define MLXSW_REG_MTPPS_ID 0x9053
10311 #define MLXSW_REG_MTPPS_LEN 0x3C
10312 
10313 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN);
10314 
10315 /* reg_mtpps_enable
10316  * Enables the PPS functionality the specific pin.
10317  * A boolean variable.
10318  * Access: RW
10319  */
10320 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
10321 
10322 enum mlxsw_reg_mtpps_pin_mode {
10323 	MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2,
10324 };
10325 
10326 /* reg_mtpps_pin_mode
10327  * Pin mode to be used. The mode must comply with the supported modes of the
10328  * requested pin.
10329  * Access: RW
10330  */
10331 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
10332 
10333 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN	7
10334 
10335 /* reg_mtpps_pin
10336  * Pin to be configured or queried out of the supported pins.
10337  * Access: Index
10338  */
10339 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
10340 
10341 /* reg_mtpps_time_stamp
10342  * When pin_mode = pps_in, the latched device time when it was triggered from
10343  * the external GPIO pin.
10344  * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target
10345  * time to generate next output signal.
10346  * Time is in units of device clock.
10347  * Access: RW
10348  */
10349 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
10350 
10351 static inline void
10352 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp)
10353 {
10354 	MLXSW_REG_ZERO(mtpps, payload);
10355 	mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN);
10356 	mlxsw_reg_mtpps_pin_mode_set(payload,
10357 				     MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN);
10358 	mlxsw_reg_mtpps_enable_set(payload, true);
10359 	mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp);
10360 }
10361 
10362 /* MTUTC - Management UTC Register
10363  * -------------------------------
10364  * Configures the HW UTC counter.
10365  */
10366 #define MLXSW_REG_MTUTC_ID 0x9055
10367 #define MLXSW_REG_MTUTC_LEN 0x1C
10368 
10369 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN);
10370 
10371 enum mlxsw_reg_mtutc_operation {
10372 	MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0,
10373 	MLXSW_REG_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 1,
10374 	MLXSW_REG_MTUTC_OPERATION_ADJUST_TIME = 2,
10375 	MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3,
10376 };
10377 
10378 /* reg_mtutc_operation
10379  * Operation.
10380  * Access: OP
10381  */
10382 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);
10383 
10384 /* reg_mtutc_freq_adjustment
10385  * Frequency adjustment: Every PPS the HW frequency will be
10386  * adjusted by this value. Units of HW clock, where HW counts
10387  * 10^9 HW clocks for 1 HW second. Range is from -50,000,000 to +50,000,000.
10388  * In Spectrum-2, the field is reversed, positive values mean to decrease the
10389  * frequency.
10390  * Access: RW
10391  */
10392 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);
10393 
10394 #define MLXSW_REG_MTUTC_MAX_FREQ_ADJ (50 * 1000 * 1000)
10395 
10396 /* reg_mtutc_utc_sec
10397  * UTC seconds.
10398  * Access: WO
10399  */
10400 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);
10401 
10402 /* reg_mtutc_utc_nsec
10403  * UTC nSecs.
10404  * Range 0..(10^9-1)
10405  * Updated when operation is SET_TIME_IMMEDIATE.
10406  * Reserved on Spectrum-1.
10407  * Access: WO
10408  */
10409 MLXSW_ITEM32(reg, mtutc, utc_nsec, 0x14, 0, 30);
10410 
10411 /* reg_mtutc_time_adjustment
10412  * Time adjustment.
10413  * Units of nSec.
10414  * Range is from -32768 to +32767.
10415  * Updated when operation is ADJUST_TIME.
10416  * Reserved on Spectrum-1.
10417  * Access: WO
10418  */
10419 MLXSW_ITEM32(reg, mtutc, time_adjustment, 0x18, 0, 32);
10420 
10421 static inline void
10422 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper,
10423 		     u32 freq_adj, u32 utc_sec, u32 utc_nsec, u32 time_adj)
10424 {
10425 	MLXSW_REG_ZERO(mtutc, payload);
10426 	mlxsw_reg_mtutc_operation_set(payload, oper);
10427 	mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj);
10428 	mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec);
10429 	mlxsw_reg_mtutc_utc_nsec_set(payload, utc_nsec);
10430 	mlxsw_reg_mtutc_time_adjustment_set(payload, time_adj);
10431 }
10432 
10433 /* MCQI - Management Component Query Information
10434  * ---------------------------------------------
10435  * This register allows querying information about firmware components.
10436  */
10437 #define MLXSW_REG_MCQI_ID 0x9061
10438 #define MLXSW_REG_MCQI_BASE_LEN 0x18
10439 #define MLXSW_REG_MCQI_CAP_LEN 0x14
10440 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
10441 
10442 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
10443 
10444 /* reg_mcqi_component_index
10445  * Index of the accessed component.
10446  * Access: Index
10447  */
10448 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
10449 
10450 enum mlxfw_reg_mcqi_info_type {
10451 	MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
10452 };
10453 
10454 /* reg_mcqi_info_type
10455  * Component properties set.
10456  * Access: RW
10457  */
10458 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
10459 
10460 /* reg_mcqi_offset
10461  * The requested/returned data offset from the section start, given in bytes.
10462  * Must be DWORD aligned.
10463  * Access: RW
10464  */
10465 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
10466 
10467 /* reg_mcqi_data_size
10468  * The requested/returned data size, given in bytes. If data_size is not DWORD
10469  * aligned, the last bytes are zero padded.
10470  * Access: RW
10471  */
10472 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
10473 
10474 /* reg_mcqi_cap_max_component_size
10475  * Maximum size for this component, given in bytes.
10476  * Access: RO
10477  */
10478 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
10479 
10480 /* reg_mcqi_cap_log_mcda_word_size
10481  * Log 2 of the access word size in bytes. Read and write access must be aligned
10482  * to the word size. Write access must be done for an integer number of words.
10483  * Access: RO
10484  */
10485 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
10486 
10487 /* reg_mcqi_cap_mcda_max_write_size
10488  * Maximal write size for MCDA register
10489  * Access: RO
10490  */
10491 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
10492 
10493 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
10494 {
10495 	MLXSW_REG_ZERO(mcqi, payload);
10496 	mlxsw_reg_mcqi_component_index_set(payload, component_index);
10497 	mlxsw_reg_mcqi_info_type_set(payload,
10498 				     MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
10499 	mlxsw_reg_mcqi_offset_set(payload, 0);
10500 	mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
10501 }
10502 
10503 static inline void mlxsw_reg_mcqi_unpack(char *payload,
10504 					 u32 *p_cap_max_component_size,
10505 					 u8 *p_cap_log_mcda_word_size,
10506 					 u16 *p_cap_mcda_max_write_size)
10507 {
10508 	*p_cap_max_component_size =
10509 		mlxsw_reg_mcqi_cap_max_component_size_get(payload);
10510 	*p_cap_log_mcda_word_size =
10511 		mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
10512 	*p_cap_mcda_max_write_size =
10513 		mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
10514 }
10515 
10516 /* MCC - Management Component Control
10517  * ----------------------------------
10518  * Controls the firmware component and updates the FSM.
10519  */
10520 #define MLXSW_REG_MCC_ID 0x9062
10521 #define MLXSW_REG_MCC_LEN 0x1C
10522 
10523 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
10524 
10525 enum mlxsw_reg_mcc_instruction {
10526 	MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
10527 	MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
10528 	MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
10529 	MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
10530 	MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
10531 	MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
10532 };
10533 
10534 /* reg_mcc_instruction
10535  * Command to be executed by the FSM.
10536  * Applicable for write operation only.
10537  * Access: RW
10538  */
10539 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
10540 
10541 /* reg_mcc_component_index
10542  * Index of the accessed component. Applicable only for commands that
10543  * refer to components. Otherwise, this field is reserved.
10544  * Access: Index
10545  */
10546 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
10547 
10548 /* reg_mcc_update_handle
10549  * Token representing the current flow executed by the FSM.
10550  * Access: WO
10551  */
10552 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
10553 
10554 /* reg_mcc_error_code
10555  * Indicates the successful completion of the instruction, or the reason it
10556  * failed
10557  * Access: RO
10558  */
10559 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
10560 
10561 /* reg_mcc_control_state
10562  * Current FSM state
10563  * Access: RO
10564  */
10565 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
10566 
10567 /* reg_mcc_component_size
10568  * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying
10569  * the size may shorten the update time. Value 0x0 means that size is
10570  * unspecified.
10571  * Access: WO
10572  */
10573 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
10574 
10575 static inline void mlxsw_reg_mcc_pack(char *payload,
10576 				      enum mlxsw_reg_mcc_instruction instr,
10577 				      u16 component_index, u32 update_handle,
10578 				      u32 component_size)
10579 {
10580 	MLXSW_REG_ZERO(mcc, payload);
10581 	mlxsw_reg_mcc_instruction_set(payload, instr);
10582 	mlxsw_reg_mcc_component_index_set(payload, component_index);
10583 	mlxsw_reg_mcc_update_handle_set(payload, update_handle);
10584 	mlxsw_reg_mcc_component_size_set(payload, component_size);
10585 }
10586 
10587 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
10588 					u8 *p_error_code, u8 *p_control_state)
10589 {
10590 	if (p_update_handle)
10591 		*p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
10592 	if (p_error_code)
10593 		*p_error_code = mlxsw_reg_mcc_error_code_get(payload);
10594 	if (p_control_state)
10595 		*p_control_state = mlxsw_reg_mcc_control_state_get(payload);
10596 }
10597 
10598 /* MCDA - Management Component Data Access
10599  * ---------------------------------------
10600  * This register allows reading and writing a firmware component.
10601  */
10602 #define MLXSW_REG_MCDA_ID 0x9063
10603 #define MLXSW_REG_MCDA_BASE_LEN 0x10
10604 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
10605 #define MLXSW_REG_MCDA_LEN \
10606 		(MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
10607 
10608 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
10609 
10610 /* reg_mcda_update_handle
10611  * Token representing the current flow executed by the FSM.
10612  * Access: RW
10613  */
10614 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
10615 
10616 /* reg_mcda_offset
10617  * Offset of accessed address relative to component start. Accesses must be in
10618  * accordance to log_mcda_word_size in MCQI reg.
10619  * Access: RW
10620  */
10621 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
10622 
10623 /* reg_mcda_size
10624  * Size of the data accessed, given in bytes.
10625  * Access: RW
10626  */
10627 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
10628 
10629 /* reg_mcda_data
10630  * Data block accessed.
10631  * Access: RW
10632  */
10633 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
10634 
10635 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
10636 				       u32 offset, u16 size, u8 *data)
10637 {
10638 	int i;
10639 
10640 	MLXSW_REG_ZERO(mcda, payload);
10641 	mlxsw_reg_mcda_update_handle_set(payload, update_handle);
10642 	mlxsw_reg_mcda_offset_set(payload, offset);
10643 	mlxsw_reg_mcda_size_set(payload, size);
10644 
10645 	for (i = 0; i < size / 4; i++)
10646 		mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
10647 }
10648 
10649 /* MCAM - Management Capabilities Mask Register
10650  * --------------------------------------------
10651  * Reports the device supported management features.
10652  */
10653 #define MLXSW_REG_MCAM_ID 0x907F
10654 #define MLXSW_REG_MCAM_LEN 0x48
10655 
10656 MLXSW_REG_DEFINE(mcam, MLXSW_REG_MCAM_ID, MLXSW_REG_MCAM_LEN);
10657 
10658 enum mlxsw_reg_mcam_feature_group {
10659 	/* Enhanced features. */
10660 	MLXSW_REG_MCAM_FEATURE_GROUP_ENHANCED_FEATURES,
10661 };
10662 
10663 /* reg_mcam_feature_group
10664  * Feature list mask index.
10665  * Access: Index
10666  */
10667 MLXSW_ITEM32(reg, mcam, feature_group, 0x00, 16, 8);
10668 
10669 enum mlxsw_reg_mcam_mng_feature_cap_mask_bits {
10670 	/* If set, MCIA supports 128 bytes payloads. Otherwise, 48 bytes. */
10671 	MLXSW_REG_MCAM_MCIA_128B = 34,
10672 	/* If set, MRSR.command=6 is supported. */
10673 	MLXSW_REG_MCAM_PCI_RESET = 48,
10674 	/* If set, MRSR.command=6 is supported with Secondary Bus Reset. */
10675 	MLXSW_REG_MCAM_PCI_RESET_SBR = 67,
10676 };
10677 
10678 #define MLXSW_REG_BYTES_PER_DWORD 0x4
10679 
10680 /* reg_mcam_mng_feature_cap_mask
10681  * Supported port's enhanced features.
10682  * Based on feature_group index.
10683  * When bit is set, the feature is supported in the device.
10684  * Access: RO
10685  */
10686 #define MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(_dw_num, _offset)	 \
10687 	MLXSW_ITEM_BIT_ARRAY(reg, mcam, mng_feature_cap_mask_dw##_dw_num, \
10688 			     _offset, MLXSW_REG_BYTES_PER_DWORD, 1)
10689 
10690 /* The access to the bits in the field 'mng_feature_cap_mask' is not same to
10691  * other mask fields in other registers. In most of the cases bit #0 is the
10692  * first one in the last dword. In MCAM register, the first dword contains bits
10693  * #0-#31 and so on, so the access to the bits is simpler using bit array per
10694  * dword. Declare each dword of 'mng_feature_cap_mask' field separately.
10695  */
10696 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(0, 0x28);
10697 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(1, 0x2C);
10698 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(2, 0x30);
10699 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(3, 0x34);
10700 
10701 static inline void
10702 mlxsw_reg_mcam_pack(char *payload, enum mlxsw_reg_mcam_feature_group feat_group)
10703 {
10704 	MLXSW_REG_ZERO(mcam, payload);
10705 	mlxsw_reg_mcam_feature_group_set(payload, feat_group);
10706 }
10707 
10708 static inline void
10709 mlxsw_reg_mcam_unpack(char *payload,
10710 		      enum mlxsw_reg_mcam_mng_feature_cap_mask_bits bit,
10711 		      bool *p_mng_feature_cap_val)
10712 {
10713 	int offset = bit % (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE);
10714 	int dword = bit / (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE);
10715 	u8 (*getters[])(const char *, u16) = {
10716 		mlxsw_reg_mcam_mng_feature_cap_mask_dw0_get,
10717 		mlxsw_reg_mcam_mng_feature_cap_mask_dw1_get,
10718 		mlxsw_reg_mcam_mng_feature_cap_mask_dw2_get,
10719 		mlxsw_reg_mcam_mng_feature_cap_mask_dw3_get,
10720 	};
10721 
10722 	if (!WARN_ON_ONCE(dword >= ARRAY_SIZE(getters)))
10723 		*p_mng_feature_cap_val = getters[dword](payload, offset);
10724 }
10725 
10726 /* MPSC - Monitoring Packet Sampling Configuration Register
10727  * --------------------------------------------------------
10728  * MPSC Register is used to configure the Packet Sampling mechanism.
10729  */
10730 #define MLXSW_REG_MPSC_ID 0x9080
10731 #define MLXSW_REG_MPSC_LEN 0x1C
10732 
10733 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
10734 
10735 /* reg_mpsc_local_port
10736  * Local port number
10737  * Not supported for CPU port
10738  * Access: Index
10739  */
10740 MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12);
10741 
10742 /* reg_mpsc_e
10743  * Enable sampling on port local_port
10744  * Access: RW
10745  */
10746 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
10747 
10748 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
10749 
10750 /* reg_mpsc_rate
10751  * Sampling rate = 1 out of rate packets (with randomization around
10752  * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX
10753  * Access: RW
10754  */
10755 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
10756 
10757 static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e,
10758 				       u32 rate)
10759 {
10760 	MLXSW_REG_ZERO(mpsc, payload);
10761 	mlxsw_reg_mpsc_local_port_set(payload, local_port);
10762 	mlxsw_reg_mpsc_e_set(payload, e);
10763 	mlxsw_reg_mpsc_rate_set(payload, rate);
10764 }
10765 
10766 /* MGPC - Monitoring General Purpose Counter Set Register
10767  * The MGPC register retrieves and sets the General Purpose Counter Set.
10768  */
10769 #define MLXSW_REG_MGPC_ID 0x9081
10770 #define MLXSW_REG_MGPC_LEN 0x18
10771 
10772 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
10773 
10774 /* reg_mgpc_counter_set_type
10775  * Counter set type.
10776  * Access: OP
10777  */
10778 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
10779 
10780 /* reg_mgpc_counter_index
10781  * Counter index.
10782  * Access: Index
10783  */
10784 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
10785 
10786 enum mlxsw_reg_mgpc_opcode {
10787 	/* Nop */
10788 	MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
10789 	/* Clear counters */
10790 	MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
10791 };
10792 
10793 /* reg_mgpc_opcode
10794  * Opcode.
10795  * Access: OP
10796  */
10797 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
10798 
10799 /* reg_mgpc_byte_counter
10800  * Byte counter value.
10801  * Access: RW
10802  */
10803 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
10804 
10805 /* reg_mgpc_packet_counter
10806  * Packet counter value.
10807  * Access: RW
10808  */
10809 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
10810 
10811 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
10812 				       enum mlxsw_reg_mgpc_opcode opcode,
10813 				       enum mlxsw_reg_flow_counter_set_type set_type)
10814 {
10815 	MLXSW_REG_ZERO(mgpc, payload);
10816 	mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
10817 	mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
10818 	mlxsw_reg_mgpc_opcode_set(payload, opcode);
10819 }
10820 
10821 /* MPRS - Monitoring Parsing State Register
10822  * ----------------------------------------
10823  * The MPRS register is used for setting up the parsing for hash,
10824  * policy-engine and routing.
10825  */
10826 #define MLXSW_REG_MPRS_ID 0x9083
10827 #define MLXSW_REG_MPRS_LEN 0x14
10828 
10829 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
10830 
10831 /* reg_mprs_parsing_depth
10832  * Minimum parsing depth.
10833  * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL
10834  * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2.
10835  * Access: RW
10836  */
10837 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
10838 
10839 /* reg_mprs_parsing_en
10840  * Parsing enable.
10841  * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and
10842  * NVGRE. Default is enabled. Reserved when SwitchX-2.
10843  * Access: RW
10844  */
10845 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
10846 
10847 /* reg_mprs_vxlan_udp_dport
10848  * VxLAN UDP destination port.
10849  * Used for identifying VxLAN packets and for dport field in
10850  * encapsulation. Default is 4789.
10851  * Access: RW
10852  */
10853 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
10854 
10855 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
10856 				       u16 vxlan_udp_dport)
10857 {
10858 	MLXSW_REG_ZERO(mprs, payload);
10859 	mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
10860 	mlxsw_reg_mprs_parsing_en_set(payload, true);
10861 	mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
10862 }
10863 
10864 /* MOGCR - Monitoring Global Configuration Register
10865  * ------------------------------------------------
10866  */
10867 #define MLXSW_REG_MOGCR_ID 0x9086
10868 #define MLXSW_REG_MOGCR_LEN 0x20
10869 
10870 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN);
10871 
10872 /* reg_mogcr_ptp_iftc
10873  * PTP Ingress FIFO Trap Clear
10874  * The PTP_ING_FIFO trap provides MTPPTR with clr according
10875  * to this value. Default 0.
10876  * Reserved when IB switches and when SwitchX/-2, Spectrum-2
10877  * Access: RW
10878  */
10879 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
10880 
10881 /* reg_mogcr_ptp_eftc
10882  * PTP Egress FIFO Trap Clear
10883  * The PTP_EGR_FIFO trap provides MTPPTR with clr according
10884  * to this value. Default 0.
10885  * Reserved when IB switches and when SwitchX/-2, Spectrum-2
10886  * Access: RW
10887  */
10888 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
10889 
10890 /* reg_mogcr_mirroring_pid_base
10891  * Base policer id for mirroring policers.
10892  * Must have an even value (e.g. 1000, not 1001).
10893  * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum.
10894  * Access: RW
10895  */
10896 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14);
10897 
10898 /* MPAGR - Monitoring Port Analyzer Global Register
10899  * ------------------------------------------------
10900  * This register is used for global port analyzer configurations.
10901  * Note: This register is not supported by current FW versions for Spectrum-1.
10902  */
10903 #define MLXSW_REG_MPAGR_ID 0x9089
10904 #define MLXSW_REG_MPAGR_LEN 0x0C
10905 
10906 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN);
10907 
10908 enum mlxsw_reg_mpagr_trigger {
10909 	MLXSW_REG_MPAGR_TRIGGER_EGRESS,
10910 	MLXSW_REG_MPAGR_TRIGGER_INGRESS,
10911 	MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED,
10912 	MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER,
10913 	MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG,
10914 	MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG,
10915 	MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN,
10916 	MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY,
10917 };
10918 
10919 /* reg_mpagr_trigger
10920  * Mirror trigger.
10921  * Access: Index
10922  */
10923 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4);
10924 
10925 /* reg_mpagr_pa_id
10926  * Port analyzer ID.
10927  * Access: RW
10928  */
10929 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4);
10930 
10931 #define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL
10932 
10933 /* reg_mpagr_probability_rate
10934  * Sampling rate.
10935  * Valid values are: 1 to 3.5*10^9
10936  * Value of 1 means "sample all". Default is 1.
10937  * Access: RW
10938  */
10939 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32);
10940 
10941 static inline void mlxsw_reg_mpagr_pack(char *payload,
10942 					enum mlxsw_reg_mpagr_trigger trigger,
10943 					u8 pa_id, u32 probability_rate)
10944 {
10945 	MLXSW_REG_ZERO(mpagr, payload);
10946 	mlxsw_reg_mpagr_trigger_set(payload, trigger);
10947 	mlxsw_reg_mpagr_pa_id_set(payload, pa_id);
10948 	mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate);
10949 }
10950 
10951 /* MOMTE - Monitoring Mirror Trigger Enable Register
10952  * -------------------------------------------------
10953  * This register is used to configure the mirror enable for different mirror
10954  * reasons.
10955  */
10956 #define MLXSW_REG_MOMTE_ID 0x908D
10957 #define MLXSW_REG_MOMTE_LEN 0x10
10958 
10959 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN);
10960 
10961 /* reg_momte_local_port
10962  * Local port number.
10963  * Access: Index
10964  */
10965 MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12);
10966 
10967 enum mlxsw_reg_momte_type {
10968 	MLXSW_REG_MOMTE_TYPE_WRED = 0x20,
10969 	MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31,
10970 	MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32,
10971 	MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33,
10972 	MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40,
10973 	MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50,
10974 	MLXSW_REG_MOMTE_TYPE_ECN = 0x60,
10975 	MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70,
10976 };
10977 
10978 /* reg_momte_type
10979  * Type of mirroring.
10980  * Access: Index
10981  */
10982 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8);
10983 
10984 /* reg_momte_tclass_en
10985  * TClass/PG mirror enable. Each bit represents corresponding tclass.
10986  * 0: disable (default)
10987  * 1: enable
10988  * Access: RW
10989  */
10990 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1);
10991 
10992 static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port,
10993 					enum mlxsw_reg_momte_type type)
10994 {
10995 	MLXSW_REG_ZERO(momte, payload);
10996 	mlxsw_reg_momte_local_port_set(payload, local_port);
10997 	mlxsw_reg_momte_type_set(payload, type);
10998 }
10999 
11000 /* MTPPPC - Time Precision Packet Port Configuration
11001  * -------------------------------------------------
11002  * This register serves for configuration of which PTP messages should be
11003  * timestamped. This is a global configuration, despite the register name.
11004  *
11005  * Reserved when Spectrum-2.
11006  */
11007 #define MLXSW_REG_MTPPPC_ID 0x9090
11008 #define MLXSW_REG_MTPPPC_LEN 0x28
11009 
11010 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN);
11011 
11012 /* reg_mtpppc_ing_timestamp_message_type
11013  * Bitwise vector of PTP message types to timestamp at ingress.
11014  * MessageType field as defined by IEEE 1588
11015  * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
11016  * Default all 0
11017  * Access: RW
11018  */
11019 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);
11020 
11021 /* reg_mtpppc_egr_timestamp_message_type
11022  * Bitwise vector of PTP message types to timestamp at egress.
11023  * MessageType field as defined by IEEE 1588
11024  * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
11025  * Default all 0
11026  * Access: RW
11027  */
11028 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);
11029 
11030 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr)
11031 {
11032 	MLXSW_REG_ZERO(mtpppc, payload);
11033 	mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing);
11034 	mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr);
11035 }
11036 
11037 /* MTPPTR - Time Precision Packet Timestamping Reading
11038  * ---------------------------------------------------
11039  * The MTPPTR is used for reading the per port PTP timestamp FIFO.
11040  * There is a trap for packets which are latched to the timestamp FIFO, thus the
11041  * SW knows which FIFO to read. Note that packets enter the FIFO before been
11042  * trapped. The sequence number is used to synchronize the timestamp FIFO
11043  * entries and the trapped packets.
11044  * Reserved when Spectrum-2.
11045  */
11046 
11047 #define MLXSW_REG_MTPPTR_ID 0x9091
11048 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */
11049 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */
11050 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4
11051 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN +		\
11052 		    MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT)
11053 
11054 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN);
11055 
11056 /* reg_mtpptr_local_port
11057  * Not supported for CPU port.
11058  * Access: Index
11059  */
11060 MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12);
11061 
11062 enum mlxsw_reg_mtpptr_dir {
11063 	MLXSW_REG_MTPPTR_DIR_INGRESS,
11064 	MLXSW_REG_MTPPTR_DIR_EGRESS,
11065 };
11066 
11067 /* reg_mtpptr_dir
11068  * Direction.
11069  * Access: Index
11070  */
11071 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1);
11072 
11073 /* reg_mtpptr_clr
11074  * Clear the records.
11075  * Access: OP
11076  */
11077 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
11078 
11079 /* reg_mtpptr_num_rec
11080  * Number of valid records in the response
11081  * Range 0.. cap_ptp_timestamp_fifo
11082  * Access: RO
11083  */
11084 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);
11085 
11086 /* reg_mtpptr_rec_message_type
11087  * MessageType field as defined by IEEE 1588 Each bit corresponds to a value
11088  * (e.g. Bit0: Sync, Bit1: Delay_Req)
11089  * Access: RO
11090  */
11091 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,
11092 		     MLXSW_REG_MTPPTR_BASE_LEN, 8, 4,
11093 		     MLXSW_REG_MTPPTR_REC_LEN, 0, false);
11094 
11095 /* reg_mtpptr_rec_domain_number
11096  * DomainNumber field as defined by IEEE 1588
11097  * Access: RO
11098  */
11099 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,
11100 		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 8,
11101 		     MLXSW_REG_MTPPTR_REC_LEN, 0, false);
11102 
11103 /* reg_mtpptr_rec_sequence_id
11104  * SequenceId field as defined by IEEE 1588
11105  * Access: RO
11106  */
11107 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,
11108 		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 16,
11109 		     MLXSW_REG_MTPPTR_REC_LEN, 0x4, false);
11110 
11111 /* reg_mtpptr_rec_timestamp_high
11112  * Timestamp of when the PTP packet has passed through the port Units of PLL
11113  * clock time.
11114  * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec.
11115  * Access: RO
11116  */
11117 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,
11118 		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
11119 		     MLXSW_REG_MTPPTR_REC_LEN, 0x8, false);
11120 
11121 /* reg_mtpptr_rec_timestamp_low
11122  * See rec_timestamp_high.
11123  * Access: RO
11124  */
11125 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low,
11126 		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
11127 		     MLXSW_REG_MTPPTR_REC_LEN, 0xC, false);
11128 
11129 static inline void mlxsw_reg_mtpptr_unpack(const char *payload,
11130 					   unsigned int rec,
11131 					   u8 *p_message_type,
11132 					   u8 *p_domain_number,
11133 					   u16 *p_sequence_id,
11134 					   u64 *p_timestamp)
11135 {
11136 	u32 timestamp_high, timestamp_low;
11137 
11138 	*p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec);
11139 	*p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec);
11140 	*p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec);
11141 	timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec);
11142 	timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec);
11143 	*p_timestamp = (u64)timestamp_high << 32 | timestamp_low;
11144 }
11145 
11146 /* MTPTPT - Monitoring Precision Time Protocol Trap Register
11147  * ---------------------------------------------------------
11148  * This register is used for configuring under which trap to deliver PTP
11149  * packets depending on type of the packet.
11150  */
11151 #define MLXSW_REG_MTPTPT_ID 0x9092
11152 #define MLXSW_REG_MTPTPT_LEN 0x08
11153 
11154 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN);
11155 
11156 enum mlxsw_reg_mtptpt_trap_id {
11157 	MLXSW_REG_MTPTPT_TRAP_ID_PTP0,
11158 	MLXSW_REG_MTPTPT_TRAP_ID_PTP1,
11159 };
11160 
11161 /* reg_mtptpt_trap_id
11162  * Trap id.
11163  * Access: Index
11164  */
11165 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4);
11166 
11167 /* reg_mtptpt_message_type
11168  * Bitwise vector of PTP message types to trap. This is a necessary but
11169  * non-sufficient condition since need to enable also per port. See MTPPPC.
11170  * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g.
11171  * Bit0: Sync, Bit1: Delay_Req)
11172  */
11173 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);
11174 
11175 static inline void mlxsw_reg_mtptpt_pack(char *payload,
11176 					 enum mlxsw_reg_mtptpt_trap_id trap_id,
11177 					 u16 message_type)
11178 {
11179 	MLXSW_REG_ZERO(mtptpt, payload);
11180 	mlxsw_reg_mtptpt_trap_id_set(payload, trap_id);
11181 	mlxsw_reg_mtptpt_message_type_set(payload, message_type);
11182 }
11183 
11184 /* MTPCPC - Monitoring Time Precision Correction Port Configuration Register
11185  * -------------------------------------------------------------------------
11186  */
11187 #define MLXSW_REG_MTPCPC_ID 0x9093
11188 #define MLXSW_REG_MTPCPC_LEN 0x2C
11189 
11190 MLXSW_REG_DEFINE(mtpcpc, MLXSW_REG_MTPCPC_ID, MLXSW_REG_MTPCPC_LEN);
11191 
11192 /* reg_mtpcpc_pport
11193  * Per port:
11194  * 0: config is global. When reading - the local_port is 1.
11195  * 1: config is per port.
11196  * Access: Index
11197  */
11198 MLXSW_ITEM32(reg, mtpcpc, pport, 0x00, 31, 1);
11199 
11200 /* reg_mtpcpc_local_port
11201  * Local port number.
11202  * Supported to/from CPU port.
11203  * Reserved when pport = 0.
11204  * Access: Index
11205  */
11206 MLXSW_ITEM32_LP(reg, mtpcpc, 0x00, 16, 0x00, 12);
11207 
11208 /* reg_mtpcpc_ptp_trap_en
11209  * Enable PTP traps.
11210  * The trap_id is configured by MTPTPT.
11211  * Access: RW
11212  */
11213 MLXSW_ITEM32(reg, mtpcpc, ptp_trap_en, 0x04, 0, 1);
11214 
11215 /* reg_mtpcpc_ing_correction_message_type
11216  * Bitwise vector of PTP message types to update correction-field at ingress.
11217  * MessageType field as defined by IEEE 1588 Each bit corresponds to a value
11218  * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port.
11219  * Default all 0
11220  * Access: RW
11221  */
11222 MLXSW_ITEM32(reg, mtpcpc, ing_correction_message_type, 0x10, 0, 16);
11223 
11224 /* reg_mtpcpc_egr_correction_message_type
11225  * Bitwise vector of PTP message types to update correction-field at egress.
11226  * MessageType field as defined by IEEE 1588 Each bit corresponds to a value
11227  * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port.
11228  * Default all 0
11229  * Access: RW
11230  */
11231 MLXSW_ITEM32(reg, mtpcpc, egr_correction_message_type, 0x14, 0, 16);
11232 
11233 static inline void mlxsw_reg_mtpcpc_pack(char *payload, bool pport,
11234 					 u16 local_port, bool ptp_trap_en,
11235 					 u16 ing, u16 egr)
11236 {
11237 	MLXSW_REG_ZERO(mtpcpc, payload);
11238 	mlxsw_reg_mtpcpc_pport_set(payload, pport);
11239 	mlxsw_reg_mtpcpc_local_port_set(payload, pport ? local_port : 0);
11240 	mlxsw_reg_mtpcpc_ptp_trap_en_set(payload, ptp_trap_en);
11241 	mlxsw_reg_mtpcpc_ing_correction_message_type_set(payload, ing);
11242 	mlxsw_reg_mtpcpc_egr_correction_message_type_set(payload, egr);
11243 }
11244 
11245 /* MFGD - Monitoring FW General Debug Register
11246  * -------------------------------------------
11247  */
11248 #define MLXSW_REG_MFGD_ID 0x90F0
11249 #define MLXSW_REG_MFGD_LEN 0x0C
11250 
11251 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN);
11252 
11253 /* reg_mfgd_fw_fatal_event_mode
11254  * 0 - don't check FW fatal (default)
11255  * 1 - check FW fatal - enable MFDE trap
11256  * Access: RW
11257  */
11258 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2);
11259 
11260 /* reg_mfgd_trigger_test
11261  * Access: WO
11262  */
11263 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1);
11264 
11265 /* MGPIR - Management General Peripheral Information Register
11266  * ----------------------------------------------------------
11267  * MGPIR register allows software to query the hardware and
11268  * firmware general information of peripheral entities.
11269  */
11270 #define MLXSW_REG_MGPIR_ID 0x9100
11271 #define MLXSW_REG_MGPIR_LEN 0xA0
11272 
11273 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN);
11274 
11275 enum mlxsw_reg_mgpir_device_type {
11276 	MLXSW_REG_MGPIR_DEVICE_TYPE_NONE,
11277 	MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE,
11278 };
11279 
11280 /* mgpir_slot_index
11281  * Slot index (0: Main board).
11282  * Access: Index
11283  */
11284 MLXSW_ITEM32(reg, mgpir, slot_index, 0x00, 28, 4);
11285 
11286 /* mgpir_device_type
11287  * Access: RO
11288  */
11289 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4);
11290 
11291 /* mgpir_devices_per_flash
11292  * Number of devices of device_type per flash (can be shared by few devices).
11293  * Access: RO
11294  */
11295 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8);
11296 
11297 /* mgpir_num_of_devices
11298  * Number of devices of device_type.
11299  * Access: RO
11300  */
11301 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8);
11302 
11303 /* max_modules_per_slot
11304  * Maximum number of modules that can be connected per slot.
11305  * Access: RO
11306  */
11307 MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8);
11308 
11309 /* mgpir_num_of_slots
11310  * Number of slots in the system.
11311  * Access: RO
11312  */
11313 MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8);
11314 
11315 /* mgpir_num_of_modules
11316  * Number of modules.
11317  * Access: RO
11318  */
11319 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8);
11320 
11321 static inline void mlxsw_reg_mgpir_pack(char *payload, u8 slot_index)
11322 {
11323 	MLXSW_REG_ZERO(mgpir, payload);
11324 	mlxsw_reg_mgpir_slot_index_set(payload, slot_index);
11325 }
11326 
11327 static inline void
11328 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices,
11329 		       enum mlxsw_reg_mgpir_device_type *device_type,
11330 		       u8 *devices_per_flash, u8 *num_of_modules,
11331 		       u8 *num_of_slots)
11332 {
11333 	if (num_of_devices)
11334 		*num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload);
11335 	if (device_type)
11336 		*device_type = mlxsw_reg_mgpir_device_type_get(payload);
11337 	if (devices_per_flash)
11338 		*devices_per_flash =
11339 				mlxsw_reg_mgpir_devices_per_flash_get(payload);
11340 	if (num_of_modules)
11341 		*num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload);
11342 	if (num_of_slots)
11343 		*num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload);
11344 }
11345 
11346 /* MBCT - Management Binary Code Transfer Register
11347  * -----------------------------------------------
11348  * This register allows to transfer binary codes from the host to
11349  * the management FW by transferring it by chunks of maximum 1KB.
11350  */
11351 #define MLXSW_REG_MBCT_ID 0x9120
11352 #define MLXSW_REG_MBCT_LEN 0x420
11353 
11354 MLXSW_REG_DEFINE(mbct, MLXSW_REG_MBCT_ID, MLXSW_REG_MBCT_LEN);
11355 
11356 /* reg_mbct_slot_index
11357  * Slot index. 0 is reserved.
11358  * Access: Index
11359  */
11360 MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4);
11361 
11362 /* reg_mbct_data_size
11363  * Actual data field size in bytes for the current data transfer.
11364  * Access: WO
11365  */
11366 MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11);
11367 
11368 enum mlxsw_reg_mbct_op {
11369 	MLXSW_REG_MBCT_OP_ERASE_INI_IMAGE = 1,
11370 	MLXSW_REG_MBCT_OP_DATA_TRANSFER, /* Download */
11371 	MLXSW_REG_MBCT_OP_ACTIVATE,
11372 	MLXSW_REG_MBCT_OP_CLEAR_ERRORS = 6,
11373 	MLXSW_REG_MBCT_OP_QUERY_STATUS,
11374 };
11375 
11376 /* reg_mbct_op
11377  * Access: WO
11378  */
11379 MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4);
11380 
11381 /* reg_mbct_last
11382  * Indicates that the current data field is the last chunk of the INI.
11383  * Access: WO
11384  */
11385 MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1);
11386 
11387 /* reg_mbct_oee
11388  * Opcode Event Enable. When set a BCTOE event will be sent once the opcode
11389  * was executed and the fsm_state has changed.
11390  * Access: WO
11391  */
11392 MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1);
11393 
11394 enum mlxsw_reg_mbct_status {
11395 	/* Partial data transfer completed successfully and ready for next
11396 	 * data transfer.
11397 	 */
11398 	MLXSW_REG_MBCT_STATUS_PART_DATA = 2,
11399 	MLXSW_REG_MBCT_STATUS_LAST_DATA,
11400 	MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE,
11401 	/* Error - trying to erase INI while it being used. */
11402 	MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE,
11403 	/* Last data transfer completed, applying magic pattern. */
11404 	MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7,
11405 	MLXSW_REG_MBCT_STATUS_INI_ERROR,
11406 	MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED,
11407 	MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11,
11408 };
11409 
11410 /* reg_mbct_status
11411  * Status.
11412  * Access: RO
11413  */
11414 MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5);
11415 
11416 enum mlxsw_reg_mbct_fsm_state {
11417 	MLXSW_REG_MBCT_FSM_STATE_INI_IN_USE = 5,
11418 	MLXSW_REG_MBCT_FSM_STATE_ERROR,
11419 };
11420 
11421 /* reg_mbct_fsm_state
11422  * FSM state.
11423  * Access: RO
11424  */
11425 MLXSW_ITEM32(reg, mbct, fsm_state,  0x0C, 16, 4);
11426 
11427 #define MLXSW_REG_MBCT_DATA_LEN 1024
11428 
11429 /* reg_mbct_data
11430  * Up to 1KB of data.
11431  * Access: WO
11432  */
11433 MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN);
11434 
11435 static inline void mlxsw_reg_mbct_pack(char *payload, u8 slot_index,
11436 				       enum mlxsw_reg_mbct_op op, bool oee)
11437 {
11438 	MLXSW_REG_ZERO(mbct, payload);
11439 	mlxsw_reg_mbct_slot_index_set(payload, slot_index);
11440 	mlxsw_reg_mbct_op_set(payload, op);
11441 	mlxsw_reg_mbct_oee_set(payload, oee);
11442 }
11443 
11444 static inline void mlxsw_reg_mbct_dt_pack(char *payload,
11445 					  u16 data_size, bool last,
11446 					  const char *data)
11447 {
11448 	if (WARN_ON(data_size > MLXSW_REG_MBCT_DATA_LEN))
11449 		return;
11450 	mlxsw_reg_mbct_data_size_set(payload, data_size);
11451 	mlxsw_reg_mbct_last_set(payload, last);
11452 	mlxsw_reg_mbct_data_memcpy_to(payload, data);
11453 }
11454 
11455 static inline void
11456 mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index,
11457 		      enum mlxsw_reg_mbct_status *p_status,
11458 		      enum mlxsw_reg_mbct_fsm_state *p_fsm_state)
11459 {
11460 	if (p_slot_index)
11461 		*p_slot_index = mlxsw_reg_mbct_slot_index_get(payload);
11462 	*p_status = mlxsw_reg_mbct_status_get(payload);
11463 	if (p_fsm_state)
11464 		*p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload);
11465 }
11466 
11467 /* MDDT - Management DownStream Device Tunneling Register
11468  * ------------------------------------------------------
11469  * This register allows to deliver query and request messages (PRM registers,
11470  * commands) to a DownStream device.
11471  */
11472 #define MLXSW_REG_MDDT_ID 0x9160
11473 #define MLXSW_REG_MDDT_LEN 0x110
11474 
11475 MLXSW_REG_DEFINE(mddt, MLXSW_REG_MDDT_ID, MLXSW_REG_MDDT_LEN);
11476 
11477 /* reg_mddt_slot_index
11478  * Slot index.
11479  * Access: Index
11480  */
11481 MLXSW_ITEM32(reg, mddt, slot_index, 0x00, 8, 4);
11482 
11483 /* reg_mddt_device_index
11484  * Device index.
11485  * Access: Index
11486  */
11487 MLXSW_ITEM32(reg, mddt, device_index, 0x00, 0, 8);
11488 
11489 /* reg_mddt_read_size
11490  * Read size in D-Words.
11491  * Access: OP
11492  */
11493 MLXSW_ITEM32(reg, mddt, read_size, 0x04, 24, 8);
11494 
11495 /* reg_mddt_write_size
11496  * Write size in D-Words.
11497  * Access: OP
11498  */
11499 MLXSW_ITEM32(reg, mddt, write_size, 0x04, 16, 8);
11500 
11501 enum mlxsw_reg_mddt_status {
11502 	MLXSW_REG_MDDT_STATUS_OK,
11503 };
11504 
11505 /* reg_mddt_status
11506  * Return code of the Downstream Device to the register that was sent.
11507  * Access: RO
11508  */
11509 MLXSW_ITEM32(reg, mddt, status, 0x0C, 24, 8);
11510 
11511 enum mlxsw_reg_mddt_method {
11512 	MLXSW_REG_MDDT_METHOD_QUERY,
11513 	MLXSW_REG_MDDT_METHOD_WRITE,
11514 };
11515 
11516 /* reg_mddt_method
11517  * Access: OP
11518  */
11519 MLXSW_ITEM32(reg, mddt, method, 0x0C, 22, 2);
11520 
11521 /* reg_mddt_register_id
11522  * Access: Index
11523  */
11524 MLXSW_ITEM32(reg, mddt, register_id, 0x0C, 0, 16);
11525 
11526 #define MLXSW_REG_MDDT_PAYLOAD_OFFSET 0x0C
11527 #define MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN 4
11528 
11529 static inline char *mlxsw_reg_mddt_inner_payload(char *payload)
11530 {
11531 	return payload + MLXSW_REG_MDDT_PAYLOAD_OFFSET +
11532 	       MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN;
11533 }
11534 
11535 static inline void mlxsw_reg_mddt_pack(char *payload, u8 slot_index,
11536 				       u8 device_index,
11537 				       enum mlxsw_reg_mddt_method method,
11538 				       const struct mlxsw_reg_info *reg,
11539 				       char **inner_payload)
11540 {
11541 	int len = reg->len + MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN;
11542 
11543 	if (WARN_ON(len + MLXSW_REG_MDDT_PAYLOAD_OFFSET > MLXSW_REG_MDDT_LEN))
11544 		len = MLXSW_REG_MDDT_LEN - MLXSW_REG_MDDT_PAYLOAD_OFFSET;
11545 
11546 	MLXSW_REG_ZERO(mddt, payload);
11547 	mlxsw_reg_mddt_slot_index_set(payload, slot_index);
11548 	mlxsw_reg_mddt_device_index_set(payload, device_index);
11549 	mlxsw_reg_mddt_method_set(payload, method);
11550 	mlxsw_reg_mddt_register_id_set(payload, reg->id);
11551 	mlxsw_reg_mddt_read_size_set(payload, len / 4);
11552 	mlxsw_reg_mddt_write_size_set(payload, len / 4);
11553 	*inner_payload = mlxsw_reg_mddt_inner_payload(payload);
11554 }
11555 
11556 /* MDDQ - Management DownStream Device Query Register
11557  * --------------------------------------------------
11558  * This register allows to query the DownStream device properties. The desired
11559  * information is chosen upon the query_type field and is delivered by 32B
11560  * of data blocks.
11561  */
11562 #define MLXSW_REG_MDDQ_ID 0x9161
11563 #define MLXSW_REG_MDDQ_LEN 0x30
11564 
11565 MLXSW_REG_DEFINE(mddq, MLXSW_REG_MDDQ_ID, MLXSW_REG_MDDQ_LEN);
11566 
11567 /* reg_mddq_sie
11568  * Slot info event enable.
11569  * When set to '1', each change in the slot_info.provisioned / sr_valid /
11570  * active / ready will generate a DSDSC event.
11571  * Access: RW
11572  */
11573 MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1);
11574 
11575 enum mlxsw_reg_mddq_query_type {
11576 	MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO = 1,
11577 	MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO, /* If there are no devices
11578 						* on the slot, data_valid
11579 						* will be '0'.
11580 						*/
11581 	MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME,
11582 };
11583 
11584 /* reg_mddq_query_type
11585  * Access: Index
11586  */
11587 MLXSW_ITEM32(reg, mddq, query_type, 0x00, 16, 8);
11588 
11589 /* reg_mddq_slot_index
11590  * Slot index. 0 is reserved.
11591  * Access: Index
11592  */
11593 MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4);
11594 
11595 /* reg_mddq_response_msg_seq
11596  * Response message sequential number. For a specific request, the response
11597  * message sequential number is the following one. In addition, the last
11598  * message should be 0.
11599  * Access: RO
11600  */
11601 MLXSW_ITEM32(reg, mddq, response_msg_seq, 0x04, 16, 8);
11602 
11603 /* reg_mddq_request_msg_seq
11604  * Request message sequential number.
11605  * The first message number should be 0.
11606  * Access: Index
11607  */
11608 MLXSW_ITEM32(reg, mddq, request_msg_seq, 0x04, 0, 8);
11609 
11610 /* reg_mddq_data_valid
11611  * If set, the data in the data field is valid and contain the information
11612  * for the queried index.
11613  * Access: RO
11614  */
11615 MLXSW_ITEM32(reg, mddq, data_valid, 0x08, 31, 1);
11616 
11617 /* reg_mddq_slot_info_provisioned
11618  * If set, the INI file is applied and the card is provisioned.
11619  * Access: RO
11620  */
11621 MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1);
11622 
11623 /* reg_mddq_slot_info_sr_valid
11624  * If set, Shift Register is valid (after being provisioned) and data
11625  * can be sent from the switch ASIC to the line-card CPLD over Shift-Register.
11626  * Access: RO
11627  */
11628 MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1);
11629 
11630 enum mlxsw_reg_mddq_slot_info_ready {
11631 	MLXSW_REG_MDDQ_SLOT_INFO_READY_NOT_READY,
11632 	MLXSW_REG_MDDQ_SLOT_INFO_READY_READY,
11633 	MLXSW_REG_MDDQ_SLOT_INFO_READY_ERROR,
11634 };
11635 
11636 /* reg_mddq_slot_info_lc_ready
11637  * If set, the LC is powered on, matching the INI version and a new FW
11638  * version can be burnt (if necessary).
11639  * Access: RO
11640  */
11641 MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2);
11642 
11643 /* reg_mddq_slot_info_active
11644  * If set, the FW has completed the MDDC.device_enable command.
11645  * Access: RO
11646  */
11647 MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1);
11648 
11649 /* reg_mddq_slot_info_hw_revision
11650  * Major user-configured version number of the current INI file.
11651  * Valid only when active or ready are '1'.
11652  * Access: RO
11653  */
11654 MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16);
11655 
11656 /* reg_mddq_slot_info_ini_file_version
11657  * User-configured version number of the current INI file.
11658  * Valid only when active or lc_ready are '1'.
11659  * Access: RO
11660  */
11661 MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16);
11662 
11663 /* reg_mddq_slot_info_card_type
11664  * Access: RO
11665  */
11666 MLXSW_ITEM32(reg, mddq, slot_info_card_type, 0x18, 0, 8);
11667 
11668 static inline void
11669 __mlxsw_reg_mddq_pack(char *payload, u8 slot_index,
11670 		      enum mlxsw_reg_mddq_query_type query_type)
11671 {
11672 	MLXSW_REG_ZERO(mddq, payload);
11673 	mlxsw_reg_mddq_slot_index_set(payload, slot_index);
11674 	mlxsw_reg_mddq_query_type_set(payload, query_type);
11675 }
11676 
11677 static inline void
11678 mlxsw_reg_mddq_slot_info_pack(char *payload, u8 slot_index, bool sie)
11679 {
11680 	__mlxsw_reg_mddq_pack(payload, slot_index,
11681 			      MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO);
11682 	mlxsw_reg_mddq_sie_set(payload, sie);
11683 }
11684 
11685 static inline void
11686 mlxsw_reg_mddq_slot_info_unpack(const char *payload, u8 *p_slot_index,
11687 				bool *p_provisioned, bool *p_sr_valid,
11688 				enum mlxsw_reg_mddq_slot_info_ready *p_lc_ready,
11689 				bool *p_active, u16 *p_hw_revision,
11690 				u16 *p_ini_file_version,
11691 				u8 *p_card_type)
11692 {
11693 	*p_slot_index = mlxsw_reg_mddq_slot_index_get(payload);
11694 	*p_provisioned = mlxsw_reg_mddq_slot_info_provisioned_get(payload);
11695 	*p_sr_valid = mlxsw_reg_mddq_slot_info_sr_valid_get(payload);
11696 	*p_lc_ready = mlxsw_reg_mddq_slot_info_lc_ready_get(payload);
11697 	*p_active = mlxsw_reg_mddq_slot_info_active_get(payload);
11698 	*p_hw_revision = mlxsw_reg_mddq_slot_info_hw_revision_get(payload);
11699 	*p_ini_file_version = mlxsw_reg_mddq_slot_info_ini_file_version_get(payload);
11700 	*p_card_type = mlxsw_reg_mddq_slot_info_card_type_get(payload);
11701 }
11702 
11703 /* reg_mddq_device_info_flash_owner
11704  * If set, the device is the flash owner. Otherwise, a shared flash
11705  * is used by this device (another device is the flash owner).
11706  * Access: RO
11707  */
11708 MLXSW_ITEM32(reg, mddq, device_info_flash_owner, 0x10, 30, 1);
11709 
11710 /* reg_mddq_device_info_device_index
11711  * Device index. The first device should number 0.
11712  * Access: RO
11713  */
11714 MLXSW_ITEM32(reg, mddq, device_info_device_index, 0x10, 0, 8);
11715 
11716 /* reg_mddq_device_info_fw_major
11717  * Major FW version number.
11718  * Access: RO
11719  */
11720 MLXSW_ITEM32(reg, mddq, device_info_fw_major, 0x14, 16, 16);
11721 
11722 /* reg_mddq_device_info_fw_minor
11723  * Minor FW version number.
11724  * Access: RO
11725  */
11726 MLXSW_ITEM32(reg, mddq, device_info_fw_minor, 0x18, 16, 16);
11727 
11728 /* reg_mddq_device_info_fw_sub_minor
11729  * Sub-minor FW version number.
11730  * Access: RO
11731  */
11732 MLXSW_ITEM32(reg, mddq, device_info_fw_sub_minor, 0x18, 0, 16);
11733 
11734 static inline void
11735 mlxsw_reg_mddq_device_info_pack(char *payload, u8 slot_index,
11736 				u8 request_msg_seq)
11737 {
11738 	__mlxsw_reg_mddq_pack(payload, slot_index,
11739 			      MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO);
11740 	mlxsw_reg_mddq_request_msg_seq_set(payload, request_msg_seq);
11741 }
11742 
11743 static inline void
11744 mlxsw_reg_mddq_device_info_unpack(const char *payload, u8 *p_response_msg_seq,
11745 				  bool *p_data_valid, bool *p_flash_owner,
11746 				  u8 *p_device_index, u16 *p_fw_major,
11747 				  u16 *p_fw_minor, u16 *p_fw_sub_minor)
11748 {
11749 	*p_response_msg_seq = mlxsw_reg_mddq_response_msg_seq_get(payload);
11750 	*p_data_valid = mlxsw_reg_mddq_data_valid_get(payload);
11751 	*p_flash_owner = mlxsw_reg_mddq_device_info_flash_owner_get(payload);
11752 	*p_device_index = mlxsw_reg_mddq_device_info_device_index_get(payload);
11753 	*p_fw_major = mlxsw_reg_mddq_device_info_fw_major_get(payload);
11754 	*p_fw_minor = mlxsw_reg_mddq_device_info_fw_minor_get(payload);
11755 	*p_fw_sub_minor = mlxsw_reg_mddq_device_info_fw_sub_minor_get(payload);
11756 }
11757 
11758 #define MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN 20
11759 
11760 /* reg_mddq_slot_ascii_name
11761  * Slot's ASCII name.
11762  * Access: RO
11763  */
11764 MLXSW_ITEM_BUF(reg, mddq, slot_ascii_name, 0x10,
11765 	       MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN);
11766 
11767 static inline void
11768 mlxsw_reg_mddq_slot_name_pack(char *payload, u8 slot_index)
11769 {
11770 	__mlxsw_reg_mddq_pack(payload, slot_index,
11771 			      MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME);
11772 }
11773 
11774 static inline void
11775 mlxsw_reg_mddq_slot_name_unpack(const char *payload, char *slot_ascii_name)
11776 {
11777 	mlxsw_reg_mddq_slot_ascii_name_memcpy_from(payload, slot_ascii_name);
11778 }
11779 
11780 /* MDDC - Management DownStream Device Control Register
11781  * ----------------------------------------------------
11782  * This register allows to control downstream devices and line cards.
11783  */
11784 #define MLXSW_REG_MDDC_ID 0x9163
11785 #define MLXSW_REG_MDDC_LEN 0x30
11786 
11787 MLXSW_REG_DEFINE(mddc, MLXSW_REG_MDDC_ID, MLXSW_REG_MDDC_LEN);
11788 
11789 /* reg_mddc_slot_index
11790  * Slot index. 0 is reserved.
11791  * Access: Index
11792  */
11793 MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4);
11794 
11795 /* reg_mddc_rst
11796  * Reset request.
11797  * Access: OP
11798  */
11799 MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1);
11800 
11801 /* reg_mddc_device_enable
11802  * When set, FW is the manager and allowed to program the downstream device.
11803  * Access: RW
11804  */
11805 MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1);
11806 
11807 static inline void mlxsw_reg_mddc_pack(char *payload, u8 slot_index, bool rst,
11808 				       bool device_enable)
11809 {
11810 	MLXSW_REG_ZERO(mddc, payload);
11811 	mlxsw_reg_mddc_slot_index_set(payload, slot_index);
11812 	mlxsw_reg_mddc_rst_set(payload, rst);
11813 	mlxsw_reg_mddc_device_enable_set(payload, device_enable);
11814 }
11815 
11816 /* MFDE - Monitoring FW Debug Register
11817  * -----------------------------------
11818  */
11819 #define MLXSW_REG_MFDE_ID 0x9200
11820 #define MLXSW_REG_MFDE_LEN 0x30
11821 
11822 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN);
11823 
11824 /* reg_mfde_irisc_id
11825  * Which irisc triggered the event
11826  * Access: RO
11827  */
11828 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8);
11829 
11830 enum mlxsw_reg_mfde_severity {
11831 	/* Unrecoverable switch behavior */
11832 	MLXSW_REG_MFDE_SEVERITY_FATL = 2,
11833 	/* Unexpected state with possible systemic failure */
11834 	MLXSW_REG_MFDE_SEVERITY_NRML = 3,
11835 	/* Unexpected state without systemic failure */
11836 	MLXSW_REG_MFDE_SEVERITY_INTR = 5,
11837 };
11838 
11839 /* reg_mfde_severity
11840  * The severity of the event.
11841  * Access: RO
11842  */
11843 MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8);
11844 
11845 enum mlxsw_reg_mfde_event_id {
11846 	/* CRspace timeout */
11847 	MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1,
11848 	/* KVD insertion machine stopped */
11849 	MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP,
11850 	/* Triggered by MFGD.trigger_test */
11851 	MLXSW_REG_MFDE_EVENT_ID_TEST,
11852 	/* Triggered when firmware hits an assert */
11853 	MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT,
11854 	/* Fatal error interrupt from hardware */
11855 	MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE,
11856 };
11857 
11858 /* reg_mfde_event_id
11859  * Access: RO
11860  */
11861 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16);
11862 
11863 enum mlxsw_reg_mfde_method {
11864 	MLXSW_REG_MFDE_METHOD_QUERY,
11865 	MLXSW_REG_MFDE_METHOD_WRITE,
11866 };
11867 
11868 /* reg_mfde_method
11869  * Access: RO
11870  */
11871 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1);
11872 
11873 /* reg_mfde_long_process
11874  * Indicates if the command is in long_process mode.
11875  * Access: RO
11876  */
11877 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1);
11878 
11879 enum mlxsw_reg_mfde_command_type {
11880 	MLXSW_REG_MFDE_COMMAND_TYPE_MAD,
11881 	MLXSW_REG_MFDE_COMMAND_TYPE_EMAD,
11882 	MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF,
11883 };
11884 
11885 /* reg_mfde_command_type
11886  * Access: RO
11887  */
11888 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2);
11889 
11890 /* reg_mfde_reg_attr_id
11891  * EMAD - register id, MAD - attibute id
11892  * Access: RO
11893  */
11894 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16);
11895 
11896 /* reg_mfde_crspace_to_log_address
11897  * crspace address accessed, which resulted in timeout.
11898  * Access: RO
11899  */
11900 MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32);
11901 
11902 /* reg_mfde_crspace_to_oe
11903  * 0 - New event
11904  * 1 - Old event, occurred before MFGD activation.
11905  * Access: RO
11906  */
11907 MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1);
11908 
11909 /* reg_mfde_crspace_to_log_id
11910  * Which irisc triggered the timeout.
11911  * Access: RO
11912  */
11913 MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4);
11914 
11915 /* reg_mfde_crspace_to_log_ip
11916  * IP (instruction pointer) that triggered the timeout.
11917  * Access: RO
11918  */
11919 MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64);
11920 
11921 /* reg_mfde_kvd_im_stop_oe
11922  * 0 - New event
11923  * 1 - Old event, occurred before MFGD activation.
11924  * Access: RO
11925  */
11926 MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1);
11927 
11928 /* reg_mfde_kvd_im_stop_pipes_mask
11929  * Bit per kvh pipe.
11930  * Access: RO
11931  */
11932 MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16);
11933 
11934 /* reg_mfde_fw_assert_var0-4
11935  * Variables passed to assert.
11936  * Access: RO
11937  */
11938 MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32);
11939 MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32);
11940 MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32);
11941 MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32);
11942 MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32);
11943 
11944 /* reg_mfde_fw_assert_existptr
11945  * The instruction pointer when assert was triggered.
11946  * Access: RO
11947  */
11948 MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32);
11949 
11950 /* reg_mfde_fw_assert_callra
11951  * The return address after triggering assert.
11952  * Access: RO
11953  */
11954 MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32);
11955 
11956 /* reg_mfde_fw_assert_oe
11957  * 0 - New event
11958  * 1 - Old event, occurred before MFGD activation.
11959  * Access: RO
11960  */
11961 MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1);
11962 
11963 /* reg_mfde_fw_assert_tile_v
11964  * 0: The assert was from main
11965  * 1: The assert was from a tile
11966  * Access: RO
11967  */
11968 MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1);
11969 
11970 /* reg_mfde_fw_assert_tile_index
11971  * When tile_v=1, the tile_index that caused the assert.
11972  * Access: RO
11973  */
11974 MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6);
11975 
11976 /* reg_mfde_fw_assert_ext_synd
11977  * A generated one-to-one identifier which is specific per-assert.
11978  * Access: RO
11979  */
11980 MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16);
11981 
11982 /* reg_mfde_fatal_cause_id
11983  * HW interrupt cause id.
11984  * Access: RO
11985  */
11986 MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18);
11987 
11988 /* reg_mfde_fatal_cause_tile_v
11989  * 0: The assert was from main
11990  * 1: The assert was from a tile
11991  * Access: RO
11992  */
11993 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1);
11994 
11995 /* reg_mfde_fatal_cause_tile_index
11996  * When tile_v=1, the tile_index that caused the assert.
11997  * Access: RO
11998  */
11999 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6);
12000 
12001 /* TNGCR - Tunneling NVE General Configuration Register
12002  * ----------------------------------------------------
12003  * The TNGCR register is used for setting up the NVE Tunneling configuration.
12004  */
12005 #define MLXSW_REG_TNGCR_ID 0xA001
12006 #define MLXSW_REG_TNGCR_LEN 0x44
12007 
12008 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
12009 
12010 enum mlxsw_reg_tngcr_type {
12011 	MLXSW_REG_TNGCR_TYPE_VXLAN,
12012 	MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
12013 	MLXSW_REG_TNGCR_TYPE_GENEVE,
12014 	MLXSW_REG_TNGCR_TYPE_NVGRE,
12015 };
12016 
12017 /* reg_tngcr_type
12018  * Tunnel type for encapsulation and decapsulation. The types are mutually
12019  * exclusive.
12020  * Note: For Spectrum the NVE parsing must be enabled in MPRS.
12021  * Access: RW
12022  */
12023 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
12024 
12025 /* reg_tngcr_nve_valid
12026  * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation.
12027  * Access: RW
12028  */
12029 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
12030 
12031 /* reg_tngcr_nve_ttl_uc
12032  * The TTL for NVE tunnel encapsulation underlay unicast packets.
12033  * Access: RW
12034  */
12035 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
12036 
12037 /* reg_tngcr_nve_ttl_mc
12038  * The TTL for NVE tunnel encapsulation underlay multicast packets.
12039  * Access: RW
12040  */
12041 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
12042 
12043 enum {
12044 	/* Do not copy flow label. Calculate flow label using nve_flh. */
12045 	MLXSW_REG_TNGCR_FL_NO_COPY,
12046 	/* Copy flow label from inner packet if packet is IPv6 and
12047 	 * encapsulation is by IPv6. Otherwise, calculate flow label using
12048 	 * nve_flh.
12049 	 */
12050 	MLXSW_REG_TNGCR_FL_COPY,
12051 };
12052 
12053 /* reg_tngcr_nve_flc
12054  * For NVE tunnel encapsulation: Flow label copy from inner packet.
12055  * Access: RW
12056  */
12057 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
12058 
12059 enum {
12060 	/* Flow label is static. In Spectrum this means '0'. Spectrum-2
12061 	 * uses {nve_fl_prefix, nve_fl_suffix}.
12062 	 */
12063 	MLXSW_REG_TNGCR_FL_NO_HASH,
12064 	/* 8 LSBs of the flow label are calculated from ECMP hash of the
12065 	 * inner packet. 12 MSBs are configured by nve_fl_prefix.
12066 	 */
12067 	MLXSW_REG_TNGCR_FL_HASH,
12068 };
12069 
12070 /* reg_tngcr_nve_flh
12071  * NVE flow label hash.
12072  * Access: RW
12073  */
12074 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
12075 
12076 /* reg_tngcr_nve_fl_prefix
12077  * NVE flow label prefix. Constant 12 MSBs of the flow label.
12078  * Access: RW
12079  */
12080 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
12081 
12082 /* reg_tngcr_nve_fl_suffix
12083  * NVE flow label suffix. Constant 8 LSBs of the flow label.
12084  * Reserved when nve_flh=1 and for Spectrum.
12085  * Access: RW
12086  */
12087 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
12088 
12089 enum {
12090 	/* Source UDP port is fixed (default '0') */
12091 	MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
12092 	/* Source UDP port is calculated based on hash */
12093 	MLXSW_REG_TNGCR_UDP_SPORT_HASH,
12094 };
12095 
12096 /* reg_tngcr_nve_udp_sport_type
12097  * NVE UDP source port type.
12098  * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2).
12099  * When the source UDP port is calculated based on hash, then the 8 LSBs
12100  * are calculated from hash the 8 MSBs are configured by
12101  * nve_udp_sport_prefix.
12102  * Access: RW
12103  */
12104 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
12105 
12106 /* reg_tngcr_nve_udp_sport_prefix
12107  * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port.
12108  * Reserved when NVE type is NVGRE.
12109  * Access: RW
12110  */
12111 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
12112 
12113 /* reg_tngcr_nve_group_size_mc
12114  * The amount of sequential linked lists of MC entries. The first linked
12115  * list is configured by SFD.underlay_mc_ptr.
12116  * Valid values: 1, 2, 4, 8, 16, 32, 64
12117  * The linked list are configured by TNUMT.
12118  * The hash is set by LAG hash.
12119  * Access: RW
12120  */
12121 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
12122 
12123 /* reg_tngcr_nve_group_size_flood
12124  * The amount of sequential linked lists of flooding entries. The first
12125  * linked list is configured by SFMR.nve_tunnel_flood_ptr
12126  * Valid values: 1, 2, 4, 8, 16, 32, 64
12127  * The linked list are configured by TNUMT.
12128  * The hash is set by LAG hash.
12129  * Access: RW
12130  */
12131 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
12132 
12133 /* reg_tngcr_learn_enable
12134  * During decapsulation, whether to learn from NVE port.
12135  * Reserved when Spectrum-2. See TNPC.
12136  * Access: RW
12137  */
12138 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
12139 
12140 /* reg_tngcr_underlay_virtual_router
12141  * Underlay virtual router.
12142  * Reserved when Spectrum-2.
12143  * Access: RW
12144  */
12145 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
12146 
12147 /* reg_tngcr_underlay_rif
12148  * Underlay ingress router interface. RIF type should be loopback generic.
12149  * Reserved when Spectrum.
12150  * Access: RW
12151  */
12152 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
12153 
12154 /* reg_tngcr_usipv4
12155  * Underlay source IPv4 address of the NVE.
12156  * Access: RW
12157  */
12158 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
12159 
12160 /* reg_tngcr_usipv6
12161  * Underlay source IPv6 address of the NVE. For Spectrum, must not be
12162  * modified under traffic of NVE tunneling encapsulation.
12163  * Access: RW
12164  */
12165 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
12166 
12167 static inline void mlxsw_reg_tngcr_pack(char *payload,
12168 					enum mlxsw_reg_tngcr_type type,
12169 					bool valid, u8 ttl)
12170 {
12171 	MLXSW_REG_ZERO(tngcr, payload);
12172 	mlxsw_reg_tngcr_type_set(payload, type);
12173 	mlxsw_reg_tngcr_nve_valid_set(payload, valid);
12174 	mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
12175 	mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
12176 	mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
12177 	mlxsw_reg_tngcr_nve_flh_set(payload, 0);
12178 	mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
12179 					       MLXSW_REG_TNGCR_UDP_SPORT_HASH);
12180 	mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
12181 	mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
12182 	mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
12183 }
12184 
12185 /* TNUMT - Tunneling NVE Underlay Multicast Table Register
12186  * -------------------------------------------------------
12187  * The TNUMT register is for building the underlay MC table. It is used
12188  * for MC, flooding and BC traffic into the NVE tunnel.
12189  */
12190 #define MLXSW_REG_TNUMT_ID 0xA003
12191 #define MLXSW_REG_TNUMT_LEN 0x20
12192 
12193 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);
12194 
12195 enum mlxsw_reg_tnumt_record_type {
12196 	MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,
12197 	MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,
12198 	MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,
12199 };
12200 
12201 /* reg_tnumt_record_type
12202  * Record type.
12203  * Access: RW
12204  */
12205 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
12206 
12207 /* reg_tnumt_tunnel_port
12208  * Tunnel port.
12209  * Access: RW
12210  */
12211 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
12212 
12213 /* reg_tnumt_underlay_mc_ptr
12214  * Index to the underlay multicast table.
12215  * For Spectrum the index is to the KVD linear.
12216  * Access: Index
12217  */
12218 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
12219 
12220 /* reg_tnumt_vnext
12221  * The next_underlay_mc_ptr is valid.
12222  * Access: RW
12223  */
12224 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
12225 
12226 /* reg_tnumt_next_underlay_mc_ptr
12227  * The next index to the underlay multicast table.
12228  * Access: RW
12229  */
12230 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
12231 
12232 /* reg_tnumt_record_size
12233  * Number of IP addresses in the record.
12234  * Range is 1..cap_max_nve_mc_entries_ipv{4,6}
12235  * Access: RW
12236  */
12237 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
12238 
12239 /* reg_tnumt_udip
12240  * The underlay IPv4 addresses. udip[i] is reserved if i >= size
12241  * Access: RW
12242  */
12243 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
12244 
12245 /* reg_tnumt_udip_ptr
12246  * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if
12247  * i >= size. The IPv6 addresses are configured by RIPS.
12248  * Access: RW
12249  */
12250 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
12251 
12252 static inline void mlxsw_reg_tnumt_pack(char *payload,
12253 					enum mlxsw_reg_tnumt_record_type type,
12254 					enum mlxsw_reg_tunnel_port tport,
12255 					u32 underlay_mc_ptr, bool vnext,
12256 					u32 next_underlay_mc_ptr,
12257 					u8 record_size)
12258 {
12259 	MLXSW_REG_ZERO(tnumt, payload);
12260 	mlxsw_reg_tnumt_record_type_set(payload, type);
12261 	mlxsw_reg_tnumt_tunnel_port_set(payload, tport);
12262 	mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);
12263 	mlxsw_reg_tnumt_vnext_set(payload, vnext);
12264 	mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);
12265 	mlxsw_reg_tnumt_record_size_set(payload, record_size);
12266 }
12267 
12268 /* TNQCR - Tunneling NVE QoS Configuration Register
12269  * ------------------------------------------------
12270  * The TNQCR register configures how QoS is set in encapsulation into the
12271  * underlay network.
12272  */
12273 #define MLXSW_REG_TNQCR_ID 0xA010
12274 #define MLXSW_REG_TNQCR_LEN 0x0C
12275 
12276 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);
12277 
12278 /* reg_tnqcr_enc_set_dscp
12279  * For encapsulation: How to set DSCP field:
12280  * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay
12281  * (outer) IP header. If there is no IP header, use TNQDR.dscp
12282  * 1 - Set the DSCP field as TNQDR.dscp
12283  * Access: RW
12284  */
12285 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
12286 
12287 static inline void mlxsw_reg_tnqcr_pack(char *payload)
12288 {
12289 	MLXSW_REG_ZERO(tnqcr, payload);
12290 	mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
12291 }
12292 
12293 /* TNQDR - Tunneling NVE QoS Default Register
12294  * ------------------------------------------
12295  * The TNQDR register configures the default QoS settings for NVE
12296  * encapsulation.
12297  */
12298 #define MLXSW_REG_TNQDR_ID 0xA011
12299 #define MLXSW_REG_TNQDR_LEN 0x08
12300 
12301 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
12302 
12303 /* reg_tnqdr_local_port
12304  * Local port number (receive port). CPU port is supported.
12305  * Access: Index
12306  */
12307 MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12);
12308 
12309 /* reg_tnqdr_dscp
12310  * For encapsulation, the default DSCP.
12311  * Access: RW
12312  */
12313 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
12314 
12315 static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port)
12316 {
12317 	MLXSW_REG_ZERO(tnqdr, payload);
12318 	mlxsw_reg_tnqdr_local_port_set(payload, local_port);
12319 	mlxsw_reg_tnqdr_dscp_set(payload, 0);
12320 }
12321 
12322 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register
12323  * --------------------------------------------------------
12324  * The TNEEM register maps ECN of the IP header at the ingress to the
12325  * encapsulation to the ECN of the underlay network.
12326  */
12327 #define MLXSW_REG_TNEEM_ID 0xA012
12328 #define MLXSW_REG_TNEEM_LEN 0x0C
12329 
12330 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);
12331 
12332 /* reg_tneem_overlay_ecn
12333  * ECN of the IP header in the overlay network.
12334  * Access: Index
12335  */
12336 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
12337 
12338 /* reg_tneem_underlay_ecn
12339  * ECN of the IP header in the underlay network.
12340  * Access: RW
12341  */
12342 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
12343 
12344 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,
12345 					u8 underlay_ecn)
12346 {
12347 	MLXSW_REG_ZERO(tneem, payload);
12348 	mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);
12349 	mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);
12350 }
12351 
12352 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register
12353  * --------------------------------------------------------
12354  * The TNDEM register configures the actions that are done in the
12355  * decapsulation.
12356  */
12357 #define MLXSW_REG_TNDEM_ID 0xA013
12358 #define MLXSW_REG_TNDEM_LEN 0x0C
12359 
12360 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);
12361 
12362 /* reg_tndem_underlay_ecn
12363  * ECN field of the IP header in the underlay network.
12364  * Access: Index
12365  */
12366 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
12367 
12368 /* reg_tndem_overlay_ecn
12369  * ECN field of the IP header in the overlay network.
12370  * Access: Index
12371  */
12372 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
12373 
12374 /* reg_tndem_eip_ecn
12375  * Egress IP ECN. ECN field of the IP header of the packet which goes out
12376  * from the decapsulation.
12377  * Access: RW
12378  */
12379 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
12380 
12381 /* reg_tndem_trap_en
12382  * Trap enable:
12383  * 0 - No trap due to decap ECN
12384  * 1 - Trap enable with trap_id
12385  * Access: RW
12386  */
12387 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
12388 
12389 /* reg_tndem_trap_id
12390  * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
12391  * Reserved when trap_en is '0'.
12392  * Access: RW
12393  */
12394 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
12395 
12396 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
12397 					u8 overlay_ecn, u8 ecn, bool trap_en,
12398 					u16 trap_id)
12399 {
12400 	MLXSW_REG_ZERO(tndem, payload);
12401 	mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);
12402 	mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);
12403 	mlxsw_reg_tndem_eip_ecn_set(payload, ecn);
12404 	mlxsw_reg_tndem_trap_en_set(payload, trap_en);
12405 	mlxsw_reg_tndem_trap_id_set(payload, trap_id);
12406 }
12407 
12408 /* TNPC - Tunnel Port Configuration Register
12409  * -----------------------------------------
12410  * The TNPC register is used for tunnel port configuration.
12411  * Reserved when Spectrum.
12412  */
12413 #define MLXSW_REG_TNPC_ID 0xA020
12414 #define MLXSW_REG_TNPC_LEN 0x18
12415 
12416 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
12417 
12418 /* reg_tnpc_tunnel_port
12419  * Tunnel port.
12420  * Access: Index
12421  */
12422 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
12423 
12424 /* reg_tnpc_learn_enable_v6
12425  * During IPv6 underlay decapsulation, whether to learn from tunnel port.
12426  * Access: RW
12427  */
12428 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
12429 
12430 /* reg_tnpc_learn_enable_v4
12431  * During IPv4 underlay decapsulation, whether to learn from tunnel port.
12432  * Access: RW
12433  */
12434 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
12435 
12436 static inline void mlxsw_reg_tnpc_pack(char *payload,
12437 				       enum mlxsw_reg_tunnel_port tport,
12438 				       bool learn_enable)
12439 {
12440 	MLXSW_REG_ZERO(tnpc, payload);
12441 	mlxsw_reg_tnpc_tunnel_port_set(payload, tport);
12442 	mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);
12443 	mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);
12444 }
12445 
12446 /* TIGCR - Tunneling IPinIP General Configuration Register
12447  * -------------------------------------------------------
12448  * The TIGCR register is used for setting up the IPinIP Tunnel configuration.
12449  */
12450 #define MLXSW_REG_TIGCR_ID 0xA801
12451 #define MLXSW_REG_TIGCR_LEN 0x10
12452 
12453 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
12454 
12455 /* reg_tigcr_ipip_ttlc
12456  * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet
12457  * header.
12458  * Access: RW
12459  */
12460 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
12461 
12462 /* reg_tigcr_ipip_ttl_uc
12463  * The TTL for IPinIP Tunnel encapsulation of unicast packets if
12464  * reg_tigcr_ipip_ttlc is unset.
12465  * Access: RW
12466  */
12467 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
12468 
12469 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
12470 {
12471 	MLXSW_REG_ZERO(tigcr, payload);
12472 	mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
12473 	mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
12474 }
12475 
12476 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register
12477  * -----------------------------------------------------------
12478  * The TIEEM register maps ECN of the IP header at the ingress to the
12479  * encapsulation to the ECN of the underlay network.
12480  */
12481 #define MLXSW_REG_TIEEM_ID 0xA812
12482 #define MLXSW_REG_TIEEM_LEN 0x0C
12483 
12484 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN);
12485 
12486 /* reg_tieem_overlay_ecn
12487  * ECN of the IP header in the overlay network.
12488  * Access: Index
12489  */
12490 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2);
12491 
12492 /* reg_tineem_underlay_ecn
12493  * ECN of the IP header in the underlay network.
12494  * Access: RW
12495  */
12496 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2);
12497 
12498 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn,
12499 					u8 underlay_ecn)
12500 {
12501 	MLXSW_REG_ZERO(tieem, payload);
12502 	mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn);
12503 	mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn);
12504 }
12505 
12506 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register
12507  * -----------------------------------------------------------
12508  * The TIDEM register configures the actions that are done in the
12509  * decapsulation.
12510  */
12511 #define MLXSW_REG_TIDEM_ID 0xA813
12512 #define MLXSW_REG_TIDEM_LEN 0x0C
12513 
12514 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN);
12515 
12516 /* reg_tidem_underlay_ecn
12517  * ECN field of the IP header in the underlay network.
12518  * Access: Index
12519  */
12520 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2);
12521 
12522 /* reg_tidem_overlay_ecn
12523  * ECN field of the IP header in the overlay network.
12524  * Access: Index
12525  */
12526 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2);
12527 
12528 /* reg_tidem_eip_ecn
12529  * Egress IP ECN. ECN field of the IP header of the packet which goes out
12530  * from the decapsulation.
12531  * Access: RW
12532  */
12533 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2);
12534 
12535 /* reg_tidem_trap_en
12536  * Trap enable:
12537  * 0 - No trap due to decap ECN
12538  * 1 - Trap enable with trap_id
12539  * Access: RW
12540  */
12541 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4);
12542 
12543 /* reg_tidem_trap_id
12544  * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
12545  * Reserved when trap_en is '0'.
12546  * Access: RW
12547  */
12548 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9);
12549 
12550 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn,
12551 					u8 overlay_ecn, u8 eip_ecn,
12552 					bool trap_en, u16 trap_id)
12553 {
12554 	MLXSW_REG_ZERO(tidem, payload);
12555 	mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn);
12556 	mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn);
12557 	mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn);
12558 	mlxsw_reg_tidem_trap_en_set(payload, trap_en);
12559 	mlxsw_reg_tidem_trap_id_set(payload, trap_id);
12560 }
12561 
12562 /* SBPR - Shared Buffer Pools Register
12563  * -----------------------------------
12564  * The SBPR configures and retrieves the shared buffer pools and configuration.
12565  */
12566 #define MLXSW_REG_SBPR_ID 0xB001
12567 #define MLXSW_REG_SBPR_LEN 0x14
12568 
12569 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
12570 
12571 /* reg_sbpr_desc
12572  * When set, configures descriptor buffer.
12573  * Access: Index
12574  */
12575 MLXSW_ITEM32(reg, sbpr, desc, 0x00, 31, 1);
12576 
12577 /* shared direstion enum for SBPR, SBCM, SBPM */
12578 enum mlxsw_reg_sbxx_dir {
12579 	MLXSW_REG_SBXX_DIR_INGRESS,
12580 	MLXSW_REG_SBXX_DIR_EGRESS,
12581 };
12582 
12583 /* reg_sbpr_dir
12584  * Direction.
12585  * Access: Index
12586  */
12587 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
12588 
12589 /* reg_sbpr_pool
12590  * Pool index.
12591  * Access: Index
12592  */
12593 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
12594 
12595 /* reg_sbpr_infi_size
12596  * Size is infinite.
12597  * Access: RW
12598  */
12599 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
12600 
12601 /* reg_sbpr_size
12602  * Pool size in buffer cells.
12603  * Reserved when infi_size = 1.
12604  * Access: RW
12605  */
12606 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
12607 
12608 enum mlxsw_reg_sbpr_mode {
12609 	MLXSW_REG_SBPR_MODE_STATIC,
12610 	MLXSW_REG_SBPR_MODE_DYNAMIC,
12611 };
12612 
12613 /* reg_sbpr_mode
12614  * Pool quota calculation mode.
12615  * Access: RW
12616  */
12617 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
12618 
12619 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
12620 				       enum mlxsw_reg_sbxx_dir dir,
12621 				       enum mlxsw_reg_sbpr_mode mode, u32 size,
12622 				       bool infi_size)
12623 {
12624 	MLXSW_REG_ZERO(sbpr, payload);
12625 	mlxsw_reg_sbpr_pool_set(payload, pool);
12626 	mlxsw_reg_sbpr_dir_set(payload, dir);
12627 	mlxsw_reg_sbpr_mode_set(payload, mode);
12628 	mlxsw_reg_sbpr_size_set(payload, size);
12629 	mlxsw_reg_sbpr_infi_size_set(payload, infi_size);
12630 }
12631 
12632 /* SBCM - Shared Buffer Class Management Register
12633  * ----------------------------------------------
12634  * The SBCM register configures and retrieves the shared buffer allocation
12635  * and configuration according to Port-PG, including the binding to pool
12636  * and definition of the associated quota.
12637  */
12638 #define MLXSW_REG_SBCM_ID 0xB002
12639 #define MLXSW_REG_SBCM_LEN 0x28
12640 
12641 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
12642 
12643 /* reg_sbcm_local_port
12644  * Local port number.
12645  * For Ingress: excludes CPU port and Router port
12646  * For Egress: excludes IP Router
12647  * Access: Index
12648  */
12649 MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4);
12650 
12651 /* reg_sbcm_pg_buff
12652  * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
12653  * For PG buffer: range is 0..cap_max_pg_buffers - 1
12654  * For traffic class: range is 0..cap_max_tclass - 1
12655  * Note that when traffic class is in MC aware mode then the traffic
12656  * classes which are MC aware cannot be configured.
12657  * Access: Index
12658  */
12659 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
12660 
12661 /* reg_sbcm_dir
12662  * Direction.
12663  * Access: Index
12664  */
12665 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
12666 
12667 /* reg_sbcm_min_buff
12668  * Minimum buffer size for the limiter, in cells.
12669  * Access: RW
12670  */
12671 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
12672 
12673 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
12674 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
12675 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
12676 
12677 /* reg_sbcm_infi_max
12678  * Max buffer is infinite.
12679  * Access: RW
12680  */
12681 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
12682 
12683 /* reg_sbcm_max_buff
12684  * When the pool associated to the port-pg/tclass is configured to
12685  * static, Maximum buffer size for the limiter configured in cells.
12686  * When the pool associated to the port-pg/tclass is configured to
12687  * dynamic, the max_buff holds the "alpha" parameter, supporting
12688  * the following values:
12689  * 0: 0
12690  * i: (1/128)*2^(i-1), for i=1..14
12691  * 0xFF: Infinity
12692  * Reserved when infi_max = 1.
12693  * Access: RW
12694  */
12695 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
12696 
12697 /* reg_sbcm_pool
12698  * Association of the port-priority to a pool.
12699  * Access: RW
12700  */
12701 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
12702 
12703 static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff,
12704 				       enum mlxsw_reg_sbxx_dir dir,
12705 				       u32 min_buff, u32 max_buff,
12706 				       bool infi_max, u8 pool)
12707 {
12708 	MLXSW_REG_ZERO(sbcm, payload);
12709 	mlxsw_reg_sbcm_local_port_set(payload, local_port);
12710 	mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
12711 	mlxsw_reg_sbcm_dir_set(payload, dir);
12712 	mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
12713 	mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
12714 	mlxsw_reg_sbcm_infi_max_set(payload, infi_max);
12715 	mlxsw_reg_sbcm_pool_set(payload, pool);
12716 }
12717 
12718 /* SBPM - Shared Buffer Port Management Register
12719  * ---------------------------------------------
12720  * The SBPM register configures and retrieves the shared buffer allocation
12721  * and configuration according to Port-Pool, including the definition
12722  * of the associated quota.
12723  */
12724 #define MLXSW_REG_SBPM_ID 0xB003
12725 #define MLXSW_REG_SBPM_LEN 0x28
12726 
12727 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
12728 
12729 /* reg_sbpm_local_port
12730  * Local port number.
12731  * For Ingress: excludes CPU port and Router port
12732  * For Egress: excludes IP Router
12733  * Access: Index
12734  */
12735 MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12);
12736 
12737 /* reg_sbpm_pool
12738  * The pool associated to quota counting on the local_port.
12739  * Access: Index
12740  */
12741 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
12742 
12743 /* reg_sbpm_dir
12744  * Direction.
12745  * Access: Index
12746  */
12747 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
12748 
12749 /* reg_sbpm_buff_occupancy
12750  * Current buffer occupancy in cells.
12751  * Access: RO
12752  */
12753 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
12754 
12755 /* reg_sbpm_clr
12756  * Clear Max Buffer Occupancy
12757  * When this bit is set, max_buff_occupancy field is cleared (and a
12758  * new max value is tracked from the time the clear was performed).
12759  * Access: OP
12760  */
12761 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
12762 
12763 /* reg_sbpm_max_buff_occupancy
12764  * Maximum value of buffer occupancy in cells monitored. Cleared by
12765  * writing to the clr field.
12766  * Access: RO
12767  */
12768 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
12769 
12770 /* reg_sbpm_min_buff
12771  * Minimum buffer size for the limiter, in cells.
12772  * Access: RW
12773  */
12774 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
12775 
12776 /* reg_sbpm_max_buff
12777  * When the pool associated to the port-pg/tclass is configured to
12778  * static, Maximum buffer size for the limiter configured in cells.
12779  * When the pool associated to the port-pg/tclass is configured to
12780  * dynamic, the max_buff holds the "alpha" parameter, supporting
12781  * the following values:
12782  * 0: 0
12783  * i: (1/128)*2^(i-1), for i=1..14
12784  * 0xFF: Infinity
12785  * Access: RW
12786  */
12787 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
12788 
12789 static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool,
12790 				       enum mlxsw_reg_sbxx_dir dir, bool clr,
12791 				       u32 min_buff, u32 max_buff)
12792 {
12793 	MLXSW_REG_ZERO(sbpm, payload);
12794 	mlxsw_reg_sbpm_local_port_set(payload, local_port);
12795 	mlxsw_reg_sbpm_pool_set(payload, pool);
12796 	mlxsw_reg_sbpm_dir_set(payload, dir);
12797 	mlxsw_reg_sbpm_clr_set(payload, clr);
12798 	mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
12799 	mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
12800 }
12801 
12802 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
12803 					 u32 *p_max_buff_occupancy)
12804 {
12805 	*p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
12806 	*p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
12807 }
12808 
12809 /* SBMM - Shared Buffer Multicast Management Register
12810  * --------------------------------------------------
12811  * The SBMM register configures and retrieves the shared buffer allocation
12812  * and configuration for MC packets according to Switch-Priority, including
12813  * the binding to pool and definition of the associated quota.
12814  */
12815 #define MLXSW_REG_SBMM_ID 0xB004
12816 #define MLXSW_REG_SBMM_LEN 0x28
12817 
12818 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
12819 
12820 /* reg_sbmm_prio
12821  * Switch Priority.
12822  * Access: Index
12823  */
12824 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
12825 
12826 /* reg_sbmm_min_buff
12827  * Minimum buffer size for the limiter, in cells.
12828  * Access: RW
12829  */
12830 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
12831 
12832 /* reg_sbmm_max_buff
12833  * When the pool associated to the port-pg/tclass is configured to
12834  * static, Maximum buffer size for the limiter configured in cells.
12835  * When the pool associated to the port-pg/tclass is configured to
12836  * dynamic, the max_buff holds the "alpha" parameter, supporting
12837  * the following values:
12838  * 0: 0
12839  * i: (1/128)*2^(i-1), for i=1..14
12840  * 0xFF: Infinity
12841  * Access: RW
12842  */
12843 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
12844 
12845 /* reg_sbmm_pool
12846  * Association of the port-priority to a pool.
12847  * Access: RW
12848  */
12849 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
12850 
12851 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
12852 				       u32 max_buff, u8 pool)
12853 {
12854 	MLXSW_REG_ZERO(sbmm, payload);
12855 	mlxsw_reg_sbmm_prio_set(payload, prio);
12856 	mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
12857 	mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
12858 	mlxsw_reg_sbmm_pool_set(payload, pool);
12859 }
12860 
12861 /* SBSR - Shared Buffer Status Register
12862  * ------------------------------------
12863  * The SBSR register retrieves the shared buffer occupancy according to
12864  * Port-Pool. Note that this register enables reading a large amount of data.
12865  * It is the user's responsibility to limit the amount of data to ensure the
12866  * response can match the maximum transfer unit. In case the response exceeds
12867  * the maximum transport unit, it will be truncated with no special notice.
12868  */
12869 #define MLXSW_REG_SBSR_ID 0xB005
12870 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
12871 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
12872 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
12873 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN +	\
12874 			    MLXSW_REG_SBSR_REC_LEN *	\
12875 			    MLXSW_REG_SBSR_REC_MAX_COUNT)
12876 
12877 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
12878 
12879 /* reg_sbsr_clr
12880  * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
12881  * field is cleared (and a new max value is tracked from the time the clear
12882  * was performed).
12883  * Access: OP
12884  */
12885 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
12886 
12887 #define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256
12888 
12889 /* reg_sbsr_port_page
12890  * Determines the range of the ports specified in the 'ingress_port_mask'
12891  * and 'egress_port_mask' bit masks.
12892  * {ingress,egress}_port_mask[x] is (256 * port_page) + x
12893  * Access: Index
12894  */
12895 MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4);
12896 
12897 /* reg_sbsr_ingress_port_mask
12898  * Bit vector for all ingress network ports.
12899  * Indicates which of the ports (for which the relevant bit is set)
12900  * are affected by the set operation. Configuration of any other port
12901  * does not change.
12902  * Access: Index
12903  */
12904 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
12905 
12906 /* reg_sbsr_pg_buff_mask
12907  * Bit vector for all switch priority groups.
12908  * Indicates which of the priorities (for which the relevant bit is set)
12909  * are affected by the set operation. Configuration of any other priority
12910  * does not change.
12911  * Range is 0..cap_max_pg_buffers - 1
12912  * Access: Index
12913  */
12914 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
12915 
12916 /* reg_sbsr_egress_port_mask
12917  * Bit vector for all egress network ports.
12918  * Indicates which of the ports (for which the relevant bit is set)
12919  * are affected by the set operation. Configuration of any other port
12920  * does not change.
12921  * Access: Index
12922  */
12923 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
12924 
12925 /* reg_sbsr_tclass_mask
12926  * Bit vector for all traffic classes.
12927  * Indicates which of the traffic classes (for which the relevant bit is
12928  * set) are affected by the set operation. Configuration of any other
12929  * traffic class does not change.
12930  * Range is 0..cap_max_tclass - 1
12931  * Access: Index
12932  */
12933 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
12934 
12935 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
12936 {
12937 	MLXSW_REG_ZERO(sbsr, payload);
12938 	mlxsw_reg_sbsr_clr_set(payload, clr);
12939 }
12940 
12941 /* reg_sbsr_rec_buff_occupancy
12942  * Current buffer occupancy in cells.
12943  * Access: RO
12944  */
12945 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
12946 		     0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
12947 
12948 /* reg_sbsr_rec_max_buff_occupancy
12949  * Maximum value of buffer occupancy in cells monitored. Cleared by
12950  * writing to the clr field.
12951  * Access: RO
12952  */
12953 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
12954 		     0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
12955 
12956 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
12957 					     u32 *p_buff_occupancy,
12958 					     u32 *p_max_buff_occupancy)
12959 {
12960 	*p_buff_occupancy =
12961 		mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
12962 	*p_max_buff_occupancy =
12963 		mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
12964 }
12965 
12966 /* SBIB - Shared Buffer Internal Buffer Register
12967  * ---------------------------------------------
12968  * The SBIB register configures per port buffers for internal use. The internal
12969  * buffers consume memory on the port buffers (note that the port buffers are
12970  * used also by PBMC).
12971  *
12972  * For Spectrum this is used for egress mirroring.
12973  */
12974 #define MLXSW_REG_SBIB_ID 0xB006
12975 #define MLXSW_REG_SBIB_LEN 0x10
12976 
12977 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
12978 
12979 /* reg_sbib_local_port
12980  * Local port number
12981  * Not supported for CPU port and router port
12982  * Access: Index
12983  */
12984 MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12);
12985 
12986 /* reg_sbib_buff_size
12987  * Units represented in cells
12988  * Allowed range is 0 to (cap_max_headroom_size - 1)
12989  * Default is 0
12990  * Access: RW
12991  */
12992 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
12993 
12994 static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port,
12995 				       u32 buff_size)
12996 {
12997 	MLXSW_REG_ZERO(sbib, payload);
12998 	mlxsw_reg_sbib_local_port_set(payload, local_port);
12999 	mlxsw_reg_sbib_buff_size_set(payload, buff_size);
13000 }
13001 
13002 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
13003 	MLXSW_REG(sgcr),
13004 	MLXSW_REG(spad),
13005 	MLXSW_REG(sspr),
13006 	MLXSW_REG(sfdat),
13007 	MLXSW_REG(sfd),
13008 	MLXSW_REG(sfn),
13009 	MLXSW_REG(spms),
13010 	MLXSW_REG(spvid),
13011 	MLXSW_REG(spvm),
13012 	MLXSW_REG(spaft),
13013 	MLXSW_REG(sfgc),
13014 	MLXSW_REG(sfdf),
13015 	MLXSW_REG(sldr),
13016 	MLXSW_REG(slcr),
13017 	MLXSW_REG(slcor),
13018 	MLXSW_REG(spmlr),
13019 	MLXSW_REG(svfa),
13020 	MLXSW_REG(spvtr),
13021 	MLXSW_REG(svpe),
13022 	MLXSW_REG(sfmr),
13023 	MLXSW_REG(spvmlr),
13024 	MLXSW_REG(spfsr),
13025 	MLXSW_REG(spvc),
13026 	MLXSW_REG(sffp),
13027 	MLXSW_REG(spevet),
13028 	MLXSW_REG(smpe),
13029 	MLXSW_REG(smid2),
13030 	MLXSW_REG(cwtp),
13031 	MLXSW_REG(cwtpm),
13032 	MLXSW_REG(pgcr),
13033 	MLXSW_REG(ppbt),
13034 	MLXSW_REG(pacl),
13035 	MLXSW_REG(pagt),
13036 	MLXSW_REG(ptar),
13037 	MLXSW_REG(pprr),
13038 	MLXSW_REG(ppbs),
13039 	MLXSW_REG(prcr),
13040 	MLXSW_REG(pefa),
13041 	MLXSW_REG(pemrbt),
13042 	MLXSW_REG(ptce2),
13043 	MLXSW_REG(perpt),
13044 	MLXSW_REG(peabfe),
13045 	MLXSW_REG(perar),
13046 	MLXSW_REG(ptce3),
13047 	MLXSW_REG(percr),
13048 	MLXSW_REG(pererp),
13049 	MLXSW_REG(iedr),
13050 	MLXSW_REG(qpts),
13051 	MLXSW_REG(qpcr),
13052 	MLXSW_REG(qtct),
13053 	MLXSW_REG(qeec),
13054 	MLXSW_REG(qrwe),
13055 	MLXSW_REG(qpdsm),
13056 	MLXSW_REG(qpdp),
13057 	MLXSW_REG(qpdpm),
13058 	MLXSW_REG(qtctm),
13059 	MLXSW_REG(qpsc),
13060 	MLXSW_REG(pmlp),
13061 	MLXSW_REG(pmtu),
13062 	MLXSW_REG(ptys),
13063 	MLXSW_REG(ppad),
13064 	MLXSW_REG(paos),
13065 	MLXSW_REG(pfcc),
13066 	MLXSW_REG(ppcnt),
13067 	MLXSW_REG(pptb),
13068 	MLXSW_REG(pbmc),
13069 	MLXSW_REG(pspa),
13070 	MLXSW_REG(pmaos),
13071 	MLXSW_REG(pplr),
13072 	MLXSW_REG(pmtdb),
13073 	MLXSW_REG(pmecr),
13074 	MLXSW_REG(pmpe),
13075 	MLXSW_REG(pddr),
13076 	MLXSW_REG(pmmp),
13077 	MLXSW_REG(pllp),
13078 	MLXSW_REG(pmtm),
13079 	MLXSW_REG(htgt),
13080 	MLXSW_REG(hpkt),
13081 	MLXSW_REG(rgcr),
13082 	MLXSW_REG(ritr),
13083 	MLXSW_REG(rtar),
13084 	MLXSW_REG(ratr),
13085 	MLXSW_REG(rtdp),
13086 	MLXSW_REG(rips),
13087 	MLXSW_REG(ratrad),
13088 	MLXSW_REG(rdpm),
13089 	MLXSW_REG(ricnt),
13090 	MLXSW_REG(rrcr),
13091 	MLXSW_REG(ralta),
13092 	MLXSW_REG(ralst),
13093 	MLXSW_REG(raltb),
13094 	MLXSW_REG(ralue),
13095 	MLXSW_REG(rauht),
13096 	MLXSW_REG(raleu),
13097 	MLXSW_REG(rauhtd),
13098 	MLXSW_REG(rigr2),
13099 	MLXSW_REG(recr2),
13100 	MLXSW_REG(rmft2),
13101 	MLXSW_REG(reiv),
13102 	MLXSW_REG(mfcr),
13103 	MLXSW_REG(mfsc),
13104 	MLXSW_REG(mfsm),
13105 	MLXSW_REG(mfsl),
13106 	MLXSW_REG(fore),
13107 	MLXSW_REG(mtcap),
13108 	MLXSW_REG(mtmp),
13109 	MLXSW_REG(mtwe),
13110 	MLXSW_REG(mtbr),
13111 	MLXSW_REG(mcia),
13112 	MLXSW_REG(mpat),
13113 	MLXSW_REG(mpar),
13114 	MLXSW_REG(mgir),
13115 	MLXSW_REG(mrsr),
13116 	MLXSW_REG(mlcr),
13117 	MLXSW_REG(mcion),
13118 	MLXSW_REG(mtpps),
13119 	MLXSW_REG(mtutc),
13120 	MLXSW_REG(mcqi),
13121 	MLXSW_REG(mcc),
13122 	MLXSW_REG(mcda),
13123 	MLXSW_REG(mcam),
13124 	MLXSW_REG(mpsc),
13125 	MLXSW_REG(mgpc),
13126 	MLXSW_REG(mprs),
13127 	MLXSW_REG(mogcr),
13128 	MLXSW_REG(mpagr),
13129 	MLXSW_REG(momte),
13130 	MLXSW_REG(mtpppc),
13131 	MLXSW_REG(mtpptr),
13132 	MLXSW_REG(mtptpt),
13133 	MLXSW_REG(mtpcpc),
13134 	MLXSW_REG(mfgd),
13135 	MLXSW_REG(mgpir),
13136 	MLXSW_REG(mbct),
13137 	MLXSW_REG(mddt),
13138 	MLXSW_REG(mddq),
13139 	MLXSW_REG(mddc),
13140 	MLXSW_REG(mfde),
13141 	MLXSW_REG(tngcr),
13142 	MLXSW_REG(tnumt),
13143 	MLXSW_REG(tnqcr),
13144 	MLXSW_REG(tnqdr),
13145 	MLXSW_REG(tneem),
13146 	MLXSW_REG(tndem),
13147 	MLXSW_REG(tnpc),
13148 	MLXSW_REG(tigcr),
13149 	MLXSW_REG(tieem),
13150 	MLXSW_REG(tidem),
13151 	MLXSW_REG(sbpr),
13152 	MLXSW_REG(sbcm),
13153 	MLXSW_REG(sbpm),
13154 	MLXSW_REG(sbmm),
13155 	MLXSW_REG(sbsr),
13156 	MLXSW_REG(sbib),
13157 };
13158 
13159 static inline const char *mlxsw_reg_id_str(u16 reg_id)
13160 {
13161 	const struct mlxsw_reg_info *reg_info;
13162 	int i;
13163 
13164 	for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
13165 		reg_info = mlxsw_reg_infos[i];
13166 		if (reg_info->id == reg_id)
13167 			return reg_info->name;
13168 	}
13169 	return "*UNKNOWN*";
13170 }
13171 
13172 /* PUDE - Port Up / Down Event
13173  * ---------------------------
13174  * Reports the operational state change of a port.
13175  */
13176 #define MLXSW_REG_PUDE_LEN 0x10
13177 
13178 /* reg_pude_swid
13179  * Switch partition ID with which to associate the port.
13180  * Access: Index
13181  */
13182 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
13183 
13184 /* reg_pude_local_port
13185  * Local port number.
13186  * Access: Index
13187  */
13188 MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12);
13189 
13190 /* reg_pude_admin_status
13191  * Port administrative state (the desired state).
13192  * 1 - Up.
13193  * 2 - Down.
13194  * 3 - Up once. This means that in case of link failure, the port won't go
13195  *     into polling mode, but will wait to be re-enabled by software.
13196  * 4 - Disabled by system. Can only be set by hardware.
13197  * Access: RO
13198  */
13199 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
13200 
13201 /* reg_pude_oper_status
13202  * Port operatioanl state.
13203  * 1 - Up.
13204  * 2 - Down.
13205  * 3 - Down by port failure. This means that the device will not let the
13206  *     port up again until explicitly specified by software.
13207  * Access: RO
13208  */
13209 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
13210 
13211 #endif
13212