1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 88 MLX5_OBJ_TYPE_STC = 0x0040, 89 MLX5_OBJ_TYPE_RTC = 0x0041, 90 MLX5_OBJ_TYPE_STE = 0x0042, 91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15, 108 }; 109 110 enum { 111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 117 }; 118 119 enum { 120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 122 MLX5_CMD_OP_INIT_HCA = 0x102, 123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 124 MLX5_CMD_OP_ENABLE_HCA = 0x104, 125 MLX5_CMD_OP_DISABLE_HCA = 0x105, 126 MLX5_CMD_OP_QUERY_PAGES = 0x107, 127 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 128 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 129 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 130 MLX5_CMD_OP_SET_ISSI = 0x10b, 131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 133 MLX5_CMD_OP_ALLOC_SF = 0x113, 134 MLX5_CMD_OP_DEALLOC_SF = 0x114, 135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 136 MLX5_CMD_OP_RESUME_VHCA = 0x116, 137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 140 MLX5_CMD_OP_CREATE_MKEY = 0x200, 141 MLX5_CMD_OP_QUERY_MKEY = 0x201, 142 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 148 MLX5_CMD_OP_CREATE_EQ = 0x301, 149 MLX5_CMD_OP_DESTROY_EQ = 0x302, 150 MLX5_CMD_OP_QUERY_EQ = 0x303, 151 MLX5_CMD_OP_GEN_EQE = 0x304, 152 MLX5_CMD_OP_CREATE_CQ = 0x400, 153 MLX5_CMD_OP_DESTROY_CQ = 0x401, 154 MLX5_CMD_OP_QUERY_CQ = 0x402, 155 MLX5_CMD_OP_MODIFY_CQ = 0x403, 156 MLX5_CMD_OP_CREATE_QP = 0x500, 157 MLX5_CMD_OP_DESTROY_QP = 0x501, 158 MLX5_CMD_OP_RST2INIT_QP = 0x502, 159 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 160 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 161 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 163 MLX5_CMD_OP_2ERR_QP = 0x507, 164 MLX5_CMD_OP_2RST_QP = 0x50a, 165 MLX5_CMD_OP_QUERY_QP = 0x50b, 166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 168 MLX5_CMD_OP_CREATE_PSV = 0x600, 169 MLX5_CMD_OP_DESTROY_PSV = 0x601, 170 MLX5_CMD_OP_CREATE_SRQ = 0x700, 171 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 172 MLX5_CMD_OP_QUERY_SRQ = 0x702, 173 MLX5_CMD_OP_ARM_RQ = 0x703, 174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 178 MLX5_CMD_OP_CREATE_DCT = 0x710, 179 MLX5_CMD_OP_DESTROY_DCT = 0x711, 180 MLX5_CMD_OP_DRAIN_DCT = 0x712, 181 MLX5_CMD_OP_QUERY_DCT = 0x713, 182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 183 MLX5_CMD_OP_CREATE_XRQ = 0x717, 184 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 185 MLX5_CMD_OP_QUERY_XRQ = 0x719, 186 MLX5_CMD_OP_ARM_XRQ = 0x71a, 187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 192 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 193 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 194 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 195 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 196 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 197 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 198 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 199 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 200 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 202 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 203 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 204 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 205 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 206 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 207 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 208 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 209 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 210 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 211 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 212 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 213 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 214 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 215 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 216 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 217 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 218 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 219 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 220 MLX5_CMD_OP_ALLOC_PD = 0x800, 221 MLX5_CMD_OP_DEALLOC_PD = 0x801, 222 MLX5_CMD_OP_ALLOC_UAR = 0x802, 223 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 224 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 225 MLX5_CMD_OP_ACCESS_REG = 0x805, 226 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 227 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 228 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 229 MLX5_CMD_OP_MAD_IFC = 0x50d, 230 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 231 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 232 MLX5_CMD_OP_NOP = 0x80d, 233 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 234 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 235 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 236 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 237 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 238 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 239 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 240 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 241 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 242 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 243 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 244 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 245 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 246 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 247 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 248 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 249 MLX5_CMD_OP_CREATE_LAG = 0x840, 250 MLX5_CMD_OP_MODIFY_LAG = 0x841, 251 MLX5_CMD_OP_QUERY_LAG = 0x842, 252 MLX5_CMD_OP_DESTROY_LAG = 0x843, 253 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 254 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 255 MLX5_CMD_OP_CREATE_TIR = 0x900, 256 MLX5_CMD_OP_MODIFY_TIR = 0x901, 257 MLX5_CMD_OP_DESTROY_TIR = 0x902, 258 MLX5_CMD_OP_QUERY_TIR = 0x903, 259 MLX5_CMD_OP_CREATE_SQ = 0x904, 260 MLX5_CMD_OP_MODIFY_SQ = 0x905, 261 MLX5_CMD_OP_DESTROY_SQ = 0x906, 262 MLX5_CMD_OP_QUERY_SQ = 0x907, 263 MLX5_CMD_OP_CREATE_RQ = 0x908, 264 MLX5_CMD_OP_MODIFY_RQ = 0x909, 265 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 266 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 267 MLX5_CMD_OP_QUERY_RQ = 0x90b, 268 MLX5_CMD_OP_CREATE_RMP = 0x90c, 269 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 270 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 271 MLX5_CMD_OP_QUERY_RMP = 0x90f, 272 MLX5_CMD_OP_CREATE_TIS = 0x912, 273 MLX5_CMD_OP_MODIFY_TIS = 0x913, 274 MLX5_CMD_OP_DESTROY_TIS = 0x914, 275 MLX5_CMD_OP_QUERY_TIS = 0x915, 276 MLX5_CMD_OP_CREATE_RQT = 0x916, 277 MLX5_CMD_OP_MODIFY_RQT = 0x917, 278 MLX5_CMD_OP_DESTROY_RQT = 0x918, 279 MLX5_CMD_OP_QUERY_RQT = 0x919, 280 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 281 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 282 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 283 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 284 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 285 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 286 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 287 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 288 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 289 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 290 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 291 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 292 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 293 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 294 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 295 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 296 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 297 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 298 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 299 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 300 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 301 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 302 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 303 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 304 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 305 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 306 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 307 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 308 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 309 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 310 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 311 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 312 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 313 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 314 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 315 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 316 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 317 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 318 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 319 MLX5_CMD_OPCODE_QUERY_VUID = 0xb22, 320 MLX5_CMD_OP_MAX 321 }; 322 323 /* Valid range for general commands that don't work over an object */ 324 enum { 325 MLX5_CMD_OP_GENERAL_START = 0xb00, 326 MLX5_CMD_OP_GENERAL_END = 0xd00, 327 }; 328 329 enum { 330 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 331 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 332 }; 333 334 enum { 335 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 336 }; 337 338 struct mlx5_ifc_flow_table_fields_supported_bits { 339 u8 outer_dmac[0x1]; 340 u8 outer_smac[0x1]; 341 u8 outer_ether_type[0x1]; 342 u8 outer_ip_version[0x1]; 343 u8 outer_first_prio[0x1]; 344 u8 outer_first_cfi[0x1]; 345 u8 outer_first_vid[0x1]; 346 u8 outer_ipv4_ttl[0x1]; 347 u8 outer_second_prio[0x1]; 348 u8 outer_second_cfi[0x1]; 349 u8 outer_second_vid[0x1]; 350 u8 reserved_at_b[0x1]; 351 u8 outer_sip[0x1]; 352 u8 outer_dip[0x1]; 353 u8 outer_frag[0x1]; 354 u8 outer_ip_protocol[0x1]; 355 u8 outer_ip_ecn[0x1]; 356 u8 outer_ip_dscp[0x1]; 357 u8 outer_udp_sport[0x1]; 358 u8 outer_udp_dport[0x1]; 359 u8 outer_tcp_sport[0x1]; 360 u8 outer_tcp_dport[0x1]; 361 u8 outer_tcp_flags[0x1]; 362 u8 outer_gre_protocol[0x1]; 363 u8 outer_gre_key[0x1]; 364 u8 outer_vxlan_vni[0x1]; 365 u8 outer_geneve_vni[0x1]; 366 u8 outer_geneve_oam[0x1]; 367 u8 outer_geneve_protocol_type[0x1]; 368 u8 outer_geneve_opt_len[0x1]; 369 u8 source_vhca_port[0x1]; 370 u8 source_eswitch_port[0x1]; 371 372 u8 inner_dmac[0x1]; 373 u8 inner_smac[0x1]; 374 u8 inner_ether_type[0x1]; 375 u8 inner_ip_version[0x1]; 376 u8 inner_first_prio[0x1]; 377 u8 inner_first_cfi[0x1]; 378 u8 inner_first_vid[0x1]; 379 u8 reserved_at_27[0x1]; 380 u8 inner_second_prio[0x1]; 381 u8 inner_second_cfi[0x1]; 382 u8 inner_second_vid[0x1]; 383 u8 reserved_at_2b[0x1]; 384 u8 inner_sip[0x1]; 385 u8 inner_dip[0x1]; 386 u8 inner_frag[0x1]; 387 u8 inner_ip_protocol[0x1]; 388 u8 inner_ip_ecn[0x1]; 389 u8 inner_ip_dscp[0x1]; 390 u8 inner_udp_sport[0x1]; 391 u8 inner_udp_dport[0x1]; 392 u8 inner_tcp_sport[0x1]; 393 u8 inner_tcp_dport[0x1]; 394 u8 inner_tcp_flags[0x1]; 395 u8 reserved_at_37[0x9]; 396 397 u8 geneve_tlv_option_0_data[0x1]; 398 u8 geneve_tlv_option_0_exist[0x1]; 399 u8 reserved_at_42[0x3]; 400 u8 outer_first_mpls_over_udp[0x4]; 401 u8 outer_first_mpls_over_gre[0x4]; 402 u8 inner_first_mpls[0x4]; 403 u8 outer_first_mpls[0x4]; 404 u8 reserved_at_55[0x2]; 405 u8 outer_esp_spi[0x1]; 406 u8 reserved_at_58[0x2]; 407 u8 bth_dst_qp[0x1]; 408 u8 reserved_at_5b[0x5]; 409 410 u8 reserved_at_60[0x18]; 411 u8 metadata_reg_c_7[0x1]; 412 u8 metadata_reg_c_6[0x1]; 413 u8 metadata_reg_c_5[0x1]; 414 u8 metadata_reg_c_4[0x1]; 415 u8 metadata_reg_c_3[0x1]; 416 u8 metadata_reg_c_2[0x1]; 417 u8 metadata_reg_c_1[0x1]; 418 u8 metadata_reg_c_0[0x1]; 419 }; 420 421 /* Table 2170 - Flow Table Fields Supported 2 Format */ 422 struct mlx5_ifc_flow_table_fields_supported_2_bits { 423 u8 inner_l4_type_ext[0x1]; 424 u8 outer_l4_type_ext[0x1]; 425 u8 inner_l4_type[0x1]; 426 u8 outer_l4_type[0x1]; 427 u8 reserved_at_4[0xa]; 428 u8 bth_opcode[0x1]; 429 u8 reserved_at_f[0x1]; 430 u8 tunnel_header_0_1[0x1]; 431 u8 reserved_at_11[0xf]; 432 433 u8 reserved_at_20[0xf]; 434 u8 ipsec_next_header[0x1]; 435 u8 reserved_at_30[0x10]; 436 437 u8 reserved_at_40[0x40]; 438 }; 439 440 struct mlx5_ifc_flow_table_prop_layout_bits { 441 u8 ft_support[0x1]; 442 u8 reserved_at_1[0x1]; 443 u8 flow_counter[0x1]; 444 u8 flow_modify_en[0x1]; 445 u8 modify_root[0x1]; 446 u8 identified_miss_table_mode[0x1]; 447 u8 flow_table_modify[0x1]; 448 u8 reformat[0x1]; 449 u8 decap[0x1]; 450 u8 reset_root_to_default[0x1]; 451 u8 pop_vlan[0x1]; 452 u8 push_vlan[0x1]; 453 u8 reserved_at_c[0x1]; 454 u8 pop_vlan_2[0x1]; 455 u8 push_vlan_2[0x1]; 456 u8 reformat_and_vlan_action[0x1]; 457 u8 reserved_at_10[0x1]; 458 u8 sw_owner[0x1]; 459 u8 reformat_l3_tunnel_to_l2[0x1]; 460 u8 reformat_l2_to_l3_tunnel[0x1]; 461 u8 reformat_and_modify_action[0x1]; 462 u8 ignore_flow_level[0x1]; 463 u8 reserved_at_16[0x1]; 464 u8 table_miss_action_domain[0x1]; 465 u8 termination_table[0x1]; 466 u8 reformat_and_fwd_to_table[0x1]; 467 u8 reserved_at_1a[0x2]; 468 u8 ipsec_encrypt[0x1]; 469 u8 ipsec_decrypt[0x1]; 470 u8 sw_owner_v2[0x1]; 471 u8 reserved_at_1f[0x1]; 472 473 u8 termination_table_raw_traffic[0x1]; 474 u8 reserved_at_21[0x1]; 475 u8 log_max_ft_size[0x6]; 476 u8 log_max_modify_header_context[0x8]; 477 u8 max_modify_header_actions[0x8]; 478 u8 max_ft_level[0x8]; 479 480 u8 reformat_add_esp_trasport[0x1]; 481 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 482 u8 reformat_add_esp_transport_over_udp[0x1]; 483 u8 reformat_del_esp_trasport[0x1]; 484 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 485 u8 reformat_del_esp_transport_over_udp[0x1]; 486 u8 execute_aso[0x1]; 487 u8 reserved_at_47[0x19]; 488 489 u8 reserved_at_60[0x2]; 490 u8 reformat_insert[0x1]; 491 u8 reformat_remove[0x1]; 492 u8 macsec_encrypt[0x1]; 493 u8 macsec_decrypt[0x1]; 494 u8 reserved_at_66[0x2]; 495 u8 reformat_add_macsec[0x1]; 496 u8 reformat_remove_macsec[0x1]; 497 u8 reparse[0x1]; 498 u8 reserved_at_6b[0x1]; 499 u8 cross_vhca_object[0x1]; 500 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 501 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 502 u8 ignore_flow_level_rtc_valid[0x1]; 503 u8 reserved_at_70[0x8]; 504 u8 log_max_ft_num[0x8]; 505 506 u8 reserved_at_80[0x10]; 507 u8 log_max_flow_counter[0x8]; 508 u8 log_max_destination[0x8]; 509 510 u8 reserved_at_a0[0x18]; 511 u8 log_max_flow[0x8]; 512 513 u8 reserved_at_c0[0x40]; 514 515 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 516 517 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 518 }; 519 520 struct mlx5_ifc_odp_per_transport_service_cap_bits { 521 u8 send[0x1]; 522 u8 receive[0x1]; 523 u8 write[0x1]; 524 u8 read[0x1]; 525 u8 atomic[0x1]; 526 u8 srq_receive[0x1]; 527 u8 reserved_at_6[0x1a]; 528 }; 529 530 struct mlx5_ifc_ipv4_layout_bits { 531 u8 reserved_at_0[0x60]; 532 533 u8 ipv4[0x20]; 534 }; 535 536 struct mlx5_ifc_ipv6_layout_bits { 537 u8 ipv6[16][0x8]; 538 }; 539 540 struct mlx5_ifc_ipv6_simple_layout_bits { 541 u8 ipv6_127_96[0x20]; 542 u8 ipv6_95_64[0x20]; 543 u8 ipv6_63_32[0x20]; 544 u8 ipv6_31_0[0x20]; 545 }; 546 547 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 548 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout; 549 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 550 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 551 u8 reserved_at_0[0x80]; 552 }; 553 554 enum { 555 MLX5_PACKET_L4_TYPE_NONE, 556 MLX5_PACKET_L4_TYPE_TCP, 557 MLX5_PACKET_L4_TYPE_UDP, 558 }; 559 560 enum { 561 MLX5_PACKET_L4_TYPE_EXT_NONE, 562 MLX5_PACKET_L4_TYPE_EXT_TCP, 563 MLX5_PACKET_L4_TYPE_EXT_UDP, 564 MLX5_PACKET_L4_TYPE_EXT_ICMP, 565 }; 566 567 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 568 u8 smac_47_16[0x20]; 569 570 u8 smac_15_0[0x10]; 571 u8 ethertype[0x10]; 572 573 u8 dmac_47_16[0x20]; 574 575 u8 dmac_15_0[0x10]; 576 u8 first_prio[0x3]; 577 u8 first_cfi[0x1]; 578 u8 first_vid[0xc]; 579 580 u8 ip_protocol[0x8]; 581 u8 ip_dscp[0x6]; 582 u8 ip_ecn[0x2]; 583 u8 cvlan_tag[0x1]; 584 u8 svlan_tag[0x1]; 585 u8 frag[0x1]; 586 u8 ip_version[0x4]; 587 u8 tcp_flags[0x9]; 588 589 u8 tcp_sport[0x10]; 590 u8 tcp_dport[0x10]; 591 592 u8 l4_type[0x2]; 593 u8 l4_type_ext[0x4]; 594 u8 reserved_at_c6[0xa]; 595 u8 ipv4_ihl[0x4]; 596 u8 reserved_at_d4[0x4]; 597 u8 ttl_hoplimit[0x8]; 598 599 u8 udp_sport[0x10]; 600 u8 udp_dport[0x10]; 601 602 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 603 604 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 605 }; 606 607 struct mlx5_ifc_nvgre_key_bits { 608 u8 hi[0x18]; 609 u8 lo[0x8]; 610 }; 611 612 union mlx5_ifc_gre_key_bits { 613 struct mlx5_ifc_nvgre_key_bits nvgre; 614 u8 key[0x20]; 615 }; 616 617 struct mlx5_ifc_fte_match_set_misc_bits { 618 u8 gre_c_present[0x1]; 619 u8 reserved_at_1[0x1]; 620 u8 gre_k_present[0x1]; 621 u8 gre_s_present[0x1]; 622 u8 source_vhca_port[0x4]; 623 u8 source_sqn[0x18]; 624 625 u8 source_eswitch_owner_vhca_id[0x10]; 626 u8 source_port[0x10]; 627 628 u8 outer_second_prio[0x3]; 629 u8 outer_second_cfi[0x1]; 630 u8 outer_second_vid[0xc]; 631 u8 inner_second_prio[0x3]; 632 u8 inner_second_cfi[0x1]; 633 u8 inner_second_vid[0xc]; 634 635 u8 outer_second_cvlan_tag[0x1]; 636 u8 inner_second_cvlan_tag[0x1]; 637 u8 outer_second_svlan_tag[0x1]; 638 u8 inner_second_svlan_tag[0x1]; 639 u8 reserved_at_64[0xc]; 640 u8 gre_protocol[0x10]; 641 642 union mlx5_ifc_gre_key_bits gre_key; 643 644 u8 vxlan_vni[0x18]; 645 u8 bth_opcode[0x8]; 646 647 u8 geneve_vni[0x18]; 648 u8 reserved_at_d8[0x6]; 649 u8 geneve_tlv_option_0_exist[0x1]; 650 u8 geneve_oam[0x1]; 651 652 u8 reserved_at_e0[0xc]; 653 u8 outer_ipv6_flow_label[0x14]; 654 655 u8 reserved_at_100[0xc]; 656 u8 inner_ipv6_flow_label[0x14]; 657 658 u8 reserved_at_120[0xa]; 659 u8 geneve_opt_len[0x6]; 660 u8 geneve_protocol_type[0x10]; 661 662 u8 reserved_at_140[0x8]; 663 u8 bth_dst_qp[0x18]; 664 u8 inner_esp_spi[0x20]; 665 u8 outer_esp_spi[0x20]; 666 u8 reserved_at_1a0[0x60]; 667 }; 668 669 struct mlx5_ifc_fte_match_mpls_bits { 670 u8 mpls_label[0x14]; 671 u8 mpls_exp[0x3]; 672 u8 mpls_s_bos[0x1]; 673 u8 mpls_ttl[0x8]; 674 }; 675 676 struct mlx5_ifc_fte_match_set_misc2_bits { 677 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 678 679 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 680 681 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 682 683 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 684 685 u8 metadata_reg_c_7[0x20]; 686 687 u8 metadata_reg_c_6[0x20]; 688 689 u8 metadata_reg_c_5[0x20]; 690 691 u8 metadata_reg_c_4[0x20]; 692 693 u8 metadata_reg_c_3[0x20]; 694 695 u8 metadata_reg_c_2[0x20]; 696 697 u8 metadata_reg_c_1[0x20]; 698 699 u8 metadata_reg_c_0[0x20]; 700 701 u8 metadata_reg_a[0x20]; 702 703 u8 reserved_at_1a0[0x8]; 704 u8 macsec_syndrome[0x8]; 705 u8 ipsec_syndrome[0x8]; 706 u8 ipsec_next_header[0x8]; 707 708 u8 reserved_at_1c0[0x40]; 709 }; 710 711 struct mlx5_ifc_fte_match_set_misc3_bits { 712 u8 inner_tcp_seq_num[0x20]; 713 714 u8 outer_tcp_seq_num[0x20]; 715 716 u8 inner_tcp_ack_num[0x20]; 717 718 u8 outer_tcp_ack_num[0x20]; 719 720 u8 reserved_at_80[0x8]; 721 u8 outer_vxlan_gpe_vni[0x18]; 722 723 u8 outer_vxlan_gpe_next_protocol[0x8]; 724 u8 outer_vxlan_gpe_flags[0x8]; 725 u8 reserved_at_b0[0x10]; 726 727 u8 icmp_header_data[0x20]; 728 729 u8 icmpv6_header_data[0x20]; 730 731 u8 icmp_type[0x8]; 732 u8 icmp_code[0x8]; 733 u8 icmpv6_type[0x8]; 734 u8 icmpv6_code[0x8]; 735 736 u8 geneve_tlv_option_0_data[0x20]; 737 738 u8 gtpu_teid[0x20]; 739 740 u8 gtpu_msg_type[0x8]; 741 u8 gtpu_msg_flags[0x8]; 742 u8 reserved_at_170[0x10]; 743 744 u8 gtpu_dw_2[0x20]; 745 746 u8 gtpu_first_ext_dw_0[0x20]; 747 748 u8 gtpu_dw_0[0x20]; 749 750 u8 reserved_at_1e0[0x20]; 751 }; 752 753 struct mlx5_ifc_fte_match_set_misc4_bits { 754 u8 prog_sample_field_value_0[0x20]; 755 756 u8 prog_sample_field_id_0[0x20]; 757 758 u8 prog_sample_field_value_1[0x20]; 759 760 u8 prog_sample_field_id_1[0x20]; 761 762 u8 prog_sample_field_value_2[0x20]; 763 764 u8 prog_sample_field_id_2[0x20]; 765 766 u8 prog_sample_field_value_3[0x20]; 767 768 u8 prog_sample_field_id_3[0x20]; 769 770 u8 reserved_at_100[0x100]; 771 }; 772 773 struct mlx5_ifc_fte_match_set_misc5_bits { 774 u8 macsec_tag_0[0x20]; 775 776 u8 macsec_tag_1[0x20]; 777 778 u8 macsec_tag_2[0x20]; 779 780 u8 macsec_tag_3[0x20]; 781 782 u8 tunnel_header_0[0x20]; 783 784 u8 tunnel_header_1[0x20]; 785 786 u8 tunnel_header_2[0x20]; 787 788 u8 tunnel_header_3[0x20]; 789 790 u8 reserved_at_100[0x100]; 791 }; 792 793 struct mlx5_ifc_cmd_pas_bits { 794 u8 pa_h[0x20]; 795 796 u8 pa_l[0x14]; 797 u8 reserved_at_34[0xc]; 798 }; 799 800 struct mlx5_ifc_uint64_bits { 801 u8 hi[0x20]; 802 803 u8 lo[0x20]; 804 }; 805 806 enum { 807 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 808 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 809 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 810 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 811 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 812 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 813 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 814 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 815 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 816 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 817 }; 818 819 struct mlx5_ifc_ads_bits { 820 u8 fl[0x1]; 821 u8 free_ar[0x1]; 822 u8 reserved_at_2[0xe]; 823 u8 pkey_index[0x10]; 824 825 u8 plane_index[0x8]; 826 u8 grh[0x1]; 827 u8 mlid[0x7]; 828 u8 rlid[0x10]; 829 830 u8 ack_timeout[0x5]; 831 u8 reserved_at_45[0x3]; 832 u8 src_addr_index[0x8]; 833 u8 reserved_at_50[0x4]; 834 u8 stat_rate[0x4]; 835 u8 hop_limit[0x8]; 836 837 u8 reserved_at_60[0x4]; 838 u8 tclass[0x8]; 839 u8 flow_label[0x14]; 840 841 u8 rgid_rip[16][0x8]; 842 843 u8 reserved_at_100[0x4]; 844 u8 f_dscp[0x1]; 845 u8 f_ecn[0x1]; 846 u8 reserved_at_106[0x1]; 847 u8 f_eth_prio[0x1]; 848 u8 ecn[0x2]; 849 u8 dscp[0x6]; 850 u8 udp_sport[0x10]; 851 852 u8 dei_cfi[0x1]; 853 u8 eth_prio[0x3]; 854 u8 sl[0x4]; 855 u8 vhca_port_num[0x8]; 856 u8 rmac_47_32[0x10]; 857 858 u8 rmac_31_0[0x20]; 859 }; 860 861 struct mlx5_ifc_flow_table_nic_cap_bits { 862 u8 nic_rx_multi_path_tirs[0x1]; 863 u8 nic_rx_multi_path_tirs_fts[0x1]; 864 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 865 u8 reserved_at_3[0x4]; 866 u8 sw_owner_reformat_supported[0x1]; 867 u8 reserved_at_8[0x18]; 868 869 u8 encap_general_header[0x1]; 870 u8 reserved_at_21[0xa]; 871 u8 log_max_packet_reformat_context[0x5]; 872 u8 reserved_at_30[0x6]; 873 u8 max_encap_header_size[0xa]; 874 u8 reserved_at_40[0x1c0]; 875 876 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 877 878 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 879 880 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 881 882 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 883 884 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 885 886 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 887 888 u8 reserved_at_e00[0x600]; 889 890 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 891 892 u8 reserved_at_1480[0x80]; 893 894 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 895 896 u8 reserved_at_1580[0x280]; 897 898 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 899 900 u8 reserved_at_1880[0x780]; 901 902 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 903 904 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 905 906 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 907 908 u8 reserved_at_20c0[0x5f40]; 909 }; 910 911 struct mlx5_ifc_port_selection_cap_bits { 912 u8 reserved_at_0[0x10]; 913 u8 port_select_flow_table[0x1]; 914 u8 reserved_at_11[0x1]; 915 u8 port_select_flow_table_bypass[0x1]; 916 u8 reserved_at_13[0xd]; 917 918 u8 reserved_at_20[0x1e0]; 919 920 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 921 922 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 923 924 u8 reserved_at_480[0x7b80]; 925 }; 926 927 enum { 928 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 929 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 930 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 931 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 932 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 933 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 934 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 935 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 936 }; 937 938 struct mlx5_ifc_flow_table_eswitch_cap_bits { 939 u8 fdb_to_vport_reg_c_id[0x8]; 940 u8 reserved_at_8[0x5]; 941 u8 fdb_uplink_hairpin[0x1]; 942 u8 fdb_multi_path_any_table_limit_regc[0x1]; 943 u8 reserved_at_f[0x1]; 944 u8 fdb_dynamic_tunnel[0x1]; 945 u8 reserved_at_11[0x1]; 946 u8 fdb_multi_path_any_table[0x1]; 947 u8 reserved_at_13[0x2]; 948 u8 fdb_modify_header_fwd_to_table[0x1]; 949 u8 fdb_ipv4_ttl_modify[0x1]; 950 u8 flow_source[0x1]; 951 u8 reserved_at_18[0x2]; 952 u8 multi_fdb_encap[0x1]; 953 u8 egress_acl_forward_to_vport[0x1]; 954 u8 fdb_multi_path_to_table[0x1]; 955 u8 reserved_at_1d[0x3]; 956 957 u8 reserved_at_20[0x1e0]; 958 959 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 960 961 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 962 963 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 964 965 u8 reserved_at_800[0xC00]; 966 967 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 968 969 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 970 971 u8 reserved_at_1500[0x300]; 972 973 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 974 975 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 976 977 u8 sw_steering_uplink_icm_address_rx[0x40]; 978 979 u8 sw_steering_uplink_icm_address_tx[0x40]; 980 981 u8 reserved_at_1900[0x6700]; 982 }; 983 984 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 985 u8 reserved_at_0[0x3]; 986 u8 log_max_num_ste[0x5]; 987 u8 reserved_at_8[0x3]; 988 u8 log_max_num_stc[0x5]; 989 u8 reserved_at_10[0x3]; 990 u8 log_max_num_rtc[0x5]; 991 u8 reserved_at_18[0x3]; 992 u8 log_max_num_header_modify_pattern[0x5]; 993 994 u8 rtc_hash_split_table[0x1]; 995 u8 rtc_linear_lookup_table[0x1]; 996 u8 reserved_at_22[0x1]; 997 u8 stc_alloc_log_granularity[0x5]; 998 u8 reserved_at_28[0x3]; 999 u8 stc_alloc_log_max[0x5]; 1000 u8 reserved_at_30[0x3]; 1001 u8 ste_alloc_log_granularity[0x5]; 1002 u8 reserved_at_38[0x3]; 1003 u8 ste_alloc_log_max[0x5]; 1004 1005 u8 reserved_at_40[0xb]; 1006 u8 rtc_reparse_mode[0x5]; 1007 u8 reserved_at_50[0x3]; 1008 u8 rtc_index_mode[0x5]; 1009 u8 reserved_at_58[0x3]; 1010 u8 rtc_log_depth_max[0x5]; 1011 1012 u8 reserved_at_60[0x10]; 1013 u8 ste_format[0x10]; 1014 1015 u8 stc_action_type[0x80]; 1016 1017 u8 header_insert_type[0x10]; 1018 u8 header_remove_type[0x10]; 1019 1020 u8 trivial_match_definer[0x20]; 1021 1022 u8 reserved_at_140[0x1b]; 1023 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 1024 1025 u8 reserved_at_160[0x18]; 1026 u8 access_index_mode[0x8]; 1027 1028 u8 reserved_at_180[0x10]; 1029 u8 ste_format_gen_wqe[0x10]; 1030 1031 u8 linear_match_definer_reg_c3[0x20]; 1032 1033 u8 fdb_jump_to_tir_stc[0x1]; 1034 u8 reserved_at_1c1[0x1f]; 1035 }; 1036 1037 struct mlx5_ifc_esw_cap_bits { 1038 u8 reserved_at_0[0x1d]; 1039 u8 merged_eswitch[0x1]; 1040 u8 reserved_at_1e[0x2]; 1041 1042 u8 reserved_at_20[0x40]; 1043 1044 u8 esw_manager_vport_number_valid[0x1]; 1045 u8 reserved_at_61[0xf]; 1046 u8 esw_manager_vport_number[0x10]; 1047 1048 u8 reserved_at_80[0x780]; 1049 }; 1050 1051 enum { 1052 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 1053 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 1054 }; 1055 1056 struct mlx5_ifc_e_switch_cap_bits { 1057 u8 vport_svlan_strip[0x1]; 1058 u8 vport_cvlan_strip[0x1]; 1059 u8 vport_svlan_insert[0x1]; 1060 u8 vport_cvlan_insert_if_not_exist[0x1]; 1061 u8 vport_cvlan_insert_overwrite[0x1]; 1062 u8 reserved_at_5[0x1]; 1063 u8 vport_cvlan_insert_always[0x1]; 1064 u8 esw_shared_ingress_acl[0x1]; 1065 u8 esw_uplink_ingress_acl[0x1]; 1066 u8 root_ft_on_other_esw[0x1]; 1067 u8 reserved_at_a[0xf]; 1068 u8 esw_functions_changed[0x1]; 1069 u8 reserved_at_1a[0x1]; 1070 u8 ecpf_vport_exists[0x1]; 1071 u8 counter_eswitch_affinity[0x1]; 1072 u8 merged_eswitch[0x1]; 1073 u8 nic_vport_node_guid_modify[0x1]; 1074 u8 nic_vport_port_guid_modify[0x1]; 1075 1076 u8 vxlan_encap_decap[0x1]; 1077 u8 nvgre_encap_decap[0x1]; 1078 u8 reserved_at_22[0x1]; 1079 u8 log_max_fdb_encap_uplink[0x5]; 1080 u8 reserved_at_21[0x3]; 1081 u8 log_max_packet_reformat_context[0x5]; 1082 u8 reserved_2b[0x6]; 1083 u8 max_encap_header_size[0xa]; 1084 1085 u8 reserved_at_40[0xb]; 1086 u8 log_max_esw_sf[0x5]; 1087 u8 esw_sf_base_id[0x10]; 1088 1089 u8 reserved_at_60[0x7a0]; 1090 1091 }; 1092 1093 struct mlx5_ifc_qos_cap_bits { 1094 u8 packet_pacing[0x1]; 1095 u8 esw_scheduling[0x1]; 1096 u8 esw_bw_share[0x1]; 1097 u8 esw_rate_limit[0x1]; 1098 u8 reserved_at_4[0x1]; 1099 u8 packet_pacing_burst_bound[0x1]; 1100 u8 packet_pacing_typical_size[0x1]; 1101 u8 reserved_at_7[0x1]; 1102 u8 nic_sq_scheduling[0x1]; 1103 u8 nic_bw_share[0x1]; 1104 u8 nic_rate_limit[0x1]; 1105 u8 packet_pacing_uid[0x1]; 1106 u8 log_esw_max_sched_depth[0x4]; 1107 u8 reserved_at_10[0x10]; 1108 1109 u8 reserved_at_20[0x9]; 1110 u8 esw_cross_esw_sched[0x1]; 1111 u8 reserved_at_2a[0x1]; 1112 u8 log_max_qos_nic_queue_group[0x5]; 1113 u8 reserved_at_30[0x10]; 1114 1115 u8 packet_pacing_max_rate[0x20]; 1116 1117 u8 packet_pacing_min_rate[0x20]; 1118 1119 u8 reserved_at_80[0xb]; 1120 u8 log_esw_max_rate_limit[0x5]; 1121 u8 packet_pacing_rate_table_size[0x10]; 1122 1123 u8 esw_element_type[0x10]; 1124 u8 esw_tsar_type[0x10]; 1125 1126 u8 reserved_at_c0[0x10]; 1127 u8 max_qos_para_vport[0x10]; 1128 1129 u8 max_tsar_bw_share[0x20]; 1130 1131 u8 nic_element_type[0x10]; 1132 u8 nic_tsar_type[0x10]; 1133 1134 u8 reserved_at_120[0x3]; 1135 u8 log_meter_aso_granularity[0x5]; 1136 u8 reserved_at_128[0x3]; 1137 u8 log_meter_aso_max_alloc[0x5]; 1138 u8 reserved_at_130[0x3]; 1139 u8 log_max_num_meter_aso[0x5]; 1140 u8 reserved_at_138[0x8]; 1141 1142 u8 reserved_at_140[0x6c0]; 1143 }; 1144 1145 struct mlx5_ifc_debug_cap_bits { 1146 u8 core_dump_general[0x1]; 1147 u8 core_dump_qp[0x1]; 1148 u8 reserved_at_2[0x7]; 1149 u8 resource_dump[0x1]; 1150 u8 reserved_at_a[0x16]; 1151 1152 u8 reserved_at_20[0x2]; 1153 u8 stall_detect[0x1]; 1154 u8 reserved_at_23[0x1d]; 1155 1156 u8 reserved_at_40[0x7c0]; 1157 }; 1158 1159 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1160 u8 csum_cap[0x1]; 1161 u8 vlan_cap[0x1]; 1162 u8 lro_cap[0x1]; 1163 u8 lro_psh_flag[0x1]; 1164 u8 lro_time_stamp[0x1]; 1165 u8 reserved_at_5[0x2]; 1166 u8 wqe_vlan_insert[0x1]; 1167 u8 self_lb_en_modifiable[0x1]; 1168 u8 reserved_at_9[0x2]; 1169 u8 max_lso_cap[0x5]; 1170 u8 multi_pkt_send_wqe[0x2]; 1171 u8 wqe_inline_mode[0x2]; 1172 u8 rss_ind_tbl_cap[0x4]; 1173 u8 reg_umr_sq[0x1]; 1174 u8 scatter_fcs[0x1]; 1175 u8 enhanced_multi_pkt_send_wqe[0x1]; 1176 u8 tunnel_lso_const_out_ip_id[0x1]; 1177 u8 tunnel_lro_gre[0x1]; 1178 u8 tunnel_lro_vxlan[0x1]; 1179 u8 tunnel_stateless_gre[0x1]; 1180 u8 tunnel_stateless_vxlan[0x1]; 1181 1182 u8 swp[0x1]; 1183 u8 swp_csum[0x1]; 1184 u8 swp_lso[0x1]; 1185 u8 cqe_checksum_full[0x1]; 1186 u8 tunnel_stateless_geneve_tx[0x1]; 1187 u8 tunnel_stateless_mpls_over_udp[0x1]; 1188 u8 tunnel_stateless_mpls_over_gre[0x1]; 1189 u8 tunnel_stateless_vxlan_gpe[0x1]; 1190 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1191 u8 tunnel_stateless_ip_over_ip[0x1]; 1192 u8 insert_trailer[0x1]; 1193 u8 reserved_at_2b[0x1]; 1194 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1195 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1196 u8 reserved_at_2e[0x2]; 1197 u8 max_vxlan_udp_ports[0x8]; 1198 u8 swp_csum_l4_partial[0x1]; 1199 u8 reserved_at_39[0x5]; 1200 u8 max_geneve_opt_len[0x1]; 1201 u8 tunnel_stateless_geneve_rx[0x1]; 1202 1203 u8 reserved_at_40[0x10]; 1204 u8 lro_min_mss_size[0x10]; 1205 1206 u8 reserved_at_60[0x120]; 1207 1208 u8 lro_timer_supported_periods[4][0x20]; 1209 1210 u8 reserved_at_200[0x600]; 1211 }; 1212 1213 enum { 1214 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1215 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1216 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1217 }; 1218 1219 struct mlx5_ifc_roce_cap_bits { 1220 u8 roce_apm[0x1]; 1221 u8 reserved_at_1[0x3]; 1222 u8 sw_r_roce_src_udp_port[0x1]; 1223 u8 fl_rc_qp_when_roce_disabled[0x1]; 1224 u8 fl_rc_qp_when_roce_enabled[0x1]; 1225 u8 roce_cc_general[0x1]; 1226 u8 qp_ooo_transmit_default[0x1]; 1227 u8 reserved_at_9[0x15]; 1228 u8 qp_ts_format[0x2]; 1229 1230 u8 reserved_at_20[0x60]; 1231 1232 u8 reserved_at_80[0xc]; 1233 u8 l3_type[0x4]; 1234 u8 reserved_at_90[0x8]; 1235 u8 roce_version[0x8]; 1236 1237 u8 reserved_at_a0[0x10]; 1238 u8 r_roce_dest_udp_port[0x10]; 1239 1240 u8 r_roce_max_src_udp_port[0x10]; 1241 u8 r_roce_min_src_udp_port[0x10]; 1242 1243 u8 reserved_at_e0[0x10]; 1244 u8 roce_address_table_size[0x10]; 1245 1246 u8 reserved_at_100[0x700]; 1247 }; 1248 1249 struct mlx5_ifc_sync_steering_in_bits { 1250 u8 opcode[0x10]; 1251 u8 uid[0x10]; 1252 1253 u8 reserved_at_20[0x10]; 1254 u8 op_mod[0x10]; 1255 1256 u8 reserved_at_40[0xc0]; 1257 }; 1258 1259 struct mlx5_ifc_sync_steering_out_bits { 1260 u8 status[0x8]; 1261 u8 reserved_at_8[0x18]; 1262 1263 u8 syndrome[0x20]; 1264 1265 u8 reserved_at_40[0x40]; 1266 }; 1267 1268 struct mlx5_ifc_sync_crypto_in_bits { 1269 u8 opcode[0x10]; 1270 u8 uid[0x10]; 1271 1272 u8 reserved_at_20[0x10]; 1273 u8 op_mod[0x10]; 1274 1275 u8 reserved_at_40[0x20]; 1276 1277 u8 reserved_at_60[0x10]; 1278 u8 crypto_type[0x10]; 1279 1280 u8 reserved_at_80[0x80]; 1281 }; 1282 1283 struct mlx5_ifc_sync_crypto_out_bits { 1284 u8 status[0x8]; 1285 u8 reserved_at_8[0x18]; 1286 1287 u8 syndrome[0x20]; 1288 1289 u8 reserved_at_40[0x40]; 1290 }; 1291 1292 struct mlx5_ifc_device_mem_cap_bits { 1293 u8 memic[0x1]; 1294 u8 reserved_at_1[0x1f]; 1295 1296 u8 reserved_at_20[0xb]; 1297 u8 log_min_memic_alloc_size[0x5]; 1298 u8 reserved_at_30[0x8]; 1299 u8 log_max_memic_addr_alignment[0x8]; 1300 1301 u8 memic_bar_start_addr[0x40]; 1302 1303 u8 memic_bar_size[0x20]; 1304 1305 u8 max_memic_size[0x20]; 1306 1307 u8 steering_sw_icm_start_address[0x40]; 1308 1309 u8 reserved_at_100[0x8]; 1310 u8 log_header_modify_sw_icm_size[0x8]; 1311 u8 reserved_at_110[0x2]; 1312 u8 log_sw_icm_alloc_granularity[0x6]; 1313 u8 log_steering_sw_icm_size[0x8]; 1314 1315 u8 log_indirect_encap_sw_icm_size[0x8]; 1316 u8 reserved_at_128[0x10]; 1317 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1318 1319 u8 header_modify_sw_icm_start_address[0x40]; 1320 1321 u8 reserved_at_180[0x40]; 1322 1323 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1324 1325 u8 memic_operations[0x20]; 1326 1327 u8 reserved_at_220[0x20]; 1328 1329 u8 indirect_encap_sw_icm_start_address[0x40]; 1330 1331 u8 reserved_at_280[0x580]; 1332 }; 1333 1334 struct mlx5_ifc_device_event_cap_bits { 1335 u8 user_affiliated_events[4][0x40]; 1336 1337 u8 user_unaffiliated_events[4][0x40]; 1338 }; 1339 1340 struct mlx5_ifc_virtio_emulation_cap_bits { 1341 u8 desc_tunnel_offload_type[0x1]; 1342 u8 eth_frame_offload_type[0x1]; 1343 u8 virtio_version_1_0[0x1]; 1344 u8 device_features_bits_mask[0xd]; 1345 u8 event_mode[0x8]; 1346 u8 virtio_queue_type[0x8]; 1347 1348 u8 max_tunnel_desc[0x10]; 1349 u8 reserved_at_30[0x3]; 1350 u8 log_doorbell_stride[0x5]; 1351 u8 reserved_at_38[0x3]; 1352 u8 log_doorbell_bar_size[0x5]; 1353 1354 u8 doorbell_bar_offset[0x40]; 1355 1356 u8 max_emulated_devices[0x8]; 1357 u8 max_num_virtio_queues[0x18]; 1358 1359 u8 reserved_at_a0[0x20]; 1360 1361 u8 reserved_at_c0[0x13]; 1362 u8 desc_group_mkey_supported[0x1]; 1363 u8 freeze_to_rdy_supported[0x1]; 1364 u8 reserved_at_d5[0xb]; 1365 1366 u8 reserved_at_e0[0x20]; 1367 1368 u8 umem_1_buffer_param_a[0x20]; 1369 1370 u8 umem_1_buffer_param_b[0x20]; 1371 1372 u8 umem_2_buffer_param_a[0x20]; 1373 1374 u8 umem_2_buffer_param_b[0x20]; 1375 1376 u8 umem_3_buffer_param_a[0x20]; 1377 1378 u8 umem_3_buffer_param_b[0x20]; 1379 1380 u8 reserved_at_1c0[0x640]; 1381 }; 1382 1383 enum { 1384 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1385 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1386 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1387 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1388 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1389 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1390 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1391 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1392 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1393 }; 1394 1395 enum { 1396 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1397 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1398 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1399 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1400 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1401 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1402 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1403 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1404 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1405 }; 1406 1407 struct mlx5_ifc_atomic_caps_bits { 1408 u8 reserved_at_0[0x40]; 1409 1410 u8 atomic_req_8B_endianness_mode[0x2]; 1411 u8 reserved_at_42[0x4]; 1412 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1413 1414 u8 reserved_at_47[0x19]; 1415 1416 u8 reserved_at_60[0x20]; 1417 1418 u8 reserved_at_80[0x10]; 1419 u8 atomic_operations[0x10]; 1420 1421 u8 reserved_at_a0[0x10]; 1422 u8 atomic_size_qp[0x10]; 1423 1424 u8 reserved_at_c0[0x10]; 1425 u8 atomic_size_dc[0x10]; 1426 1427 u8 reserved_at_e0[0x720]; 1428 }; 1429 1430 struct mlx5_ifc_odp_scheme_cap_bits { 1431 u8 reserved_at_0[0x40]; 1432 1433 u8 sig[0x1]; 1434 u8 reserved_at_41[0x4]; 1435 u8 page_prefetch[0x1]; 1436 u8 reserved_at_46[0x1a]; 1437 1438 u8 reserved_at_60[0x20]; 1439 1440 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1441 1442 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1443 1444 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1445 1446 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1447 1448 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1449 1450 u8 reserved_at_120[0xe0]; 1451 }; 1452 1453 struct mlx5_ifc_odp_cap_bits { 1454 struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap; 1455 1456 struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap; 1457 1458 u8 reserved_at_400[0x200]; 1459 1460 u8 mem_page_fault[0x1]; 1461 u8 reserved_at_601[0x1f]; 1462 1463 u8 reserved_at_620[0x1e0]; 1464 }; 1465 1466 struct mlx5_ifc_tls_cap_bits { 1467 u8 tls_1_2_aes_gcm_128[0x1]; 1468 u8 tls_1_3_aes_gcm_128[0x1]; 1469 u8 tls_1_2_aes_gcm_256[0x1]; 1470 u8 tls_1_3_aes_gcm_256[0x1]; 1471 u8 reserved_at_4[0x1c]; 1472 1473 u8 reserved_at_20[0x7e0]; 1474 }; 1475 1476 struct mlx5_ifc_ipsec_cap_bits { 1477 u8 ipsec_full_offload[0x1]; 1478 u8 ipsec_crypto_offload[0x1]; 1479 u8 ipsec_esn[0x1]; 1480 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1481 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1482 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1483 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1484 u8 reserved_at_7[0x4]; 1485 u8 log_max_ipsec_offload[0x5]; 1486 u8 reserved_at_10[0x10]; 1487 1488 u8 min_log_ipsec_full_replay_window[0x8]; 1489 u8 max_log_ipsec_full_replay_window[0x8]; 1490 u8 reserved_at_30[0x7d0]; 1491 }; 1492 1493 struct mlx5_ifc_macsec_cap_bits { 1494 u8 macsec_epn[0x1]; 1495 u8 reserved_at_1[0x2]; 1496 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1497 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1498 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1499 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1500 u8 reserved_at_7[0x4]; 1501 u8 log_max_macsec_offload[0x5]; 1502 u8 reserved_at_10[0x10]; 1503 1504 u8 min_log_macsec_full_replay_window[0x8]; 1505 u8 max_log_macsec_full_replay_window[0x8]; 1506 u8 reserved_at_30[0x10]; 1507 1508 u8 reserved_at_40[0x7c0]; 1509 }; 1510 1511 enum { 1512 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1513 MLX5_WQ_TYPE_CYCLIC = 0x1, 1514 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1515 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1516 }; 1517 1518 enum { 1519 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1520 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1521 }; 1522 1523 enum { 1524 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1525 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1526 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1527 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1528 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1529 }; 1530 1531 enum { 1532 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1533 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1534 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1535 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1536 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1537 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1538 }; 1539 1540 enum { 1541 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1542 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1543 }; 1544 1545 enum { 1546 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1547 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1548 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1549 }; 1550 1551 enum { 1552 MLX5_CAP_PORT_TYPE_IB = 0x0, 1553 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1554 }; 1555 1556 enum { 1557 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1558 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1559 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1560 }; 1561 1562 enum { 1563 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0, 1564 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1, 1565 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2, 1566 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1567 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1568 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1569 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6, 1570 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1571 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1572 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1573 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1574 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1575 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1576 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1577 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1578 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1579 }; 1580 1581 enum { 1582 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1583 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1584 MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3, 1585 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4, 1586 }; 1587 1588 #define MLX5_FC_BULK_SIZE_FACTOR 128 1589 1590 enum mlx5_fc_bulk_alloc_bitmask { 1591 MLX5_FC_BULK_128 = (1 << 0), 1592 MLX5_FC_BULK_256 = (1 << 1), 1593 MLX5_FC_BULK_512 = (1 << 2), 1594 MLX5_FC_BULK_1024 = (1 << 3), 1595 MLX5_FC_BULK_2048 = (1 << 4), 1596 MLX5_FC_BULK_4096 = (1 << 5), 1597 MLX5_FC_BULK_8192 = (1 << 6), 1598 MLX5_FC_BULK_16384 = (1 << 7), 1599 }; 1600 1601 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1602 1603 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1604 1605 enum { 1606 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1607 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1608 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1609 MLX5_STEERING_FORMAT_CONNECTX_8 = 3, 1610 }; 1611 1612 struct mlx5_ifc_cmd_hca_cap_bits { 1613 u8 reserved_at_0[0x6]; 1614 u8 page_request_disable[0x1]; 1615 u8 abs_native_port_num[0x1]; 1616 u8 reserved_at_8[0x8]; 1617 u8 shared_object_to_user_object_allowed[0x1]; 1618 u8 reserved_at_13[0xe]; 1619 u8 vhca_resource_manager[0x1]; 1620 1621 u8 hca_cap_2[0x1]; 1622 u8 create_lag_when_not_master_up[0x1]; 1623 u8 dtor[0x1]; 1624 u8 event_on_vhca_state_teardown_request[0x1]; 1625 u8 event_on_vhca_state_in_use[0x1]; 1626 u8 event_on_vhca_state_active[0x1]; 1627 u8 event_on_vhca_state_allocated[0x1]; 1628 u8 event_on_vhca_state_invalid[0x1]; 1629 u8 reserved_at_28[0x8]; 1630 u8 vhca_id[0x10]; 1631 1632 u8 reserved_at_40[0x40]; 1633 1634 u8 log_max_srq_sz[0x8]; 1635 u8 log_max_qp_sz[0x8]; 1636 u8 event_cap[0x1]; 1637 u8 reserved_at_91[0x2]; 1638 u8 isolate_vl_tc_new[0x1]; 1639 u8 reserved_at_94[0x4]; 1640 u8 prio_tag_required[0x1]; 1641 u8 reserved_at_99[0x2]; 1642 u8 log_max_qp[0x5]; 1643 1644 u8 reserved_at_a0[0x3]; 1645 u8 ece_support[0x1]; 1646 u8 reserved_at_a4[0x5]; 1647 u8 reg_c_preserve[0x1]; 1648 u8 reserved_at_aa[0x1]; 1649 u8 log_max_srq[0x5]; 1650 u8 reserved_at_b0[0x1]; 1651 u8 uplink_follow[0x1]; 1652 u8 ts_cqe_to_dest_cqn[0x1]; 1653 u8 reserved_at_b3[0x6]; 1654 u8 go_back_n[0x1]; 1655 u8 reserved_at_ba[0x6]; 1656 1657 u8 max_sgl_for_optimized_performance[0x8]; 1658 u8 log_max_cq_sz[0x8]; 1659 u8 relaxed_ordering_write_umr[0x1]; 1660 u8 relaxed_ordering_read_umr[0x1]; 1661 u8 reserved_at_d2[0x7]; 1662 u8 virtio_net_device_emualtion_manager[0x1]; 1663 u8 virtio_blk_device_emualtion_manager[0x1]; 1664 u8 log_max_cq[0x5]; 1665 1666 u8 log_max_eq_sz[0x8]; 1667 u8 relaxed_ordering_write[0x1]; 1668 u8 relaxed_ordering_read_pci_enabled[0x1]; 1669 u8 log_max_mkey[0x6]; 1670 u8 reserved_at_f0[0x6]; 1671 u8 terminate_scatter_list_mkey[0x1]; 1672 u8 repeated_mkey[0x1]; 1673 u8 dump_fill_mkey[0x1]; 1674 u8 reserved_at_f9[0x2]; 1675 u8 fast_teardown[0x1]; 1676 u8 log_max_eq[0x4]; 1677 1678 u8 max_indirection[0x8]; 1679 u8 fixed_buffer_size[0x1]; 1680 u8 log_max_mrw_sz[0x7]; 1681 u8 force_teardown[0x1]; 1682 u8 reserved_at_111[0x1]; 1683 u8 log_max_bsf_list_size[0x6]; 1684 u8 umr_extended_translation_offset[0x1]; 1685 u8 null_mkey[0x1]; 1686 u8 log_max_klm_list_size[0x6]; 1687 1688 u8 reserved_at_120[0x2]; 1689 u8 qpc_extension[0x1]; 1690 u8 reserved_at_123[0x7]; 1691 u8 log_max_ra_req_dc[0x6]; 1692 u8 reserved_at_130[0x2]; 1693 u8 eth_wqe_too_small[0x1]; 1694 u8 reserved_at_133[0x6]; 1695 u8 vnic_env_cq_overrun[0x1]; 1696 u8 log_max_ra_res_dc[0x6]; 1697 1698 u8 reserved_at_140[0x5]; 1699 u8 release_all_pages[0x1]; 1700 u8 must_not_use[0x1]; 1701 u8 reserved_at_147[0x2]; 1702 u8 roce_accl[0x1]; 1703 u8 log_max_ra_req_qp[0x6]; 1704 u8 reserved_at_150[0xa]; 1705 u8 log_max_ra_res_qp[0x6]; 1706 1707 u8 end_pad[0x1]; 1708 u8 cc_query_allowed[0x1]; 1709 u8 cc_modify_allowed[0x1]; 1710 u8 start_pad[0x1]; 1711 u8 cache_line_128byte[0x1]; 1712 u8 reserved_at_165[0x4]; 1713 u8 rts2rts_qp_counters_set_id[0x1]; 1714 u8 reserved_at_16a[0x2]; 1715 u8 vnic_env_int_rq_oob[0x1]; 1716 u8 sbcam_reg[0x1]; 1717 u8 reserved_at_16e[0x1]; 1718 u8 qcam_reg[0x1]; 1719 u8 gid_table_size[0x10]; 1720 1721 u8 out_of_seq_cnt[0x1]; 1722 u8 vport_counters[0x1]; 1723 u8 retransmission_q_counters[0x1]; 1724 u8 debug[0x1]; 1725 u8 modify_rq_counter_set_id[0x1]; 1726 u8 rq_delay_drop[0x1]; 1727 u8 max_qp_cnt[0xa]; 1728 u8 pkey_table_size[0x10]; 1729 1730 u8 vport_group_manager[0x1]; 1731 u8 vhca_group_manager[0x1]; 1732 u8 ib_virt[0x1]; 1733 u8 eth_virt[0x1]; 1734 u8 vnic_env_queue_counters[0x1]; 1735 u8 ets[0x1]; 1736 u8 nic_flow_table[0x1]; 1737 u8 eswitch_manager[0x1]; 1738 u8 device_memory[0x1]; 1739 u8 mcam_reg[0x1]; 1740 u8 pcam_reg[0x1]; 1741 u8 local_ca_ack_delay[0x5]; 1742 u8 port_module_event[0x1]; 1743 u8 enhanced_error_q_counters[0x1]; 1744 u8 ports_check[0x1]; 1745 u8 reserved_at_1b3[0x1]; 1746 u8 disable_link_up[0x1]; 1747 u8 beacon_led[0x1]; 1748 u8 port_type[0x2]; 1749 u8 num_ports[0x8]; 1750 1751 u8 reserved_at_1c0[0x1]; 1752 u8 pps[0x1]; 1753 u8 pps_modify[0x1]; 1754 u8 log_max_msg[0x5]; 1755 u8 reserved_at_1c8[0x4]; 1756 u8 max_tc[0x4]; 1757 u8 temp_warn_event[0x1]; 1758 u8 dcbx[0x1]; 1759 u8 general_notification_event[0x1]; 1760 u8 reserved_at_1d3[0x2]; 1761 u8 fpga[0x1]; 1762 u8 rol_s[0x1]; 1763 u8 rol_g[0x1]; 1764 u8 reserved_at_1d8[0x1]; 1765 u8 wol_s[0x1]; 1766 u8 wol_g[0x1]; 1767 u8 wol_a[0x1]; 1768 u8 wol_b[0x1]; 1769 u8 wol_m[0x1]; 1770 u8 wol_u[0x1]; 1771 u8 wol_p[0x1]; 1772 1773 u8 stat_rate_support[0x10]; 1774 u8 reserved_at_1f0[0x1]; 1775 u8 pci_sync_for_fw_update_event[0x1]; 1776 u8 reserved_at_1f2[0x6]; 1777 u8 init2_lag_tx_port_affinity[0x1]; 1778 u8 reserved_at_1fa[0x2]; 1779 u8 wqe_based_flow_table_update_cap[0x1]; 1780 u8 cqe_version[0x4]; 1781 1782 u8 compact_address_vector[0x1]; 1783 u8 striding_rq[0x1]; 1784 u8 reserved_at_202[0x1]; 1785 u8 ipoib_enhanced_offloads[0x1]; 1786 u8 ipoib_basic_offloads[0x1]; 1787 u8 reserved_at_205[0x1]; 1788 u8 repeated_block_disabled[0x1]; 1789 u8 umr_modify_entity_size_disabled[0x1]; 1790 u8 umr_modify_atomic_disabled[0x1]; 1791 u8 umr_indirect_mkey_disabled[0x1]; 1792 u8 umr_fence[0x2]; 1793 u8 dc_req_scat_data_cqe[0x1]; 1794 u8 reserved_at_20d[0x2]; 1795 u8 drain_sigerr[0x1]; 1796 u8 cmdif_checksum[0x2]; 1797 u8 sigerr_cqe[0x1]; 1798 u8 reserved_at_213[0x1]; 1799 u8 wq_signature[0x1]; 1800 u8 sctr_data_cqe[0x1]; 1801 u8 reserved_at_216[0x1]; 1802 u8 sho[0x1]; 1803 u8 tph[0x1]; 1804 u8 rf[0x1]; 1805 u8 dct[0x1]; 1806 u8 qos[0x1]; 1807 u8 eth_net_offloads[0x1]; 1808 u8 roce[0x1]; 1809 u8 atomic[0x1]; 1810 u8 reserved_at_21f[0x1]; 1811 1812 u8 cq_oi[0x1]; 1813 u8 cq_resize[0x1]; 1814 u8 cq_moderation[0x1]; 1815 u8 cq_period_mode_modify[0x1]; 1816 u8 reserved_at_224[0x2]; 1817 u8 cq_eq_remap[0x1]; 1818 u8 pg[0x1]; 1819 u8 block_lb_mc[0x1]; 1820 u8 reserved_at_229[0x1]; 1821 u8 scqe_break_moderation[0x1]; 1822 u8 cq_period_start_from_cqe[0x1]; 1823 u8 cd[0x1]; 1824 u8 reserved_at_22d[0x1]; 1825 u8 apm[0x1]; 1826 u8 vector_calc[0x1]; 1827 u8 umr_ptr_rlky[0x1]; 1828 u8 imaicl[0x1]; 1829 u8 qp_packet_based[0x1]; 1830 u8 reserved_at_233[0x3]; 1831 u8 qkv[0x1]; 1832 u8 pkv[0x1]; 1833 u8 set_deth_sqpn[0x1]; 1834 u8 reserved_at_239[0x3]; 1835 u8 xrc[0x1]; 1836 u8 ud[0x1]; 1837 u8 uc[0x1]; 1838 u8 rc[0x1]; 1839 1840 u8 uar_4k[0x1]; 1841 u8 reserved_at_241[0x7]; 1842 u8 fl_rc_qp_when_roce_disabled[0x1]; 1843 u8 regexp_params[0x1]; 1844 u8 uar_sz[0x6]; 1845 u8 port_selection_cap[0x1]; 1846 u8 nic_cap_reg[0x1]; 1847 u8 umem_uid_0[0x1]; 1848 u8 reserved_at_253[0x5]; 1849 u8 log_pg_sz[0x8]; 1850 1851 u8 bf[0x1]; 1852 u8 driver_version[0x1]; 1853 u8 pad_tx_eth_packet[0x1]; 1854 u8 reserved_at_263[0x3]; 1855 u8 mkey_by_name[0x1]; 1856 u8 reserved_at_267[0x4]; 1857 1858 u8 log_bf_reg_size[0x5]; 1859 1860 u8 disciplined_fr_counter[0x1]; 1861 u8 reserved_at_271[0x2]; 1862 u8 qp_error_syndrome[0x1]; 1863 u8 reserved_at_274[0x2]; 1864 u8 lag_dct[0x2]; 1865 u8 lag_tx_port_affinity[0x1]; 1866 u8 lag_native_fdb_selection[0x1]; 1867 u8 reserved_at_27a[0x1]; 1868 u8 lag_master[0x1]; 1869 u8 num_lag_ports[0x4]; 1870 1871 u8 reserved_at_280[0x10]; 1872 u8 max_wqe_sz_sq[0x10]; 1873 1874 u8 reserved_at_2a0[0x7]; 1875 u8 mkey_pcie_tph[0x1]; 1876 u8 reserved_at_2a8[0x3]; 1877 u8 shampo[0x1]; 1878 u8 reserved_at_2ac[0x4]; 1879 u8 max_wqe_sz_rq[0x10]; 1880 1881 u8 max_flow_counter_31_16[0x10]; 1882 u8 max_wqe_sz_sq_dc[0x10]; 1883 1884 u8 reserved_at_2e0[0x7]; 1885 u8 max_qp_mcg[0x19]; 1886 1887 u8 reserved_at_300[0x10]; 1888 u8 flow_counter_bulk_alloc[0x8]; 1889 u8 log_max_mcg[0x8]; 1890 1891 u8 reserved_at_320[0x3]; 1892 u8 log_max_transport_domain[0x5]; 1893 u8 reserved_at_328[0x2]; 1894 u8 relaxed_ordering_read[0x1]; 1895 u8 log_max_pd[0x5]; 1896 u8 dp_ordering_ooo_all_ud[0x1]; 1897 u8 dp_ordering_ooo_all_uc[0x1]; 1898 u8 dp_ordering_ooo_all_xrc[0x1]; 1899 u8 dp_ordering_ooo_all_dc[0x1]; 1900 u8 dp_ordering_ooo_all_rc[0x1]; 1901 u8 pcie_reset_using_hotreset_method[0x1]; 1902 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1903 u8 vnic_env_cnt_steering_fail[0x1]; 1904 u8 vport_counter_local_loopback[0x1]; 1905 u8 q_counter_aggregation[0x1]; 1906 u8 q_counter_other_vport[0x1]; 1907 u8 log_max_xrcd[0x5]; 1908 1909 u8 nic_receive_steering_discard[0x1]; 1910 u8 receive_discard_vport_down[0x1]; 1911 u8 transmit_discard_vport_down[0x1]; 1912 u8 eq_overrun_count[0x1]; 1913 u8 reserved_at_344[0x1]; 1914 u8 invalid_command_count[0x1]; 1915 u8 quota_exceeded_count[0x1]; 1916 u8 reserved_at_347[0x1]; 1917 u8 log_max_flow_counter_bulk[0x8]; 1918 u8 max_flow_counter_15_0[0x10]; 1919 1920 1921 u8 reserved_at_360[0x3]; 1922 u8 log_max_rq[0x5]; 1923 u8 reserved_at_368[0x3]; 1924 u8 log_max_sq[0x5]; 1925 u8 reserved_at_370[0x3]; 1926 u8 log_max_tir[0x5]; 1927 u8 reserved_at_378[0x3]; 1928 u8 log_max_tis[0x5]; 1929 1930 u8 basic_cyclic_rcv_wqe[0x1]; 1931 u8 reserved_at_381[0x2]; 1932 u8 log_max_rmp[0x5]; 1933 u8 reserved_at_388[0x3]; 1934 u8 log_max_rqt[0x5]; 1935 u8 reserved_at_390[0x3]; 1936 u8 log_max_rqt_size[0x5]; 1937 u8 reserved_at_398[0x3]; 1938 u8 log_max_tis_per_sq[0x5]; 1939 1940 u8 ext_stride_num_range[0x1]; 1941 u8 roce_rw_supported[0x1]; 1942 u8 log_max_current_uc_list_wr_supported[0x1]; 1943 u8 log_max_stride_sz_rq[0x5]; 1944 u8 reserved_at_3a8[0x3]; 1945 u8 log_min_stride_sz_rq[0x5]; 1946 u8 reserved_at_3b0[0x3]; 1947 u8 log_max_stride_sz_sq[0x5]; 1948 u8 reserved_at_3b8[0x3]; 1949 u8 log_min_stride_sz_sq[0x5]; 1950 1951 u8 hairpin[0x1]; 1952 u8 reserved_at_3c1[0x2]; 1953 u8 log_max_hairpin_queues[0x5]; 1954 u8 reserved_at_3c8[0x3]; 1955 u8 log_max_hairpin_wq_data_sz[0x5]; 1956 u8 reserved_at_3d0[0x3]; 1957 u8 log_max_hairpin_num_packets[0x5]; 1958 u8 reserved_at_3d8[0x3]; 1959 u8 log_max_wq_sz[0x5]; 1960 1961 u8 nic_vport_change_event[0x1]; 1962 u8 disable_local_lb_uc[0x1]; 1963 u8 disable_local_lb_mc[0x1]; 1964 u8 log_min_hairpin_wq_data_sz[0x5]; 1965 u8 reserved_at_3e8[0x1]; 1966 u8 silent_mode[0x1]; 1967 u8 vhca_state[0x1]; 1968 u8 log_max_vlan_list[0x5]; 1969 u8 reserved_at_3f0[0x3]; 1970 u8 log_max_current_mc_list[0x5]; 1971 u8 reserved_at_3f8[0x3]; 1972 u8 log_max_current_uc_list[0x5]; 1973 1974 u8 general_obj_types[0x40]; 1975 1976 u8 sq_ts_format[0x2]; 1977 u8 rq_ts_format[0x2]; 1978 u8 steering_format_version[0x4]; 1979 u8 create_qp_start_hint[0x18]; 1980 1981 u8 reserved_at_460[0x1]; 1982 u8 ats[0x1]; 1983 u8 cross_vhca_rqt[0x1]; 1984 u8 log_max_uctx[0x5]; 1985 u8 reserved_at_468[0x1]; 1986 u8 crypto[0x1]; 1987 u8 ipsec_offload[0x1]; 1988 u8 log_max_umem[0x5]; 1989 u8 max_num_eqs[0x10]; 1990 1991 u8 reserved_at_480[0x1]; 1992 u8 tls_tx[0x1]; 1993 u8 tls_rx[0x1]; 1994 u8 log_max_l2_table[0x5]; 1995 u8 reserved_at_488[0x8]; 1996 u8 log_uar_page_sz[0x10]; 1997 1998 u8 reserved_at_4a0[0x20]; 1999 u8 device_frequency_mhz[0x20]; 2000 u8 device_frequency_khz[0x20]; 2001 2002 u8 reserved_at_500[0x20]; 2003 u8 num_of_uars_per_page[0x20]; 2004 2005 u8 flex_parser_protocols[0x20]; 2006 2007 u8 max_geneve_tlv_options[0x8]; 2008 u8 reserved_at_568[0x3]; 2009 u8 max_geneve_tlv_option_data_len[0x5]; 2010 u8 reserved_at_570[0x1]; 2011 u8 adv_rdma[0x1]; 2012 u8 reserved_at_572[0x7]; 2013 u8 adv_virtualization[0x1]; 2014 u8 reserved_at_57a[0x6]; 2015 2016 u8 reserved_at_580[0xb]; 2017 u8 log_max_dci_stream_channels[0x5]; 2018 u8 reserved_at_590[0x3]; 2019 u8 log_max_dci_errored_streams[0x5]; 2020 u8 reserved_at_598[0x8]; 2021 2022 u8 reserved_at_5a0[0x10]; 2023 u8 enhanced_cqe_compression[0x1]; 2024 u8 reserved_at_5b1[0x1]; 2025 u8 crossing_vhca_mkey[0x1]; 2026 u8 log_max_dek[0x5]; 2027 u8 reserved_at_5b8[0x4]; 2028 u8 mini_cqe_resp_stride_index[0x1]; 2029 u8 cqe_128_always[0x1]; 2030 u8 cqe_compression_128[0x1]; 2031 u8 cqe_compression[0x1]; 2032 2033 u8 cqe_compression_timeout[0x10]; 2034 u8 cqe_compression_max_num[0x10]; 2035 2036 u8 reserved_at_5e0[0x8]; 2037 u8 flex_parser_id_gtpu_dw_0[0x4]; 2038 u8 reserved_at_5ec[0x4]; 2039 u8 tag_matching[0x1]; 2040 u8 rndv_offload_rc[0x1]; 2041 u8 rndv_offload_dc[0x1]; 2042 u8 log_tag_matching_list_sz[0x5]; 2043 u8 reserved_at_5f8[0x3]; 2044 u8 log_max_xrq[0x5]; 2045 2046 u8 affiliate_nic_vport_criteria[0x8]; 2047 u8 native_port_num[0x8]; 2048 u8 num_vhca_ports[0x8]; 2049 u8 flex_parser_id_gtpu_teid[0x4]; 2050 u8 reserved_at_61c[0x2]; 2051 u8 sw_owner_id[0x1]; 2052 u8 reserved_at_61f[0x1]; 2053 2054 u8 max_num_of_monitor_counters[0x10]; 2055 u8 num_ppcnt_monitor_counters[0x10]; 2056 2057 u8 max_num_sf[0x10]; 2058 u8 num_q_monitor_counters[0x10]; 2059 2060 u8 reserved_at_660[0x20]; 2061 2062 u8 sf[0x1]; 2063 u8 sf_set_partition[0x1]; 2064 u8 reserved_at_682[0x1]; 2065 u8 log_max_sf[0x5]; 2066 u8 apu[0x1]; 2067 u8 reserved_at_689[0x4]; 2068 u8 migration[0x1]; 2069 u8 reserved_at_68e[0x2]; 2070 u8 log_min_sf_size[0x8]; 2071 u8 max_num_sf_partitions[0x8]; 2072 2073 u8 uctx_cap[0x20]; 2074 2075 u8 reserved_at_6c0[0x4]; 2076 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 2077 u8 flex_parser_id_icmp_dw1[0x4]; 2078 u8 flex_parser_id_icmp_dw0[0x4]; 2079 u8 flex_parser_id_icmpv6_dw1[0x4]; 2080 u8 flex_parser_id_icmpv6_dw0[0x4]; 2081 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 2082 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 2083 2084 u8 max_num_match_definer[0x10]; 2085 u8 sf_base_id[0x10]; 2086 2087 u8 flex_parser_id_gtpu_dw_2[0x4]; 2088 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 2089 u8 num_total_dynamic_vf_msix[0x18]; 2090 u8 reserved_at_720[0x14]; 2091 u8 dynamic_msix_table_size[0xc]; 2092 u8 reserved_at_740[0xc]; 2093 u8 min_dynamic_vf_msix_table_size[0x4]; 2094 u8 reserved_at_750[0x2]; 2095 u8 data_direct[0x1]; 2096 u8 reserved_at_753[0x1]; 2097 u8 max_dynamic_vf_msix_table_size[0xc]; 2098 2099 u8 reserved_at_760[0x3]; 2100 u8 log_max_num_header_modify_argument[0x5]; 2101 u8 log_header_modify_argument_granularity_offset[0x4]; 2102 u8 log_header_modify_argument_granularity[0x4]; 2103 u8 reserved_at_770[0x3]; 2104 u8 log_header_modify_argument_max_alloc[0x5]; 2105 u8 reserved_at_778[0x8]; 2106 2107 u8 vhca_tunnel_commands[0x40]; 2108 u8 match_definer_format_supported[0x40]; 2109 }; 2110 2111 enum { 2112 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 2113 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 2114 }; 2115 2116 enum { 2117 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 2118 }; 2119 2120 struct mlx5_ifc_cmd_hca_cap_2_bits { 2121 u8 reserved_at_0[0x80]; 2122 2123 u8 migratable[0x1]; 2124 u8 reserved_at_81[0x7]; 2125 u8 dp_ordering_force[0x1]; 2126 u8 reserved_at_89[0x9]; 2127 u8 query_vuid[0x1]; 2128 u8 reserved_at_93[0x5]; 2129 u8 umr_log_entity_size_5[0x1]; 2130 u8 reserved_at_99[0x7]; 2131 2132 u8 max_reformat_insert_size[0x8]; 2133 u8 max_reformat_insert_offset[0x8]; 2134 u8 max_reformat_remove_size[0x8]; 2135 u8 max_reformat_remove_offset[0x8]; 2136 2137 u8 reserved_at_c0[0x8]; 2138 u8 migration_multi_load[0x1]; 2139 u8 migration_tracking_state[0x1]; 2140 u8 multiplane_qp_ud[0x1]; 2141 u8 reserved_at_cb[0x5]; 2142 u8 migration_in_chunks[0x1]; 2143 u8 reserved_at_d1[0x1]; 2144 u8 sf_eq_usage[0x1]; 2145 u8 reserved_at_d3[0x5]; 2146 u8 multiplane[0x1]; 2147 u8 reserved_at_d9[0x7]; 2148 2149 u8 cross_vhca_object_to_object_supported[0x20]; 2150 2151 u8 allowed_object_for_other_vhca_access[0x40]; 2152 2153 u8 reserved_at_140[0x60]; 2154 2155 u8 flow_table_type_2_type[0x8]; 2156 u8 reserved_at_1a8[0x2]; 2157 u8 format_select_dw_8_6_ext[0x1]; 2158 u8 log_min_mkey_entity_size[0x5]; 2159 u8 reserved_at_1b0[0x10]; 2160 2161 u8 general_obj_types_127_64[0x40]; 2162 u8 reserved_at_200[0x20]; 2163 2164 u8 reserved_at_220[0x1]; 2165 u8 sw_vhca_id_valid[0x1]; 2166 u8 sw_vhca_id[0xe]; 2167 u8 reserved_at_230[0x10]; 2168 2169 u8 reserved_at_240[0xb]; 2170 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2171 u8 reserved_at_250[0x10]; 2172 2173 u8 reserved_at_260[0x20]; 2174 2175 u8 format_select_dw_gtpu_dw_0[0x8]; 2176 u8 format_select_dw_gtpu_dw_1[0x8]; 2177 u8 format_select_dw_gtpu_dw_2[0x8]; 2178 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2179 2180 u8 generate_wqe_type[0x20]; 2181 2182 u8 reserved_at_2c0[0xc0]; 2183 2184 u8 reserved_at_380[0xb]; 2185 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2186 u8 ec_vf_vport_base[0x10]; 2187 2188 u8 reserved_at_3a0[0x2]; 2189 u8 max_mkey_log_entity_size_fixed_buffer[0x6]; 2190 u8 reserved_at_3a8[0x2]; 2191 u8 max_mkey_log_entity_size_mtt[0x6]; 2192 u8 max_rqt_vhca_id[0x10]; 2193 2194 u8 reserved_at_3c0[0x20]; 2195 2196 u8 reserved_at_3e0[0x10]; 2197 u8 pcc_ifa2[0x1]; 2198 u8 reserved_at_3f1[0xf]; 2199 2200 u8 reserved_at_400[0x1]; 2201 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2202 u8 reserved_at_402[0xe]; 2203 u8 return_reg_id[0x10]; 2204 2205 u8 reserved_at_420[0x1c]; 2206 u8 flow_table_hash_type[0x4]; 2207 2208 u8 reserved_at_440[0x8]; 2209 u8 max_num_eqs_24b[0x18]; 2210 u8 reserved_at_460[0x3a0]; 2211 }; 2212 2213 enum mlx5_ifc_flow_destination_type { 2214 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2215 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2216 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2217 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2218 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2219 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2220 }; 2221 2222 enum mlx5_flow_table_miss_action { 2223 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2224 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2225 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2226 }; 2227 2228 struct mlx5_ifc_dest_format_struct_bits { 2229 u8 destination_type[0x8]; 2230 u8 destination_id[0x18]; 2231 2232 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2233 u8 packet_reformat[0x1]; 2234 u8 reserved_at_22[0x6]; 2235 u8 destination_table_type[0x8]; 2236 u8 destination_eswitch_owner_vhca_id[0x10]; 2237 }; 2238 2239 struct mlx5_ifc_flow_counter_list_bits { 2240 u8 flow_counter_id[0x20]; 2241 2242 u8 reserved_at_20[0x20]; 2243 }; 2244 2245 struct mlx5_ifc_extended_dest_format_bits { 2246 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2247 2248 u8 packet_reformat_id[0x20]; 2249 2250 u8 reserved_at_60[0x20]; 2251 }; 2252 2253 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 2254 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2255 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2256 }; 2257 2258 struct mlx5_ifc_fte_match_param_bits { 2259 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2260 2261 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2262 2263 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2264 2265 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2266 2267 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2268 2269 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2270 2271 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2272 2273 u8 reserved_at_e00[0x200]; 2274 }; 2275 2276 enum { 2277 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2278 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2279 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2280 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2281 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2282 }; 2283 2284 struct mlx5_ifc_rx_hash_field_select_bits { 2285 u8 l3_prot_type[0x1]; 2286 u8 l4_prot_type[0x1]; 2287 u8 selected_fields[0x1e]; 2288 }; 2289 2290 enum { 2291 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2292 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2293 }; 2294 2295 enum { 2296 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2297 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2298 }; 2299 2300 struct mlx5_ifc_wq_bits { 2301 u8 wq_type[0x4]; 2302 u8 wq_signature[0x1]; 2303 u8 end_padding_mode[0x2]; 2304 u8 cd_slave[0x1]; 2305 u8 reserved_at_8[0x18]; 2306 2307 u8 hds_skip_first_sge[0x1]; 2308 u8 log2_hds_buf_size[0x3]; 2309 u8 reserved_at_24[0x7]; 2310 u8 page_offset[0x5]; 2311 u8 lwm[0x10]; 2312 2313 u8 reserved_at_40[0x8]; 2314 u8 pd[0x18]; 2315 2316 u8 reserved_at_60[0x8]; 2317 u8 uar_page[0x18]; 2318 2319 u8 dbr_addr[0x40]; 2320 2321 u8 hw_counter[0x20]; 2322 2323 u8 sw_counter[0x20]; 2324 2325 u8 reserved_at_100[0xc]; 2326 u8 log_wq_stride[0x4]; 2327 u8 reserved_at_110[0x3]; 2328 u8 log_wq_pg_sz[0x5]; 2329 u8 reserved_at_118[0x3]; 2330 u8 log_wq_sz[0x5]; 2331 2332 u8 dbr_umem_valid[0x1]; 2333 u8 wq_umem_valid[0x1]; 2334 u8 reserved_at_122[0x1]; 2335 u8 log_hairpin_num_packets[0x5]; 2336 u8 reserved_at_128[0x3]; 2337 u8 log_hairpin_data_sz[0x5]; 2338 2339 u8 reserved_at_130[0x4]; 2340 u8 log_wqe_num_of_strides[0x4]; 2341 u8 two_byte_shift_en[0x1]; 2342 u8 reserved_at_139[0x4]; 2343 u8 log_wqe_stride_size[0x3]; 2344 2345 u8 dbr_umem_id[0x20]; 2346 u8 wq_umem_id[0x20]; 2347 2348 u8 wq_umem_offset[0x40]; 2349 2350 u8 headers_mkey[0x20]; 2351 2352 u8 shampo_enable[0x1]; 2353 u8 reserved_at_1e1[0x1]; 2354 u8 shampo_mode[0x2]; 2355 u8 reserved_at_1e4[0x1]; 2356 u8 log_reservation_size[0x3]; 2357 u8 reserved_at_1e8[0x5]; 2358 u8 log_max_num_of_packets_per_reservation[0x3]; 2359 u8 reserved_at_1f0[0x6]; 2360 u8 log_headers_entry_size[0x2]; 2361 u8 reserved_at_1f8[0x4]; 2362 u8 log_headers_buffer_entry_num[0x4]; 2363 2364 u8 reserved_at_200[0x400]; 2365 2366 struct mlx5_ifc_cmd_pas_bits pas[]; 2367 }; 2368 2369 struct mlx5_ifc_rq_num_bits { 2370 u8 reserved_at_0[0x8]; 2371 u8 rq_num[0x18]; 2372 }; 2373 2374 struct mlx5_ifc_rq_vhca_bits { 2375 u8 reserved_at_0[0x8]; 2376 u8 rq_num[0x18]; 2377 u8 reserved_at_20[0x10]; 2378 u8 rq_vhca_id[0x10]; 2379 }; 2380 2381 struct mlx5_ifc_mac_address_layout_bits { 2382 u8 reserved_at_0[0x10]; 2383 u8 mac_addr_47_32[0x10]; 2384 2385 u8 mac_addr_31_0[0x20]; 2386 }; 2387 2388 struct mlx5_ifc_vlan_layout_bits { 2389 u8 reserved_at_0[0x14]; 2390 u8 vlan[0x0c]; 2391 2392 u8 reserved_at_20[0x20]; 2393 }; 2394 2395 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2396 u8 reserved_at_0[0xa0]; 2397 2398 u8 min_time_between_cnps[0x20]; 2399 2400 u8 reserved_at_c0[0x12]; 2401 u8 cnp_dscp[0x6]; 2402 u8 reserved_at_d8[0x4]; 2403 u8 cnp_prio_mode[0x1]; 2404 u8 cnp_802p_prio[0x3]; 2405 2406 u8 reserved_at_e0[0x720]; 2407 }; 2408 2409 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2410 u8 reserved_at_0[0x60]; 2411 2412 u8 reserved_at_60[0x4]; 2413 u8 clamp_tgt_rate[0x1]; 2414 u8 reserved_at_65[0x3]; 2415 u8 clamp_tgt_rate_after_time_inc[0x1]; 2416 u8 reserved_at_69[0x17]; 2417 2418 u8 reserved_at_80[0x20]; 2419 2420 u8 rpg_time_reset[0x20]; 2421 2422 u8 rpg_byte_reset[0x20]; 2423 2424 u8 rpg_threshold[0x20]; 2425 2426 u8 rpg_max_rate[0x20]; 2427 2428 u8 rpg_ai_rate[0x20]; 2429 2430 u8 rpg_hai_rate[0x20]; 2431 2432 u8 rpg_gd[0x20]; 2433 2434 u8 rpg_min_dec_fac[0x20]; 2435 2436 u8 rpg_min_rate[0x20]; 2437 2438 u8 reserved_at_1c0[0xe0]; 2439 2440 u8 rate_to_set_on_first_cnp[0x20]; 2441 2442 u8 dce_tcp_g[0x20]; 2443 2444 u8 dce_tcp_rtt[0x20]; 2445 2446 u8 rate_reduce_monitor_period[0x20]; 2447 2448 u8 reserved_at_320[0x20]; 2449 2450 u8 initial_alpha_value[0x20]; 2451 2452 u8 reserved_at_360[0x4a0]; 2453 }; 2454 2455 struct mlx5_ifc_cong_control_r_roce_general_bits { 2456 u8 reserved_at_0[0x80]; 2457 2458 u8 reserved_at_80[0x10]; 2459 u8 rtt_resp_dscp_valid[0x1]; 2460 u8 reserved_at_91[0x9]; 2461 u8 rtt_resp_dscp[0x6]; 2462 2463 u8 reserved_at_a0[0x760]; 2464 }; 2465 2466 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2467 u8 reserved_at_0[0x80]; 2468 2469 u8 rppp_max_rps[0x20]; 2470 2471 u8 rpg_time_reset[0x20]; 2472 2473 u8 rpg_byte_reset[0x20]; 2474 2475 u8 rpg_threshold[0x20]; 2476 2477 u8 rpg_max_rate[0x20]; 2478 2479 u8 rpg_ai_rate[0x20]; 2480 2481 u8 rpg_hai_rate[0x20]; 2482 2483 u8 rpg_gd[0x20]; 2484 2485 u8 rpg_min_dec_fac[0x20]; 2486 2487 u8 rpg_min_rate[0x20]; 2488 2489 u8 reserved_at_1c0[0x640]; 2490 }; 2491 2492 enum { 2493 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2494 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2495 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2496 }; 2497 2498 struct mlx5_ifc_resize_field_select_bits { 2499 u8 resize_field_select[0x20]; 2500 }; 2501 2502 struct mlx5_ifc_resource_dump_bits { 2503 u8 more_dump[0x1]; 2504 u8 inline_dump[0x1]; 2505 u8 reserved_at_2[0xa]; 2506 u8 seq_num[0x4]; 2507 u8 segment_type[0x10]; 2508 2509 u8 reserved_at_20[0x10]; 2510 u8 vhca_id[0x10]; 2511 2512 u8 index1[0x20]; 2513 2514 u8 index2[0x20]; 2515 2516 u8 num_of_obj1[0x10]; 2517 u8 num_of_obj2[0x10]; 2518 2519 u8 reserved_at_a0[0x20]; 2520 2521 u8 device_opaque[0x40]; 2522 2523 u8 mkey[0x20]; 2524 2525 u8 size[0x20]; 2526 2527 u8 address[0x40]; 2528 2529 u8 inline_data[52][0x20]; 2530 }; 2531 2532 struct mlx5_ifc_resource_dump_menu_record_bits { 2533 u8 reserved_at_0[0x4]; 2534 u8 num_of_obj2_supports_active[0x1]; 2535 u8 num_of_obj2_supports_all[0x1]; 2536 u8 must_have_num_of_obj2[0x1]; 2537 u8 support_num_of_obj2[0x1]; 2538 u8 num_of_obj1_supports_active[0x1]; 2539 u8 num_of_obj1_supports_all[0x1]; 2540 u8 must_have_num_of_obj1[0x1]; 2541 u8 support_num_of_obj1[0x1]; 2542 u8 must_have_index2[0x1]; 2543 u8 support_index2[0x1]; 2544 u8 must_have_index1[0x1]; 2545 u8 support_index1[0x1]; 2546 u8 segment_type[0x10]; 2547 2548 u8 segment_name[4][0x20]; 2549 2550 u8 index1_name[4][0x20]; 2551 2552 u8 index2_name[4][0x20]; 2553 }; 2554 2555 struct mlx5_ifc_resource_dump_segment_header_bits { 2556 u8 length_dw[0x10]; 2557 u8 segment_type[0x10]; 2558 }; 2559 2560 struct mlx5_ifc_resource_dump_command_segment_bits { 2561 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2562 2563 u8 segment_called[0x10]; 2564 u8 vhca_id[0x10]; 2565 2566 u8 index1[0x20]; 2567 2568 u8 index2[0x20]; 2569 2570 u8 num_of_obj1[0x10]; 2571 u8 num_of_obj2[0x10]; 2572 }; 2573 2574 struct mlx5_ifc_resource_dump_error_segment_bits { 2575 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2576 2577 u8 reserved_at_20[0x10]; 2578 u8 syndrome_id[0x10]; 2579 2580 u8 reserved_at_40[0x40]; 2581 2582 u8 error[8][0x20]; 2583 }; 2584 2585 struct mlx5_ifc_resource_dump_info_segment_bits { 2586 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2587 2588 u8 reserved_at_20[0x18]; 2589 u8 dump_version[0x8]; 2590 2591 u8 hw_version[0x20]; 2592 2593 u8 fw_version[0x20]; 2594 }; 2595 2596 struct mlx5_ifc_resource_dump_menu_segment_bits { 2597 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2598 2599 u8 reserved_at_20[0x10]; 2600 u8 num_of_records[0x10]; 2601 2602 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2603 }; 2604 2605 struct mlx5_ifc_resource_dump_resource_segment_bits { 2606 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2607 2608 u8 reserved_at_20[0x20]; 2609 2610 u8 index1[0x20]; 2611 2612 u8 index2[0x20]; 2613 2614 u8 payload[][0x20]; 2615 }; 2616 2617 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2618 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2619 }; 2620 2621 struct mlx5_ifc_menu_resource_dump_response_bits { 2622 struct mlx5_ifc_resource_dump_info_segment_bits info; 2623 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2624 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2625 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2626 }; 2627 2628 enum { 2629 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2630 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2631 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2632 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2633 }; 2634 2635 struct mlx5_ifc_modify_field_select_bits { 2636 u8 modify_field_select[0x20]; 2637 }; 2638 2639 struct mlx5_ifc_field_select_r_roce_np_bits { 2640 u8 field_select_r_roce_np[0x20]; 2641 }; 2642 2643 struct mlx5_ifc_field_select_r_roce_rp_bits { 2644 u8 field_select_r_roce_rp[0x20]; 2645 }; 2646 2647 enum { 2648 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2649 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2650 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2651 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2652 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2653 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2654 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2655 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2656 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2657 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2658 }; 2659 2660 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2661 u8 field_select_8021qaurp[0x20]; 2662 }; 2663 2664 struct mlx5_ifc_phys_layer_recovery_cntrs_bits { 2665 u8 total_successful_recovery_events[0x20]; 2666 2667 u8 reserved_at_20[0x7a0]; 2668 }; 2669 2670 struct mlx5_ifc_phys_layer_cntrs_bits { 2671 u8 time_since_last_clear_high[0x20]; 2672 2673 u8 time_since_last_clear_low[0x20]; 2674 2675 u8 symbol_errors_high[0x20]; 2676 2677 u8 symbol_errors_low[0x20]; 2678 2679 u8 sync_headers_errors_high[0x20]; 2680 2681 u8 sync_headers_errors_low[0x20]; 2682 2683 u8 edpl_bip_errors_lane0_high[0x20]; 2684 2685 u8 edpl_bip_errors_lane0_low[0x20]; 2686 2687 u8 edpl_bip_errors_lane1_high[0x20]; 2688 2689 u8 edpl_bip_errors_lane1_low[0x20]; 2690 2691 u8 edpl_bip_errors_lane2_high[0x20]; 2692 2693 u8 edpl_bip_errors_lane2_low[0x20]; 2694 2695 u8 edpl_bip_errors_lane3_high[0x20]; 2696 2697 u8 edpl_bip_errors_lane3_low[0x20]; 2698 2699 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2700 2701 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2702 2703 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2704 2705 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2706 2707 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2708 2709 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2710 2711 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2712 2713 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2714 2715 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2716 2717 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2718 2719 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2720 2721 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2722 2723 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2724 2725 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2726 2727 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2728 2729 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2730 2731 u8 rs_fec_corrected_blocks_high[0x20]; 2732 2733 u8 rs_fec_corrected_blocks_low[0x20]; 2734 2735 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2736 2737 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2738 2739 u8 rs_fec_no_errors_blocks_high[0x20]; 2740 2741 u8 rs_fec_no_errors_blocks_low[0x20]; 2742 2743 u8 rs_fec_single_error_blocks_high[0x20]; 2744 2745 u8 rs_fec_single_error_blocks_low[0x20]; 2746 2747 u8 rs_fec_corrected_symbols_total_high[0x20]; 2748 2749 u8 rs_fec_corrected_symbols_total_low[0x20]; 2750 2751 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2752 2753 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2754 2755 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2756 2757 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2758 2759 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2760 2761 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2762 2763 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2764 2765 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2766 2767 u8 link_down_events[0x20]; 2768 2769 u8 successful_recovery_events[0x20]; 2770 2771 u8 reserved_at_640[0x180]; 2772 }; 2773 2774 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2775 u8 time_since_last_clear_high[0x20]; 2776 2777 u8 time_since_last_clear_low[0x20]; 2778 2779 u8 phy_received_bits_high[0x20]; 2780 2781 u8 phy_received_bits_low[0x20]; 2782 2783 u8 phy_symbol_errors_high[0x20]; 2784 2785 u8 phy_symbol_errors_low[0x20]; 2786 2787 u8 phy_corrected_bits_high[0x20]; 2788 2789 u8 phy_corrected_bits_low[0x20]; 2790 2791 u8 phy_corrected_bits_lane0_high[0x20]; 2792 2793 u8 phy_corrected_bits_lane0_low[0x20]; 2794 2795 u8 phy_corrected_bits_lane1_high[0x20]; 2796 2797 u8 phy_corrected_bits_lane1_low[0x20]; 2798 2799 u8 phy_corrected_bits_lane2_high[0x20]; 2800 2801 u8 phy_corrected_bits_lane2_low[0x20]; 2802 2803 u8 phy_corrected_bits_lane3_high[0x20]; 2804 2805 u8 phy_corrected_bits_lane3_low[0x20]; 2806 2807 u8 reserved_at_200[0x5c0]; 2808 }; 2809 2810 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2811 u8 symbol_error_counter[0x10]; 2812 2813 u8 link_error_recovery_counter[0x8]; 2814 2815 u8 link_downed_counter[0x8]; 2816 2817 u8 port_rcv_errors[0x10]; 2818 2819 u8 port_rcv_remote_physical_errors[0x10]; 2820 2821 u8 port_rcv_switch_relay_errors[0x10]; 2822 2823 u8 port_xmit_discards[0x10]; 2824 2825 u8 port_xmit_constraint_errors[0x8]; 2826 2827 u8 port_rcv_constraint_errors[0x8]; 2828 2829 u8 reserved_at_70[0x8]; 2830 2831 u8 link_overrun_errors[0x8]; 2832 2833 u8 reserved_at_80[0x10]; 2834 2835 u8 vl_15_dropped[0x10]; 2836 2837 u8 reserved_at_a0[0x80]; 2838 2839 u8 port_xmit_wait[0x20]; 2840 }; 2841 2842 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2843 u8 reserved_at_0[0x300]; 2844 2845 u8 port_xmit_data_high[0x20]; 2846 2847 u8 port_xmit_data_low[0x20]; 2848 2849 u8 port_rcv_data_high[0x20]; 2850 2851 u8 port_rcv_data_low[0x20]; 2852 2853 u8 port_xmit_pkts_high[0x20]; 2854 2855 u8 port_xmit_pkts_low[0x20]; 2856 2857 u8 port_rcv_pkts_high[0x20]; 2858 2859 u8 port_rcv_pkts_low[0x20]; 2860 2861 u8 reserved_at_400[0x80]; 2862 2863 u8 port_unicast_xmit_pkts_high[0x20]; 2864 2865 u8 port_unicast_xmit_pkts_low[0x20]; 2866 2867 u8 port_multicast_xmit_pkts_high[0x20]; 2868 2869 u8 port_multicast_xmit_pkts_low[0x20]; 2870 2871 u8 port_unicast_rcv_pkts_high[0x20]; 2872 2873 u8 port_unicast_rcv_pkts_low[0x20]; 2874 2875 u8 port_multicast_rcv_pkts_high[0x20]; 2876 2877 u8 port_multicast_rcv_pkts_low[0x20]; 2878 2879 u8 reserved_at_580[0x240]; 2880 }; 2881 2882 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2883 u8 transmit_queue_high[0x20]; 2884 2885 u8 transmit_queue_low[0x20]; 2886 2887 u8 no_buffer_discard_uc_high[0x20]; 2888 2889 u8 no_buffer_discard_uc_low[0x20]; 2890 2891 u8 reserved_at_80[0x740]; 2892 }; 2893 2894 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2895 u8 wred_discard_high[0x20]; 2896 2897 u8 wred_discard_low[0x20]; 2898 2899 u8 ecn_marked_tc_high[0x20]; 2900 2901 u8 ecn_marked_tc_low[0x20]; 2902 2903 u8 reserved_at_80[0x740]; 2904 }; 2905 2906 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2907 u8 rx_octets_high[0x20]; 2908 2909 u8 rx_octets_low[0x20]; 2910 2911 u8 reserved_at_40[0xc0]; 2912 2913 u8 rx_frames_high[0x20]; 2914 2915 u8 rx_frames_low[0x20]; 2916 2917 u8 tx_octets_high[0x20]; 2918 2919 u8 tx_octets_low[0x20]; 2920 2921 u8 reserved_at_180[0xc0]; 2922 2923 u8 tx_frames_high[0x20]; 2924 2925 u8 tx_frames_low[0x20]; 2926 2927 u8 rx_pause_high[0x20]; 2928 2929 u8 rx_pause_low[0x20]; 2930 2931 u8 rx_pause_duration_high[0x20]; 2932 2933 u8 rx_pause_duration_low[0x20]; 2934 2935 u8 tx_pause_high[0x20]; 2936 2937 u8 tx_pause_low[0x20]; 2938 2939 u8 tx_pause_duration_high[0x20]; 2940 2941 u8 tx_pause_duration_low[0x20]; 2942 2943 u8 rx_pause_transition_high[0x20]; 2944 2945 u8 rx_pause_transition_low[0x20]; 2946 2947 u8 rx_discards_high[0x20]; 2948 2949 u8 rx_discards_low[0x20]; 2950 2951 u8 device_stall_minor_watermark_cnt_high[0x20]; 2952 2953 u8 device_stall_minor_watermark_cnt_low[0x20]; 2954 2955 u8 device_stall_critical_watermark_cnt_high[0x20]; 2956 2957 u8 device_stall_critical_watermark_cnt_low[0x20]; 2958 2959 u8 reserved_at_480[0x340]; 2960 }; 2961 2962 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2963 u8 port_transmit_wait_high[0x20]; 2964 2965 u8 port_transmit_wait_low[0x20]; 2966 2967 u8 reserved_at_40[0x100]; 2968 2969 u8 rx_buffer_almost_full_high[0x20]; 2970 2971 u8 rx_buffer_almost_full_low[0x20]; 2972 2973 u8 rx_buffer_full_high[0x20]; 2974 2975 u8 rx_buffer_full_low[0x20]; 2976 2977 u8 rx_icrc_encapsulated_high[0x20]; 2978 2979 u8 rx_icrc_encapsulated_low[0x20]; 2980 2981 u8 reserved_at_200[0x5c0]; 2982 }; 2983 2984 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2985 u8 dot3stats_alignment_errors_high[0x20]; 2986 2987 u8 dot3stats_alignment_errors_low[0x20]; 2988 2989 u8 dot3stats_fcs_errors_high[0x20]; 2990 2991 u8 dot3stats_fcs_errors_low[0x20]; 2992 2993 u8 dot3stats_single_collision_frames_high[0x20]; 2994 2995 u8 dot3stats_single_collision_frames_low[0x20]; 2996 2997 u8 dot3stats_multiple_collision_frames_high[0x20]; 2998 2999 u8 dot3stats_multiple_collision_frames_low[0x20]; 3000 3001 u8 dot3stats_sqe_test_errors_high[0x20]; 3002 3003 u8 dot3stats_sqe_test_errors_low[0x20]; 3004 3005 u8 dot3stats_deferred_transmissions_high[0x20]; 3006 3007 u8 dot3stats_deferred_transmissions_low[0x20]; 3008 3009 u8 dot3stats_late_collisions_high[0x20]; 3010 3011 u8 dot3stats_late_collisions_low[0x20]; 3012 3013 u8 dot3stats_excessive_collisions_high[0x20]; 3014 3015 u8 dot3stats_excessive_collisions_low[0x20]; 3016 3017 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 3018 3019 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 3020 3021 u8 dot3stats_carrier_sense_errors_high[0x20]; 3022 3023 u8 dot3stats_carrier_sense_errors_low[0x20]; 3024 3025 u8 dot3stats_frame_too_longs_high[0x20]; 3026 3027 u8 dot3stats_frame_too_longs_low[0x20]; 3028 3029 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 3030 3031 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 3032 3033 u8 dot3stats_symbol_errors_high[0x20]; 3034 3035 u8 dot3stats_symbol_errors_low[0x20]; 3036 3037 u8 dot3control_in_unknown_opcodes_high[0x20]; 3038 3039 u8 dot3control_in_unknown_opcodes_low[0x20]; 3040 3041 u8 dot3in_pause_frames_high[0x20]; 3042 3043 u8 dot3in_pause_frames_low[0x20]; 3044 3045 u8 dot3out_pause_frames_high[0x20]; 3046 3047 u8 dot3out_pause_frames_low[0x20]; 3048 3049 u8 reserved_at_400[0x3c0]; 3050 }; 3051 3052 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 3053 u8 ether_stats_drop_events_high[0x20]; 3054 3055 u8 ether_stats_drop_events_low[0x20]; 3056 3057 u8 ether_stats_octets_high[0x20]; 3058 3059 u8 ether_stats_octets_low[0x20]; 3060 3061 u8 ether_stats_pkts_high[0x20]; 3062 3063 u8 ether_stats_pkts_low[0x20]; 3064 3065 u8 ether_stats_broadcast_pkts_high[0x20]; 3066 3067 u8 ether_stats_broadcast_pkts_low[0x20]; 3068 3069 u8 ether_stats_multicast_pkts_high[0x20]; 3070 3071 u8 ether_stats_multicast_pkts_low[0x20]; 3072 3073 u8 ether_stats_crc_align_errors_high[0x20]; 3074 3075 u8 ether_stats_crc_align_errors_low[0x20]; 3076 3077 u8 ether_stats_undersize_pkts_high[0x20]; 3078 3079 u8 ether_stats_undersize_pkts_low[0x20]; 3080 3081 u8 ether_stats_oversize_pkts_high[0x20]; 3082 3083 u8 ether_stats_oversize_pkts_low[0x20]; 3084 3085 u8 ether_stats_fragments_high[0x20]; 3086 3087 u8 ether_stats_fragments_low[0x20]; 3088 3089 u8 ether_stats_jabbers_high[0x20]; 3090 3091 u8 ether_stats_jabbers_low[0x20]; 3092 3093 u8 ether_stats_collisions_high[0x20]; 3094 3095 u8 ether_stats_collisions_low[0x20]; 3096 3097 u8 ether_stats_pkts64octets_high[0x20]; 3098 3099 u8 ether_stats_pkts64octets_low[0x20]; 3100 3101 u8 ether_stats_pkts65to127octets_high[0x20]; 3102 3103 u8 ether_stats_pkts65to127octets_low[0x20]; 3104 3105 u8 ether_stats_pkts128to255octets_high[0x20]; 3106 3107 u8 ether_stats_pkts128to255octets_low[0x20]; 3108 3109 u8 ether_stats_pkts256to511octets_high[0x20]; 3110 3111 u8 ether_stats_pkts256to511octets_low[0x20]; 3112 3113 u8 ether_stats_pkts512to1023octets_high[0x20]; 3114 3115 u8 ether_stats_pkts512to1023octets_low[0x20]; 3116 3117 u8 ether_stats_pkts1024to1518octets_high[0x20]; 3118 3119 u8 ether_stats_pkts1024to1518octets_low[0x20]; 3120 3121 u8 ether_stats_pkts1519to2047octets_high[0x20]; 3122 3123 u8 ether_stats_pkts1519to2047octets_low[0x20]; 3124 3125 u8 ether_stats_pkts2048to4095octets_high[0x20]; 3126 3127 u8 ether_stats_pkts2048to4095octets_low[0x20]; 3128 3129 u8 ether_stats_pkts4096to8191octets_high[0x20]; 3130 3131 u8 ether_stats_pkts4096to8191octets_low[0x20]; 3132 3133 u8 ether_stats_pkts8192to10239octets_high[0x20]; 3134 3135 u8 ether_stats_pkts8192to10239octets_low[0x20]; 3136 3137 u8 reserved_at_540[0x280]; 3138 }; 3139 3140 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 3141 u8 if_in_octets_high[0x20]; 3142 3143 u8 if_in_octets_low[0x20]; 3144 3145 u8 if_in_ucast_pkts_high[0x20]; 3146 3147 u8 if_in_ucast_pkts_low[0x20]; 3148 3149 u8 if_in_discards_high[0x20]; 3150 3151 u8 if_in_discards_low[0x20]; 3152 3153 u8 if_in_errors_high[0x20]; 3154 3155 u8 if_in_errors_low[0x20]; 3156 3157 u8 if_in_unknown_protos_high[0x20]; 3158 3159 u8 if_in_unknown_protos_low[0x20]; 3160 3161 u8 if_out_octets_high[0x20]; 3162 3163 u8 if_out_octets_low[0x20]; 3164 3165 u8 if_out_ucast_pkts_high[0x20]; 3166 3167 u8 if_out_ucast_pkts_low[0x20]; 3168 3169 u8 if_out_discards_high[0x20]; 3170 3171 u8 if_out_discards_low[0x20]; 3172 3173 u8 if_out_errors_high[0x20]; 3174 3175 u8 if_out_errors_low[0x20]; 3176 3177 u8 if_in_multicast_pkts_high[0x20]; 3178 3179 u8 if_in_multicast_pkts_low[0x20]; 3180 3181 u8 if_in_broadcast_pkts_high[0x20]; 3182 3183 u8 if_in_broadcast_pkts_low[0x20]; 3184 3185 u8 if_out_multicast_pkts_high[0x20]; 3186 3187 u8 if_out_multicast_pkts_low[0x20]; 3188 3189 u8 if_out_broadcast_pkts_high[0x20]; 3190 3191 u8 if_out_broadcast_pkts_low[0x20]; 3192 3193 u8 reserved_at_340[0x480]; 3194 }; 3195 3196 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3197 u8 a_frames_transmitted_ok_high[0x20]; 3198 3199 u8 a_frames_transmitted_ok_low[0x20]; 3200 3201 u8 a_frames_received_ok_high[0x20]; 3202 3203 u8 a_frames_received_ok_low[0x20]; 3204 3205 u8 a_frame_check_sequence_errors_high[0x20]; 3206 3207 u8 a_frame_check_sequence_errors_low[0x20]; 3208 3209 u8 a_alignment_errors_high[0x20]; 3210 3211 u8 a_alignment_errors_low[0x20]; 3212 3213 u8 a_octets_transmitted_ok_high[0x20]; 3214 3215 u8 a_octets_transmitted_ok_low[0x20]; 3216 3217 u8 a_octets_received_ok_high[0x20]; 3218 3219 u8 a_octets_received_ok_low[0x20]; 3220 3221 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3222 3223 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3224 3225 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3226 3227 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3228 3229 u8 a_multicast_frames_received_ok_high[0x20]; 3230 3231 u8 a_multicast_frames_received_ok_low[0x20]; 3232 3233 u8 a_broadcast_frames_received_ok_high[0x20]; 3234 3235 u8 a_broadcast_frames_received_ok_low[0x20]; 3236 3237 u8 a_in_range_length_errors_high[0x20]; 3238 3239 u8 a_in_range_length_errors_low[0x20]; 3240 3241 u8 a_out_of_range_length_field_high[0x20]; 3242 3243 u8 a_out_of_range_length_field_low[0x20]; 3244 3245 u8 a_frame_too_long_errors_high[0x20]; 3246 3247 u8 a_frame_too_long_errors_low[0x20]; 3248 3249 u8 a_symbol_error_during_carrier_high[0x20]; 3250 3251 u8 a_symbol_error_during_carrier_low[0x20]; 3252 3253 u8 a_mac_control_frames_transmitted_high[0x20]; 3254 3255 u8 a_mac_control_frames_transmitted_low[0x20]; 3256 3257 u8 a_mac_control_frames_received_high[0x20]; 3258 3259 u8 a_mac_control_frames_received_low[0x20]; 3260 3261 u8 a_unsupported_opcodes_received_high[0x20]; 3262 3263 u8 a_unsupported_opcodes_received_low[0x20]; 3264 3265 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3266 3267 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3268 3269 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3270 3271 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3272 3273 u8 reserved_at_4c0[0x300]; 3274 }; 3275 3276 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3277 u8 life_time_counter_high[0x20]; 3278 3279 u8 life_time_counter_low[0x20]; 3280 3281 u8 rx_errors[0x20]; 3282 3283 u8 tx_errors[0x20]; 3284 3285 u8 l0_to_recovery_eieos[0x20]; 3286 3287 u8 l0_to_recovery_ts[0x20]; 3288 3289 u8 l0_to_recovery_framing[0x20]; 3290 3291 u8 l0_to_recovery_retrain[0x20]; 3292 3293 u8 crc_error_dllp[0x20]; 3294 3295 u8 crc_error_tlp[0x20]; 3296 3297 u8 tx_overflow_buffer_pkt_high[0x20]; 3298 3299 u8 tx_overflow_buffer_pkt_low[0x20]; 3300 3301 u8 outbound_stalled_reads[0x20]; 3302 3303 u8 outbound_stalled_writes[0x20]; 3304 3305 u8 outbound_stalled_reads_events[0x20]; 3306 3307 u8 outbound_stalled_writes_events[0x20]; 3308 3309 u8 reserved_at_200[0x5c0]; 3310 }; 3311 3312 struct mlx5_ifc_cmd_inter_comp_event_bits { 3313 u8 command_completion_vector[0x20]; 3314 3315 u8 reserved_at_20[0xc0]; 3316 }; 3317 3318 struct mlx5_ifc_stall_vl_event_bits { 3319 u8 reserved_at_0[0x18]; 3320 u8 port_num[0x1]; 3321 u8 reserved_at_19[0x3]; 3322 u8 vl[0x4]; 3323 3324 u8 reserved_at_20[0xa0]; 3325 }; 3326 3327 struct mlx5_ifc_db_bf_congestion_event_bits { 3328 u8 event_subtype[0x8]; 3329 u8 reserved_at_8[0x8]; 3330 u8 congestion_level[0x8]; 3331 u8 reserved_at_18[0x8]; 3332 3333 u8 reserved_at_20[0xa0]; 3334 }; 3335 3336 struct mlx5_ifc_gpio_event_bits { 3337 u8 reserved_at_0[0x60]; 3338 3339 u8 gpio_event_hi[0x20]; 3340 3341 u8 gpio_event_lo[0x20]; 3342 3343 u8 reserved_at_a0[0x40]; 3344 }; 3345 3346 struct mlx5_ifc_port_state_change_event_bits { 3347 u8 reserved_at_0[0x40]; 3348 3349 u8 port_num[0x4]; 3350 u8 reserved_at_44[0x1c]; 3351 3352 u8 reserved_at_60[0x80]; 3353 }; 3354 3355 struct mlx5_ifc_dropped_packet_logged_bits { 3356 u8 reserved_at_0[0xe0]; 3357 }; 3358 3359 struct mlx5_ifc_nic_cap_reg_bits { 3360 u8 reserved_at_0[0x1a]; 3361 u8 vhca_icm_ctrl[0x1]; 3362 u8 reserved_at_1b[0x5]; 3363 3364 u8 reserved_at_20[0x60]; 3365 }; 3366 3367 struct mlx5_ifc_default_timeout_bits { 3368 u8 to_multiplier[0x3]; 3369 u8 reserved_at_3[0x9]; 3370 u8 to_value[0x14]; 3371 }; 3372 3373 struct mlx5_ifc_dtor_reg_bits { 3374 u8 reserved_at_0[0x20]; 3375 3376 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3377 3378 u8 reserved_at_40[0x60]; 3379 3380 struct mlx5_ifc_default_timeout_bits health_poll_to; 3381 3382 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3383 3384 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3385 3386 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3387 3388 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3389 3390 struct mlx5_ifc_default_timeout_bits tear_down_to; 3391 3392 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3393 3394 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3395 3396 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3397 3398 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3399 3400 u8 reserved_at_1c0[0x20]; 3401 }; 3402 3403 struct mlx5_ifc_vhca_icm_ctrl_reg_bits { 3404 u8 vhca_id_valid[0x1]; 3405 u8 reserved_at_1[0xf]; 3406 u8 vhca_id[0x10]; 3407 3408 u8 reserved_at_20[0xa0]; 3409 3410 u8 cur_alloc_icm[0x20]; 3411 3412 u8 reserved_at_e0[0x120]; 3413 }; 3414 3415 enum { 3416 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3417 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3418 }; 3419 3420 struct mlx5_ifc_cq_error_bits { 3421 u8 reserved_at_0[0x8]; 3422 u8 cqn[0x18]; 3423 3424 u8 reserved_at_20[0x20]; 3425 3426 u8 reserved_at_40[0x18]; 3427 u8 syndrome[0x8]; 3428 3429 u8 reserved_at_60[0x80]; 3430 }; 3431 3432 struct mlx5_ifc_rdma_page_fault_event_bits { 3433 u8 bytes_committed[0x20]; 3434 3435 u8 r_key[0x20]; 3436 3437 u8 reserved_at_40[0x10]; 3438 u8 packet_len[0x10]; 3439 3440 u8 rdma_op_len[0x20]; 3441 3442 u8 rdma_va[0x40]; 3443 3444 u8 reserved_at_c0[0x5]; 3445 u8 rdma[0x1]; 3446 u8 write[0x1]; 3447 u8 requestor[0x1]; 3448 u8 qp_number[0x18]; 3449 }; 3450 3451 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3452 u8 bytes_committed[0x20]; 3453 3454 u8 reserved_at_20[0x10]; 3455 u8 wqe_index[0x10]; 3456 3457 u8 reserved_at_40[0x10]; 3458 u8 len[0x10]; 3459 3460 u8 reserved_at_60[0x60]; 3461 3462 u8 reserved_at_c0[0x5]; 3463 u8 rdma[0x1]; 3464 u8 write_read[0x1]; 3465 u8 requestor[0x1]; 3466 u8 qpn[0x18]; 3467 }; 3468 3469 struct mlx5_ifc_qp_events_bits { 3470 u8 reserved_at_0[0xa0]; 3471 3472 u8 type[0x8]; 3473 u8 reserved_at_a8[0x18]; 3474 3475 u8 reserved_at_c0[0x8]; 3476 u8 qpn_rqn_sqn[0x18]; 3477 }; 3478 3479 struct mlx5_ifc_dct_events_bits { 3480 u8 reserved_at_0[0xc0]; 3481 3482 u8 reserved_at_c0[0x8]; 3483 u8 dct_number[0x18]; 3484 }; 3485 3486 struct mlx5_ifc_comp_event_bits { 3487 u8 reserved_at_0[0xc0]; 3488 3489 u8 reserved_at_c0[0x8]; 3490 u8 cq_number[0x18]; 3491 }; 3492 3493 enum { 3494 MLX5_QPC_STATE_RST = 0x0, 3495 MLX5_QPC_STATE_INIT = 0x1, 3496 MLX5_QPC_STATE_RTR = 0x2, 3497 MLX5_QPC_STATE_RTS = 0x3, 3498 MLX5_QPC_STATE_SQER = 0x4, 3499 MLX5_QPC_STATE_ERR = 0x6, 3500 MLX5_QPC_STATE_SQD = 0x7, 3501 MLX5_QPC_STATE_SUSPENDED = 0x9, 3502 }; 3503 3504 enum { 3505 MLX5_QPC_ST_RC = 0x0, 3506 MLX5_QPC_ST_UC = 0x1, 3507 MLX5_QPC_ST_UD = 0x2, 3508 MLX5_QPC_ST_XRC = 0x3, 3509 MLX5_QPC_ST_DCI = 0x5, 3510 MLX5_QPC_ST_QP0 = 0x7, 3511 MLX5_QPC_ST_QP1 = 0x8, 3512 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3513 MLX5_QPC_ST_REG_UMR = 0xc, 3514 }; 3515 3516 enum { 3517 MLX5_QPC_PM_STATE_ARMED = 0x0, 3518 MLX5_QPC_PM_STATE_REARM = 0x1, 3519 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3520 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3521 }; 3522 3523 enum { 3524 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3525 }; 3526 3527 enum { 3528 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3529 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3530 }; 3531 3532 enum { 3533 MLX5_QPC_MTU_256_BYTES = 0x1, 3534 MLX5_QPC_MTU_512_BYTES = 0x2, 3535 MLX5_QPC_MTU_1K_BYTES = 0x3, 3536 MLX5_QPC_MTU_2K_BYTES = 0x4, 3537 MLX5_QPC_MTU_4K_BYTES = 0x5, 3538 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3539 }; 3540 3541 enum { 3542 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3543 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3544 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3545 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3546 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3547 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3548 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3549 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3550 }; 3551 3552 enum { 3553 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3554 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3555 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3556 }; 3557 3558 enum { 3559 MLX5_QPC_CS_RES_DISABLE = 0x0, 3560 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3561 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3562 }; 3563 3564 enum { 3565 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3566 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3567 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3568 }; 3569 3570 struct mlx5_ifc_qpc_bits { 3571 u8 state[0x4]; 3572 u8 lag_tx_port_affinity[0x4]; 3573 u8 st[0x8]; 3574 u8 reserved_at_10[0x2]; 3575 u8 isolate_vl_tc[0x1]; 3576 u8 pm_state[0x2]; 3577 u8 reserved_at_15[0x1]; 3578 u8 req_e2e_credit_mode[0x2]; 3579 u8 offload_type[0x4]; 3580 u8 end_padding_mode[0x2]; 3581 u8 reserved_at_1e[0x2]; 3582 3583 u8 wq_signature[0x1]; 3584 u8 block_lb_mc[0x1]; 3585 u8 atomic_like_write_en[0x1]; 3586 u8 latency_sensitive[0x1]; 3587 u8 reserved_at_24[0x1]; 3588 u8 drain_sigerr[0x1]; 3589 u8 reserved_at_26[0x1]; 3590 u8 dp_ordering_force[0x1]; 3591 u8 pd[0x18]; 3592 3593 u8 mtu[0x3]; 3594 u8 log_msg_max[0x5]; 3595 u8 reserved_at_48[0x1]; 3596 u8 log_rq_size[0x4]; 3597 u8 log_rq_stride[0x3]; 3598 u8 no_sq[0x1]; 3599 u8 log_sq_size[0x4]; 3600 u8 reserved_at_55[0x1]; 3601 u8 retry_mode[0x2]; 3602 u8 ts_format[0x2]; 3603 u8 reserved_at_5a[0x1]; 3604 u8 rlky[0x1]; 3605 u8 ulp_stateless_offload_mode[0x4]; 3606 3607 u8 counter_set_id[0x8]; 3608 u8 uar_page[0x18]; 3609 3610 u8 reserved_at_80[0x8]; 3611 u8 user_index[0x18]; 3612 3613 u8 reserved_at_a0[0x3]; 3614 u8 log_page_size[0x5]; 3615 u8 remote_qpn[0x18]; 3616 3617 struct mlx5_ifc_ads_bits primary_address_path; 3618 3619 struct mlx5_ifc_ads_bits secondary_address_path; 3620 3621 u8 log_ack_req_freq[0x4]; 3622 u8 reserved_at_384[0x4]; 3623 u8 log_sra_max[0x3]; 3624 u8 reserved_at_38b[0x2]; 3625 u8 retry_count[0x3]; 3626 u8 rnr_retry[0x3]; 3627 u8 reserved_at_393[0x1]; 3628 u8 fre[0x1]; 3629 u8 cur_rnr_retry[0x3]; 3630 u8 cur_retry_count[0x3]; 3631 u8 reserved_at_39b[0x5]; 3632 3633 u8 reserved_at_3a0[0x20]; 3634 3635 u8 reserved_at_3c0[0x8]; 3636 u8 next_send_psn[0x18]; 3637 3638 u8 reserved_at_3e0[0x3]; 3639 u8 log_num_dci_stream_channels[0x5]; 3640 u8 cqn_snd[0x18]; 3641 3642 u8 reserved_at_400[0x3]; 3643 u8 log_num_dci_errored_streams[0x5]; 3644 u8 deth_sqpn[0x18]; 3645 3646 u8 reserved_at_420[0x20]; 3647 3648 u8 reserved_at_440[0x8]; 3649 u8 last_acked_psn[0x18]; 3650 3651 u8 reserved_at_460[0x8]; 3652 u8 ssn[0x18]; 3653 3654 u8 reserved_at_480[0x8]; 3655 u8 log_rra_max[0x3]; 3656 u8 reserved_at_48b[0x1]; 3657 u8 atomic_mode[0x4]; 3658 u8 rre[0x1]; 3659 u8 rwe[0x1]; 3660 u8 rae[0x1]; 3661 u8 reserved_at_493[0x1]; 3662 u8 page_offset[0x6]; 3663 u8 reserved_at_49a[0x2]; 3664 u8 dp_ordering_1[0x1]; 3665 u8 cd_slave_receive[0x1]; 3666 u8 cd_slave_send[0x1]; 3667 u8 cd_master[0x1]; 3668 3669 u8 reserved_at_4a0[0x3]; 3670 u8 min_rnr_nak[0x5]; 3671 u8 next_rcv_psn[0x18]; 3672 3673 u8 reserved_at_4c0[0x8]; 3674 u8 xrcd[0x18]; 3675 3676 u8 reserved_at_4e0[0x8]; 3677 u8 cqn_rcv[0x18]; 3678 3679 u8 dbr_addr[0x40]; 3680 3681 u8 q_key[0x20]; 3682 3683 u8 reserved_at_560[0x5]; 3684 u8 rq_type[0x3]; 3685 u8 srqn_rmpn_xrqn[0x18]; 3686 3687 u8 reserved_at_580[0x8]; 3688 u8 rmsn[0x18]; 3689 3690 u8 hw_sq_wqebb_counter[0x10]; 3691 u8 sw_sq_wqebb_counter[0x10]; 3692 3693 u8 hw_rq_counter[0x20]; 3694 3695 u8 sw_rq_counter[0x20]; 3696 3697 u8 reserved_at_600[0x20]; 3698 3699 u8 reserved_at_620[0xf]; 3700 u8 cgs[0x1]; 3701 u8 cs_req[0x8]; 3702 u8 cs_res[0x8]; 3703 3704 u8 dc_access_key[0x40]; 3705 3706 u8 reserved_at_680[0x3]; 3707 u8 dbr_umem_valid[0x1]; 3708 3709 u8 reserved_at_684[0xbc]; 3710 }; 3711 3712 struct mlx5_ifc_roce_addr_layout_bits { 3713 u8 source_l3_address[16][0x8]; 3714 3715 u8 reserved_at_80[0x3]; 3716 u8 vlan_valid[0x1]; 3717 u8 vlan_id[0xc]; 3718 u8 source_mac_47_32[0x10]; 3719 3720 u8 source_mac_31_0[0x20]; 3721 3722 u8 reserved_at_c0[0x14]; 3723 u8 roce_l3_type[0x4]; 3724 u8 roce_version[0x8]; 3725 3726 u8 reserved_at_e0[0x20]; 3727 }; 3728 3729 struct mlx5_ifc_crypto_cap_bits { 3730 u8 reserved_at_0[0x3]; 3731 u8 synchronize_dek[0x1]; 3732 u8 int_kek_manual[0x1]; 3733 u8 int_kek_auto[0x1]; 3734 u8 reserved_at_6[0x1a]; 3735 3736 u8 reserved_at_20[0x3]; 3737 u8 log_dek_max_alloc[0x5]; 3738 u8 reserved_at_28[0x3]; 3739 u8 log_max_num_deks[0x5]; 3740 u8 reserved_at_30[0x10]; 3741 3742 u8 reserved_at_40[0x20]; 3743 3744 u8 reserved_at_60[0x3]; 3745 u8 log_dek_granularity[0x5]; 3746 u8 reserved_at_68[0x3]; 3747 u8 log_max_num_int_kek[0x5]; 3748 u8 sw_wrapped_dek[0x10]; 3749 3750 u8 reserved_at_80[0x780]; 3751 }; 3752 3753 struct mlx5_ifc_shampo_cap_bits { 3754 u8 reserved_at_0[0x3]; 3755 u8 shampo_log_max_reservation_size[0x5]; 3756 u8 reserved_at_8[0x3]; 3757 u8 shampo_log_min_reservation_size[0x5]; 3758 u8 shampo_min_mss_size[0x10]; 3759 3760 u8 shampo_header_split[0x1]; 3761 u8 shampo_header_split_data_merge[0x1]; 3762 u8 reserved_at_22[0x1]; 3763 u8 shampo_log_max_headers_entry_size[0x5]; 3764 u8 reserved_at_28[0x18]; 3765 3766 u8 reserved_at_40[0x7c0]; 3767 }; 3768 3769 union mlx5_ifc_hca_cap_union_bits { 3770 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3771 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3772 struct mlx5_ifc_odp_cap_bits odp_cap; 3773 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3774 struct mlx5_ifc_roce_cap_bits roce_cap; 3775 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3776 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3777 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3778 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 3779 struct mlx5_ifc_esw_cap_bits esw_cap; 3780 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3781 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3782 struct mlx5_ifc_qos_cap_bits qos_cap; 3783 struct mlx5_ifc_debug_cap_bits debug_cap; 3784 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3785 struct mlx5_ifc_tls_cap_bits tls_cap; 3786 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3787 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3788 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3789 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3790 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3791 u8 reserved_at_0[0x8000]; 3792 }; 3793 3794 enum { 3795 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3796 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3797 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3798 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3799 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3800 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3801 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3802 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3803 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3804 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3805 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3806 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3807 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3808 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3809 }; 3810 3811 enum { 3812 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3813 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3814 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3815 }; 3816 3817 enum { 3818 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3819 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3820 }; 3821 3822 struct mlx5_ifc_vlan_bits { 3823 u8 ethtype[0x10]; 3824 u8 prio[0x3]; 3825 u8 cfi[0x1]; 3826 u8 vid[0xc]; 3827 }; 3828 3829 enum { 3830 MLX5_FLOW_METER_COLOR_RED = 0x0, 3831 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3832 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3833 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3834 }; 3835 3836 enum { 3837 MLX5_EXE_ASO_FLOW_METER = 0x2, 3838 }; 3839 3840 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3841 u8 return_reg_id[0x4]; 3842 u8 aso_type[0x4]; 3843 u8 reserved_at_8[0x14]; 3844 u8 action[0x1]; 3845 u8 init_color[0x2]; 3846 u8 meter_id[0x1]; 3847 }; 3848 3849 union mlx5_ifc_exe_aso_ctrl { 3850 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3851 }; 3852 3853 struct mlx5_ifc_execute_aso_bits { 3854 u8 valid[0x1]; 3855 u8 reserved_at_1[0x7]; 3856 u8 aso_object_id[0x18]; 3857 3858 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3859 }; 3860 3861 struct mlx5_ifc_flow_context_bits { 3862 struct mlx5_ifc_vlan_bits push_vlan; 3863 3864 u8 group_id[0x20]; 3865 3866 u8 reserved_at_40[0x8]; 3867 u8 flow_tag[0x18]; 3868 3869 u8 reserved_at_60[0x10]; 3870 u8 action[0x10]; 3871 3872 u8 extended_destination[0x1]; 3873 u8 uplink_hairpin_en[0x1]; 3874 u8 flow_source[0x2]; 3875 u8 encrypt_decrypt_type[0x4]; 3876 u8 destination_list_size[0x18]; 3877 3878 u8 reserved_at_a0[0x8]; 3879 u8 flow_counter_list_size[0x18]; 3880 3881 u8 packet_reformat_id[0x20]; 3882 3883 u8 modify_header_id[0x20]; 3884 3885 struct mlx5_ifc_vlan_bits push_vlan_2; 3886 3887 u8 encrypt_decrypt_obj_id[0x20]; 3888 u8 reserved_at_140[0xc0]; 3889 3890 struct mlx5_ifc_fte_match_param_bits match_value; 3891 3892 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3893 3894 u8 reserved_at_1300[0x500]; 3895 3896 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 3897 }; 3898 3899 enum { 3900 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3901 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3902 }; 3903 3904 struct mlx5_ifc_xrc_srqc_bits { 3905 u8 state[0x4]; 3906 u8 log_xrc_srq_size[0x4]; 3907 u8 reserved_at_8[0x18]; 3908 3909 u8 wq_signature[0x1]; 3910 u8 cont_srq[0x1]; 3911 u8 reserved_at_22[0x1]; 3912 u8 rlky[0x1]; 3913 u8 basic_cyclic_rcv_wqe[0x1]; 3914 u8 log_rq_stride[0x3]; 3915 u8 xrcd[0x18]; 3916 3917 u8 page_offset[0x6]; 3918 u8 reserved_at_46[0x1]; 3919 u8 dbr_umem_valid[0x1]; 3920 u8 cqn[0x18]; 3921 3922 u8 reserved_at_60[0x20]; 3923 3924 u8 user_index_equal_xrc_srqn[0x1]; 3925 u8 reserved_at_81[0x1]; 3926 u8 log_page_size[0x6]; 3927 u8 user_index[0x18]; 3928 3929 u8 reserved_at_a0[0x20]; 3930 3931 u8 reserved_at_c0[0x8]; 3932 u8 pd[0x18]; 3933 3934 u8 lwm[0x10]; 3935 u8 wqe_cnt[0x10]; 3936 3937 u8 reserved_at_100[0x40]; 3938 3939 u8 db_record_addr_h[0x20]; 3940 3941 u8 db_record_addr_l[0x1e]; 3942 u8 reserved_at_17e[0x2]; 3943 3944 u8 reserved_at_180[0x80]; 3945 }; 3946 3947 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3948 u8 counter_error_queues[0x20]; 3949 3950 u8 total_error_queues[0x20]; 3951 3952 u8 send_queue_priority_update_flow[0x20]; 3953 3954 u8 reserved_at_60[0x20]; 3955 3956 u8 nic_receive_steering_discard[0x40]; 3957 3958 u8 receive_discard_vport_down[0x40]; 3959 3960 u8 transmit_discard_vport_down[0x40]; 3961 3962 u8 async_eq_overrun[0x20]; 3963 3964 u8 comp_eq_overrun[0x20]; 3965 3966 u8 reserved_at_180[0x20]; 3967 3968 u8 invalid_command[0x20]; 3969 3970 u8 quota_exceeded_command[0x20]; 3971 3972 u8 internal_rq_out_of_buffer[0x20]; 3973 3974 u8 cq_overrun[0x20]; 3975 3976 u8 eth_wqe_too_small[0x20]; 3977 3978 u8 reserved_at_220[0xc0]; 3979 3980 u8 generated_pkt_steering_fail[0x40]; 3981 3982 u8 handled_pkt_steering_fail[0x40]; 3983 3984 u8 reserved_at_360[0xc80]; 3985 }; 3986 3987 struct mlx5_ifc_traffic_counter_bits { 3988 u8 packets[0x40]; 3989 3990 u8 octets[0x40]; 3991 }; 3992 3993 struct mlx5_ifc_tisc_bits { 3994 u8 strict_lag_tx_port_affinity[0x1]; 3995 u8 tls_en[0x1]; 3996 u8 reserved_at_2[0x2]; 3997 u8 lag_tx_port_affinity[0x04]; 3998 3999 u8 reserved_at_8[0x4]; 4000 u8 prio[0x4]; 4001 u8 reserved_at_10[0x10]; 4002 4003 u8 reserved_at_20[0x100]; 4004 4005 u8 reserved_at_120[0x8]; 4006 u8 transport_domain[0x18]; 4007 4008 u8 reserved_at_140[0x8]; 4009 u8 underlay_qpn[0x18]; 4010 4011 u8 reserved_at_160[0x8]; 4012 u8 pd[0x18]; 4013 4014 u8 reserved_at_180[0x380]; 4015 }; 4016 4017 enum { 4018 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 4019 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 4020 }; 4021 4022 enum { 4023 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 4024 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 4025 }; 4026 4027 enum { 4028 MLX5_RX_HASH_FN_NONE = 0x0, 4029 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 4030 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 4031 }; 4032 4033 enum { 4034 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 4035 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 4036 }; 4037 4038 struct mlx5_ifc_tirc_bits { 4039 u8 reserved_at_0[0x20]; 4040 4041 u8 disp_type[0x4]; 4042 u8 tls_en[0x1]; 4043 u8 reserved_at_25[0x1b]; 4044 4045 u8 reserved_at_40[0x40]; 4046 4047 u8 reserved_at_80[0x4]; 4048 u8 lro_timeout_period_usecs[0x10]; 4049 u8 packet_merge_mask[0x4]; 4050 u8 lro_max_ip_payload_size[0x8]; 4051 4052 u8 reserved_at_a0[0x40]; 4053 4054 u8 reserved_at_e0[0x8]; 4055 u8 inline_rqn[0x18]; 4056 4057 u8 rx_hash_symmetric[0x1]; 4058 u8 reserved_at_101[0x1]; 4059 u8 tunneled_offload_en[0x1]; 4060 u8 reserved_at_103[0x5]; 4061 u8 indirect_table[0x18]; 4062 4063 u8 rx_hash_fn[0x4]; 4064 u8 reserved_at_124[0x2]; 4065 u8 self_lb_block[0x2]; 4066 u8 transport_domain[0x18]; 4067 4068 u8 rx_hash_toeplitz_key[10][0x20]; 4069 4070 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 4071 4072 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 4073 4074 u8 reserved_at_2c0[0x4c0]; 4075 }; 4076 4077 enum { 4078 MLX5_SRQC_STATE_GOOD = 0x0, 4079 MLX5_SRQC_STATE_ERROR = 0x1, 4080 }; 4081 4082 struct mlx5_ifc_srqc_bits { 4083 u8 state[0x4]; 4084 u8 log_srq_size[0x4]; 4085 u8 reserved_at_8[0x18]; 4086 4087 u8 wq_signature[0x1]; 4088 u8 cont_srq[0x1]; 4089 u8 reserved_at_22[0x1]; 4090 u8 rlky[0x1]; 4091 u8 reserved_at_24[0x1]; 4092 u8 log_rq_stride[0x3]; 4093 u8 xrcd[0x18]; 4094 4095 u8 page_offset[0x6]; 4096 u8 reserved_at_46[0x2]; 4097 u8 cqn[0x18]; 4098 4099 u8 reserved_at_60[0x20]; 4100 4101 u8 reserved_at_80[0x2]; 4102 u8 log_page_size[0x6]; 4103 u8 reserved_at_88[0x18]; 4104 4105 u8 reserved_at_a0[0x20]; 4106 4107 u8 reserved_at_c0[0x8]; 4108 u8 pd[0x18]; 4109 4110 u8 lwm[0x10]; 4111 u8 wqe_cnt[0x10]; 4112 4113 u8 reserved_at_100[0x40]; 4114 4115 u8 dbr_addr[0x40]; 4116 4117 u8 reserved_at_180[0x80]; 4118 }; 4119 4120 enum { 4121 MLX5_SQC_STATE_RST = 0x0, 4122 MLX5_SQC_STATE_RDY = 0x1, 4123 MLX5_SQC_STATE_ERR = 0x3, 4124 }; 4125 4126 struct mlx5_ifc_sqc_bits { 4127 u8 rlky[0x1]; 4128 u8 cd_master[0x1]; 4129 u8 fre[0x1]; 4130 u8 flush_in_error_en[0x1]; 4131 u8 allow_multi_pkt_send_wqe[0x1]; 4132 u8 min_wqe_inline_mode[0x3]; 4133 u8 state[0x4]; 4134 u8 reg_umr[0x1]; 4135 u8 allow_swp[0x1]; 4136 u8 hairpin[0x1]; 4137 u8 non_wire[0x1]; 4138 u8 reserved_at_10[0xa]; 4139 u8 ts_format[0x2]; 4140 u8 reserved_at_1c[0x4]; 4141 4142 u8 reserved_at_20[0x8]; 4143 u8 user_index[0x18]; 4144 4145 u8 reserved_at_40[0x8]; 4146 u8 cqn[0x18]; 4147 4148 u8 reserved_at_60[0x8]; 4149 u8 hairpin_peer_rq[0x18]; 4150 4151 u8 reserved_at_80[0x10]; 4152 u8 hairpin_peer_vhca[0x10]; 4153 4154 u8 reserved_at_a0[0x20]; 4155 4156 u8 reserved_at_c0[0x8]; 4157 u8 ts_cqe_to_dest_cqn[0x18]; 4158 4159 u8 reserved_at_e0[0x10]; 4160 u8 packet_pacing_rate_limit_index[0x10]; 4161 u8 tis_lst_sz[0x10]; 4162 u8 qos_queue_group_id[0x10]; 4163 4164 u8 reserved_at_120[0x40]; 4165 4166 u8 reserved_at_160[0x8]; 4167 u8 tis_num_0[0x18]; 4168 4169 struct mlx5_ifc_wq_bits wq; 4170 }; 4171 4172 enum { 4173 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 4174 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 4175 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 4176 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 4177 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 4178 SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, 4179 }; 4180 4181 enum { 4182 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 4183 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 4184 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 4185 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 4186 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 4187 ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, 4188 }; 4189 4190 enum { 4191 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4192 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4193 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4194 TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, 4195 }; 4196 4197 enum { 4198 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 4199 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, 4200 TSAR_TYPE_CAP_MASK_ETS = 1 << 2, 4201 TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, 4202 }; 4203 4204 struct mlx5_ifc_tsar_element_bits { 4205 u8 traffic_class[0x4]; 4206 u8 reserved_at_4[0x4]; 4207 u8 tsar_type[0x8]; 4208 u8 reserved_at_10[0x10]; 4209 }; 4210 4211 struct mlx5_ifc_vport_element_bits { 4212 u8 reserved_at_0[0x4]; 4213 u8 eswitch_owner_vhca_id_valid[0x1]; 4214 u8 eswitch_owner_vhca_id[0xb]; 4215 u8 vport_number[0x10]; 4216 }; 4217 4218 struct mlx5_ifc_vport_tc_element_bits { 4219 u8 traffic_class[0x4]; 4220 u8 eswitch_owner_vhca_id_valid[0x1]; 4221 u8 eswitch_owner_vhca_id[0xb]; 4222 u8 vport_number[0x10]; 4223 }; 4224 4225 union mlx5_ifc_element_attributes_bits { 4226 struct mlx5_ifc_tsar_element_bits tsar; 4227 struct mlx5_ifc_vport_element_bits vport; 4228 struct mlx5_ifc_vport_tc_element_bits vport_tc; 4229 u8 reserved_at_0[0x20]; 4230 }; 4231 4232 struct mlx5_ifc_scheduling_context_bits { 4233 u8 element_type[0x8]; 4234 u8 reserved_at_8[0x18]; 4235 4236 union mlx5_ifc_element_attributes_bits element_attributes; 4237 4238 u8 parent_element_id[0x20]; 4239 4240 u8 reserved_at_60[0x40]; 4241 4242 u8 bw_share[0x20]; 4243 4244 u8 max_average_bw[0x20]; 4245 4246 u8 max_bw_obj_id[0x20]; 4247 4248 u8 reserved_at_100[0x100]; 4249 }; 4250 4251 struct mlx5_ifc_rqtc_bits { 4252 u8 reserved_at_0[0xa0]; 4253 4254 u8 reserved_at_a0[0x5]; 4255 u8 list_q_type[0x3]; 4256 u8 reserved_at_a8[0x8]; 4257 u8 rqt_max_size[0x10]; 4258 4259 u8 rq_vhca_id_format[0x1]; 4260 u8 reserved_at_c1[0xf]; 4261 u8 rqt_actual_size[0x10]; 4262 4263 u8 reserved_at_e0[0x6a0]; 4264 4265 union { 4266 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4267 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4268 }; 4269 }; 4270 4271 enum { 4272 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4273 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4274 }; 4275 4276 enum { 4277 MLX5_RQC_STATE_RST = 0x0, 4278 MLX5_RQC_STATE_RDY = 0x1, 4279 MLX5_RQC_STATE_ERR = 0x3, 4280 }; 4281 4282 enum { 4283 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4284 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4285 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4286 }; 4287 4288 enum { 4289 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4290 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4291 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4292 }; 4293 4294 struct mlx5_ifc_rqc_bits { 4295 u8 rlky[0x1]; 4296 u8 delay_drop_en[0x1]; 4297 u8 scatter_fcs[0x1]; 4298 u8 vsd[0x1]; 4299 u8 mem_rq_type[0x4]; 4300 u8 state[0x4]; 4301 u8 reserved_at_c[0x1]; 4302 u8 flush_in_error_en[0x1]; 4303 u8 hairpin[0x1]; 4304 u8 reserved_at_f[0xb]; 4305 u8 ts_format[0x2]; 4306 u8 reserved_at_1c[0x4]; 4307 4308 u8 reserved_at_20[0x8]; 4309 u8 user_index[0x18]; 4310 4311 u8 reserved_at_40[0x8]; 4312 u8 cqn[0x18]; 4313 4314 u8 counter_set_id[0x8]; 4315 u8 reserved_at_68[0x18]; 4316 4317 u8 reserved_at_80[0x8]; 4318 u8 rmpn[0x18]; 4319 4320 u8 reserved_at_a0[0x8]; 4321 u8 hairpin_peer_sq[0x18]; 4322 4323 u8 reserved_at_c0[0x10]; 4324 u8 hairpin_peer_vhca[0x10]; 4325 4326 u8 reserved_at_e0[0x46]; 4327 u8 shampo_no_match_alignment_granularity[0x2]; 4328 u8 reserved_at_128[0x6]; 4329 u8 shampo_match_criteria_type[0x2]; 4330 u8 reservation_timeout[0x10]; 4331 4332 u8 reserved_at_140[0x40]; 4333 4334 struct mlx5_ifc_wq_bits wq; 4335 }; 4336 4337 enum { 4338 MLX5_RMPC_STATE_RDY = 0x1, 4339 MLX5_RMPC_STATE_ERR = 0x3, 4340 }; 4341 4342 struct mlx5_ifc_rmpc_bits { 4343 u8 reserved_at_0[0x8]; 4344 u8 state[0x4]; 4345 u8 reserved_at_c[0x14]; 4346 4347 u8 basic_cyclic_rcv_wqe[0x1]; 4348 u8 reserved_at_21[0x1f]; 4349 4350 u8 reserved_at_40[0x140]; 4351 4352 struct mlx5_ifc_wq_bits wq; 4353 }; 4354 4355 enum { 4356 VHCA_ID_TYPE_HW = 0, 4357 VHCA_ID_TYPE_SW = 1, 4358 }; 4359 4360 struct mlx5_ifc_nic_vport_context_bits { 4361 u8 reserved_at_0[0x5]; 4362 u8 min_wqe_inline_mode[0x3]; 4363 u8 reserved_at_8[0x15]; 4364 u8 disable_mc_local_lb[0x1]; 4365 u8 disable_uc_local_lb[0x1]; 4366 u8 roce_en[0x1]; 4367 4368 u8 arm_change_event[0x1]; 4369 u8 reserved_at_21[0x1a]; 4370 u8 event_on_mtu[0x1]; 4371 u8 event_on_promisc_change[0x1]; 4372 u8 event_on_vlan_change[0x1]; 4373 u8 event_on_mc_address_change[0x1]; 4374 u8 event_on_uc_address_change[0x1]; 4375 4376 u8 vhca_id_type[0x1]; 4377 u8 reserved_at_41[0xb]; 4378 u8 affiliation_criteria[0x4]; 4379 u8 affiliated_vhca_id[0x10]; 4380 4381 u8 reserved_at_60[0xa0]; 4382 4383 u8 reserved_at_100[0x1]; 4384 u8 sd_group[0x3]; 4385 u8 reserved_at_104[0x1c]; 4386 4387 u8 reserved_at_120[0x10]; 4388 u8 mtu[0x10]; 4389 4390 u8 system_image_guid[0x40]; 4391 u8 port_guid[0x40]; 4392 u8 node_guid[0x40]; 4393 4394 u8 reserved_at_200[0x140]; 4395 u8 qkey_violation_counter[0x10]; 4396 u8 reserved_at_350[0x430]; 4397 4398 u8 promisc_uc[0x1]; 4399 u8 promisc_mc[0x1]; 4400 u8 promisc_all[0x1]; 4401 u8 reserved_at_783[0x2]; 4402 u8 allowed_list_type[0x3]; 4403 u8 reserved_at_788[0xc]; 4404 u8 allowed_list_size[0xc]; 4405 4406 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4407 4408 u8 reserved_at_7e0[0x20]; 4409 4410 u8 current_uc_mac_address[][0x40]; 4411 }; 4412 4413 enum { 4414 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4415 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4416 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4417 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4418 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4419 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4420 MLX5_MKC_ACCESS_MODE_CROSSING = 0x6, 4421 }; 4422 4423 enum { 4424 MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX = 0, 4425 }; 4426 4427 struct mlx5_ifc_mkc_bits { 4428 u8 reserved_at_0[0x1]; 4429 u8 free[0x1]; 4430 u8 reserved_at_2[0x1]; 4431 u8 access_mode_4_2[0x3]; 4432 u8 reserved_at_6[0x7]; 4433 u8 relaxed_ordering_write[0x1]; 4434 u8 reserved_at_e[0x1]; 4435 u8 small_fence_on_rdma_read_response[0x1]; 4436 u8 umr_en[0x1]; 4437 u8 a[0x1]; 4438 u8 rw[0x1]; 4439 u8 rr[0x1]; 4440 u8 lw[0x1]; 4441 u8 lr[0x1]; 4442 u8 access_mode_1_0[0x2]; 4443 u8 reserved_at_18[0x2]; 4444 u8 ma_translation_mode[0x2]; 4445 u8 reserved_at_1c[0x4]; 4446 4447 u8 qpn[0x18]; 4448 u8 mkey_7_0[0x8]; 4449 4450 u8 reserved_at_40[0x20]; 4451 4452 u8 length64[0x1]; 4453 u8 bsf_en[0x1]; 4454 u8 sync_umr[0x1]; 4455 u8 reserved_at_63[0x2]; 4456 u8 expected_sigerr_count[0x1]; 4457 u8 reserved_at_66[0x1]; 4458 u8 en_rinval[0x1]; 4459 u8 pd[0x18]; 4460 4461 u8 start_addr[0x40]; 4462 4463 u8 len[0x40]; 4464 4465 u8 bsf_octword_size[0x20]; 4466 4467 u8 reserved_at_120[0x60]; 4468 4469 u8 crossing_target_vhca_id[0x10]; 4470 u8 reserved_at_190[0x10]; 4471 4472 u8 translations_octword_size[0x20]; 4473 4474 u8 reserved_at_1c0[0x19]; 4475 u8 relaxed_ordering_read[0x1]; 4476 u8 log_page_size[0x6]; 4477 4478 u8 reserved_at_1e0[0x5]; 4479 u8 pcie_tph_en[0x1]; 4480 u8 pcie_tph_ph[0x2]; 4481 u8 pcie_tph_steering_tag_index[0x8]; 4482 u8 reserved_at_1f0[0x10]; 4483 }; 4484 4485 struct mlx5_ifc_pkey_bits { 4486 u8 reserved_at_0[0x10]; 4487 u8 pkey[0x10]; 4488 }; 4489 4490 struct mlx5_ifc_array128_auto_bits { 4491 u8 array128_auto[16][0x8]; 4492 }; 4493 4494 struct mlx5_ifc_hca_vport_context_bits { 4495 u8 field_select[0x20]; 4496 4497 u8 reserved_at_20[0xe0]; 4498 4499 u8 sm_virt_aware[0x1]; 4500 u8 has_smi[0x1]; 4501 u8 has_raw[0x1]; 4502 u8 grh_required[0x1]; 4503 u8 reserved_at_104[0x4]; 4504 u8 num_port_plane[0x8]; 4505 u8 port_physical_state[0x4]; 4506 u8 vport_state_policy[0x4]; 4507 u8 port_state[0x4]; 4508 u8 vport_state[0x4]; 4509 4510 u8 reserved_at_120[0x20]; 4511 4512 u8 system_image_guid[0x40]; 4513 4514 u8 port_guid[0x40]; 4515 4516 u8 node_guid[0x40]; 4517 4518 u8 cap_mask1[0x20]; 4519 4520 u8 cap_mask1_field_select[0x20]; 4521 4522 u8 cap_mask2[0x20]; 4523 4524 u8 cap_mask2_field_select[0x20]; 4525 4526 u8 reserved_at_280[0x80]; 4527 4528 u8 lid[0x10]; 4529 u8 reserved_at_310[0x4]; 4530 u8 init_type_reply[0x4]; 4531 u8 lmc[0x3]; 4532 u8 subnet_timeout[0x5]; 4533 4534 u8 sm_lid[0x10]; 4535 u8 sm_sl[0x4]; 4536 u8 reserved_at_334[0xc]; 4537 4538 u8 qkey_violation_counter[0x10]; 4539 u8 pkey_violation_counter[0x10]; 4540 4541 u8 reserved_at_360[0xca0]; 4542 }; 4543 4544 struct mlx5_ifc_esw_vport_context_bits { 4545 u8 fdb_to_vport_reg_c[0x1]; 4546 u8 reserved_at_1[0x2]; 4547 u8 vport_svlan_strip[0x1]; 4548 u8 vport_cvlan_strip[0x1]; 4549 u8 vport_svlan_insert[0x1]; 4550 u8 vport_cvlan_insert[0x2]; 4551 u8 fdb_to_vport_reg_c_id[0x8]; 4552 u8 reserved_at_10[0x10]; 4553 4554 u8 reserved_at_20[0x20]; 4555 4556 u8 svlan_cfi[0x1]; 4557 u8 svlan_pcp[0x3]; 4558 u8 svlan_id[0xc]; 4559 u8 cvlan_cfi[0x1]; 4560 u8 cvlan_pcp[0x3]; 4561 u8 cvlan_id[0xc]; 4562 4563 u8 reserved_at_60[0x720]; 4564 4565 u8 sw_steering_vport_icm_address_rx[0x40]; 4566 4567 u8 sw_steering_vport_icm_address_tx[0x40]; 4568 }; 4569 4570 enum { 4571 MLX5_EQC_STATUS_OK = 0x0, 4572 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4573 }; 4574 4575 enum { 4576 MLX5_EQC_ST_ARMED = 0x9, 4577 MLX5_EQC_ST_FIRED = 0xa, 4578 }; 4579 4580 struct mlx5_ifc_eqc_bits { 4581 u8 status[0x4]; 4582 u8 reserved_at_4[0x9]; 4583 u8 ec[0x1]; 4584 u8 oi[0x1]; 4585 u8 reserved_at_f[0x5]; 4586 u8 st[0x4]; 4587 u8 reserved_at_18[0x8]; 4588 4589 u8 reserved_at_20[0x20]; 4590 4591 u8 reserved_at_40[0x14]; 4592 u8 page_offset[0x6]; 4593 u8 reserved_at_5a[0x6]; 4594 4595 u8 reserved_at_60[0x3]; 4596 u8 log_eq_size[0x5]; 4597 u8 uar_page[0x18]; 4598 4599 u8 reserved_at_80[0x20]; 4600 4601 u8 reserved_at_a0[0x14]; 4602 u8 intr[0xc]; 4603 4604 u8 reserved_at_c0[0x3]; 4605 u8 log_page_size[0x5]; 4606 u8 reserved_at_c8[0x18]; 4607 4608 u8 reserved_at_e0[0x60]; 4609 4610 u8 reserved_at_140[0x8]; 4611 u8 consumer_counter[0x18]; 4612 4613 u8 reserved_at_160[0x8]; 4614 u8 producer_counter[0x18]; 4615 4616 u8 reserved_at_180[0x80]; 4617 }; 4618 4619 enum { 4620 MLX5_DCTC_STATE_ACTIVE = 0x0, 4621 MLX5_DCTC_STATE_DRAINING = 0x1, 4622 MLX5_DCTC_STATE_DRAINED = 0x2, 4623 }; 4624 4625 enum { 4626 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4627 MLX5_DCTC_CS_RES_NA = 0x1, 4628 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4629 }; 4630 4631 enum { 4632 MLX5_DCTC_MTU_256_BYTES = 0x1, 4633 MLX5_DCTC_MTU_512_BYTES = 0x2, 4634 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4635 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4636 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4637 }; 4638 4639 struct mlx5_ifc_dctc_bits { 4640 u8 reserved_at_0[0x4]; 4641 u8 state[0x4]; 4642 u8 reserved_at_8[0x18]; 4643 4644 u8 reserved_at_20[0x7]; 4645 u8 dp_ordering_force[0x1]; 4646 u8 user_index[0x18]; 4647 4648 u8 reserved_at_40[0x8]; 4649 u8 cqn[0x18]; 4650 4651 u8 counter_set_id[0x8]; 4652 u8 atomic_mode[0x4]; 4653 u8 rre[0x1]; 4654 u8 rwe[0x1]; 4655 u8 rae[0x1]; 4656 u8 atomic_like_write_en[0x1]; 4657 u8 latency_sensitive[0x1]; 4658 u8 rlky[0x1]; 4659 u8 free_ar[0x1]; 4660 u8 reserved_at_73[0x1]; 4661 u8 dp_ordering_1[0x1]; 4662 u8 reserved_at_75[0xb]; 4663 4664 u8 reserved_at_80[0x8]; 4665 u8 cs_res[0x8]; 4666 u8 reserved_at_90[0x3]; 4667 u8 min_rnr_nak[0x5]; 4668 u8 reserved_at_98[0x8]; 4669 4670 u8 reserved_at_a0[0x8]; 4671 u8 srqn_xrqn[0x18]; 4672 4673 u8 reserved_at_c0[0x8]; 4674 u8 pd[0x18]; 4675 4676 u8 tclass[0x8]; 4677 u8 reserved_at_e8[0x4]; 4678 u8 flow_label[0x14]; 4679 4680 u8 dc_access_key[0x40]; 4681 4682 u8 reserved_at_140[0x5]; 4683 u8 mtu[0x3]; 4684 u8 port[0x8]; 4685 u8 pkey_index[0x10]; 4686 4687 u8 reserved_at_160[0x8]; 4688 u8 my_addr_index[0x8]; 4689 u8 reserved_at_170[0x8]; 4690 u8 hop_limit[0x8]; 4691 4692 u8 dc_access_key_violation_count[0x20]; 4693 4694 u8 reserved_at_1a0[0x14]; 4695 u8 dei_cfi[0x1]; 4696 u8 eth_prio[0x3]; 4697 u8 ecn[0x2]; 4698 u8 dscp[0x6]; 4699 4700 u8 reserved_at_1c0[0x20]; 4701 u8 ece[0x20]; 4702 }; 4703 4704 enum { 4705 MLX5_CQC_STATUS_OK = 0x0, 4706 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4707 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4708 }; 4709 4710 enum { 4711 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4712 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4713 }; 4714 4715 enum { 4716 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4717 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4718 MLX5_CQC_ST_FIRED = 0xa, 4719 }; 4720 4721 enum mlx5_cq_period_mode { 4722 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4723 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4724 MLX5_CQ_PERIOD_NUM_MODES, 4725 }; 4726 4727 struct mlx5_ifc_cqc_bits { 4728 u8 status[0x4]; 4729 u8 reserved_at_4[0x2]; 4730 u8 dbr_umem_valid[0x1]; 4731 u8 apu_cq[0x1]; 4732 u8 cqe_sz[0x3]; 4733 u8 cc[0x1]; 4734 u8 reserved_at_c[0x1]; 4735 u8 scqe_break_moderation_en[0x1]; 4736 u8 oi[0x1]; 4737 u8 cq_period_mode[0x2]; 4738 u8 cqe_comp_en[0x1]; 4739 u8 mini_cqe_res_format[0x2]; 4740 u8 st[0x4]; 4741 u8 reserved_at_18[0x6]; 4742 u8 cqe_compression_layout[0x2]; 4743 4744 u8 reserved_at_20[0x20]; 4745 4746 u8 reserved_at_40[0x14]; 4747 u8 page_offset[0x6]; 4748 u8 reserved_at_5a[0x6]; 4749 4750 u8 reserved_at_60[0x3]; 4751 u8 log_cq_size[0x5]; 4752 u8 uar_page[0x18]; 4753 4754 u8 reserved_at_80[0x4]; 4755 u8 cq_period[0xc]; 4756 u8 cq_max_count[0x10]; 4757 4758 u8 c_eqn_or_apu_element[0x20]; 4759 4760 u8 reserved_at_c0[0x3]; 4761 u8 log_page_size[0x5]; 4762 u8 reserved_at_c8[0x18]; 4763 4764 u8 reserved_at_e0[0x20]; 4765 4766 u8 reserved_at_100[0x8]; 4767 u8 last_notified_index[0x18]; 4768 4769 u8 reserved_at_120[0x8]; 4770 u8 last_solicit_index[0x18]; 4771 4772 u8 reserved_at_140[0x8]; 4773 u8 consumer_counter[0x18]; 4774 4775 u8 reserved_at_160[0x8]; 4776 u8 producer_counter[0x18]; 4777 4778 u8 reserved_at_180[0x40]; 4779 4780 u8 dbr_addr[0x40]; 4781 }; 4782 4783 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4784 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4785 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4786 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4787 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4788 u8 reserved_at_0[0x800]; 4789 }; 4790 4791 struct mlx5_ifc_query_adapter_param_block_bits { 4792 u8 reserved_at_0[0xc0]; 4793 4794 u8 reserved_at_c0[0x8]; 4795 u8 ieee_vendor_id[0x18]; 4796 4797 u8 reserved_at_e0[0x10]; 4798 u8 vsd_vendor_id[0x10]; 4799 4800 u8 vsd[208][0x8]; 4801 4802 u8 vsd_contd_psid[16][0x8]; 4803 }; 4804 4805 enum { 4806 MLX5_XRQC_STATE_GOOD = 0x0, 4807 MLX5_XRQC_STATE_ERROR = 0x1, 4808 }; 4809 4810 enum { 4811 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4812 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4813 }; 4814 4815 enum { 4816 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4817 }; 4818 4819 struct mlx5_ifc_tag_matching_topology_context_bits { 4820 u8 log_matching_list_sz[0x4]; 4821 u8 reserved_at_4[0xc]; 4822 u8 append_next_index[0x10]; 4823 4824 u8 sw_phase_cnt[0x10]; 4825 u8 hw_phase_cnt[0x10]; 4826 4827 u8 reserved_at_40[0x40]; 4828 }; 4829 4830 struct mlx5_ifc_xrqc_bits { 4831 u8 state[0x4]; 4832 u8 rlkey[0x1]; 4833 u8 reserved_at_5[0xf]; 4834 u8 topology[0x4]; 4835 u8 reserved_at_18[0x4]; 4836 u8 offload[0x4]; 4837 4838 u8 reserved_at_20[0x8]; 4839 u8 user_index[0x18]; 4840 4841 u8 reserved_at_40[0x8]; 4842 u8 cqn[0x18]; 4843 4844 u8 reserved_at_60[0xa0]; 4845 4846 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4847 4848 u8 reserved_at_180[0x280]; 4849 4850 struct mlx5_ifc_wq_bits wq; 4851 }; 4852 4853 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4854 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4855 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4856 u8 reserved_at_0[0x20]; 4857 }; 4858 4859 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4860 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4861 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4862 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4863 u8 reserved_at_0[0x20]; 4864 }; 4865 4866 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4867 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4868 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4869 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4870 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4871 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4872 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4873 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4874 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4875 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4876 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4877 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4878 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4879 struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs; 4880 u8 reserved_at_0[0x7c0]; 4881 }; 4882 4883 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4884 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4885 u8 reserved_at_0[0x7c0]; 4886 }; 4887 4888 union mlx5_ifc_event_auto_bits { 4889 struct mlx5_ifc_comp_event_bits comp_event; 4890 struct mlx5_ifc_dct_events_bits dct_events; 4891 struct mlx5_ifc_qp_events_bits qp_events; 4892 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4893 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4894 struct mlx5_ifc_cq_error_bits cq_error; 4895 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4896 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4897 struct mlx5_ifc_gpio_event_bits gpio_event; 4898 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4899 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4900 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4901 u8 reserved_at_0[0xe0]; 4902 }; 4903 4904 struct mlx5_ifc_health_buffer_bits { 4905 u8 reserved_at_0[0x100]; 4906 4907 u8 assert_existptr[0x20]; 4908 4909 u8 assert_callra[0x20]; 4910 4911 u8 reserved_at_140[0x20]; 4912 4913 u8 time[0x20]; 4914 4915 u8 fw_version[0x20]; 4916 4917 u8 hw_id[0x20]; 4918 4919 u8 rfr[0x1]; 4920 u8 reserved_at_1c1[0x3]; 4921 u8 valid[0x1]; 4922 u8 severity[0x3]; 4923 u8 reserved_at_1c8[0x18]; 4924 4925 u8 irisc_index[0x8]; 4926 u8 synd[0x8]; 4927 u8 ext_synd[0x10]; 4928 }; 4929 4930 struct mlx5_ifc_register_loopback_control_bits { 4931 u8 no_lb[0x1]; 4932 u8 reserved_at_1[0x7]; 4933 u8 port[0x8]; 4934 u8 reserved_at_10[0x10]; 4935 4936 u8 reserved_at_20[0x60]; 4937 }; 4938 4939 enum { 4940 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4941 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4942 }; 4943 4944 struct mlx5_ifc_teardown_hca_out_bits { 4945 u8 status[0x8]; 4946 u8 reserved_at_8[0x18]; 4947 4948 u8 syndrome[0x20]; 4949 4950 u8 reserved_at_40[0x3f]; 4951 4952 u8 state[0x1]; 4953 }; 4954 4955 enum { 4956 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4957 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4958 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4959 }; 4960 4961 struct mlx5_ifc_teardown_hca_in_bits { 4962 u8 opcode[0x10]; 4963 u8 reserved_at_10[0x10]; 4964 4965 u8 reserved_at_20[0x10]; 4966 u8 op_mod[0x10]; 4967 4968 u8 reserved_at_40[0x10]; 4969 u8 profile[0x10]; 4970 4971 u8 reserved_at_60[0x20]; 4972 }; 4973 4974 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4975 u8 status[0x8]; 4976 u8 reserved_at_8[0x18]; 4977 4978 u8 syndrome[0x20]; 4979 4980 u8 reserved_at_40[0x40]; 4981 }; 4982 4983 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4984 u8 opcode[0x10]; 4985 u8 uid[0x10]; 4986 4987 u8 reserved_at_20[0x10]; 4988 u8 op_mod[0x10]; 4989 4990 u8 reserved_at_40[0x8]; 4991 u8 qpn[0x18]; 4992 4993 u8 reserved_at_60[0x20]; 4994 4995 u8 opt_param_mask[0x20]; 4996 4997 u8 reserved_at_a0[0x20]; 4998 4999 struct mlx5_ifc_qpc_bits qpc; 5000 5001 u8 reserved_at_800[0x80]; 5002 }; 5003 5004 struct mlx5_ifc_sqd2rts_qp_out_bits { 5005 u8 status[0x8]; 5006 u8 reserved_at_8[0x18]; 5007 5008 u8 syndrome[0x20]; 5009 5010 u8 reserved_at_40[0x40]; 5011 }; 5012 5013 struct mlx5_ifc_sqd2rts_qp_in_bits { 5014 u8 opcode[0x10]; 5015 u8 uid[0x10]; 5016 5017 u8 reserved_at_20[0x10]; 5018 u8 op_mod[0x10]; 5019 5020 u8 reserved_at_40[0x8]; 5021 u8 qpn[0x18]; 5022 5023 u8 reserved_at_60[0x20]; 5024 5025 u8 opt_param_mask[0x20]; 5026 5027 u8 reserved_at_a0[0x20]; 5028 5029 struct mlx5_ifc_qpc_bits qpc; 5030 5031 u8 reserved_at_800[0x80]; 5032 }; 5033 5034 struct mlx5_ifc_set_roce_address_out_bits { 5035 u8 status[0x8]; 5036 u8 reserved_at_8[0x18]; 5037 5038 u8 syndrome[0x20]; 5039 5040 u8 reserved_at_40[0x40]; 5041 }; 5042 5043 struct mlx5_ifc_set_roce_address_in_bits { 5044 u8 opcode[0x10]; 5045 u8 reserved_at_10[0x10]; 5046 5047 u8 reserved_at_20[0x10]; 5048 u8 op_mod[0x10]; 5049 5050 u8 roce_address_index[0x10]; 5051 u8 reserved_at_50[0xc]; 5052 u8 vhca_port_num[0x4]; 5053 5054 u8 reserved_at_60[0x20]; 5055 5056 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5057 }; 5058 5059 struct mlx5_ifc_set_mad_demux_out_bits { 5060 u8 status[0x8]; 5061 u8 reserved_at_8[0x18]; 5062 5063 u8 syndrome[0x20]; 5064 5065 u8 reserved_at_40[0x40]; 5066 }; 5067 5068 enum { 5069 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 5070 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 5071 }; 5072 5073 struct mlx5_ifc_set_mad_demux_in_bits { 5074 u8 opcode[0x10]; 5075 u8 reserved_at_10[0x10]; 5076 5077 u8 reserved_at_20[0x10]; 5078 u8 op_mod[0x10]; 5079 5080 u8 reserved_at_40[0x20]; 5081 5082 u8 reserved_at_60[0x6]; 5083 u8 demux_mode[0x2]; 5084 u8 reserved_at_68[0x18]; 5085 }; 5086 5087 struct mlx5_ifc_set_l2_table_entry_out_bits { 5088 u8 status[0x8]; 5089 u8 reserved_at_8[0x18]; 5090 5091 u8 syndrome[0x20]; 5092 5093 u8 reserved_at_40[0x40]; 5094 }; 5095 5096 struct mlx5_ifc_set_l2_table_entry_in_bits { 5097 u8 opcode[0x10]; 5098 u8 reserved_at_10[0x10]; 5099 5100 u8 reserved_at_20[0x10]; 5101 u8 op_mod[0x10]; 5102 5103 u8 reserved_at_40[0x60]; 5104 5105 u8 reserved_at_a0[0x8]; 5106 u8 table_index[0x18]; 5107 5108 u8 reserved_at_c0[0x20]; 5109 5110 u8 reserved_at_e0[0x10]; 5111 u8 silent_mode_valid[0x1]; 5112 u8 silent_mode[0x1]; 5113 u8 reserved_at_f2[0x1]; 5114 u8 vlan_valid[0x1]; 5115 u8 vlan[0xc]; 5116 5117 struct mlx5_ifc_mac_address_layout_bits mac_address; 5118 5119 u8 reserved_at_140[0xc0]; 5120 }; 5121 5122 struct mlx5_ifc_set_issi_out_bits { 5123 u8 status[0x8]; 5124 u8 reserved_at_8[0x18]; 5125 5126 u8 syndrome[0x20]; 5127 5128 u8 reserved_at_40[0x40]; 5129 }; 5130 5131 struct mlx5_ifc_set_issi_in_bits { 5132 u8 opcode[0x10]; 5133 u8 reserved_at_10[0x10]; 5134 5135 u8 reserved_at_20[0x10]; 5136 u8 op_mod[0x10]; 5137 5138 u8 reserved_at_40[0x10]; 5139 u8 current_issi[0x10]; 5140 5141 u8 reserved_at_60[0x20]; 5142 }; 5143 5144 struct mlx5_ifc_set_hca_cap_out_bits { 5145 u8 status[0x8]; 5146 u8 reserved_at_8[0x18]; 5147 5148 u8 syndrome[0x20]; 5149 5150 u8 reserved_at_40[0x40]; 5151 }; 5152 5153 struct mlx5_ifc_set_hca_cap_in_bits { 5154 u8 opcode[0x10]; 5155 u8 reserved_at_10[0x10]; 5156 5157 u8 reserved_at_20[0x10]; 5158 u8 op_mod[0x10]; 5159 5160 u8 other_function[0x1]; 5161 u8 ec_vf_function[0x1]; 5162 u8 reserved_at_42[0xe]; 5163 u8 function_id[0x10]; 5164 5165 u8 reserved_at_60[0x20]; 5166 5167 union mlx5_ifc_hca_cap_union_bits capability; 5168 }; 5169 5170 enum { 5171 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 5172 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 5173 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 5174 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 5175 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 5176 }; 5177 5178 struct mlx5_ifc_set_fte_out_bits { 5179 u8 status[0x8]; 5180 u8 reserved_at_8[0x18]; 5181 5182 u8 syndrome[0x20]; 5183 5184 u8 reserved_at_40[0x40]; 5185 }; 5186 5187 struct mlx5_ifc_set_fte_in_bits { 5188 u8 opcode[0x10]; 5189 u8 reserved_at_10[0x10]; 5190 5191 u8 reserved_at_20[0x10]; 5192 u8 op_mod[0x10]; 5193 5194 u8 other_vport[0x1]; 5195 u8 reserved_at_41[0xf]; 5196 u8 vport_number[0x10]; 5197 5198 u8 reserved_at_60[0x20]; 5199 5200 u8 table_type[0x8]; 5201 u8 reserved_at_88[0x18]; 5202 5203 u8 reserved_at_a0[0x8]; 5204 u8 table_id[0x18]; 5205 5206 u8 ignore_flow_level[0x1]; 5207 u8 reserved_at_c1[0x17]; 5208 u8 modify_enable_mask[0x8]; 5209 5210 u8 reserved_at_e0[0x20]; 5211 5212 u8 flow_index[0x20]; 5213 5214 u8 reserved_at_120[0xe0]; 5215 5216 struct mlx5_ifc_flow_context_bits flow_context; 5217 }; 5218 5219 struct mlx5_ifc_dest_format_bits { 5220 u8 destination_type[0x8]; 5221 u8 destination_id[0x18]; 5222 5223 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5224 u8 packet_reformat[0x1]; 5225 u8 reserved_at_22[0xe]; 5226 u8 destination_eswitch_owner_vhca_id[0x10]; 5227 }; 5228 5229 struct mlx5_ifc_rts2rts_qp_out_bits { 5230 u8 status[0x8]; 5231 u8 reserved_at_8[0x18]; 5232 5233 u8 syndrome[0x20]; 5234 5235 u8 reserved_at_40[0x20]; 5236 u8 ece[0x20]; 5237 }; 5238 5239 struct mlx5_ifc_rts2rts_qp_in_bits { 5240 u8 opcode[0x10]; 5241 u8 uid[0x10]; 5242 5243 u8 reserved_at_20[0x10]; 5244 u8 op_mod[0x10]; 5245 5246 u8 reserved_at_40[0x8]; 5247 u8 qpn[0x18]; 5248 5249 u8 reserved_at_60[0x20]; 5250 5251 u8 opt_param_mask[0x20]; 5252 5253 u8 ece[0x20]; 5254 5255 struct mlx5_ifc_qpc_bits qpc; 5256 5257 u8 reserved_at_800[0x80]; 5258 }; 5259 5260 struct mlx5_ifc_rtr2rts_qp_out_bits { 5261 u8 status[0x8]; 5262 u8 reserved_at_8[0x18]; 5263 5264 u8 syndrome[0x20]; 5265 5266 u8 reserved_at_40[0x20]; 5267 u8 ece[0x20]; 5268 }; 5269 5270 struct mlx5_ifc_rtr2rts_qp_in_bits { 5271 u8 opcode[0x10]; 5272 u8 uid[0x10]; 5273 5274 u8 reserved_at_20[0x10]; 5275 u8 op_mod[0x10]; 5276 5277 u8 reserved_at_40[0x8]; 5278 u8 qpn[0x18]; 5279 5280 u8 reserved_at_60[0x20]; 5281 5282 u8 opt_param_mask[0x20]; 5283 5284 u8 ece[0x20]; 5285 5286 struct mlx5_ifc_qpc_bits qpc; 5287 5288 u8 reserved_at_800[0x80]; 5289 }; 5290 5291 struct mlx5_ifc_rst2init_qp_out_bits { 5292 u8 status[0x8]; 5293 u8 reserved_at_8[0x18]; 5294 5295 u8 syndrome[0x20]; 5296 5297 u8 reserved_at_40[0x20]; 5298 u8 ece[0x20]; 5299 }; 5300 5301 struct mlx5_ifc_rst2init_qp_in_bits { 5302 u8 opcode[0x10]; 5303 u8 uid[0x10]; 5304 5305 u8 reserved_at_20[0x10]; 5306 u8 op_mod[0x10]; 5307 5308 u8 reserved_at_40[0x8]; 5309 u8 qpn[0x18]; 5310 5311 u8 reserved_at_60[0x20]; 5312 5313 u8 opt_param_mask[0x20]; 5314 5315 u8 ece[0x20]; 5316 5317 struct mlx5_ifc_qpc_bits qpc; 5318 5319 u8 reserved_at_800[0x80]; 5320 }; 5321 5322 struct mlx5_ifc_query_xrq_out_bits { 5323 u8 status[0x8]; 5324 u8 reserved_at_8[0x18]; 5325 5326 u8 syndrome[0x20]; 5327 5328 u8 reserved_at_40[0x40]; 5329 5330 struct mlx5_ifc_xrqc_bits xrq_context; 5331 }; 5332 5333 struct mlx5_ifc_query_xrq_in_bits { 5334 u8 opcode[0x10]; 5335 u8 reserved_at_10[0x10]; 5336 5337 u8 reserved_at_20[0x10]; 5338 u8 op_mod[0x10]; 5339 5340 u8 reserved_at_40[0x8]; 5341 u8 xrqn[0x18]; 5342 5343 u8 reserved_at_60[0x20]; 5344 }; 5345 5346 struct mlx5_ifc_query_xrc_srq_out_bits { 5347 u8 status[0x8]; 5348 u8 reserved_at_8[0x18]; 5349 5350 u8 syndrome[0x20]; 5351 5352 u8 reserved_at_40[0x40]; 5353 5354 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5355 5356 u8 reserved_at_280[0x600]; 5357 5358 u8 pas[][0x40]; 5359 }; 5360 5361 struct mlx5_ifc_query_xrc_srq_in_bits { 5362 u8 opcode[0x10]; 5363 u8 reserved_at_10[0x10]; 5364 5365 u8 reserved_at_20[0x10]; 5366 u8 op_mod[0x10]; 5367 5368 u8 reserved_at_40[0x8]; 5369 u8 xrc_srqn[0x18]; 5370 5371 u8 reserved_at_60[0x20]; 5372 }; 5373 5374 enum { 5375 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5376 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5377 }; 5378 5379 struct mlx5_ifc_query_vport_state_out_bits { 5380 u8 status[0x8]; 5381 u8 reserved_at_8[0x18]; 5382 5383 u8 syndrome[0x20]; 5384 5385 u8 reserved_at_40[0x20]; 5386 5387 u8 reserved_at_60[0x18]; 5388 u8 admin_state[0x4]; 5389 u8 state[0x4]; 5390 }; 5391 5392 struct mlx5_ifc_array1024_auto_bits { 5393 u8 array1024_auto[32][0x20]; 5394 }; 5395 5396 struct mlx5_ifc_query_vuid_in_bits { 5397 u8 opcode[0x10]; 5398 u8 uid[0x10]; 5399 5400 u8 reserved_at_20[0x40]; 5401 5402 u8 query_vfs_vuid[0x1]; 5403 u8 data_direct[0x1]; 5404 u8 reserved_at_62[0xe]; 5405 u8 vhca_id[0x10]; 5406 }; 5407 5408 struct mlx5_ifc_query_vuid_out_bits { 5409 u8 status[0x8]; 5410 u8 reserved_at_8[0x18]; 5411 5412 u8 syndrome[0x20]; 5413 5414 u8 reserved_at_40[0x1a0]; 5415 5416 u8 reserved_at_1e0[0x10]; 5417 u8 num_of_entries[0x10]; 5418 5419 struct mlx5_ifc_array1024_auto_bits vuid[]; 5420 }; 5421 5422 enum { 5423 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5424 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5425 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5426 }; 5427 5428 struct mlx5_ifc_arm_monitor_counter_in_bits { 5429 u8 opcode[0x10]; 5430 u8 uid[0x10]; 5431 5432 u8 reserved_at_20[0x10]; 5433 u8 op_mod[0x10]; 5434 5435 u8 reserved_at_40[0x20]; 5436 5437 u8 reserved_at_60[0x20]; 5438 }; 5439 5440 struct mlx5_ifc_arm_monitor_counter_out_bits { 5441 u8 status[0x8]; 5442 u8 reserved_at_8[0x18]; 5443 5444 u8 syndrome[0x20]; 5445 5446 u8 reserved_at_40[0x40]; 5447 }; 5448 5449 enum { 5450 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5451 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5452 }; 5453 5454 enum mlx5_monitor_counter_ppcnt { 5455 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5456 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5457 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5458 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5459 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5460 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5461 }; 5462 5463 enum { 5464 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5465 }; 5466 5467 struct mlx5_ifc_monitor_counter_output_bits { 5468 u8 reserved_at_0[0x4]; 5469 u8 type[0x4]; 5470 u8 reserved_at_8[0x8]; 5471 u8 counter[0x10]; 5472 5473 u8 counter_group_id[0x20]; 5474 }; 5475 5476 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5477 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5478 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5479 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5480 5481 struct mlx5_ifc_set_monitor_counter_in_bits { 5482 u8 opcode[0x10]; 5483 u8 uid[0x10]; 5484 5485 u8 reserved_at_20[0x10]; 5486 u8 op_mod[0x10]; 5487 5488 u8 reserved_at_40[0x10]; 5489 u8 num_of_counters[0x10]; 5490 5491 u8 reserved_at_60[0x20]; 5492 5493 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5494 }; 5495 5496 struct mlx5_ifc_set_monitor_counter_out_bits { 5497 u8 status[0x8]; 5498 u8 reserved_at_8[0x18]; 5499 5500 u8 syndrome[0x20]; 5501 5502 u8 reserved_at_40[0x40]; 5503 }; 5504 5505 struct mlx5_ifc_query_vport_state_in_bits { 5506 u8 opcode[0x10]; 5507 u8 reserved_at_10[0x10]; 5508 5509 u8 reserved_at_20[0x10]; 5510 u8 op_mod[0x10]; 5511 5512 u8 other_vport[0x1]; 5513 u8 reserved_at_41[0xf]; 5514 u8 vport_number[0x10]; 5515 5516 u8 reserved_at_60[0x20]; 5517 }; 5518 5519 struct mlx5_ifc_query_vnic_env_out_bits { 5520 u8 status[0x8]; 5521 u8 reserved_at_8[0x18]; 5522 5523 u8 syndrome[0x20]; 5524 5525 u8 reserved_at_40[0x40]; 5526 5527 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5528 }; 5529 5530 enum { 5531 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5532 }; 5533 5534 struct mlx5_ifc_query_vnic_env_in_bits { 5535 u8 opcode[0x10]; 5536 u8 reserved_at_10[0x10]; 5537 5538 u8 reserved_at_20[0x10]; 5539 u8 op_mod[0x10]; 5540 5541 u8 other_vport[0x1]; 5542 u8 reserved_at_41[0xf]; 5543 u8 vport_number[0x10]; 5544 5545 u8 reserved_at_60[0x20]; 5546 }; 5547 5548 struct mlx5_ifc_query_vport_counter_out_bits { 5549 u8 status[0x8]; 5550 u8 reserved_at_8[0x18]; 5551 5552 u8 syndrome[0x20]; 5553 5554 u8 reserved_at_40[0x40]; 5555 5556 struct mlx5_ifc_traffic_counter_bits received_errors; 5557 5558 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5559 5560 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5561 5562 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5563 5564 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5565 5566 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5567 5568 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5569 5570 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5571 5572 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5573 5574 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5575 5576 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5577 5578 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5579 5580 struct mlx5_ifc_traffic_counter_bits local_loopback; 5581 5582 u8 reserved_at_700[0x980]; 5583 }; 5584 5585 enum { 5586 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5587 }; 5588 5589 struct mlx5_ifc_query_vport_counter_in_bits { 5590 u8 opcode[0x10]; 5591 u8 reserved_at_10[0x10]; 5592 5593 u8 reserved_at_20[0x10]; 5594 u8 op_mod[0x10]; 5595 5596 u8 other_vport[0x1]; 5597 u8 reserved_at_41[0xb]; 5598 u8 port_num[0x4]; 5599 u8 vport_number[0x10]; 5600 5601 u8 reserved_at_60[0x60]; 5602 5603 u8 clear[0x1]; 5604 u8 reserved_at_c1[0x1f]; 5605 5606 u8 reserved_at_e0[0x20]; 5607 }; 5608 5609 struct mlx5_ifc_query_tis_out_bits { 5610 u8 status[0x8]; 5611 u8 reserved_at_8[0x18]; 5612 5613 u8 syndrome[0x20]; 5614 5615 u8 reserved_at_40[0x40]; 5616 5617 struct mlx5_ifc_tisc_bits tis_context; 5618 }; 5619 5620 struct mlx5_ifc_query_tis_in_bits { 5621 u8 opcode[0x10]; 5622 u8 reserved_at_10[0x10]; 5623 5624 u8 reserved_at_20[0x10]; 5625 u8 op_mod[0x10]; 5626 5627 u8 reserved_at_40[0x8]; 5628 u8 tisn[0x18]; 5629 5630 u8 reserved_at_60[0x20]; 5631 }; 5632 5633 struct mlx5_ifc_query_tir_out_bits { 5634 u8 status[0x8]; 5635 u8 reserved_at_8[0x18]; 5636 5637 u8 syndrome[0x20]; 5638 5639 u8 reserved_at_40[0xc0]; 5640 5641 struct mlx5_ifc_tirc_bits tir_context; 5642 }; 5643 5644 struct mlx5_ifc_query_tir_in_bits { 5645 u8 opcode[0x10]; 5646 u8 reserved_at_10[0x10]; 5647 5648 u8 reserved_at_20[0x10]; 5649 u8 op_mod[0x10]; 5650 5651 u8 reserved_at_40[0x8]; 5652 u8 tirn[0x18]; 5653 5654 u8 reserved_at_60[0x20]; 5655 }; 5656 5657 struct mlx5_ifc_query_srq_out_bits { 5658 u8 status[0x8]; 5659 u8 reserved_at_8[0x18]; 5660 5661 u8 syndrome[0x20]; 5662 5663 u8 reserved_at_40[0x40]; 5664 5665 struct mlx5_ifc_srqc_bits srq_context_entry; 5666 5667 u8 reserved_at_280[0x600]; 5668 5669 u8 pas[][0x40]; 5670 }; 5671 5672 struct mlx5_ifc_query_srq_in_bits { 5673 u8 opcode[0x10]; 5674 u8 reserved_at_10[0x10]; 5675 5676 u8 reserved_at_20[0x10]; 5677 u8 op_mod[0x10]; 5678 5679 u8 reserved_at_40[0x8]; 5680 u8 srqn[0x18]; 5681 5682 u8 reserved_at_60[0x20]; 5683 }; 5684 5685 struct mlx5_ifc_query_sq_out_bits { 5686 u8 status[0x8]; 5687 u8 reserved_at_8[0x18]; 5688 5689 u8 syndrome[0x20]; 5690 5691 u8 reserved_at_40[0xc0]; 5692 5693 struct mlx5_ifc_sqc_bits sq_context; 5694 }; 5695 5696 struct mlx5_ifc_query_sq_in_bits { 5697 u8 opcode[0x10]; 5698 u8 reserved_at_10[0x10]; 5699 5700 u8 reserved_at_20[0x10]; 5701 u8 op_mod[0x10]; 5702 5703 u8 reserved_at_40[0x8]; 5704 u8 sqn[0x18]; 5705 5706 u8 reserved_at_60[0x20]; 5707 }; 5708 5709 struct mlx5_ifc_query_special_contexts_out_bits { 5710 u8 status[0x8]; 5711 u8 reserved_at_8[0x18]; 5712 5713 u8 syndrome[0x20]; 5714 5715 u8 dump_fill_mkey[0x20]; 5716 5717 u8 resd_lkey[0x20]; 5718 5719 u8 null_mkey[0x20]; 5720 5721 u8 terminate_scatter_list_mkey[0x20]; 5722 5723 u8 repeated_mkey[0x20]; 5724 5725 u8 reserved_at_a0[0x20]; 5726 }; 5727 5728 struct mlx5_ifc_query_special_contexts_in_bits { 5729 u8 opcode[0x10]; 5730 u8 reserved_at_10[0x10]; 5731 5732 u8 reserved_at_20[0x10]; 5733 u8 op_mod[0x10]; 5734 5735 u8 reserved_at_40[0x40]; 5736 }; 5737 5738 struct mlx5_ifc_query_scheduling_element_out_bits { 5739 u8 opcode[0x10]; 5740 u8 reserved_at_10[0x10]; 5741 5742 u8 reserved_at_20[0x10]; 5743 u8 op_mod[0x10]; 5744 5745 u8 reserved_at_40[0xc0]; 5746 5747 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5748 5749 u8 reserved_at_300[0x100]; 5750 }; 5751 5752 enum { 5753 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5754 SCHEDULING_HIERARCHY_NIC = 0x3, 5755 }; 5756 5757 struct mlx5_ifc_query_scheduling_element_in_bits { 5758 u8 opcode[0x10]; 5759 u8 reserved_at_10[0x10]; 5760 5761 u8 reserved_at_20[0x10]; 5762 u8 op_mod[0x10]; 5763 5764 u8 scheduling_hierarchy[0x8]; 5765 u8 reserved_at_48[0x18]; 5766 5767 u8 scheduling_element_id[0x20]; 5768 5769 u8 reserved_at_80[0x180]; 5770 }; 5771 5772 struct mlx5_ifc_query_rqt_out_bits { 5773 u8 status[0x8]; 5774 u8 reserved_at_8[0x18]; 5775 5776 u8 syndrome[0x20]; 5777 5778 u8 reserved_at_40[0xc0]; 5779 5780 struct mlx5_ifc_rqtc_bits rqt_context; 5781 }; 5782 5783 struct mlx5_ifc_query_rqt_in_bits { 5784 u8 opcode[0x10]; 5785 u8 reserved_at_10[0x10]; 5786 5787 u8 reserved_at_20[0x10]; 5788 u8 op_mod[0x10]; 5789 5790 u8 reserved_at_40[0x8]; 5791 u8 rqtn[0x18]; 5792 5793 u8 reserved_at_60[0x20]; 5794 }; 5795 5796 struct mlx5_ifc_query_rq_out_bits { 5797 u8 status[0x8]; 5798 u8 reserved_at_8[0x18]; 5799 5800 u8 syndrome[0x20]; 5801 5802 u8 reserved_at_40[0xc0]; 5803 5804 struct mlx5_ifc_rqc_bits rq_context; 5805 }; 5806 5807 struct mlx5_ifc_query_rq_in_bits { 5808 u8 opcode[0x10]; 5809 u8 reserved_at_10[0x10]; 5810 5811 u8 reserved_at_20[0x10]; 5812 u8 op_mod[0x10]; 5813 5814 u8 reserved_at_40[0x8]; 5815 u8 rqn[0x18]; 5816 5817 u8 reserved_at_60[0x20]; 5818 }; 5819 5820 struct mlx5_ifc_query_roce_address_out_bits { 5821 u8 status[0x8]; 5822 u8 reserved_at_8[0x18]; 5823 5824 u8 syndrome[0x20]; 5825 5826 u8 reserved_at_40[0x40]; 5827 5828 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5829 }; 5830 5831 struct mlx5_ifc_query_roce_address_in_bits { 5832 u8 opcode[0x10]; 5833 u8 reserved_at_10[0x10]; 5834 5835 u8 reserved_at_20[0x10]; 5836 u8 op_mod[0x10]; 5837 5838 u8 roce_address_index[0x10]; 5839 u8 reserved_at_50[0xc]; 5840 u8 vhca_port_num[0x4]; 5841 5842 u8 reserved_at_60[0x20]; 5843 }; 5844 5845 struct mlx5_ifc_query_rmp_out_bits { 5846 u8 status[0x8]; 5847 u8 reserved_at_8[0x18]; 5848 5849 u8 syndrome[0x20]; 5850 5851 u8 reserved_at_40[0xc0]; 5852 5853 struct mlx5_ifc_rmpc_bits rmp_context; 5854 }; 5855 5856 struct mlx5_ifc_query_rmp_in_bits { 5857 u8 opcode[0x10]; 5858 u8 reserved_at_10[0x10]; 5859 5860 u8 reserved_at_20[0x10]; 5861 u8 op_mod[0x10]; 5862 5863 u8 reserved_at_40[0x8]; 5864 u8 rmpn[0x18]; 5865 5866 u8 reserved_at_60[0x20]; 5867 }; 5868 5869 struct mlx5_ifc_cqe_error_syndrome_bits { 5870 u8 hw_error_syndrome[0x8]; 5871 u8 hw_syndrome_type[0x4]; 5872 u8 reserved_at_c[0x4]; 5873 u8 vendor_error_syndrome[0x8]; 5874 u8 syndrome[0x8]; 5875 }; 5876 5877 struct mlx5_ifc_qp_context_extension_bits { 5878 u8 reserved_at_0[0x60]; 5879 5880 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5881 5882 u8 reserved_at_80[0x580]; 5883 }; 5884 5885 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5886 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5887 5888 u8 pas[0][0x40]; 5889 }; 5890 5891 struct mlx5_ifc_qp_pas_list_in_bits { 5892 struct mlx5_ifc_cmd_pas_bits pas[0]; 5893 }; 5894 5895 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5896 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5897 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5898 }; 5899 5900 struct mlx5_ifc_query_qp_out_bits { 5901 u8 status[0x8]; 5902 u8 reserved_at_8[0x18]; 5903 5904 u8 syndrome[0x20]; 5905 5906 u8 reserved_at_40[0x40]; 5907 5908 u8 opt_param_mask[0x20]; 5909 5910 u8 ece[0x20]; 5911 5912 struct mlx5_ifc_qpc_bits qpc; 5913 5914 u8 reserved_at_800[0x80]; 5915 5916 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5917 }; 5918 5919 struct mlx5_ifc_query_qp_in_bits { 5920 u8 opcode[0x10]; 5921 u8 reserved_at_10[0x10]; 5922 5923 u8 reserved_at_20[0x10]; 5924 u8 op_mod[0x10]; 5925 5926 u8 qpc_ext[0x1]; 5927 u8 reserved_at_41[0x7]; 5928 u8 qpn[0x18]; 5929 5930 u8 reserved_at_60[0x20]; 5931 }; 5932 5933 struct mlx5_ifc_query_q_counter_out_bits { 5934 u8 status[0x8]; 5935 u8 reserved_at_8[0x18]; 5936 5937 u8 syndrome[0x20]; 5938 5939 u8 reserved_at_40[0x40]; 5940 5941 u8 rx_write_requests[0x20]; 5942 5943 u8 reserved_at_a0[0x20]; 5944 5945 u8 rx_read_requests[0x20]; 5946 5947 u8 reserved_at_e0[0x20]; 5948 5949 u8 rx_atomic_requests[0x20]; 5950 5951 u8 reserved_at_120[0x20]; 5952 5953 u8 rx_dct_connect[0x20]; 5954 5955 u8 reserved_at_160[0x20]; 5956 5957 u8 out_of_buffer[0x20]; 5958 5959 u8 reserved_at_1a0[0x20]; 5960 5961 u8 out_of_sequence[0x20]; 5962 5963 u8 reserved_at_1e0[0x20]; 5964 5965 u8 duplicate_request[0x20]; 5966 5967 u8 reserved_at_220[0x20]; 5968 5969 u8 rnr_nak_retry_err[0x20]; 5970 5971 u8 reserved_at_260[0x20]; 5972 5973 u8 packet_seq_err[0x20]; 5974 5975 u8 reserved_at_2a0[0x20]; 5976 5977 u8 implied_nak_seq_err[0x20]; 5978 5979 u8 reserved_at_2e0[0x20]; 5980 5981 u8 local_ack_timeout_err[0x20]; 5982 5983 u8 reserved_at_320[0x60]; 5984 5985 u8 req_rnr_retries_exceeded[0x20]; 5986 5987 u8 reserved_at_3a0[0x20]; 5988 5989 u8 resp_local_length_error[0x20]; 5990 5991 u8 req_local_length_error[0x20]; 5992 5993 u8 resp_local_qp_error[0x20]; 5994 5995 u8 local_operation_error[0x20]; 5996 5997 u8 resp_local_protection[0x20]; 5998 5999 u8 req_local_protection[0x20]; 6000 6001 u8 resp_cqe_error[0x20]; 6002 6003 u8 req_cqe_error[0x20]; 6004 6005 u8 req_mw_binding[0x20]; 6006 6007 u8 req_bad_response[0x20]; 6008 6009 u8 req_remote_invalid_request[0x20]; 6010 6011 u8 resp_remote_invalid_request[0x20]; 6012 6013 u8 req_remote_access_errors[0x20]; 6014 6015 u8 resp_remote_access_errors[0x20]; 6016 6017 u8 req_remote_operation_errors[0x20]; 6018 6019 u8 req_transport_retries_exceeded[0x20]; 6020 6021 u8 cq_overflow[0x20]; 6022 6023 u8 resp_cqe_flush_error[0x20]; 6024 6025 u8 req_cqe_flush_error[0x20]; 6026 6027 u8 reserved_at_620[0x20]; 6028 6029 u8 roce_adp_retrans[0x20]; 6030 6031 u8 roce_adp_retrans_to[0x20]; 6032 6033 u8 roce_slow_restart[0x20]; 6034 6035 u8 roce_slow_restart_cnps[0x20]; 6036 6037 u8 roce_slow_restart_trans[0x20]; 6038 6039 u8 reserved_at_6e0[0x120]; 6040 }; 6041 6042 struct mlx5_ifc_query_q_counter_in_bits { 6043 u8 opcode[0x10]; 6044 u8 reserved_at_10[0x10]; 6045 6046 u8 reserved_at_20[0x10]; 6047 u8 op_mod[0x10]; 6048 6049 u8 other_vport[0x1]; 6050 u8 reserved_at_41[0xf]; 6051 u8 vport_number[0x10]; 6052 6053 u8 reserved_at_60[0x60]; 6054 6055 u8 clear[0x1]; 6056 u8 aggregate[0x1]; 6057 u8 reserved_at_c2[0x1e]; 6058 6059 u8 reserved_at_e0[0x18]; 6060 u8 counter_set_id[0x8]; 6061 }; 6062 6063 struct mlx5_ifc_query_pages_out_bits { 6064 u8 status[0x8]; 6065 u8 reserved_at_8[0x18]; 6066 6067 u8 syndrome[0x20]; 6068 6069 u8 embedded_cpu_function[0x1]; 6070 u8 reserved_at_41[0xf]; 6071 u8 function_id[0x10]; 6072 6073 u8 num_pages[0x20]; 6074 }; 6075 6076 enum { 6077 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 6078 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 6079 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 6080 }; 6081 6082 struct mlx5_ifc_query_pages_in_bits { 6083 u8 opcode[0x10]; 6084 u8 reserved_at_10[0x10]; 6085 6086 u8 reserved_at_20[0x10]; 6087 u8 op_mod[0x10]; 6088 6089 u8 embedded_cpu_function[0x1]; 6090 u8 reserved_at_41[0xf]; 6091 u8 function_id[0x10]; 6092 6093 u8 reserved_at_60[0x20]; 6094 }; 6095 6096 struct mlx5_ifc_query_nic_vport_context_out_bits { 6097 u8 status[0x8]; 6098 u8 reserved_at_8[0x18]; 6099 6100 u8 syndrome[0x20]; 6101 6102 u8 reserved_at_40[0x40]; 6103 6104 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6105 }; 6106 6107 struct mlx5_ifc_query_nic_vport_context_in_bits { 6108 u8 opcode[0x10]; 6109 u8 reserved_at_10[0x10]; 6110 6111 u8 reserved_at_20[0x10]; 6112 u8 op_mod[0x10]; 6113 6114 u8 other_vport[0x1]; 6115 u8 reserved_at_41[0xf]; 6116 u8 vport_number[0x10]; 6117 6118 u8 reserved_at_60[0x5]; 6119 u8 allowed_list_type[0x3]; 6120 u8 reserved_at_68[0x18]; 6121 }; 6122 6123 struct mlx5_ifc_query_mkey_out_bits { 6124 u8 status[0x8]; 6125 u8 reserved_at_8[0x18]; 6126 6127 u8 syndrome[0x20]; 6128 6129 u8 reserved_at_40[0x40]; 6130 6131 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6132 6133 u8 reserved_at_280[0x600]; 6134 6135 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 6136 6137 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 6138 }; 6139 6140 struct mlx5_ifc_query_mkey_in_bits { 6141 u8 opcode[0x10]; 6142 u8 reserved_at_10[0x10]; 6143 6144 u8 reserved_at_20[0x10]; 6145 u8 op_mod[0x10]; 6146 6147 u8 reserved_at_40[0x8]; 6148 u8 mkey_index[0x18]; 6149 6150 u8 pg_access[0x1]; 6151 u8 reserved_at_61[0x1f]; 6152 }; 6153 6154 struct mlx5_ifc_query_mad_demux_out_bits { 6155 u8 status[0x8]; 6156 u8 reserved_at_8[0x18]; 6157 6158 u8 syndrome[0x20]; 6159 6160 u8 reserved_at_40[0x40]; 6161 6162 u8 mad_dumux_parameters_block[0x20]; 6163 }; 6164 6165 struct mlx5_ifc_query_mad_demux_in_bits { 6166 u8 opcode[0x10]; 6167 u8 reserved_at_10[0x10]; 6168 6169 u8 reserved_at_20[0x10]; 6170 u8 op_mod[0x10]; 6171 6172 u8 reserved_at_40[0x40]; 6173 }; 6174 6175 struct mlx5_ifc_query_l2_table_entry_out_bits { 6176 u8 status[0x8]; 6177 u8 reserved_at_8[0x18]; 6178 6179 u8 syndrome[0x20]; 6180 6181 u8 reserved_at_40[0xa0]; 6182 6183 u8 reserved_at_e0[0x13]; 6184 u8 vlan_valid[0x1]; 6185 u8 vlan[0xc]; 6186 6187 struct mlx5_ifc_mac_address_layout_bits mac_address; 6188 6189 u8 reserved_at_140[0xc0]; 6190 }; 6191 6192 struct mlx5_ifc_query_l2_table_entry_in_bits { 6193 u8 opcode[0x10]; 6194 u8 reserved_at_10[0x10]; 6195 6196 u8 reserved_at_20[0x10]; 6197 u8 op_mod[0x10]; 6198 6199 u8 reserved_at_40[0x60]; 6200 6201 u8 reserved_at_a0[0x8]; 6202 u8 table_index[0x18]; 6203 6204 u8 reserved_at_c0[0x140]; 6205 }; 6206 6207 struct mlx5_ifc_query_issi_out_bits { 6208 u8 status[0x8]; 6209 u8 reserved_at_8[0x18]; 6210 6211 u8 syndrome[0x20]; 6212 6213 u8 reserved_at_40[0x10]; 6214 u8 current_issi[0x10]; 6215 6216 u8 reserved_at_60[0xa0]; 6217 6218 u8 reserved_at_100[76][0x8]; 6219 u8 supported_issi_dw0[0x20]; 6220 }; 6221 6222 struct mlx5_ifc_query_issi_in_bits { 6223 u8 opcode[0x10]; 6224 u8 reserved_at_10[0x10]; 6225 6226 u8 reserved_at_20[0x10]; 6227 u8 op_mod[0x10]; 6228 6229 u8 reserved_at_40[0x40]; 6230 }; 6231 6232 struct mlx5_ifc_set_driver_version_out_bits { 6233 u8 status[0x8]; 6234 u8 reserved_0[0x18]; 6235 6236 u8 syndrome[0x20]; 6237 u8 reserved_1[0x40]; 6238 }; 6239 6240 struct mlx5_ifc_set_driver_version_in_bits { 6241 u8 opcode[0x10]; 6242 u8 reserved_0[0x10]; 6243 6244 u8 reserved_1[0x10]; 6245 u8 op_mod[0x10]; 6246 6247 u8 reserved_2[0x40]; 6248 u8 driver_version[64][0x8]; 6249 }; 6250 6251 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 6252 u8 status[0x8]; 6253 u8 reserved_at_8[0x18]; 6254 6255 u8 syndrome[0x20]; 6256 6257 u8 reserved_at_40[0x40]; 6258 6259 struct mlx5_ifc_pkey_bits pkey[]; 6260 }; 6261 6262 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 6263 u8 opcode[0x10]; 6264 u8 reserved_at_10[0x10]; 6265 6266 u8 reserved_at_20[0x10]; 6267 u8 op_mod[0x10]; 6268 6269 u8 other_vport[0x1]; 6270 u8 reserved_at_41[0xb]; 6271 u8 port_num[0x4]; 6272 u8 vport_number[0x10]; 6273 6274 u8 reserved_at_60[0x10]; 6275 u8 pkey_index[0x10]; 6276 }; 6277 6278 enum { 6279 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 6280 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 6281 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 6282 }; 6283 6284 struct mlx5_ifc_query_hca_vport_gid_out_bits { 6285 u8 status[0x8]; 6286 u8 reserved_at_8[0x18]; 6287 6288 u8 syndrome[0x20]; 6289 6290 u8 reserved_at_40[0x20]; 6291 6292 u8 gids_num[0x10]; 6293 u8 reserved_at_70[0x10]; 6294 6295 struct mlx5_ifc_array128_auto_bits gid[]; 6296 }; 6297 6298 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6299 u8 opcode[0x10]; 6300 u8 reserved_at_10[0x10]; 6301 6302 u8 reserved_at_20[0x10]; 6303 u8 op_mod[0x10]; 6304 6305 u8 other_vport[0x1]; 6306 u8 reserved_at_41[0xb]; 6307 u8 port_num[0x4]; 6308 u8 vport_number[0x10]; 6309 6310 u8 reserved_at_60[0x10]; 6311 u8 gid_index[0x10]; 6312 }; 6313 6314 struct mlx5_ifc_query_hca_vport_context_out_bits { 6315 u8 status[0x8]; 6316 u8 reserved_at_8[0x18]; 6317 6318 u8 syndrome[0x20]; 6319 6320 u8 reserved_at_40[0x40]; 6321 6322 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6323 }; 6324 6325 struct mlx5_ifc_query_hca_vport_context_in_bits { 6326 u8 opcode[0x10]; 6327 u8 reserved_at_10[0x10]; 6328 6329 u8 reserved_at_20[0x10]; 6330 u8 op_mod[0x10]; 6331 6332 u8 other_vport[0x1]; 6333 u8 reserved_at_41[0xb]; 6334 u8 port_num[0x4]; 6335 u8 vport_number[0x10]; 6336 6337 u8 reserved_at_60[0x20]; 6338 }; 6339 6340 struct mlx5_ifc_query_hca_cap_out_bits { 6341 u8 status[0x8]; 6342 u8 reserved_at_8[0x18]; 6343 6344 u8 syndrome[0x20]; 6345 6346 u8 reserved_at_40[0x40]; 6347 6348 union mlx5_ifc_hca_cap_union_bits capability; 6349 }; 6350 6351 struct mlx5_ifc_query_hca_cap_in_bits { 6352 u8 opcode[0x10]; 6353 u8 reserved_at_10[0x10]; 6354 6355 u8 reserved_at_20[0x10]; 6356 u8 op_mod[0x10]; 6357 6358 u8 other_function[0x1]; 6359 u8 ec_vf_function[0x1]; 6360 u8 reserved_at_42[0xe]; 6361 u8 function_id[0x10]; 6362 6363 u8 reserved_at_60[0x20]; 6364 }; 6365 6366 struct mlx5_ifc_other_hca_cap_bits { 6367 u8 roce[0x1]; 6368 u8 reserved_at_1[0x27f]; 6369 }; 6370 6371 struct mlx5_ifc_query_other_hca_cap_out_bits { 6372 u8 status[0x8]; 6373 u8 reserved_at_8[0x18]; 6374 6375 u8 syndrome[0x20]; 6376 6377 u8 reserved_at_40[0x40]; 6378 6379 struct mlx5_ifc_other_hca_cap_bits other_capability; 6380 }; 6381 6382 struct mlx5_ifc_query_other_hca_cap_in_bits { 6383 u8 opcode[0x10]; 6384 u8 reserved_at_10[0x10]; 6385 6386 u8 reserved_at_20[0x10]; 6387 u8 op_mod[0x10]; 6388 6389 u8 reserved_at_40[0x10]; 6390 u8 function_id[0x10]; 6391 6392 u8 reserved_at_60[0x20]; 6393 }; 6394 6395 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6396 u8 status[0x8]; 6397 u8 reserved_at_8[0x18]; 6398 6399 u8 syndrome[0x20]; 6400 6401 u8 reserved_at_40[0x40]; 6402 }; 6403 6404 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6405 u8 opcode[0x10]; 6406 u8 reserved_at_10[0x10]; 6407 6408 u8 reserved_at_20[0x10]; 6409 u8 op_mod[0x10]; 6410 6411 u8 reserved_at_40[0x10]; 6412 u8 function_id[0x10]; 6413 u8 field_select[0x20]; 6414 6415 struct mlx5_ifc_other_hca_cap_bits other_capability; 6416 }; 6417 6418 struct mlx5_ifc_sw_owner_icm_root_params_bits { 6419 u8 sw_owner_icm_root_1[0x40]; 6420 6421 u8 sw_owner_icm_root_0[0x40]; 6422 }; 6423 6424 struct mlx5_ifc_rtc_params_bits { 6425 u8 rtc_id_0[0x20]; 6426 6427 u8 rtc_id_1[0x20]; 6428 6429 u8 reserved_at_40[0x40]; 6430 }; 6431 6432 struct mlx5_ifc_flow_table_context_bits { 6433 u8 reformat_en[0x1]; 6434 u8 decap_en[0x1]; 6435 u8 sw_owner[0x1]; 6436 u8 termination_table[0x1]; 6437 u8 table_miss_action[0x4]; 6438 u8 level[0x8]; 6439 u8 rtc_valid[0x1]; 6440 u8 reserved_at_11[0x7]; 6441 u8 log_size[0x8]; 6442 6443 u8 reserved_at_20[0x8]; 6444 u8 table_miss_id[0x18]; 6445 6446 u8 reserved_at_40[0x8]; 6447 u8 lag_master_next_table_id[0x18]; 6448 6449 u8 reserved_at_60[0x60]; 6450 6451 union { 6452 struct mlx5_ifc_sw_owner_icm_root_params_bits sws; 6453 struct mlx5_ifc_rtc_params_bits hws; 6454 }; 6455 }; 6456 6457 struct mlx5_ifc_query_flow_table_out_bits { 6458 u8 status[0x8]; 6459 u8 reserved_at_8[0x18]; 6460 6461 u8 syndrome[0x20]; 6462 6463 u8 reserved_at_40[0x80]; 6464 6465 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6466 }; 6467 6468 struct mlx5_ifc_query_flow_table_in_bits { 6469 u8 opcode[0x10]; 6470 u8 reserved_at_10[0x10]; 6471 6472 u8 reserved_at_20[0x10]; 6473 u8 op_mod[0x10]; 6474 6475 u8 reserved_at_40[0x40]; 6476 6477 u8 table_type[0x8]; 6478 u8 reserved_at_88[0x18]; 6479 6480 u8 reserved_at_a0[0x8]; 6481 u8 table_id[0x18]; 6482 6483 u8 reserved_at_c0[0x140]; 6484 }; 6485 6486 struct mlx5_ifc_query_fte_out_bits { 6487 u8 status[0x8]; 6488 u8 reserved_at_8[0x18]; 6489 6490 u8 syndrome[0x20]; 6491 6492 u8 reserved_at_40[0x1c0]; 6493 6494 struct mlx5_ifc_flow_context_bits flow_context; 6495 }; 6496 6497 struct mlx5_ifc_query_fte_in_bits { 6498 u8 opcode[0x10]; 6499 u8 reserved_at_10[0x10]; 6500 6501 u8 reserved_at_20[0x10]; 6502 u8 op_mod[0x10]; 6503 6504 u8 reserved_at_40[0x40]; 6505 6506 u8 table_type[0x8]; 6507 u8 reserved_at_88[0x18]; 6508 6509 u8 reserved_at_a0[0x8]; 6510 u8 table_id[0x18]; 6511 6512 u8 reserved_at_c0[0x40]; 6513 6514 u8 flow_index[0x20]; 6515 6516 u8 reserved_at_120[0xe0]; 6517 }; 6518 6519 struct mlx5_ifc_match_definer_format_0_bits { 6520 u8 reserved_at_0[0x100]; 6521 6522 u8 metadata_reg_c_0[0x20]; 6523 6524 u8 metadata_reg_c_1[0x20]; 6525 6526 u8 outer_dmac_47_16[0x20]; 6527 6528 u8 outer_dmac_15_0[0x10]; 6529 u8 outer_ethertype[0x10]; 6530 6531 u8 reserved_at_180[0x1]; 6532 u8 sx_sniffer[0x1]; 6533 u8 functional_lb[0x1]; 6534 u8 outer_ip_frag[0x1]; 6535 u8 outer_qp_type[0x2]; 6536 u8 outer_encap_type[0x2]; 6537 u8 port_number[0x2]; 6538 u8 outer_l3_type[0x2]; 6539 u8 outer_l4_type[0x2]; 6540 u8 outer_first_vlan_type[0x2]; 6541 u8 outer_first_vlan_prio[0x3]; 6542 u8 outer_first_vlan_cfi[0x1]; 6543 u8 outer_first_vlan_vid[0xc]; 6544 6545 u8 outer_l4_type_ext[0x4]; 6546 u8 reserved_at_1a4[0x2]; 6547 u8 outer_ipsec_layer[0x2]; 6548 u8 outer_l2_type[0x2]; 6549 u8 force_lb[0x1]; 6550 u8 outer_l2_ok[0x1]; 6551 u8 outer_l3_ok[0x1]; 6552 u8 outer_l4_ok[0x1]; 6553 u8 outer_second_vlan_type[0x2]; 6554 u8 outer_second_vlan_prio[0x3]; 6555 u8 outer_second_vlan_cfi[0x1]; 6556 u8 outer_second_vlan_vid[0xc]; 6557 6558 u8 outer_smac_47_16[0x20]; 6559 6560 u8 outer_smac_15_0[0x10]; 6561 u8 inner_ipv4_checksum_ok[0x1]; 6562 u8 inner_l4_checksum_ok[0x1]; 6563 u8 outer_ipv4_checksum_ok[0x1]; 6564 u8 outer_l4_checksum_ok[0x1]; 6565 u8 inner_l3_ok[0x1]; 6566 u8 inner_l4_ok[0x1]; 6567 u8 outer_l3_ok_duplicate[0x1]; 6568 u8 outer_l4_ok_duplicate[0x1]; 6569 u8 outer_tcp_cwr[0x1]; 6570 u8 outer_tcp_ece[0x1]; 6571 u8 outer_tcp_urg[0x1]; 6572 u8 outer_tcp_ack[0x1]; 6573 u8 outer_tcp_psh[0x1]; 6574 u8 outer_tcp_rst[0x1]; 6575 u8 outer_tcp_syn[0x1]; 6576 u8 outer_tcp_fin[0x1]; 6577 }; 6578 6579 struct mlx5_ifc_match_definer_format_22_bits { 6580 u8 reserved_at_0[0x100]; 6581 6582 u8 outer_ip_src_addr[0x20]; 6583 6584 u8 outer_ip_dest_addr[0x20]; 6585 6586 u8 outer_l4_sport[0x10]; 6587 u8 outer_l4_dport[0x10]; 6588 6589 u8 reserved_at_160[0x1]; 6590 u8 sx_sniffer[0x1]; 6591 u8 functional_lb[0x1]; 6592 u8 outer_ip_frag[0x1]; 6593 u8 outer_qp_type[0x2]; 6594 u8 outer_encap_type[0x2]; 6595 u8 port_number[0x2]; 6596 u8 outer_l3_type[0x2]; 6597 u8 outer_l4_type[0x2]; 6598 u8 outer_first_vlan_type[0x2]; 6599 u8 outer_first_vlan_prio[0x3]; 6600 u8 outer_first_vlan_cfi[0x1]; 6601 u8 outer_first_vlan_vid[0xc]; 6602 6603 u8 metadata_reg_c_0[0x20]; 6604 6605 u8 outer_dmac_47_16[0x20]; 6606 6607 u8 outer_smac_47_16[0x20]; 6608 6609 u8 outer_smac_15_0[0x10]; 6610 u8 outer_dmac_15_0[0x10]; 6611 }; 6612 6613 struct mlx5_ifc_match_definer_format_23_bits { 6614 u8 reserved_at_0[0x100]; 6615 6616 u8 inner_ip_src_addr[0x20]; 6617 6618 u8 inner_ip_dest_addr[0x20]; 6619 6620 u8 inner_l4_sport[0x10]; 6621 u8 inner_l4_dport[0x10]; 6622 6623 u8 reserved_at_160[0x1]; 6624 u8 sx_sniffer[0x1]; 6625 u8 functional_lb[0x1]; 6626 u8 inner_ip_frag[0x1]; 6627 u8 inner_qp_type[0x2]; 6628 u8 inner_encap_type[0x2]; 6629 u8 port_number[0x2]; 6630 u8 inner_l3_type[0x2]; 6631 u8 inner_l4_type[0x2]; 6632 u8 inner_first_vlan_type[0x2]; 6633 u8 inner_first_vlan_prio[0x3]; 6634 u8 inner_first_vlan_cfi[0x1]; 6635 u8 inner_first_vlan_vid[0xc]; 6636 6637 u8 tunnel_header_0[0x20]; 6638 6639 u8 inner_dmac_47_16[0x20]; 6640 6641 u8 inner_smac_47_16[0x20]; 6642 6643 u8 inner_smac_15_0[0x10]; 6644 u8 inner_dmac_15_0[0x10]; 6645 }; 6646 6647 struct mlx5_ifc_match_definer_format_29_bits { 6648 u8 reserved_at_0[0xc0]; 6649 6650 u8 outer_ip_dest_addr[0x80]; 6651 6652 u8 outer_ip_src_addr[0x80]; 6653 6654 u8 outer_l4_sport[0x10]; 6655 u8 outer_l4_dport[0x10]; 6656 6657 u8 reserved_at_1e0[0x20]; 6658 }; 6659 6660 struct mlx5_ifc_match_definer_format_30_bits { 6661 u8 reserved_at_0[0xa0]; 6662 6663 u8 outer_ip_dest_addr[0x80]; 6664 6665 u8 outer_ip_src_addr[0x80]; 6666 6667 u8 outer_dmac_47_16[0x20]; 6668 6669 u8 outer_smac_47_16[0x20]; 6670 6671 u8 outer_smac_15_0[0x10]; 6672 u8 outer_dmac_15_0[0x10]; 6673 }; 6674 6675 struct mlx5_ifc_match_definer_format_31_bits { 6676 u8 reserved_at_0[0xc0]; 6677 6678 u8 inner_ip_dest_addr[0x80]; 6679 6680 u8 inner_ip_src_addr[0x80]; 6681 6682 u8 inner_l4_sport[0x10]; 6683 u8 inner_l4_dport[0x10]; 6684 6685 u8 reserved_at_1e0[0x20]; 6686 }; 6687 6688 struct mlx5_ifc_match_definer_format_32_bits { 6689 u8 reserved_at_0[0xa0]; 6690 6691 u8 inner_ip_dest_addr[0x80]; 6692 6693 u8 inner_ip_src_addr[0x80]; 6694 6695 u8 inner_dmac_47_16[0x20]; 6696 6697 u8 inner_smac_47_16[0x20]; 6698 6699 u8 inner_smac_15_0[0x10]; 6700 u8 inner_dmac_15_0[0x10]; 6701 }; 6702 6703 enum { 6704 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6705 }; 6706 6707 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6708 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6709 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6710 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6711 6712 struct mlx5_ifc_match_definer_match_mask_bits { 6713 u8 reserved_at_1c0[5][0x20]; 6714 u8 match_dw_8[0x20]; 6715 u8 match_dw_7[0x20]; 6716 u8 match_dw_6[0x20]; 6717 u8 match_dw_5[0x20]; 6718 u8 match_dw_4[0x20]; 6719 u8 match_dw_3[0x20]; 6720 u8 match_dw_2[0x20]; 6721 u8 match_dw_1[0x20]; 6722 u8 match_dw_0[0x20]; 6723 6724 u8 match_byte_7[0x8]; 6725 u8 match_byte_6[0x8]; 6726 u8 match_byte_5[0x8]; 6727 u8 match_byte_4[0x8]; 6728 6729 u8 match_byte_3[0x8]; 6730 u8 match_byte_2[0x8]; 6731 u8 match_byte_1[0x8]; 6732 u8 match_byte_0[0x8]; 6733 }; 6734 6735 struct mlx5_ifc_match_definer_bits { 6736 u8 modify_field_select[0x40]; 6737 6738 u8 reserved_at_40[0x40]; 6739 6740 u8 reserved_at_80[0x10]; 6741 u8 format_id[0x10]; 6742 6743 u8 reserved_at_a0[0x60]; 6744 6745 u8 format_select_dw3[0x8]; 6746 u8 format_select_dw2[0x8]; 6747 u8 format_select_dw1[0x8]; 6748 u8 format_select_dw0[0x8]; 6749 6750 u8 format_select_dw7[0x8]; 6751 u8 format_select_dw6[0x8]; 6752 u8 format_select_dw5[0x8]; 6753 u8 format_select_dw4[0x8]; 6754 6755 u8 reserved_at_100[0x18]; 6756 u8 format_select_dw8[0x8]; 6757 6758 u8 reserved_at_120[0x20]; 6759 6760 u8 format_select_byte3[0x8]; 6761 u8 format_select_byte2[0x8]; 6762 u8 format_select_byte1[0x8]; 6763 u8 format_select_byte0[0x8]; 6764 6765 u8 format_select_byte7[0x8]; 6766 u8 format_select_byte6[0x8]; 6767 u8 format_select_byte5[0x8]; 6768 u8 format_select_byte4[0x8]; 6769 6770 u8 reserved_at_180[0x40]; 6771 6772 union { 6773 struct { 6774 u8 match_mask[16][0x20]; 6775 }; 6776 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6777 }; 6778 }; 6779 6780 struct mlx5_ifc_general_obj_create_param_bits { 6781 u8 alias_object[0x1]; 6782 u8 reserved_at_1[0x2]; 6783 u8 log_obj_range[0x5]; 6784 u8 reserved_at_8[0x18]; 6785 }; 6786 6787 struct mlx5_ifc_general_obj_query_param_bits { 6788 u8 alias_object[0x1]; 6789 u8 obj_offset[0x1f]; 6790 }; 6791 6792 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6793 u8 opcode[0x10]; 6794 u8 uid[0x10]; 6795 6796 u8 vhca_tunnel_id[0x10]; 6797 u8 obj_type[0x10]; 6798 6799 u8 obj_id[0x20]; 6800 6801 union { 6802 struct mlx5_ifc_general_obj_create_param_bits create; 6803 struct mlx5_ifc_general_obj_query_param_bits query; 6804 } op_param; 6805 }; 6806 6807 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6808 u8 status[0x8]; 6809 u8 reserved_at_8[0x18]; 6810 6811 u8 syndrome[0x20]; 6812 6813 u8 obj_id[0x20]; 6814 6815 u8 reserved_at_60[0x20]; 6816 }; 6817 6818 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6819 u8 opcode[0x10]; 6820 u8 uid[0x10]; 6821 u8 reserved_at_20[0x10]; 6822 u8 op_mod[0x10]; 6823 u8 reserved_at_40[0x50]; 6824 u8 object_type_to_be_accessed[0x10]; 6825 u8 object_id_to_be_accessed[0x20]; 6826 u8 reserved_at_c0[0x40]; 6827 union { 6828 u8 access_key_raw[0x100]; 6829 u8 access_key[8][0x20]; 6830 }; 6831 }; 6832 6833 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6834 u8 status[0x8]; 6835 u8 reserved_at_8[0x18]; 6836 u8 syndrome[0x20]; 6837 u8 reserved_at_40[0x40]; 6838 }; 6839 6840 struct mlx5_ifc_modify_header_arg_bits { 6841 u8 reserved_at_0[0x80]; 6842 6843 u8 reserved_at_80[0x8]; 6844 u8 access_pd[0x18]; 6845 }; 6846 6847 struct mlx5_ifc_create_modify_header_arg_in_bits { 6848 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6849 struct mlx5_ifc_modify_header_arg_bits arg; 6850 }; 6851 6852 struct mlx5_ifc_create_match_definer_in_bits { 6853 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6854 6855 struct mlx5_ifc_match_definer_bits obj_context; 6856 }; 6857 6858 struct mlx5_ifc_create_match_definer_out_bits { 6859 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6860 }; 6861 6862 struct mlx5_ifc_alias_context_bits { 6863 u8 vhca_id_to_be_accessed[0x10]; 6864 u8 reserved_at_10[0xd]; 6865 u8 status[0x3]; 6866 u8 object_id_to_be_accessed[0x20]; 6867 u8 reserved_at_40[0x40]; 6868 union { 6869 u8 access_key_raw[0x100]; 6870 u8 access_key[8][0x20]; 6871 }; 6872 u8 metadata[0x80]; 6873 }; 6874 6875 struct mlx5_ifc_create_alias_obj_in_bits { 6876 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6877 struct mlx5_ifc_alias_context_bits alias_ctx; 6878 }; 6879 6880 enum { 6881 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6882 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6883 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6884 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6885 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6886 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6887 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6888 }; 6889 6890 struct mlx5_ifc_query_flow_group_out_bits { 6891 u8 status[0x8]; 6892 u8 reserved_at_8[0x18]; 6893 6894 u8 syndrome[0x20]; 6895 6896 u8 reserved_at_40[0xa0]; 6897 6898 u8 start_flow_index[0x20]; 6899 6900 u8 reserved_at_100[0x20]; 6901 6902 u8 end_flow_index[0x20]; 6903 6904 u8 reserved_at_140[0xa0]; 6905 6906 u8 reserved_at_1e0[0x18]; 6907 u8 match_criteria_enable[0x8]; 6908 6909 struct mlx5_ifc_fte_match_param_bits match_criteria; 6910 6911 u8 reserved_at_1200[0xe00]; 6912 }; 6913 6914 struct mlx5_ifc_query_flow_group_in_bits { 6915 u8 opcode[0x10]; 6916 u8 reserved_at_10[0x10]; 6917 6918 u8 reserved_at_20[0x10]; 6919 u8 op_mod[0x10]; 6920 6921 u8 reserved_at_40[0x40]; 6922 6923 u8 table_type[0x8]; 6924 u8 reserved_at_88[0x18]; 6925 6926 u8 reserved_at_a0[0x8]; 6927 u8 table_id[0x18]; 6928 6929 u8 group_id[0x20]; 6930 6931 u8 reserved_at_e0[0x120]; 6932 }; 6933 6934 struct mlx5_ifc_query_flow_counter_out_bits { 6935 u8 status[0x8]; 6936 u8 reserved_at_8[0x18]; 6937 6938 u8 syndrome[0x20]; 6939 6940 u8 reserved_at_40[0x40]; 6941 6942 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6943 }; 6944 6945 struct mlx5_ifc_query_flow_counter_in_bits { 6946 u8 opcode[0x10]; 6947 u8 reserved_at_10[0x10]; 6948 6949 u8 reserved_at_20[0x10]; 6950 u8 op_mod[0x10]; 6951 6952 u8 reserved_at_40[0x80]; 6953 6954 u8 clear[0x1]; 6955 u8 reserved_at_c1[0xf]; 6956 u8 num_of_counters[0x10]; 6957 6958 u8 flow_counter_id[0x20]; 6959 }; 6960 6961 struct mlx5_ifc_query_esw_vport_context_out_bits { 6962 u8 status[0x8]; 6963 u8 reserved_at_8[0x18]; 6964 6965 u8 syndrome[0x20]; 6966 6967 u8 reserved_at_40[0x40]; 6968 6969 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6970 }; 6971 6972 struct mlx5_ifc_query_esw_vport_context_in_bits { 6973 u8 opcode[0x10]; 6974 u8 reserved_at_10[0x10]; 6975 6976 u8 reserved_at_20[0x10]; 6977 u8 op_mod[0x10]; 6978 6979 u8 other_vport[0x1]; 6980 u8 reserved_at_41[0xf]; 6981 u8 vport_number[0x10]; 6982 6983 u8 reserved_at_60[0x20]; 6984 }; 6985 6986 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6987 u8 status[0x8]; 6988 u8 reserved_at_8[0x18]; 6989 6990 u8 syndrome[0x20]; 6991 6992 u8 reserved_at_40[0x40]; 6993 }; 6994 6995 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6996 u8 reserved_at_0[0x1b]; 6997 u8 fdb_to_vport_reg_c_id[0x1]; 6998 u8 vport_cvlan_insert[0x1]; 6999 u8 vport_svlan_insert[0x1]; 7000 u8 vport_cvlan_strip[0x1]; 7001 u8 vport_svlan_strip[0x1]; 7002 }; 7003 7004 struct mlx5_ifc_modify_esw_vport_context_in_bits { 7005 u8 opcode[0x10]; 7006 u8 reserved_at_10[0x10]; 7007 7008 u8 reserved_at_20[0x10]; 7009 u8 op_mod[0x10]; 7010 7011 u8 other_vport[0x1]; 7012 u8 reserved_at_41[0xf]; 7013 u8 vport_number[0x10]; 7014 7015 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 7016 7017 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 7018 }; 7019 7020 struct mlx5_ifc_query_eq_out_bits { 7021 u8 status[0x8]; 7022 u8 reserved_at_8[0x18]; 7023 7024 u8 syndrome[0x20]; 7025 7026 u8 reserved_at_40[0x40]; 7027 7028 struct mlx5_ifc_eqc_bits eq_context_entry; 7029 7030 u8 reserved_at_280[0x40]; 7031 7032 u8 event_bitmask[0x40]; 7033 7034 u8 reserved_at_300[0x580]; 7035 7036 u8 pas[][0x40]; 7037 }; 7038 7039 struct mlx5_ifc_query_eq_in_bits { 7040 u8 opcode[0x10]; 7041 u8 reserved_at_10[0x10]; 7042 7043 u8 reserved_at_20[0x10]; 7044 u8 op_mod[0x10]; 7045 7046 u8 reserved_at_40[0x18]; 7047 u8 eq_number[0x8]; 7048 7049 u8 reserved_at_60[0x20]; 7050 }; 7051 7052 struct mlx5_ifc_packet_reformat_context_in_bits { 7053 u8 reformat_type[0x8]; 7054 u8 reserved_at_8[0x4]; 7055 u8 reformat_param_0[0x4]; 7056 u8 reserved_at_10[0x6]; 7057 u8 reformat_data_size[0xa]; 7058 7059 u8 reformat_param_1[0x8]; 7060 u8 reserved_at_28[0x8]; 7061 u8 reformat_data[2][0x8]; 7062 7063 u8 more_reformat_data[][0x8]; 7064 }; 7065 7066 struct mlx5_ifc_query_packet_reformat_context_out_bits { 7067 u8 status[0x8]; 7068 u8 reserved_at_8[0x18]; 7069 7070 u8 syndrome[0x20]; 7071 7072 u8 reserved_at_40[0xa0]; 7073 7074 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 7075 }; 7076 7077 struct mlx5_ifc_query_packet_reformat_context_in_bits { 7078 u8 opcode[0x10]; 7079 u8 reserved_at_10[0x10]; 7080 7081 u8 reserved_at_20[0x10]; 7082 u8 op_mod[0x10]; 7083 7084 u8 packet_reformat_id[0x20]; 7085 7086 u8 reserved_at_60[0xa0]; 7087 }; 7088 7089 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 7090 u8 status[0x8]; 7091 u8 reserved_at_8[0x18]; 7092 7093 u8 syndrome[0x20]; 7094 7095 u8 packet_reformat_id[0x20]; 7096 7097 u8 reserved_at_60[0x20]; 7098 }; 7099 7100 enum { 7101 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 7102 MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2, 7103 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 7104 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 7105 }; 7106 7107 enum mlx5_reformat_ctx_type { 7108 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 7109 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 7110 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 7111 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 7112 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 7113 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 7114 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 7115 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 7116 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 7117 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 7118 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 7119 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 7120 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 7121 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 7122 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 7123 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 7124 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 7125 }; 7126 7127 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 7128 u8 opcode[0x10]; 7129 u8 reserved_at_10[0x10]; 7130 7131 u8 reserved_at_20[0x10]; 7132 u8 op_mod[0x10]; 7133 7134 u8 reserved_at_40[0xa0]; 7135 7136 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 7137 }; 7138 7139 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 7140 u8 status[0x8]; 7141 u8 reserved_at_8[0x18]; 7142 7143 u8 syndrome[0x20]; 7144 7145 u8 reserved_at_40[0x40]; 7146 }; 7147 7148 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 7149 u8 opcode[0x10]; 7150 u8 reserved_at_10[0x10]; 7151 7152 u8 reserved_20[0x10]; 7153 u8 op_mod[0x10]; 7154 7155 u8 packet_reformat_id[0x20]; 7156 7157 u8 reserved_60[0x20]; 7158 }; 7159 7160 struct mlx5_ifc_set_action_in_bits { 7161 u8 action_type[0x4]; 7162 u8 field[0xc]; 7163 u8 reserved_at_10[0x3]; 7164 u8 offset[0x5]; 7165 u8 reserved_at_18[0x3]; 7166 u8 length[0x5]; 7167 7168 u8 data[0x20]; 7169 }; 7170 7171 struct mlx5_ifc_add_action_in_bits { 7172 u8 action_type[0x4]; 7173 u8 field[0xc]; 7174 u8 reserved_at_10[0x10]; 7175 7176 u8 data[0x20]; 7177 }; 7178 7179 struct mlx5_ifc_copy_action_in_bits { 7180 u8 action_type[0x4]; 7181 u8 src_field[0xc]; 7182 u8 reserved_at_10[0x3]; 7183 u8 src_offset[0x5]; 7184 u8 reserved_at_18[0x3]; 7185 u8 length[0x5]; 7186 7187 u8 reserved_at_20[0x4]; 7188 u8 dst_field[0xc]; 7189 u8 reserved_at_30[0x3]; 7190 u8 dst_offset[0x5]; 7191 u8 reserved_at_38[0x8]; 7192 }; 7193 7194 union mlx5_ifc_set_add_copy_action_in_auto_bits { 7195 struct mlx5_ifc_set_action_in_bits set_action_in; 7196 struct mlx5_ifc_add_action_in_bits add_action_in; 7197 struct mlx5_ifc_copy_action_in_bits copy_action_in; 7198 u8 reserved_at_0[0x40]; 7199 }; 7200 7201 enum { 7202 MLX5_ACTION_TYPE_SET = 0x1, 7203 MLX5_ACTION_TYPE_ADD = 0x2, 7204 MLX5_ACTION_TYPE_COPY = 0x3, 7205 }; 7206 7207 enum { 7208 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 7209 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 7210 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 7211 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 7212 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 7213 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 7214 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 7215 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 7216 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 7217 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 7218 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 7219 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 7220 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 7221 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 7222 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 7223 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 7224 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 7225 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 7226 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 7227 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 7228 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 7229 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 7230 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 7231 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 7232 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 7233 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 7234 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 7235 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 7236 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 7237 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 7238 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 7239 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 7240 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 7241 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 7242 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 7243 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 7244 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7245 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7246 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7247 }; 7248 7249 struct mlx5_ifc_alloc_modify_header_context_out_bits { 7250 u8 status[0x8]; 7251 u8 reserved_at_8[0x18]; 7252 7253 u8 syndrome[0x20]; 7254 7255 u8 modify_header_id[0x20]; 7256 7257 u8 reserved_at_60[0x20]; 7258 }; 7259 7260 struct mlx5_ifc_alloc_modify_header_context_in_bits { 7261 u8 opcode[0x10]; 7262 u8 reserved_at_10[0x10]; 7263 7264 u8 reserved_at_20[0x10]; 7265 u8 op_mod[0x10]; 7266 7267 u8 reserved_at_40[0x20]; 7268 7269 u8 table_type[0x8]; 7270 u8 reserved_at_68[0x10]; 7271 u8 num_of_actions[0x8]; 7272 7273 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 7274 }; 7275 7276 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 7277 u8 status[0x8]; 7278 u8 reserved_at_8[0x18]; 7279 7280 u8 syndrome[0x20]; 7281 7282 u8 reserved_at_40[0x40]; 7283 }; 7284 7285 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 7286 u8 opcode[0x10]; 7287 u8 reserved_at_10[0x10]; 7288 7289 u8 reserved_at_20[0x10]; 7290 u8 op_mod[0x10]; 7291 7292 u8 modify_header_id[0x20]; 7293 7294 u8 reserved_at_60[0x20]; 7295 }; 7296 7297 struct mlx5_ifc_query_modify_header_context_in_bits { 7298 u8 opcode[0x10]; 7299 u8 uid[0x10]; 7300 7301 u8 reserved_at_20[0x10]; 7302 u8 op_mod[0x10]; 7303 7304 u8 modify_header_id[0x20]; 7305 7306 u8 reserved_at_60[0xa0]; 7307 }; 7308 7309 struct mlx5_ifc_query_dct_out_bits { 7310 u8 status[0x8]; 7311 u8 reserved_at_8[0x18]; 7312 7313 u8 syndrome[0x20]; 7314 7315 u8 reserved_at_40[0x40]; 7316 7317 struct mlx5_ifc_dctc_bits dct_context_entry; 7318 7319 u8 reserved_at_280[0x180]; 7320 }; 7321 7322 struct mlx5_ifc_query_dct_in_bits { 7323 u8 opcode[0x10]; 7324 u8 reserved_at_10[0x10]; 7325 7326 u8 reserved_at_20[0x10]; 7327 u8 op_mod[0x10]; 7328 7329 u8 reserved_at_40[0x8]; 7330 u8 dctn[0x18]; 7331 7332 u8 reserved_at_60[0x20]; 7333 }; 7334 7335 struct mlx5_ifc_query_cq_out_bits { 7336 u8 status[0x8]; 7337 u8 reserved_at_8[0x18]; 7338 7339 u8 syndrome[0x20]; 7340 7341 u8 reserved_at_40[0x40]; 7342 7343 struct mlx5_ifc_cqc_bits cq_context; 7344 7345 u8 reserved_at_280[0x600]; 7346 7347 u8 pas[][0x40]; 7348 }; 7349 7350 struct mlx5_ifc_query_cq_in_bits { 7351 u8 opcode[0x10]; 7352 u8 reserved_at_10[0x10]; 7353 7354 u8 reserved_at_20[0x10]; 7355 u8 op_mod[0x10]; 7356 7357 u8 reserved_at_40[0x8]; 7358 u8 cqn[0x18]; 7359 7360 u8 reserved_at_60[0x20]; 7361 }; 7362 7363 struct mlx5_ifc_query_cong_status_out_bits { 7364 u8 status[0x8]; 7365 u8 reserved_at_8[0x18]; 7366 7367 u8 syndrome[0x20]; 7368 7369 u8 reserved_at_40[0x20]; 7370 7371 u8 enable[0x1]; 7372 u8 tag_enable[0x1]; 7373 u8 reserved_at_62[0x1e]; 7374 }; 7375 7376 struct mlx5_ifc_query_cong_status_in_bits { 7377 u8 opcode[0x10]; 7378 u8 reserved_at_10[0x10]; 7379 7380 u8 reserved_at_20[0x10]; 7381 u8 op_mod[0x10]; 7382 7383 u8 reserved_at_40[0x18]; 7384 u8 priority[0x4]; 7385 u8 cong_protocol[0x4]; 7386 7387 u8 reserved_at_60[0x20]; 7388 }; 7389 7390 struct mlx5_ifc_query_cong_statistics_out_bits { 7391 u8 status[0x8]; 7392 u8 reserved_at_8[0x18]; 7393 7394 u8 syndrome[0x20]; 7395 7396 u8 reserved_at_40[0x40]; 7397 7398 u8 rp_cur_flows[0x20]; 7399 7400 u8 sum_flows[0x20]; 7401 7402 u8 rp_cnp_ignored_high[0x20]; 7403 7404 u8 rp_cnp_ignored_low[0x20]; 7405 7406 u8 rp_cnp_handled_high[0x20]; 7407 7408 u8 rp_cnp_handled_low[0x20]; 7409 7410 u8 reserved_at_140[0x100]; 7411 7412 u8 time_stamp_high[0x20]; 7413 7414 u8 time_stamp_low[0x20]; 7415 7416 u8 accumulators_period[0x20]; 7417 7418 u8 np_ecn_marked_roce_packets_high[0x20]; 7419 7420 u8 np_ecn_marked_roce_packets_low[0x20]; 7421 7422 u8 np_cnp_sent_high[0x20]; 7423 7424 u8 np_cnp_sent_low[0x20]; 7425 7426 u8 reserved_at_320[0x560]; 7427 }; 7428 7429 struct mlx5_ifc_query_cong_statistics_in_bits { 7430 u8 opcode[0x10]; 7431 u8 reserved_at_10[0x10]; 7432 7433 u8 reserved_at_20[0x10]; 7434 u8 op_mod[0x10]; 7435 7436 u8 clear[0x1]; 7437 u8 reserved_at_41[0x1f]; 7438 7439 u8 reserved_at_60[0x20]; 7440 }; 7441 7442 struct mlx5_ifc_query_cong_params_out_bits { 7443 u8 status[0x8]; 7444 u8 reserved_at_8[0x18]; 7445 7446 u8 syndrome[0x20]; 7447 7448 u8 reserved_at_40[0x40]; 7449 7450 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7451 }; 7452 7453 struct mlx5_ifc_query_cong_params_in_bits { 7454 u8 opcode[0x10]; 7455 u8 reserved_at_10[0x10]; 7456 7457 u8 reserved_at_20[0x10]; 7458 u8 op_mod[0x10]; 7459 7460 u8 reserved_at_40[0x1c]; 7461 u8 cong_protocol[0x4]; 7462 7463 u8 reserved_at_60[0x20]; 7464 }; 7465 7466 struct mlx5_ifc_query_adapter_out_bits { 7467 u8 status[0x8]; 7468 u8 reserved_at_8[0x18]; 7469 7470 u8 syndrome[0x20]; 7471 7472 u8 reserved_at_40[0x40]; 7473 7474 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7475 }; 7476 7477 struct mlx5_ifc_query_adapter_in_bits { 7478 u8 opcode[0x10]; 7479 u8 reserved_at_10[0x10]; 7480 7481 u8 reserved_at_20[0x10]; 7482 u8 op_mod[0x10]; 7483 7484 u8 reserved_at_40[0x40]; 7485 }; 7486 7487 struct mlx5_ifc_qp_2rst_out_bits { 7488 u8 status[0x8]; 7489 u8 reserved_at_8[0x18]; 7490 7491 u8 syndrome[0x20]; 7492 7493 u8 reserved_at_40[0x40]; 7494 }; 7495 7496 struct mlx5_ifc_qp_2rst_in_bits { 7497 u8 opcode[0x10]; 7498 u8 uid[0x10]; 7499 7500 u8 reserved_at_20[0x10]; 7501 u8 op_mod[0x10]; 7502 7503 u8 reserved_at_40[0x8]; 7504 u8 qpn[0x18]; 7505 7506 u8 reserved_at_60[0x20]; 7507 }; 7508 7509 struct mlx5_ifc_qp_2err_out_bits { 7510 u8 status[0x8]; 7511 u8 reserved_at_8[0x18]; 7512 7513 u8 syndrome[0x20]; 7514 7515 u8 reserved_at_40[0x40]; 7516 }; 7517 7518 struct mlx5_ifc_qp_2err_in_bits { 7519 u8 opcode[0x10]; 7520 u8 uid[0x10]; 7521 7522 u8 reserved_at_20[0x10]; 7523 u8 op_mod[0x10]; 7524 7525 u8 reserved_at_40[0x8]; 7526 u8 qpn[0x18]; 7527 7528 u8 reserved_at_60[0x20]; 7529 }; 7530 7531 struct mlx5_ifc_trans_page_fault_info_bits { 7532 u8 error[0x1]; 7533 u8 reserved_at_1[0x4]; 7534 u8 page_fault_type[0x3]; 7535 u8 wq_number[0x18]; 7536 7537 u8 reserved_at_20[0x8]; 7538 u8 fault_token[0x18]; 7539 }; 7540 7541 struct mlx5_ifc_mem_page_fault_info_bits { 7542 u8 error[0x1]; 7543 u8 reserved_at_1[0xf]; 7544 u8 fault_token_47_32[0x10]; 7545 7546 u8 fault_token_31_0[0x20]; 7547 }; 7548 7549 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits { 7550 struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info; 7551 struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info; 7552 u8 reserved_at_0[0x40]; 7553 }; 7554 7555 struct mlx5_ifc_page_fault_resume_out_bits { 7556 u8 status[0x8]; 7557 u8 reserved_at_8[0x18]; 7558 7559 u8 syndrome[0x20]; 7560 7561 u8 reserved_at_40[0x40]; 7562 }; 7563 7564 struct mlx5_ifc_page_fault_resume_in_bits { 7565 u8 opcode[0x10]; 7566 u8 reserved_at_10[0x10]; 7567 7568 u8 reserved_at_20[0x10]; 7569 u8 op_mod[0x10]; 7570 7571 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits 7572 page_fault_info; 7573 }; 7574 7575 struct mlx5_ifc_nop_out_bits { 7576 u8 status[0x8]; 7577 u8 reserved_at_8[0x18]; 7578 7579 u8 syndrome[0x20]; 7580 7581 u8 reserved_at_40[0x40]; 7582 }; 7583 7584 struct mlx5_ifc_nop_in_bits { 7585 u8 opcode[0x10]; 7586 u8 reserved_at_10[0x10]; 7587 7588 u8 reserved_at_20[0x10]; 7589 u8 op_mod[0x10]; 7590 7591 u8 reserved_at_40[0x40]; 7592 }; 7593 7594 struct mlx5_ifc_modify_vport_state_out_bits { 7595 u8 status[0x8]; 7596 u8 reserved_at_8[0x18]; 7597 7598 u8 syndrome[0x20]; 7599 7600 u8 reserved_at_40[0x40]; 7601 }; 7602 7603 struct mlx5_ifc_modify_vport_state_in_bits { 7604 u8 opcode[0x10]; 7605 u8 reserved_at_10[0x10]; 7606 7607 u8 reserved_at_20[0x10]; 7608 u8 op_mod[0x10]; 7609 7610 u8 other_vport[0x1]; 7611 u8 reserved_at_41[0xf]; 7612 u8 vport_number[0x10]; 7613 7614 u8 reserved_at_60[0x18]; 7615 u8 admin_state[0x4]; 7616 u8 reserved_at_7c[0x4]; 7617 }; 7618 7619 struct mlx5_ifc_modify_tis_out_bits { 7620 u8 status[0x8]; 7621 u8 reserved_at_8[0x18]; 7622 7623 u8 syndrome[0x20]; 7624 7625 u8 reserved_at_40[0x40]; 7626 }; 7627 7628 struct mlx5_ifc_modify_tis_bitmask_bits { 7629 u8 reserved_at_0[0x20]; 7630 7631 u8 reserved_at_20[0x1d]; 7632 u8 lag_tx_port_affinity[0x1]; 7633 u8 strict_lag_tx_port_affinity[0x1]; 7634 u8 prio[0x1]; 7635 }; 7636 7637 struct mlx5_ifc_modify_tis_in_bits { 7638 u8 opcode[0x10]; 7639 u8 uid[0x10]; 7640 7641 u8 reserved_at_20[0x10]; 7642 u8 op_mod[0x10]; 7643 7644 u8 reserved_at_40[0x8]; 7645 u8 tisn[0x18]; 7646 7647 u8 reserved_at_60[0x20]; 7648 7649 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7650 7651 u8 reserved_at_c0[0x40]; 7652 7653 struct mlx5_ifc_tisc_bits ctx; 7654 }; 7655 7656 struct mlx5_ifc_modify_tir_bitmask_bits { 7657 u8 reserved_at_0[0x20]; 7658 7659 u8 reserved_at_20[0x1b]; 7660 u8 self_lb_en[0x1]; 7661 u8 reserved_at_3c[0x1]; 7662 u8 hash[0x1]; 7663 u8 reserved_at_3e[0x1]; 7664 u8 packet_merge[0x1]; 7665 }; 7666 7667 struct mlx5_ifc_modify_tir_out_bits { 7668 u8 status[0x8]; 7669 u8 reserved_at_8[0x18]; 7670 7671 u8 syndrome[0x20]; 7672 7673 u8 reserved_at_40[0x40]; 7674 }; 7675 7676 struct mlx5_ifc_modify_tir_in_bits { 7677 u8 opcode[0x10]; 7678 u8 uid[0x10]; 7679 7680 u8 reserved_at_20[0x10]; 7681 u8 op_mod[0x10]; 7682 7683 u8 reserved_at_40[0x8]; 7684 u8 tirn[0x18]; 7685 7686 u8 reserved_at_60[0x20]; 7687 7688 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7689 7690 u8 reserved_at_c0[0x40]; 7691 7692 struct mlx5_ifc_tirc_bits ctx; 7693 }; 7694 7695 struct mlx5_ifc_modify_sq_out_bits { 7696 u8 status[0x8]; 7697 u8 reserved_at_8[0x18]; 7698 7699 u8 syndrome[0x20]; 7700 7701 u8 reserved_at_40[0x40]; 7702 }; 7703 7704 struct mlx5_ifc_modify_sq_in_bits { 7705 u8 opcode[0x10]; 7706 u8 uid[0x10]; 7707 7708 u8 reserved_at_20[0x10]; 7709 u8 op_mod[0x10]; 7710 7711 u8 sq_state[0x4]; 7712 u8 reserved_at_44[0x4]; 7713 u8 sqn[0x18]; 7714 7715 u8 reserved_at_60[0x20]; 7716 7717 u8 modify_bitmask[0x40]; 7718 7719 u8 reserved_at_c0[0x40]; 7720 7721 struct mlx5_ifc_sqc_bits ctx; 7722 }; 7723 7724 struct mlx5_ifc_modify_scheduling_element_out_bits { 7725 u8 status[0x8]; 7726 u8 reserved_at_8[0x18]; 7727 7728 u8 syndrome[0x20]; 7729 7730 u8 reserved_at_40[0x1c0]; 7731 }; 7732 7733 enum { 7734 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7735 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7736 }; 7737 7738 struct mlx5_ifc_modify_scheduling_element_in_bits { 7739 u8 opcode[0x10]; 7740 u8 reserved_at_10[0x10]; 7741 7742 u8 reserved_at_20[0x10]; 7743 u8 op_mod[0x10]; 7744 7745 u8 scheduling_hierarchy[0x8]; 7746 u8 reserved_at_48[0x18]; 7747 7748 u8 scheduling_element_id[0x20]; 7749 7750 u8 reserved_at_80[0x20]; 7751 7752 u8 modify_bitmask[0x20]; 7753 7754 u8 reserved_at_c0[0x40]; 7755 7756 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7757 7758 u8 reserved_at_300[0x100]; 7759 }; 7760 7761 struct mlx5_ifc_modify_rqt_out_bits { 7762 u8 status[0x8]; 7763 u8 reserved_at_8[0x18]; 7764 7765 u8 syndrome[0x20]; 7766 7767 u8 reserved_at_40[0x40]; 7768 }; 7769 7770 struct mlx5_ifc_rqt_bitmask_bits { 7771 u8 reserved_at_0[0x20]; 7772 7773 u8 reserved_at_20[0x1f]; 7774 u8 rqn_list[0x1]; 7775 }; 7776 7777 struct mlx5_ifc_modify_rqt_in_bits { 7778 u8 opcode[0x10]; 7779 u8 uid[0x10]; 7780 7781 u8 reserved_at_20[0x10]; 7782 u8 op_mod[0x10]; 7783 7784 u8 reserved_at_40[0x8]; 7785 u8 rqtn[0x18]; 7786 7787 u8 reserved_at_60[0x20]; 7788 7789 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7790 7791 u8 reserved_at_c0[0x40]; 7792 7793 struct mlx5_ifc_rqtc_bits ctx; 7794 }; 7795 7796 struct mlx5_ifc_modify_rq_out_bits { 7797 u8 status[0x8]; 7798 u8 reserved_at_8[0x18]; 7799 7800 u8 syndrome[0x20]; 7801 7802 u8 reserved_at_40[0x40]; 7803 }; 7804 7805 enum { 7806 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7807 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7808 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7809 }; 7810 7811 struct mlx5_ifc_modify_rq_in_bits { 7812 u8 opcode[0x10]; 7813 u8 uid[0x10]; 7814 7815 u8 reserved_at_20[0x10]; 7816 u8 op_mod[0x10]; 7817 7818 u8 rq_state[0x4]; 7819 u8 reserved_at_44[0x4]; 7820 u8 rqn[0x18]; 7821 7822 u8 reserved_at_60[0x20]; 7823 7824 u8 modify_bitmask[0x40]; 7825 7826 u8 reserved_at_c0[0x40]; 7827 7828 struct mlx5_ifc_rqc_bits ctx; 7829 }; 7830 7831 struct mlx5_ifc_modify_rmp_out_bits { 7832 u8 status[0x8]; 7833 u8 reserved_at_8[0x18]; 7834 7835 u8 syndrome[0x20]; 7836 7837 u8 reserved_at_40[0x40]; 7838 }; 7839 7840 struct mlx5_ifc_rmp_bitmask_bits { 7841 u8 reserved_at_0[0x20]; 7842 7843 u8 reserved_at_20[0x1f]; 7844 u8 lwm[0x1]; 7845 }; 7846 7847 struct mlx5_ifc_modify_rmp_in_bits { 7848 u8 opcode[0x10]; 7849 u8 uid[0x10]; 7850 7851 u8 reserved_at_20[0x10]; 7852 u8 op_mod[0x10]; 7853 7854 u8 rmp_state[0x4]; 7855 u8 reserved_at_44[0x4]; 7856 u8 rmpn[0x18]; 7857 7858 u8 reserved_at_60[0x20]; 7859 7860 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7861 7862 u8 reserved_at_c0[0x40]; 7863 7864 struct mlx5_ifc_rmpc_bits ctx; 7865 }; 7866 7867 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7868 u8 status[0x8]; 7869 u8 reserved_at_8[0x18]; 7870 7871 u8 syndrome[0x20]; 7872 7873 u8 reserved_at_40[0x40]; 7874 }; 7875 7876 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7877 u8 reserved_at_0[0x12]; 7878 u8 affiliation[0x1]; 7879 u8 reserved_at_13[0x1]; 7880 u8 disable_uc_local_lb[0x1]; 7881 u8 disable_mc_local_lb[0x1]; 7882 u8 node_guid[0x1]; 7883 u8 port_guid[0x1]; 7884 u8 min_inline[0x1]; 7885 u8 mtu[0x1]; 7886 u8 change_event[0x1]; 7887 u8 promisc[0x1]; 7888 u8 permanent_address[0x1]; 7889 u8 addresses_list[0x1]; 7890 u8 roce_en[0x1]; 7891 u8 reserved_at_1f[0x1]; 7892 }; 7893 7894 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7895 u8 opcode[0x10]; 7896 u8 reserved_at_10[0x10]; 7897 7898 u8 reserved_at_20[0x10]; 7899 u8 op_mod[0x10]; 7900 7901 u8 other_vport[0x1]; 7902 u8 reserved_at_41[0xf]; 7903 u8 vport_number[0x10]; 7904 7905 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7906 7907 u8 reserved_at_80[0x780]; 7908 7909 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7910 }; 7911 7912 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7913 u8 status[0x8]; 7914 u8 reserved_at_8[0x18]; 7915 7916 u8 syndrome[0x20]; 7917 7918 u8 reserved_at_40[0x40]; 7919 }; 7920 7921 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7922 u8 opcode[0x10]; 7923 u8 reserved_at_10[0x10]; 7924 7925 u8 reserved_at_20[0x10]; 7926 u8 op_mod[0x10]; 7927 7928 u8 other_vport[0x1]; 7929 u8 reserved_at_41[0xb]; 7930 u8 port_num[0x4]; 7931 u8 vport_number[0x10]; 7932 7933 u8 reserved_at_60[0x20]; 7934 7935 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7936 }; 7937 7938 struct mlx5_ifc_modify_cq_out_bits { 7939 u8 status[0x8]; 7940 u8 reserved_at_8[0x18]; 7941 7942 u8 syndrome[0x20]; 7943 7944 u8 reserved_at_40[0x40]; 7945 }; 7946 7947 enum { 7948 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7949 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7950 }; 7951 7952 struct mlx5_ifc_modify_cq_in_bits { 7953 u8 opcode[0x10]; 7954 u8 uid[0x10]; 7955 7956 u8 reserved_at_20[0x10]; 7957 u8 op_mod[0x10]; 7958 7959 u8 reserved_at_40[0x8]; 7960 u8 cqn[0x18]; 7961 7962 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7963 7964 struct mlx5_ifc_cqc_bits cq_context; 7965 7966 u8 reserved_at_280[0x60]; 7967 7968 u8 cq_umem_valid[0x1]; 7969 u8 reserved_at_2e1[0x1f]; 7970 7971 u8 reserved_at_300[0x580]; 7972 7973 u8 pas[][0x40]; 7974 }; 7975 7976 struct mlx5_ifc_modify_cong_status_out_bits { 7977 u8 status[0x8]; 7978 u8 reserved_at_8[0x18]; 7979 7980 u8 syndrome[0x20]; 7981 7982 u8 reserved_at_40[0x40]; 7983 }; 7984 7985 struct mlx5_ifc_modify_cong_status_in_bits { 7986 u8 opcode[0x10]; 7987 u8 reserved_at_10[0x10]; 7988 7989 u8 reserved_at_20[0x10]; 7990 u8 op_mod[0x10]; 7991 7992 u8 reserved_at_40[0x18]; 7993 u8 priority[0x4]; 7994 u8 cong_protocol[0x4]; 7995 7996 u8 enable[0x1]; 7997 u8 tag_enable[0x1]; 7998 u8 reserved_at_62[0x1e]; 7999 }; 8000 8001 struct mlx5_ifc_modify_cong_params_out_bits { 8002 u8 status[0x8]; 8003 u8 reserved_at_8[0x18]; 8004 8005 u8 syndrome[0x20]; 8006 8007 u8 reserved_at_40[0x40]; 8008 }; 8009 8010 struct mlx5_ifc_modify_cong_params_in_bits { 8011 u8 opcode[0x10]; 8012 u8 reserved_at_10[0x10]; 8013 8014 u8 reserved_at_20[0x10]; 8015 u8 op_mod[0x10]; 8016 8017 u8 reserved_at_40[0x1c]; 8018 u8 cong_protocol[0x4]; 8019 8020 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 8021 8022 u8 reserved_at_80[0x80]; 8023 8024 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 8025 }; 8026 8027 struct mlx5_ifc_manage_pages_out_bits { 8028 u8 status[0x8]; 8029 u8 reserved_at_8[0x18]; 8030 8031 u8 syndrome[0x20]; 8032 8033 u8 output_num_entries[0x20]; 8034 8035 u8 reserved_at_60[0x20]; 8036 8037 u8 pas[][0x40]; 8038 }; 8039 8040 enum { 8041 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 8042 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 8043 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 8044 }; 8045 8046 struct mlx5_ifc_manage_pages_in_bits { 8047 u8 opcode[0x10]; 8048 u8 reserved_at_10[0x10]; 8049 8050 u8 reserved_at_20[0x10]; 8051 u8 op_mod[0x10]; 8052 8053 u8 embedded_cpu_function[0x1]; 8054 u8 reserved_at_41[0xf]; 8055 u8 function_id[0x10]; 8056 8057 u8 input_num_entries[0x20]; 8058 8059 u8 pas[][0x40]; 8060 }; 8061 8062 struct mlx5_ifc_mad_ifc_out_bits { 8063 u8 status[0x8]; 8064 u8 reserved_at_8[0x18]; 8065 8066 u8 syndrome[0x20]; 8067 8068 u8 reserved_at_40[0x40]; 8069 8070 u8 response_mad_packet[256][0x8]; 8071 }; 8072 8073 struct mlx5_ifc_mad_ifc_in_bits { 8074 u8 opcode[0x10]; 8075 u8 reserved_at_10[0x10]; 8076 8077 u8 reserved_at_20[0x10]; 8078 u8 op_mod[0x10]; 8079 8080 u8 remote_lid[0x10]; 8081 u8 plane_index[0x8]; 8082 u8 port[0x8]; 8083 8084 u8 reserved_at_60[0x20]; 8085 8086 u8 mad[256][0x8]; 8087 }; 8088 8089 struct mlx5_ifc_init_hca_out_bits { 8090 u8 status[0x8]; 8091 u8 reserved_at_8[0x18]; 8092 8093 u8 syndrome[0x20]; 8094 8095 u8 reserved_at_40[0x40]; 8096 }; 8097 8098 struct mlx5_ifc_init_hca_in_bits { 8099 u8 opcode[0x10]; 8100 u8 reserved_at_10[0x10]; 8101 8102 u8 reserved_at_20[0x10]; 8103 u8 op_mod[0x10]; 8104 8105 u8 reserved_at_40[0x20]; 8106 8107 u8 reserved_at_60[0x2]; 8108 u8 sw_vhca_id[0xe]; 8109 u8 reserved_at_70[0x10]; 8110 8111 u8 sw_owner_id[4][0x20]; 8112 }; 8113 8114 struct mlx5_ifc_init2rtr_qp_out_bits { 8115 u8 status[0x8]; 8116 u8 reserved_at_8[0x18]; 8117 8118 u8 syndrome[0x20]; 8119 8120 u8 reserved_at_40[0x20]; 8121 u8 ece[0x20]; 8122 }; 8123 8124 struct mlx5_ifc_init2rtr_qp_in_bits { 8125 u8 opcode[0x10]; 8126 u8 uid[0x10]; 8127 8128 u8 reserved_at_20[0x10]; 8129 u8 op_mod[0x10]; 8130 8131 u8 reserved_at_40[0x8]; 8132 u8 qpn[0x18]; 8133 8134 u8 reserved_at_60[0x20]; 8135 8136 u8 opt_param_mask[0x20]; 8137 8138 u8 ece[0x20]; 8139 8140 struct mlx5_ifc_qpc_bits qpc; 8141 8142 u8 reserved_at_800[0x80]; 8143 }; 8144 8145 struct mlx5_ifc_init2init_qp_out_bits { 8146 u8 status[0x8]; 8147 u8 reserved_at_8[0x18]; 8148 8149 u8 syndrome[0x20]; 8150 8151 u8 reserved_at_40[0x20]; 8152 u8 ece[0x20]; 8153 }; 8154 8155 struct mlx5_ifc_init2init_qp_in_bits { 8156 u8 opcode[0x10]; 8157 u8 uid[0x10]; 8158 8159 u8 reserved_at_20[0x10]; 8160 u8 op_mod[0x10]; 8161 8162 u8 reserved_at_40[0x8]; 8163 u8 qpn[0x18]; 8164 8165 u8 reserved_at_60[0x20]; 8166 8167 u8 opt_param_mask[0x20]; 8168 8169 u8 ece[0x20]; 8170 8171 struct mlx5_ifc_qpc_bits qpc; 8172 8173 u8 reserved_at_800[0x80]; 8174 }; 8175 8176 struct mlx5_ifc_get_dropped_packet_log_out_bits { 8177 u8 status[0x8]; 8178 u8 reserved_at_8[0x18]; 8179 8180 u8 syndrome[0x20]; 8181 8182 u8 reserved_at_40[0x40]; 8183 8184 u8 packet_headers_log[128][0x8]; 8185 8186 u8 packet_syndrome[64][0x8]; 8187 }; 8188 8189 struct mlx5_ifc_get_dropped_packet_log_in_bits { 8190 u8 opcode[0x10]; 8191 u8 reserved_at_10[0x10]; 8192 8193 u8 reserved_at_20[0x10]; 8194 u8 op_mod[0x10]; 8195 8196 u8 reserved_at_40[0x40]; 8197 }; 8198 8199 struct mlx5_ifc_gen_eqe_in_bits { 8200 u8 opcode[0x10]; 8201 u8 reserved_at_10[0x10]; 8202 8203 u8 reserved_at_20[0x10]; 8204 u8 op_mod[0x10]; 8205 8206 u8 reserved_at_40[0x18]; 8207 u8 eq_number[0x8]; 8208 8209 u8 reserved_at_60[0x20]; 8210 8211 u8 eqe[64][0x8]; 8212 }; 8213 8214 struct mlx5_ifc_gen_eq_out_bits { 8215 u8 status[0x8]; 8216 u8 reserved_at_8[0x18]; 8217 8218 u8 syndrome[0x20]; 8219 8220 u8 reserved_at_40[0x40]; 8221 }; 8222 8223 struct mlx5_ifc_enable_hca_out_bits { 8224 u8 status[0x8]; 8225 u8 reserved_at_8[0x18]; 8226 8227 u8 syndrome[0x20]; 8228 8229 u8 reserved_at_40[0x20]; 8230 }; 8231 8232 struct mlx5_ifc_enable_hca_in_bits { 8233 u8 opcode[0x10]; 8234 u8 reserved_at_10[0x10]; 8235 8236 u8 reserved_at_20[0x10]; 8237 u8 op_mod[0x10]; 8238 8239 u8 embedded_cpu_function[0x1]; 8240 u8 reserved_at_41[0xf]; 8241 u8 function_id[0x10]; 8242 8243 u8 reserved_at_60[0x20]; 8244 }; 8245 8246 struct mlx5_ifc_drain_dct_out_bits { 8247 u8 status[0x8]; 8248 u8 reserved_at_8[0x18]; 8249 8250 u8 syndrome[0x20]; 8251 8252 u8 reserved_at_40[0x40]; 8253 }; 8254 8255 struct mlx5_ifc_drain_dct_in_bits { 8256 u8 opcode[0x10]; 8257 u8 uid[0x10]; 8258 8259 u8 reserved_at_20[0x10]; 8260 u8 op_mod[0x10]; 8261 8262 u8 reserved_at_40[0x8]; 8263 u8 dctn[0x18]; 8264 8265 u8 reserved_at_60[0x20]; 8266 }; 8267 8268 struct mlx5_ifc_disable_hca_out_bits { 8269 u8 status[0x8]; 8270 u8 reserved_at_8[0x18]; 8271 8272 u8 syndrome[0x20]; 8273 8274 u8 reserved_at_40[0x20]; 8275 }; 8276 8277 struct mlx5_ifc_disable_hca_in_bits { 8278 u8 opcode[0x10]; 8279 u8 reserved_at_10[0x10]; 8280 8281 u8 reserved_at_20[0x10]; 8282 u8 op_mod[0x10]; 8283 8284 u8 embedded_cpu_function[0x1]; 8285 u8 reserved_at_41[0xf]; 8286 u8 function_id[0x10]; 8287 8288 u8 reserved_at_60[0x20]; 8289 }; 8290 8291 struct mlx5_ifc_detach_from_mcg_out_bits { 8292 u8 status[0x8]; 8293 u8 reserved_at_8[0x18]; 8294 8295 u8 syndrome[0x20]; 8296 8297 u8 reserved_at_40[0x40]; 8298 }; 8299 8300 struct mlx5_ifc_detach_from_mcg_in_bits { 8301 u8 opcode[0x10]; 8302 u8 uid[0x10]; 8303 8304 u8 reserved_at_20[0x10]; 8305 u8 op_mod[0x10]; 8306 8307 u8 reserved_at_40[0x8]; 8308 u8 qpn[0x18]; 8309 8310 u8 reserved_at_60[0x20]; 8311 8312 u8 multicast_gid[16][0x8]; 8313 }; 8314 8315 struct mlx5_ifc_destroy_xrq_out_bits { 8316 u8 status[0x8]; 8317 u8 reserved_at_8[0x18]; 8318 8319 u8 syndrome[0x20]; 8320 8321 u8 reserved_at_40[0x40]; 8322 }; 8323 8324 struct mlx5_ifc_destroy_xrq_in_bits { 8325 u8 opcode[0x10]; 8326 u8 uid[0x10]; 8327 8328 u8 reserved_at_20[0x10]; 8329 u8 op_mod[0x10]; 8330 8331 u8 reserved_at_40[0x8]; 8332 u8 xrqn[0x18]; 8333 8334 u8 reserved_at_60[0x20]; 8335 }; 8336 8337 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8338 u8 status[0x8]; 8339 u8 reserved_at_8[0x18]; 8340 8341 u8 syndrome[0x20]; 8342 8343 u8 reserved_at_40[0x40]; 8344 }; 8345 8346 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8347 u8 opcode[0x10]; 8348 u8 uid[0x10]; 8349 8350 u8 reserved_at_20[0x10]; 8351 u8 op_mod[0x10]; 8352 8353 u8 reserved_at_40[0x8]; 8354 u8 xrc_srqn[0x18]; 8355 8356 u8 reserved_at_60[0x20]; 8357 }; 8358 8359 struct mlx5_ifc_destroy_tis_out_bits { 8360 u8 status[0x8]; 8361 u8 reserved_at_8[0x18]; 8362 8363 u8 syndrome[0x20]; 8364 8365 u8 reserved_at_40[0x40]; 8366 }; 8367 8368 struct mlx5_ifc_destroy_tis_in_bits { 8369 u8 opcode[0x10]; 8370 u8 uid[0x10]; 8371 8372 u8 reserved_at_20[0x10]; 8373 u8 op_mod[0x10]; 8374 8375 u8 reserved_at_40[0x8]; 8376 u8 tisn[0x18]; 8377 8378 u8 reserved_at_60[0x20]; 8379 }; 8380 8381 struct mlx5_ifc_destroy_tir_out_bits { 8382 u8 status[0x8]; 8383 u8 reserved_at_8[0x18]; 8384 8385 u8 syndrome[0x20]; 8386 8387 u8 reserved_at_40[0x40]; 8388 }; 8389 8390 struct mlx5_ifc_destroy_tir_in_bits { 8391 u8 opcode[0x10]; 8392 u8 uid[0x10]; 8393 8394 u8 reserved_at_20[0x10]; 8395 u8 op_mod[0x10]; 8396 8397 u8 reserved_at_40[0x8]; 8398 u8 tirn[0x18]; 8399 8400 u8 reserved_at_60[0x20]; 8401 }; 8402 8403 struct mlx5_ifc_destroy_srq_out_bits { 8404 u8 status[0x8]; 8405 u8 reserved_at_8[0x18]; 8406 8407 u8 syndrome[0x20]; 8408 8409 u8 reserved_at_40[0x40]; 8410 }; 8411 8412 struct mlx5_ifc_destroy_srq_in_bits { 8413 u8 opcode[0x10]; 8414 u8 uid[0x10]; 8415 8416 u8 reserved_at_20[0x10]; 8417 u8 op_mod[0x10]; 8418 8419 u8 reserved_at_40[0x8]; 8420 u8 srqn[0x18]; 8421 8422 u8 reserved_at_60[0x20]; 8423 }; 8424 8425 struct mlx5_ifc_destroy_sq_out_bits { 8426 u8 status[0x8]; 8427 u8 reserved_at_8[0x18]; 8428 8429 u8 syndrome[0x20]; 8430 8431 u8 reserved_at_40[0x40]; 8432 }; 8433 8434 struct mlx5_ifc_destroy_sq_in_bits { 8435 u8 opcode[0x10]; 8436 u8 uid[0x10]; 8437 8438 u8 reserved_at_20[0x10]; 8439 u8 op_mod[0x10]; 8440 8441 u8 reserved_at_40[0x8]; 8442 u8 sqn[0x18]; 8443 8444 u8 reserved_at_60[0x20]; 8445 }; 8446 8447 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8448 u8 status[0x8]; 8449 u8 reserved_at_8[0x18]; 8450 8451 u8 syndrome[0x20]; 8452 8453 u8 reserved_at_40[0x1c0]; 8454 }; 8455 8456 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8457 u8 opcode[0x10]; 8458 u8 reserved_at_10[0x10]; 8459 8460 u8 reserved_at_20[0x10]; 8461 u8 op_mod[0x10]; 8462 8463 u8 scheduling_hierarchy[0x8]; 8464 u8 reserved_at_48[0x18]; 8465 8466 u8 scheduling_element_id[0x20]; 8467 8468 u8 reserved_at_80[0x180]; 8469 }; 8470 8471 struct mlx5_ifc_destroy_rqt_out_bits { 8472 u8 status[0x8]; 8473 u8 reserved_at_8[0x18]; 8474 8475 u8 syndrome[0x20]; 8476 8477 u8 reserved_at_40[0x40]; 8478 }; 8479 8480 struct mlx5_ifc_destroy_rqt_in_bits { 8481 u8 opcode[0x10]; 8482 u8 uid[0x10]; 8483 8484 u8 reserved_at_20[0x10]; 8485 u8 op_mod[0x10]; 8486 8487 u8 reserved_at_40[0x8]; 8488 u8 rqtn[0x18]; 8489 8490 u8 reserved_at_60[0x20]; 8491 }; 8492 8493 struct mlx5_ifc_destroy_rq_out_bits { 8494 u8 status[0x8]; 8495 u8 reserved_at_8[0x18]; 8496 8497 u8 syndrome[0x20]; 8498 8499 u8 reserved_at_40[0x40]; 8500 }; 8501 8502 struct mlx5_ifc_destroy_rq_in_bits { 8503 u8 opcode[0x10]; 8504 u8 uid[0x10]; 8505 8506 u8 reserved_at_20[0x10]; 8507 u8 op_mod[0x10]; 8508 8509 u8 reserved_at_40[0x8]; 8510 u8 rqn[0x18]; 8511 8512 u8 reserved_at_60[0x20]; 8513 }; 8514 8515 struct mlx5_ifc_set_delay_drop_params_in_bits { 8516 u8 opcode[0x10]; 8517 u8 reserved_at_10[0x10]; 8518 8519 u8 reserved_at_20[0x10]; 8520 u8 op_mod[0x10]; 8521 8522 u8 reserved_at_40[0x20]; 8523 8524 u8 reserved_at_60[0x10]; 8525 u8 delay_drop_timeout[0x10]; 8526 }; 8527 8528 struct mlx5_ifc_set_delay_drop_params_out_bits { 8529 u8 status[0x8]; 8530 u8 reserved_at_8[0x18]; 8531 8532 u8 syndrome[0x20]; 8533 8534 u8 reserved_at_40[0x40]; 8535 }; 8536 8537 struct mlx5_ifc_destroy_rmp_out_bits { 8538 u8 status[0x8]; 8539 u8 reserved_at_8[0x18]; 8540 8541 u8 syndrome[0x20]; 8542 8543 u8 reserved_at_40[0x40]; 8544 }; 8545 8546 struct mlx5_ifc_destroy_rmp_in_bits { 8547 u8 opcode[0x10]; 8548 u8 uid[0x10]; 8549 8550 u8 reserved_at_20[0x10]; 8551 u8 op_mod[0x10]; 8552 8553 u8 reserved_at_40[0x8]; 8554 u8 rmpn[0x18]; 8555 8556 u8 reserved_at_60[0x20]; 8557 }; 8558 8559 struct mlx5_ifc_destroy_qp_out_bits { 8560 u8 status[0x8]; 8561 u8 reserved_at_8[0x18]; 8562 8563 u8 syndrome[0x20]; 8564 8565 u8 reserved_at_40[0x40]; 8566 }; 8567 8568 struct mlx5_ifc_destroy_qp_in_bits { 8569 u8 opcode[0x10]; 8570 u8 uid[0x10]; 8571 8572 u8 reserved_at_20[0x10]; 8573 u8 op_mod[0x10]; 8574 8575 u8 reserved_at_40[0x8]; 8576 u8 qpn[0x18]; 8577 8578 u8 reserved_at_60[0x20]; 8579 }; 8580 8581 struct mlx5_ifc_destroy_psv_out_bits { 8582 u8 status[0x8]; 8583 u8 reserved_at_8[0x18]; 8584 8585 u8 syndrome[0x20]; 8586 8587 u8 reserved_at_40[0x40]; 8588 }; 8589 8590 struct mlx5_ifc_destroy_psv_in_bits { 8591 u8 opcode[0x10]; 8592 u8 reserved_at_10[0x10]; 8593 8594 u8 reserved_at_20[0x10]; 8595 u8 op_mod[0x10]; 8596 8597 u8 reserved_at_40[0x8]; 8598 u8 psvn[0x18]; 8599 8600 u8 reserved_at_60[0x20]; 8601 }; 8602 8603 struct mlx5_ifc_destroy_mkey_out_bits { 8604 u8 status[0x8]; 8605 u8 reserved_at_8[0x18]; 8606 8607 u8 syndrome[0x20]; 8608 8609 u8 reserved_at_40[0x40]; 8610 }; 8611 8612 struct mlx5_ifc_destroy_mkey_in_bits { 8613 u8 opcode[0x10]; 8614 u8 uid[0x10]; 8615 8616 u8 reserved_at_20[0x10]; 8617 u8 op_mod[0x10]; 8618 8619 u8 reserved_at_40[0x8]; 8620 u8 mkey_index[0x18]; 8621 8622 u8 reserved_at_60[0x20]; 8623 }; 8624 8625 struct mlx5_ifc_destroy_flow_table_out_bits { 8626 u8 status[0x8]; 8627 u8 reserved_at_8[0x18]; 8628 8629 u8 syndrome[0x20]; 8630 8631 u8 reserved_at_40[0x40]; 8632 }; 8633 8634 struct mlx5_ifc_destroy_flow_table_in_bits { 8635 u8 opcode[0x10]; 8636 u8 reserved_at_10[0x10]; 8637 8638 u8 reserved_at_20[0x10]; 8639 u8 op_mod[0x10]; 8640 8641 u8 other_vport[0x1]; 8642 u8 reserved_at_41[0xf]; 8643 u8 vport_number[0x10]; 8644 8645 u8 reserved_at_60[0x20]; 8646 8647 u8 table_type[0x8]; 8648 u8 reserved_at_88[0x18]; 8649 8650 u8 reserved_at_a0[0x8]; 8651 u8 table_id[0x18]; 8652 8653 u8 reserved_at_c0[0x140]; 8654 }; 8655 8656 struct mlx5_ifc_destroy_flow_group_out_bits { 8657 u8 status[0x8]; 8658 u8 reserved_at_8[0x18]; 8659 8660 u8 syndrome[0x20]; 8661 8662 u8 reserved_at_40[0x40]; 8663 }; 8664 8665 struct mlx5_ifc_destroy_flow_group_in_bits { 8666 u8 opcode[0x10]; 8667 u8 reserved_at_10[0x10]; 8668 8669 u8 reserved_at_20[0x10]; 8670 u8 op_mod[0x10]; 8671 8672 u8 other_vport[0x1]; 8673 u8 reserved_at_41[0xf]; 8674 u8 vport_number[0x10]; 8675 8676 u8 reserved_at_60[0x20]; 8677 8678 u8 table_type[0x8]; 8679 u8 reserved_at_88[0x18]; 8680 8681 u8 reserved_at_a0[0x8]; 8682 u8 table_id[0x18]; 8683 8684 u8 group_id[0x20]; 8685 8686 u8 reserved_at_e0[0x120]; 8687 }; 8688 8689 struct mlx5_ifc_destroy_eq_out_bits { 8690 u8 status[0x8]; 8691 u8 reserved_at_8[0x18]; 8692 8693 u8 syndrome[0x20]; 8694 8695 u8 reserved_at_40[0x40]; 8696 }; 8697 8698 struct mlx5_ifc_destroy_eq_in_bits { 8699 u8 opcode[0x10]; 8700 u8 reserved_at_10[0x10]; 8701 8702 u8 reserved_at_20[0x10]; 8703 u8 op_mod[0x10]; 8704 8705 u8 reserved_at_40[0x18]; 8706 u8 eq_number[0x8]; 8707 8708 u8 reserved_at_60[0x20]; 8709 }; 8710 8711 struct mlx5_ifc_destroy_dct_out_bits { 8712 u8 status[0x8]; 8713 u8 reserved_at_8[0x18]; 8714 8715 u8 syndrome[0x20]; 8716 8717 u8 reserved_at_40[0x40]; 8718 }; 8719 8720 struct mlx5_ifc_destroy_dct_in_bits { 8721 u8 opcode[0x10]; 8722 u8 uid[0x10]; 8723 8724 u8 reserved_at_20[0x10]; 8725 u8 op_mod[0x10]; 8726 8727 u8 reserved_at_40[0x8]; 8728 u8 dctn[0x18]; 8729 8730 u8 reserved_at_60[0x20]; 8731 }; 8732 8733 struct mlx5_ifc_destroy_cq_out_bits { 8734 u8 status[0x8]; 8735 u8 reserved_at_8[0x18]; 8736 8737 u8 syndrome[0x20]; 8738 8739 u8 reserved_at_40[0x40]; 8740 }; 8741 8742 struct mlx5_ifc_destroy_cq_in_bits { 8743 u8 opcode[0x10]; 8744 u8 uid[0x10]; 8745 8746 u8 reserved_at_20[0x10]; 8747 u8 op_mod[0x10]; 8748 8749 u8 reserved_at_40[0x8]; 8750 u8 cqn[0x18]; 8751 8752 u8 reserved_at_60[0x20]; 8753 }; 8754 8755 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8756 u8 status[0x8]; 8757 u8 reserved_at_8[0x18]; 8758 8759 u8 syndrome[0x20]; 8760 8761 u8 reserved_at_40[0x40]; 8762 }; 8763 8764 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8765 u8 opcode[0x10]; 8766 u8 reserved_at_10[0x10]; 8767 8768 u8 reserved_at_20[0x10]; 8769 u8 op_mod[0x10]; 8770 8771 u8 reserved_at_40[0x20]; 8772 8773 u8 reserved_at_60[0x10]; 8774 u8 vxlan_udp_port[0x10]; 8775 }; 8776 8777 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8778 u8 status[0x8]; 8779 u8 reserved_at_8[0x18]; 8780 8781 u8 syndrome[0x20]; 8782 8783 u8 reserved_at_40[0x40]; 8784 }; 8785 8786 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8787 u8 opcode[0x10]; 8788 u8 reserved_at_10[0x10]; 8789 8790 u8 reserved_at_20[0x10]; 8791 u8 op_mod[0x10]; 8792 8793 u8 reserved_at_40[0x60]; 8794 8795 u8 reserved_at_a0[0x8]; 8796 u8 table_index[0x18]; 8797 8798 u8 reserved_at_c0[0x140]; 8799 }; 8800 8801 struct mlx5_ifc_delete_fte_out_bits { 8802 u8 status[0x8]; 8803 u8 reserved_at_8[0x18]; 8804 8805 u8 syndrome[0x20]; 8806 8807 u8 reserved_at_40[0x40]; 8808 }; 8809 8810 struct mlx5_ifc_delete_fte_in_bits { 8811 u8 opcode[0x10]; 8812 u8 reserved_at_10[0x10]; 8813 8814 u8 reserved_at_20[0x10]; 8815 u8 op_mod[0x10]; 8816 8817 u8 other_vport[0x1]; 8818 u8 reserved_at_41[0xf]; 8819 u8 vport_number[0x10]; 8820 8821 u8 reserved_at_60[0x20]; 8822 8823 u8 table_type[0x8]; 8824 u8 reserved_at_88[0x18]; 8825 8826 u8 reserved_at_a0[0x8]; 8827 u8 table_id[0x18]; 8828 8829 u8 reserved_at_c0[0x40]; 8830 8831 u8 flow_index[0x20]; 8832 8833 u8 reserved_at_120[0xe0]; 8834 }; 8835 8836 struct mlx5_ifc_dealloc_xrcd_out_bits { 8837 u8 status[0x8]; 8838 u8 reserved_at_8[0x18]; 8839 8840 u8 syndrome[0x20]; 8841 8842 u8 reserved_at_40[0x40]; 8843 }; 8844 8845 struct mlx5_ifc_dealloc_xrcd_in_bits { 8846 u8 opcode[0x10]; 8847 u8 uid[0x10]; 8848 8849 u8 reserved_at_20[0x10]; 8850 u8 op_mod[0x10]; 8851 8852 u8 reserved_at_40[0x8]; 8853 u8 xrcd[0x18]; 8854 8855 u8 reserved_at_60[0x20]; 8856 }; 8857 8858 struct mlx5_ifc_dealloc_uar_out_bits { 8859 u8 status[0x8]; 8860 u8 reserved_at_8[0x18]; 8861 8862 u8 syndrome[0x20]; 8863 8864 u8 reserved_at_40[0x40]; 8865 }; 8866 8867 struct mlx5_ifc_dealloc_uar_in_bits { 8868 u8 opcode[0x10]; 8869 u8 uid[0x10]; 8870 8871 u8 reserved_at_20[0x10]; 8872 u8 op_mod[0x10]; 8873 8874 u8 reserved_at_40[0x8]; 8875 u8 uar[0x18]; 8876 8877 u8 reserved_at_60[0x20]; 8878 }; 8879 8880 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8881 u8 status[0x8]; 8882 u8 reserved_at_8[0x18]; 8883 8884 u8 syndrome[0x20]; 8885 8886 u8 reserved_at_40[0x40]; 8887 }; 8888 8889 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8890 u8 opcode[0x10]; 8891 u8 uid[0x10]; 8892 8893 u8 reserved_at_20[0x10]; 8894 u8 op_mod[0x10]; 8895 8896 u8 reserved_at_40[0x8]; 8897 u8 transport_domain[0x18]; 8898 8899 u8 reserved_at_60[0x20]; 8900 }; 8901 8902 struct mlx5_ifc_dealloc_q_counter_out_bits { 8903 u8 status[0x8]; 8904 u8 reserved_at_8[0x18]; 8905 8906 u8 syndrome[0x20]; 8907 8908 u8 reserved_at_40[0x40]; 8909 }; 8910 8911 struct mlx5_ifc_dealloc_q_counter_in_bits { 8912 u8 opcode[0x10]; 8913 u8 reserved_at_10[0x10]; 8914 8915 u8 reserved_at_20[0x10]; 8916 u8 op_mod[0x10]; 8917 8918 u8 reserved_at_40[0x18]; 8919 u8 counter_set_id[0x8]; 8920 8921 u8 reserved_at_60[0x20]; 8922 }; 8923 8924 struct mlx5_ifc_dealloc_pd_out_bits { 8925 u8 status[0x8]; 8926 u8 reserved_at_8[0x18]; 8927 8928 u8 syndrome[0x20]; 8929 8930 u8 reserved_at_40[0x40]; 8931 }; 8932 8933 struct mlx5_ifc_dealloc_pd_in_bits { 8934 u8 opcode[0x10]; 8935 u8 uid[0x10]; 8936 8937 u8 reserved_at_20[0x10]; 8938 u8 op_mod[0x10]; 8939 8940 u8 reserved_at_40[0x8]; 8941 u8 pd[0x18]; 8942 8943 u8 reserved_at_60[0x20]; 8944 }; 8945 8946 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8947 u8 status[0x8]; 8948 u8 reserved_at_8[0x18]; 8949 8950 u8 syndrome[0x20]; 8951 8952 u8 reserved_at_40[0x40]; 8953 }; 8954 8955 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8956 u8 opcode[0x10]; 8957 u8 reserved_at_10[0x10]; 8958 8959 u8 reserved_at_20[0x10]; 8960 u8 op_mod[0x10]; 8961 8962 u8 flow_counter_id[0x20]; 8963 8964 u8 reserved_at_60[0x20]; 8965 }; 8966 8967 struct mlx5_ifc_create_xrq_out_bits { 8968 u8 status[0x8]; 8969 u8 reserved_at_8[0x18]; 8970 8971 u8 syndrome[0x20]; 8972 8973 u8 reserved_at_40[0x8]; 8974 u8 xrqn[0x18]; 8975 8976 u8 reserved_at_60[0x20]; 8977 }; 8978 8979 struct mlx5_ifc_create_xrq_in_bits { 8980 u8 opcode[0x10]; 8981 u8 uid[0x10]; 8982 8983 u8 reserved_at_20[0x10]; 8984 u8 op_mod[0x10]; 8985 8986 u8 reserved_at_40[0x40]; 8987 8988 struct mlx5_ifc_xrqc_bits xrq_context; 8989 }; 8990 8991 struct mlx5_ifc_create_xrc_srq_out_bits { 8992 u8 status[0x8]; 8993 u8 reserved_at_8[0x18]; 8994 8995 u8 syndrome[0x20]; 8996 8997 u8 reserved_at_40[0x8]; 8998 u8 xrc_srqn[0x18]; 8999 9000 u8 reserved_at_60[0x20]; 9001 }; 9002 9003 struct mlx5_ifc_create_xrc_srq_in_bits { 9004 u8 opcode[0x10]; 9005 u8 uid[0x10]; 9006 9007 u8 reserved_at_20[0x10]; 9008 u8 op_mod[0x10]; 9009 9010 u8 reserved_at_40[0x40]; 9011 9012 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 9013 9014 u8 reserved_at_280[0x60]; 9015 9016 u8 xrc_srq_umem_valid[0x1]; 9017 u8 reserved_at_2e1[0x1f]; 9018 9019 u8 reserved_at_300[0x580]; 9020 9021 u8 pas[][0x40]; 9022 }; 9023 9024 struct mlx5_ifc_create_tis_out_bits { 9025 u8 status[0x8]; 9026 u8 reserved_at_8[0x18]; 9027 9028 u8 syndrome[0x20]; 9029 9030 u8 reserved_at_40[0x8]; 9031 u8 tisn[0x18]; 9032 9033 u8 reserved_at_60[0x20]; 9034 }; 9035 9036 struct mlx5_ifc_create_tis_in_bits { 9037 u8 opcode[0x10]; 9038 u8 uid[0x10]; 9039 9040 u8 reserved_at_20[0x10]; 9041 u8 op_mod[0x10]; 9042 9043 u8 reserved_at_40[0xc0]; 9044 9045 struct mlx5_ifc_tisc_bits ctx; 9046 }; 9047 9048 struct mlx5_ifc_create_tir_out_bits { 9049 u8 status[0x8]; 9050 u8 icm_address_63_40[0x18]; 9051 9052 u8 syndrome[0x20]; 9053 9054 u8 icm_address_39_32[0x8]; 9055 u8 tirn[0x18]; 9056 9057 u8 icm_address_31_0[0x20]; 9058 }; 9059 9060 struct mlx5_ifc_create_tir_in_bits { 9061 u8 opcode[0x10]; 9062 u8 uid[0x10]; 9063 9064 u8 reserved_at_20[0x10]; 9065 u8 op_mod[0x10]; 9066 9067 u8 reserved_at_40[0xc0]; 9068 9069 struct mlx5_ifc_tirc_bits ctx; 9070 }; 9071 9072 struct mlx5_ifc_create_srq_out_bits { 9073 u8 status[0x8]; 9074 u8 reserved_at_8[0x18]; 9075 9076 u8 syndrome[0x20]; 9077 9078 u8 reserved_at_40[0x8]; 9079 u8 srqn[0x18]; 9080 9081 u8 reserved_at_60[0x20]; 9082 }; 9083 9084 struct mlx5_ifc_create_srq_in_bits { 9085 u8 opcode[0x10]; 9086 u8 uid[0x10]; 9087 9088 u8 reserved_at_20[0x10]; 9089 u8 op_mod[0x10]; 9090 9091 u8 reserved_at_40[0x40]; 9092 9093 struct mlx5_ifc_srqc_bits srq_context_entry; 9094 9095 u8 reserved_at_280[0x600]; 9096 9097 u8 pas[][0x40]; 9098 }; 9099 9100 struct mlx5_ifc_create_sq_out_bits { 9101 u8 status[0x8]; 9102 u8 reserved_at_8[0x18]; 9103 9104 u8 syndrome[0x20]; 9105 9106 u8 reserved_at_40[0x8]; 9107 u8 sqn[0x18]; 9108 9109 u8 reserved_at_60[0x20]; 9110 }; 9111 9112 struct mlx5_ifc_create_sq_in_bits { 9113 u8 opcode[0x10]; 9114 u8 uid[0x10]; 9115 9116 u8 reserved_at_20[0x10]; 9117 u8 op_mod[0x10]; 9118 9119 u8 reserved_at_40[0xc0]; 9120 9121 struct mlx5_ifc_sqc_bits ctx; 9122 }; 9123 9124 struct mlx5_ifc_create_scheduling_element_out_bits { 9125 u8 status[0x8]; 9126 u8 reserved_at_8[0x18]; 9127 9128 u8 syndrome[0x20]; 9129 9130 u8 reserved_at_40[0x40]; 9131 9132 u8 scheduling_element_id[0x20]; 9133 9134 u8 reserved_at_a0[0x160]; 9135 }; 9136 9137 struct mlx5_ifc_create_scheduling_element_in_bits { 9138 u8 opcode[0x10]; 9139 u8 reserved_at_10[0x10]; 9140 9141 u8 reserved_at_20[0x10]; 9142 u8 op_mod[0x10]; 9143 9144 u8 scheduling_hierarchy[0x8]; 9145 u8 reserved_at_48[0x18]; 9146 9147 u8 reserved_at_60[0xa0]; 9148 9149 struct mlx5_ifc_scheduling_context_bits scheduling_context; 9150 9151 u8 reserved_at_300[0x100]; 9152 }; 9153 9154 struct mlx5_ifc_create_rqt_out_bits { 9155 u8 status[0x8]; 9156 u8 reserved_at_8[0x18]; 9157 9158 u8 syndrome[0x20]; 9159 9160 u8 reserved_at_40[0x8]; 9161 u8 rqtn[0x18]; 9162 9163 u8 reserved_at_60[0x20]; 9164 }; 9165 9166 struct mlx5_ifc_create_rqt_in_bits { 9167 u8 opcode[0x10]; 9168 u8 uid[0x10]; 9169 9170 u8 reserved_at_20[0x10]; 9171 u8 op_mod[0x10]; 9172 9173 u8 reserved_at_40[0xc0]; 9174 9175 struct mlx5_ifc_rqtc_bits rqt_context; 9176 }; 9177 9178 struct mlx5_ifc_create_rq_out_bits { 9179 u8 status[0x8]; 9180 u8 reserved_at_8[0x18]; 9181 9182 u8 syndrome[0x20]; 9183 9184 u8 reserved_at_40[0x8]; 9185 u8 rqn[0x18]; 9186 9187 u8 reserved_at_60[0x20]; 9188 }; 9189 9190 struct mlx5_ifc_create_rq_in_bits { 9191 u8 opcode[0x10]; 9192 u8 uid[0x10]; 9193 9194 u8 reserved_at_20[0x10]; 9195 u8 op_mod[0x10]; 9196 9197 u8 reserved_at_40[0xc0]; 9198 9199 struct mlx5_ifc_rqc_bits ctx; 9200 }; 9201 9202 struct mlx5_ifc_create_rmp_out_bits { 9203 u8 status[0x8]; 9204 u8 reserved_at_8[0x18]; 9205 9206 u8 syndrome[0x20]; 9207 9208 u8 reserved_at_40[0x8]; 9209 u8 rmpn[0x18]; 9210 9211 u8 reserved_at_60[0x20]; 9212 }; 9213 9214 struct mlx5_ifc_create_rmp_in_bits { 9215 u8 opcode[0x10]; 9216 u8 uid[0x10]; 9217 9218 u8 reserved_at_20[0x10]; 9219 u8 op_mod[0x10]; 9220 9221 u8 reserved_at_40[0xc0]; 9222 9223 struct mlx5_ifc_rmpc_bits ctx; 9224 }; 9225 9226 struct mlx5_ifc_create_qp_out_bits { 9227 u8 status[0x8]; 9228 u8 reserved_at_8[0x18]; 9229 9230 u8 syndrome[0x20]; 9231 9232 u8 reserved_at_40[0x8]; 9233 u8 qpn[0x18]; 9234 9235 u8 ece[0x20]; 9236 }; 9237 9238 struct mlx5_ifc_create_qp_in_bits { 9239 u8 opcode[0x10]; 9240 u8 uid[0x10]; 9241 9242 u8 reserved_at_20[0x10]; 9243 u8 op_mod[0x10]; 9244 9245 u8 qpc_ext[0x1]; 9246 u8 reserved_at_41[0x7]; 9247 u8 input_qpn[0x18]; 9248 9249 u8 reserved_at_60[0x20]; 9250 u8 opt_param_mask[0x20]; 9251 9252 u8 ece[0x20]; 9253 9254 struct mlx5_ifc_qpc_bits qpc; 9255 9256 u8 wq_umem_offset[0x40]; 9257 9258 u8 wq_umem_id[0x20]; 9259 9260 u8 wq_umem_valid[0x1]; 9261 u8 reserved_at_861[0x1f]; 9262 9263 u8 pas[][0x40]; 9264 }; 9265 9266 struct mlx5_ifc_create_psv_out_bits { 9267 u8 status[0x8]; 9268 u8 reserved_at_8[0x18]; 9269 9270 u8 syndrome[0x20]; 9271 9272 u8 reserved_at_40[0x40]; 9273 9274 u8 reserved_at_80[0x8]; 9275 u8 psv0_index[0x18]; 9276 9277 u8 reserved_at_a0[0x8]; 9278 u8 psv1_index[0x18]; 9279 9280 u8 reserved_at_c0[0x8]; 9281 u8 psv2_index[0x18]; 9282 9283 u8 reserved_at_e0[0x8]; 9284 u8 psv3_index[0x18]; 9285 }; 9286 9287 struct mlx5_ifc_create_psv_in_bits { 9288 u8 opcode[0x10]; 9289 u8 reserved_at_10[0x10]; 9290 9291 u8 reserved_at_20[0x10]; 9292 u8 op_mod[0x10]; 9293 9294 u8 num_psv[0x4]; 9295 u8 reserved_at_44[0x4]; 9296 u8 pd[0x18]; 9297 9298 u8 reserved_at_60[0x20]; 9299 }; 9300 9301 struct mlx5_ifc_create_mkey_out_bits { 9302 u8 status[0x8]; 9303 u8 reserved_at_8[0x18]; 9304 9305 u8 syndrome[0x20]; 9306 9307 u8 reserved_at_40[0x8]; 9308 u8 mkey_index[0x18]; 9309 9310 u8 reserved_at_60[0x20]; 9311 }; 9312 9313 struct mlx5_ifc_create_mkey_in_bits { 9314 u8 opcode[0x10]; 9315 u8 uid[0x10]; 9316 9317 u8 reserved_at_20[0x10]; 9318 u8 op_mod[0x10]; 9319 9320 u8 reserved_at_40[0x20]; 9321 9322 u8 pg_access[0x1]; 9323 u8 mkey_umem_valid[0x1]; 9324 u8 data_direct[0x1]; 9325 u8 reserved_at_63[0x1d]; 9326 9327 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9328 9329 u8 reserved_at_280[0x80]; 9330 9331 u8 translations_octword_actual_size[0x20]; 9332 9333 u8 reserved_at_320[0x560]; 9334 9335 u8 klm_pas_mtt[][0x20]; 9336 }; 9337 9338 enum { 9339 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9340 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9341 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9342 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9343 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9344 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9345 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9346 }; 9347 9348 struct mlx5_ifc_create_flow_table_out_bits { 9349 u8 status[0x8]; 9350 u8 icm_address_63_40[0x18]; 9351 9352 u8 syndrome[0x20]; 9353 9354 u8 icm_address_39_32[0x8]; 9355 u8 table_id[0x18]; 9356 9357 u8 icm_address_31_0[0x20]; 9358 }; 9359 9360 struct mlx5_ifc_create_flow_table_in_bits { 9361 u8 opcode[0x10]; 9362 u8 uid[0x10]; 9363 9364 u8 reserved_at_20[0x10]; 9365 u8 op_mod[0x10]; 9366 9367 u8 other_vport[0x1]; 9368 u8 reserved_at_41[0xf]; 9369 u8 vport_number[0x10]; 9370 9371 u8 reserved_at_60[0x20]; 9372 9373 u8 table_type[0x8]; 9374 u8 reserved_at_88[0x18]; 9375 9376 u8 reserved_at_a0[0x20]; 9377 9378 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9379 }; 9380 9381 struct mlx5_ifc_create_flow_group_out_bits { 9382 u8 status[0x8]; 9383 u8 reserved_at_8[0x18]; 9384 9385 u8 syndrome[0x20]; 9386 9387 u8 reserved_at_40[0x8]; 9388 u8 group_id[0x18]; 9389 9390 u8 reserved_at_60[0x20]; 9391 }; 9392 9393 enum { 9394 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9395 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9396 }; 9397 9398 enum { 9399 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9400 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9401 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9402 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9403 }; 9404 9405 struct mlx5_ifc_create_flow_group_in_bits { 9406 u8 opcode[0x10]; 9407 u8 reserved_at_10[0x10]; 9408 9409 u8 reserved_at_20[0x10]; 9410 u8 op_mod[0x10]; 9411 9412 u8 other_vport[0x1]; 9413 u8 reserved_at_41[0xf]; 9414 u8 vport_number[0x10]; 9415 9416 u8 reserved_at_60[0x20]; 9417 9418 u8 table_type[0x8]; 9419 u8 reserved_at_88[0x4]; 9420 u8 group_type[0x4]; 9421 u8 reserved_at_90[0x10]; 9422 9423 u8 reserved_at_a0[0x8]; 9424 u8 table_id[0x18]; 9425 9426 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9427 9428 u8 reserved_at_c1[0x1f]; 9429 9430 u8 start_flow_index[0x20]; 9431 9432 u8 reserved_at_100[0x20]; 9433 9434 u8 end_flow_index[0x20]; 9435 9436 u8 reserved_at_140[0x10]; 9437 u8 match_definer_id[0x10]; 9438 9439 u8 reserved_at_160[0x80]; 9440 9441 u8 reserved_at_1e0[0x18]; 9442 u8 match_criteria_enable[0x8]; 9443 9444 struct mlx5_ifc_fte_match_param_bits match_criteria; 9445 9446 u8 reserved_at_1200[0xe00]; 9447 }; 9448 9449 struct mlx5_ifc_create_eq_out_bits { 9450 u8 status[0x8]; 9451 u8 reserved_at_8[0x18]; 9452 9453 u8 syndrome[0x20]; 9454 9455 u8 reserved_at_40[0x18]; 9456 u8 eq_number[0x8]; 9457 9458 u8 reserved_at_60[0x20]; 9459 }; 9460 9461 struct mlx5_ifc_create_eq_in_bits { 9462 u8 opcode[0x10]; 9463 u8 uid[0x10]; 9464 9465 u8 reserved_at_20[0x10]; 9466 u8 op_mod[0x10]; 9467 9468 u8 reserved_at_40[0x40]; 9469 9470 struct mlx5_ifc_eqc_bits eq_context_entry; 9471 9472 u8 reserved_at_280[0x40]; 9473 9474 u8 event_bitmask[4][0x40]; 9475 9476 u8 reserved_at_3c0[0x4c0]; 9477 9478 u8 pas[][0x40]; 9479 }; 9480 9481 struct mlx5_ifc_create_dct_out_bits { 9482 u8 status[0x8]; 9483 u8 reserved_at_8[0x18]; 9484 9485 u8 syndrome[0x20]; 9486 9487 u8 reserved_at_40[0x8]; 9488 u8 dctn[0x18]; 9489 9490 u8 ece[0x20]; 9491 }; 9492 9493 struct mlx5_ifc_create_dct_in_bits { 9494 u8 opcode[0x10]; 9495 u8 uid[0x10]; 9496 9497 u8 reserved_at_20[0x10]; 9498 u8 op_mod[0x10]; 9499 9500 u8 reserved_at_40[0x40]; 9501 9502 struct mlx5_ifc_dctc_bits dct_context_entry; 9503 9504 u8 reserved_at_280[0x180]; 9505 }; 9506 9507 struct mlx5_ifc_create_cq_out_bits { 9508 u8 status[0x8]; 9509 u8 reserved_at_8[0x18]; 9510 9511 u8 syndrome[0x20]; 9512 9513 u8 reserved_at_40[0x8]; 9514 u8 cqn[0x18]; 9515 9516 u8 reserved_at_60[0x20]; 9517 }; 9518 9519 struct mlx5_ifc_create_cq_in_bits { 9520 u8 opcode[0x10]; 9521 u8 uid[0x10]; 9522 9523 u8 reserved_at_20[0x10]; 9524 u8 op_mod[0x10]; 9525 9526 u8 reserved_at_40[0x40]; 9527 9528 struct mlx5_ifc_cqc_bits cq_context; 9529 9530 u8 reserved_at_280[0x60]; 9531 9532 u8 cq_umem_valid[0x1]; 9533 u8 reserved_at_2e1[0x59f]; 9534 9535 u8 pas[][0x40]; 9536 }; 9537 9538 struct mlx5_ifc_config_int_moderation_out_bits { 9539 u8 status[0x8]; 9540 u8 reserved_at_8[0x18]; 9541 9542 u8 syndrome[0x20]; 9543 9544 u8 reserved_at_40[0x4]; 9545 u8 min_delay[0xc]; 9546 u8 int_vector[0x10]; 9547 9548 u8 reserved_at_60[0x20]; 9549 }; 9550 9551 enum { 9552 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9553 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9554 }; 9555 9556 struct mlx5_ifc_config_int_moderation_in_bits { 9557 u8 opcode[0x10]; 9558 u8 reserved_at_10[0x10]; 9559 9560 u8 reserved_at_20[0x10]; 9561 u8 op_mod[0x10]; 9562 9563 u8 reserved_at_40[0x4]; 9564 u8 min_delay[0xc]; 9565 u8 int_vector[0x10]; 9566 9567 u8 reserved_at_60[0x20]; 9568 }; 9569 9570 struct mlx5_ifc_attach_to_mcg_out_bits { 9571 u8 status[0x8]; 9572 u8 reserved_at_8[0x18]; 9573 9574 u8 syndrome[0x20]; 9575 9576 u8 reserved_at_40[0x40]; 9577 }; 9578 9579 struct mlx5_ifc_attach_to_mcg_in_bits { 9580 u8 opcode[0x10]; 9581 u8 uid[0x10]; 9582 9583 u8 reserved_at_20[0x10]; 9584 u8 op_mod[0x10]; 9585 9586 u8 reserved_at_40[0x8]; 9587 u8 qpn[0x18]; 9588 9589 u8 reserved_at_60[0x20]; 9590 9591 u8 multicast_gid[16][0x8]; 9592 }; 9593 9594 struct mlx5_ifc_arm_xrq_out_bits { 9595 u8 status[0x8]; 9596 u8 reserved_at_8[0x18]; 9597 9598 u8 syndrome[0x20]; 9599 9600 u8 reserved_at_40[0x40]; 9601 }; 9602 9603 struct mlx5_ifc_arm_xrq_in_bits { 9604 u8 opcode[0x10]; 9605 u8 reserved_at_10[0x10]; 9606 9607 u8 reserved_at_20[0x10]; 9608 u8 op_mod[0x10]; 9609 9610 u8 reserved_at_40[0x8]; 9611 u8 xrqn[0x18]; 9612 9613 u8 reserved_at_60[0x10]; 9614 u8 lwm[0x10]; 9615 }; 9616 9617 struct mlx5_ifc_arm_xrc_srq_out_bits { 9618 u8 status[0x8]; 9619 u8 reserved_at_8[0x18]; 9620 9621 u8 syndrome[0x20]; 9622 9623 u8 reserved_at_40[0x40]; 9624 }; 9625 9626 enum { 9627 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9628 }; 9629 9630 struct mlx5_ifc_arm_xrc_srq_in_bits { 9631 u8 opcode[0x10]; 9632 u8 uid[0x10]; 9633 9634 u8 reserved_at_20[0x10]; 9635 u8 op_mod[0x10]; 9636 9637 u8 reserved_at_40[0x8]; 9638 u8 xrc_srqn[0x18]; 9639 9640 u8 reserved_at_60[0x10]; 9641 u8 lwm[0x10]; 9642 }; 9643 9644 struct mlx5_ifc_arm_rq_out_bits { 9645 u8 status[0x8]; 9646 u8 reserved_at_8[0x18]; 9647 9648 u8 syndrome[0x20]; 9649 9650 u8 reserved_at_40[0x40]; 9651 }; 9652 9653 enum { 9654 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9655 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9656 }; 9657 9658 struct mlx5_ifc_arm_rq_in_bits { 9659 u8 opcode[0x10]; 9660 u8 uid[0x10]; 9661 9662 u8 reserved_at_20[0x10]; 9663 u8 op_mod[0x10]; 9664 9665 u8 reserved_at_40[0x8]; 9666 u8 srq_number[0x18]; 9667 9668 u8 reserved_at_60[0x10]; 9669 u8 lwm[0x10]; 9670 }; 9671 9672 struct mlx5_ifc_arm_dct_out_bits { 9673 u8 status[0x8]; 9674 u8 reserved_at_8[0x18]; 9675 9676 u8 syndrome[0x20]; 9677 9678 u8 reserved_at_40[0x40]; 9679 }; 9680 9681 struct mlx5_ifc_arm_dct_in_bits { 9682 u8 opcode[0x10]; 9683 u8 reserved_at_10[0x10]; 9684 9685 u8 reserved_at_20[0x10]; 9686 u8 op_mod[0x10]; 9687 9688 u8 reserved_at_40[0x8]; 9689 u8 dct_number[0x18]; 9690 9691 u8 reserved_at_60[0x20]; 9692 }; 9693 9694 struct mlx5_ifc_alloc_xrcd_out_bits { 9695 u8 status[0x8]; 9696 u8 reserved_at_8[0x18]; 9697 9698 u8 syndrome[0x20]; 9699 9700 u8 reserved_at_40[0x8]; 9701 u8 xrcd[0x18]; 9702 9703 u8 reserved_at_60[0x20]; 9704 }; 9705 9706 struct mlx5_ifc_alloc_xrcd_in_bits { 9707 u8 opcode[0x10]; 9708 u8 uid[0x10]; 9709 9710 u8 reserved_at_20[0x10]; 9711 u8 op_mod[0x10]; 9712 9713 u8 reserved_at_40[0x40]; 9714 }; 9715 9716 struct mlx5_ifc_alloc_uar_out_bits { 9717 u8 status[0x8]; 9718 u8 reserved_at_8[0x18]; 9719 9720 u8 syndrome[0x20]; 9721 9722 u8 reserved_at_40[0x8]; 9723 u8 uar[0x18]; 9724 9725 u8 reserved_at_60[0x20]; 9726 }; 9727 9728 struct mlx5_ifc_alloc_uar_in_bits { 9729 u8 opcode[0x10]; 9730 u8 uid[0x10]; 9731 9732 u8 reserved_at_20[0x10]; 9733 u8 op_mod[0x10]; 9734 9735 u8 reserved_at_40[0x40]; 9736 }; 9737 9738 struct mlx5_ifc_alloc_transport_domain_out_bits { 9739 u8 status[0x8]; 9740 u8 reserved_at_8[0x18]; 9741 9742 u8 syndrome[0x20]; 9743 9744 u8 reserved_at_40[0x8]; 9745 u8 transport_domain[0x18]; 9746 9747 u8 reserved_at_60[0x20]; 9748 }; 9749 9750 struct mlx5_ifc_alloc_transport_domain_in_bits { 9751 u8 opcode[0x10]; 9752 u8 uid[0x10]; 9753 9754 u8 reserved_at_20[0x10]; 9755 u8 op_mod[0x10]; 9756 9757 u8 reserved_at_40[0x40]; 9758 }; 9759 9760 struct mlx5_ifc_alloc_q_counter_out_bits { 9761 u8 status[0x8]; 9762 u8 reserved_at_8[0x18]; 9763 9764 u8 syndrome[0x20]; 9765 9766 u8 reserved_at_40[0x18]; 9767 u8 counter_set_id[0x8]; 9768 9769 u8 reserved_at_60[0x20]; 9770 }; 9771 9772 struct mlx5_ifc_alloc_q_counter_in_bits { 9773 u8 opcode[0x10]; 9774 u8 uid[0x10]; 9775 9776 u8 reserved_at_20[0x10]; 9777 u8 op_mod[0x10]; 9778 9779 u8 reserved_at_40[0x40]; 9780 }; 9781 9782 struct mlx5_ifc_alloc_pd_out_bits { 9783 u8 status[0x8]; 9784 u8 reserved_at_8[0x18]; 9785 9786 u8 syndrome[0x20]; 9787 9788 u8 reserved_at_40[0x8]; 9789 u8 pd[0x18]; 9790 9791 u8 reserved_at_60[0x20]; 9792 }; 9793 9794 struct mlx5_ifc_alloc_pd_in_bits { 9795 u8 opcode[0x10]; 9796 u8 uid[0x10]; 9797 9798 u8 reserved_at_20[0x10]; 9799 u8 op_mod[0x10]; 9800 9801 u8 reserved_at_40[0x40]; 9802 }; 9803 9804 struct mlx5_ifc_alloc_flow_counter_out_bits { 9805 u8 status[0x8]; 9806 u8 reserved_at_8[0x18]; 9807 9808 u8 syndrome[0x20]; 9809 9810 u8 flow_counter_id[0x20]; 9811 9812 u8 reserved_at_60[0x20]; 9813 }; 9814 9815 struct mlx5_ifc_alloc_flow_counter_in_bits { 9816 u8 opcode[0x10]; 9817 u8 reserved_at_10[0x10]; 9818 9819 u8 reserved_at_20[0x10]; 9820 u8 op_mod[0x10]; 9821 9822 u8 reserved_at_40[0x33]; 9823 u8 flow_counter_bulk_log_size[0x5]; 9824 u8 flow_counter_bulk[0x8]; 9825 }; 9826 9827 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9828 u8 status[0x8]; 9829 u8 reserved_at_8[0x18]; 9830 9831 u8 syndrome[0x20]; 9832 9833 u8 reserved_at_40[0x40]; 9834 }; 9835 9836 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9837 u8 opcode[0x10]; 9838 u8 reserved_at_10[0x10]; 9839 9840 u8 reserved_at_20[0x10]; 9841 u8 op_mod[0x10]; 9842 9843 u8 reserved_at_40[0x20]; 9844 9845 u8 reserved_at_60[0x10]; 9846 u8 vxlan_udp_port[0x10]; 9847 }; 9848 9849 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9850 u8 status[0x8]; 9851 u8 reserved_at_8[0x18]; 9852 9853 u8 syndrome[0x20]; 9854 9855 u8 reserved_at_40[0x40]; 9856 }; 9857 9858 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9859 u8 rate_limit[0x20]; 9860 9861 u8 burst_upper_bound[0x20]; 9862 9863 u8 reserved_at_40[0x10]; 9864 u8 typical_packet_size[0x10]; 9865 9866 u8 reserved_at_60[0x120]; 9867 }; 9868 9869 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9870 u8 opcode[0x10]; 9871 u8 uid[0x10]; 9872 9873 u8 reserved_at_20[0x10]; 9874 u8 op_mod[0x10]; 9875 9876 u8 reserved_at_40[0x10]; 9877 u8 rate_limit_index[0x10]; 9878 9879 u8 reserved_at_60[0x20]; 9880 9881 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9882 }; 9883 9884 struct mlx5_ifc_access_register_out_bits { 9885 u8 status[0x8]; 9886 u8 reserved_at_8[0x18]; 9887 9888 u8 syndrome[0x20]; 9889 9890 u8 reserved_at_40[0x40]; 9891 9892 u8 register_data[][0x20]; 9893 }; 9894 9895 enum { 9896 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9897 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9898 }; 9899 9900 struct mlx5_ifc_access_register_in_bits { 9901 u8 opcode[0x10]; 9902 u8 reserved_at_10[0x10]; 9903 9904 u8 reserved_at_20[0x10]; 9905 u8 op_mod[0x10]; 9906 9907 u8 reserved_at_40[0x10]; 9908 u8 register_id[0x10]; 9909 9910 u8 argument[0x20]; 9911 9912 u8 register_data[][0x20]; 9913 }; 9914 9915 struct mlx5_ifc_sltp_reg_bits { 9916 u8 status[0x4]; 9917 u8 version[0x4]; 9918 u8 local_port[0x8]; 9919 u8 pnat[0x2]; 9920 u8 reserved_at_12[0x2]; 9921 u8 lane[0x4]; 9922 u8 reserved_at_18[0x8]; 9923 9924 u8 reserved_at_20[0x20]; 9925 9926 u8 reserved_at_40[0x7]; 9927 u8 polarity[0x1]; 9928 u8 ob_tap0[0x8]; 9929 u8 ob_tap1[0x8]; 9930 u8 ob_tap2[0x8]; 9931 9932 u8 reserved_at_60[0xc]; 9933 u8 ob_preemp_mode[0x4]; 9934 u8 ob_reg[0x8]; 9935 u8 ob_bias[0x8]; 9936 9937 u8 reserved_at_80[0x20]; 9938 }; 9939 9940 struct mlx5_ifc_slrg_reg_bits { 9941 u8 status[0x4]; 9942 u8 version[0x4]; 9943 u8 local_port[0x8]; 9944 u8 pnat[0x2]; 9945 u8 reserved_at_12[0x2]; 9946 u8 lane[0x4]; 9947 u8 reserved_at_18[0x8]; 9948 9949 u8 time_to_link_up[0x10]; 9950 u8 reserved_at_30[0xc]; 9951 u8 grade_lane_speed[0x4]; 9952 9953 u8 grade_version[0x8]; 9954 u8 grade[0x18]; 9955 9956 u8 reserved_at_60[0x4]; 9957 u8 height_grade_type[0x4]; 9958 u8 height_grade[0x18]; 9959 9960 u8 height_dz[0x10]; 9961 u8 height_dv[0x10]; 9962 9963 u8 reserved_at_a0[0x10]; 9964 u8 height_sigma[0x10]; 9965 9966 u8 reserved_at_c0[0x20]; 9967 9968 u8 reserved_at_e0[0x4]; 9969 u8 phase_grade_type[0x4]; 9970 u8 phase_grade[0x18]; 9971 9972 u8 reserved_at_100[0x8]; 9973 u8 phase_eo_pos[0x8]; 9974 u8 reserved_at_110[0x8]; 9975 u8 phase_eo_neg[0x8]; 9976 9977 u8 ffe_set_tested[0x10]; 9978 u8 test_errors_per_lane[0x10]; 9979 }; 9980 9981 struct mlx5_ifc_pvlc_reg_bits { 9982 u8 reserved_at_0[0x8]; 9983 u8 local_port[0x8]; 9984 u8 reserved_at_10[0x10]; 9985 9986 u8 reserved_at_20[0x1c]; 9987 u8 vl_hw_cap[0x4]; 9988 9989 u8 reserved_at_40[0x1c]; 9990 u8 vl_admin[0x4]; 9991 9992 u8 reserved_at_60[0x1c]; 9993 u8 vl_operational[0x4]; 9994 }; 9995 9996 struct mlx5_ifc_pude_reg_bits { 9997 u8 swid[0x8]; 9998 u8 local_port[0x8]; 9999 u8 reserved_at_10[0x4]; 10000 u8 admin_status[0x4]; 10001 u8 reserved_at_18[0x4]; 10002 u8 oper_status[0x4]; 10003 10004 u8 reserved_at_20[0x60]; 10005 }; 10006 10007 enum { 10008 MLX5_PTYS_CONNECTOR_TYPE_PORT_DA = 0x7, 10009 }; 10010 10011 struct mlx5_ifc_ptys_reg_bits { 10012 u8 reserved_at_0[0x1]; 10013 u8 an_disable_admin[0x1]; 10014 u8 an_disable_cap[0x1]; 10015 u8 reserved_at_3[0x5]; 10016 u8 local_port[0x8]; 10017 u8 reserved_at_10[0x8]; 10018 u8 plane_ind[0x4]; 10019 u8 reserved_at_1c[0x1]; 10020 u8 proto_mask[0x3]; 10021 10022 u8 an_status[0x4]; 10023 u8 reserved_at_24[0xc]; 10024 u8 data_rate_oper[0x10]; 10025 10026 u8 ext_eth_proto_capability[0x20]; 10027 10028 u8 eth_proto_capability[0x20]; 10029 10030 u8 ib_link_width_capability[0x10]; 10031 u8 ib_proto_capability[0x10]; 10032 10033 u8 ext_eth_proto_admin[0x20]; 10034 10035 u8 eth_proto_admin[0x20]; 10036 10037 u8 ib_link_width_admin[0x10]; 10038 u8 ib_proto_admin[0x10]; 10039 10040 u8 ext_eth_proto_oper[0x20]; 10041 10042 u8 eth_proto_oper[0x20]; 10043 10044 u8 ib_link_width_oper[0x10]; 10045 u8 ib_proto_oper[0x10]; 10046 10047 u8 reserved_at_160[0x8]; 10048 u8 lane_rate_oper[0x14]; 10049 u8 connector_type[0x4]; 10050 10051 u8 eth_proto_lp_advertise[0x20]; 10052 10053 u8 reserved_at_1a0[0x60]; 10054 }; 10055 10056 struct mlx5_ifc_mlcr_reg_bits { 10057 u8 reserved_at_0[0x8]; 10058 u8 local_port[0x8]; 10059 u8 reserved_at_10[0x20]; 10060 10061 u8 beacon_duration[0x10]; 10062 u8 reserved_at_40[0x10]; 10063 10064 u8 beacon_remain[0x10]; 10065 }; 10066 10067 struct mlx5_ifc_ptas_reg_bits { 10068 u8 reserved_at_0[0x20]; 10069 10070 u8 algorithm_options[0x10]; 10071 u8 reserved_at_30[0x4]; 10072 u8 repetitions_mode[0x4]; 10073 u8 num_of_repetitions[0x8]; 10074 10075 u8 grade_version[0x8]; 10076 u8 height_grade_type[0x4]; 10077 u8 phase_grade_type[0x4]; 10078 u8 height_grade_weight[0x8]; 10079 u8 phase_grade_weight[0x8]; 10080 10081 u8 gisim_measure_bits[0x10]; 10082 u8 adaptive_tap_measure_bits[0x10]; 10083 10084 u8 ber_bath_high_error_threshold[0x10]; 10085 u8 ber_bath_mid_error_threshold[0x10]; 10086 10087 u8 ber_bath_low_error_threshold[0x10]; 10088 u8 one_ratio_high_threshold[0x10]; 10089 10090 u8 one_ratio_high_mid_threshold[0x10]; 10091 u8 one_ratio_low_mid_threshold[0x10]; 10092 10093 u8 one_ratio_low_threshold[0x10]; 10094 u8 ndeo_error_threshold[0x10]; 10095 10096 u8 mixer_offset_step_size[0x10]; 10097 u8 reserved_at_110[0x8]; 10098 u8 mix90_phase_for_voltage_bath[0x8]; 10099 10100 u8 mixer_offset_start[0x10]; 10101 u8 mixer_offset_end[0x10]; 10102 10103 u8 reserved_at_140[0x15]; 10104 u8 ber_test_time[0xb]; 10105 }; 10106 10107 struct mlx5_ifc_pspa_reg_bits { 10108 u8 swid[0x8]; 10109 u8 local_port[0x8]; 10110 u8 sub_port[0x8]; 10111 u8 reserved_at_18[0x8]; 10112 10113 u8 reserved_at_20[0x20]; 10114 }; 10115 10116 struct mlx5_ifc_pqdr_reg_bits { 10117 u8 reserved_at_0[0x8]; 10118 u8 local_port[0x8]; 10119 u8 reserved_at_10[0x5]; 10120 u8 prio[0x3]; 10121 u8 reserved_at_18[0x6]; 10122 u8 mode[0x2]; 10123 10124 u8 reserved_at_20[0x20]; 10125 10126 u8 reserved_at_40[0x10]; 10127 u8 min_threshold[0x10]; 10128 10129 u8 reserved_at_60[0x10]; 10130 u8 max_threshold[0x10]; 10131 10132 u8 reserved_at_80[0x10]; 10133 u8 mark_probability_denominator[0x10]; 10134 10135 u8 reserved_at_a0[0x60]; 10136 }; 10137 10138 struct mlx5_ifc_ppsc_reg_bits { 10139 u8 reserved_at_0[0x8]; 10140 u8 local_port[0x8]; 10141 u8 reserved_at_10[0x10]; 10142 10143 u8 reserved_at_20[0x60]; 10144 10145 u8 reserved_at_80[0x1c]; 10146 u8 wrps_admin[0x4]; 10147 10148 u8 reserved_at_a0[0x1c]; 10149 u8 wrps_status[0x4]; 10150 10151 u8 reserved_at_c0[0x8]; 10152 u8 up_threshold[0x8]; 10153 u8 reserved_at_d0[0x8]; 10154 u8 down_threshold[0x8]; 10155 10156 u8 reserved_at_e0[0x20]; 10157 10158 u8 reserved_at_100[0x1c]; 10159 u8 srps_admin[0x4]; 10160 10161 u8 reserved_at_120[0x1c]; 10162 u8 srps_status[0x4]; 10163 10164 u8 reserved_at_140[0x40]; 10165 }; 10166 10167 struct mlx5_ifc_pplr_reg_bits { 10168 u8 reserved_at_0[0x8]; 10169 u8 local_port[0x8]; 10170 u8 reserved_at_10[0x10]; 10171 10172 u8 reserved_at_20[0x8]; 10173 u8 lb_cap[0x8]; 10174 u8 reserved_at_30[0x8]; 10175 u8 lb_en[0x8]; 10176 }; 10177 10178 struct mlx5_ifc_pplm_reg_bits { 10179 u8 reserved_at_0[0x8]; 10180 u8 local_port[0x8]; 10181 u8 reserved_at_10[0x10]; 10182 10183 u8 reserved_at_20[0x20]; 10184 10185 u8 port_profile_mode[0x8]; 10186 u8 static_port_profile[0x8]; 10187 u8 active_port_profile[0x8]; 10188 u8 reserved_at_58[0x8]; 10189 10190 u8 retransmission_active[0x8]; 10191 u8 fec_mode_active[0x18]; 10192 10193 u8 rs_fec_correction_bypass_cap[0x4]; 10194 u8 reserved_at_84[0x8]; 10195 u8 fec_override_cap_56g[0x4]; 10196 u8 fec_override_cap_100g[0x4]; 10197 u8 fec_override_cap_50g[0x4]; 10198 u8 fec_override_cap_25g[0x4]; 10199 u8 fec_override_cap_10g_40g[0x4]; 10200 10201 u8 rs_fec_correction_bypass_admin[0x4]; 10202 u8 reserved_at_a4[0x8]; 10203 u8 fec_override_admin_56g[0x4]; 10204 u8 fec_override_admin_100g[0x4]; 10205 u8 fec_override_admin_50g[0x4]; 10206 u8 fec_override_admin_25g[0x4]; 10207 u8 fec_override_admin_10g_40g[0x4]; 10208 10209 u8 fec_override_cap_400g_8x[0x10]; 10210 u8 fec_override_cap_200g_4x[0x10]; 10211 10212 u8 fec_override_cap_100g_2x[0x10]; 10213 u8 fec_override_cap_50g_1x[0x10]; 10214 10215 u8 fec_override_admin_400g_8x[0x10]; 10216 u8 fec_override_admin_200g_4x[0x10]; 10217 10218 u8 fec_override_admin_100g_2x[0x10]; 10219 u8 fec_override_admin_50g_1x[0x10]; 10220 10221 u8 fec_override_cap_800g_8x[0x10]; 10222 u8 fec_override_cap_400g_4x[0x10]; 10223 10224 u8 fec_override_cap_200g_2x[0x10]; 10225 u8 fec_override_cap_100g_1x[0x10]; 10226 10227 u8 reserved_at_180[0xa0]; 10228 10229 u8 fec_override_admin_800g_8x[0x10]; 10230 u8 fec_override_admin_400g_4x[0x10]; 10231 10232 u8 fec_override_admin_200g_2x[0x10]; 10233 u8 fec_override_admin_100g_1x[0x10]; 10234 10235 u8 reserved_at_260[0x60]; 10236 10237 u8 fec_override_cap_1600g_8x[0x10]; 10238 u8 fec_override_cap_800g_4x[0x10]; 10239 10240 u8 fec_override_cap_400g_2x[0x10]; 10241 u8 fec_override_cap_200g_1x[0x10]; 10242 10243 u8 fec_override_admin_1600g_8x[0x10]; 10244 u8 fec_override_admin_800g_4x[0x10]; 10245 10246 u8 fec_override_admin_400g_2x[0x10]; 10247 u8 fec_override_admin_200g_1x[0x10]; 10248 10249 u8 reserved_at_340[0x80]; 10250 }; 10251 10252 struct mlx5_ifc_ppcnt_reg_bits { 10253 u8 swid[0x8]; 10254 u8 local_port[0x8]; 10255 u8 pnat[0x2]; 10256 u8 reserved_at_12[0x8]; 10257 u8 grp[0x6]; 10258 10259 u8 clr[0x1]; 10260 u8 reserved_at_21[0x13]; 10261 u8 plane_ind[0x4]; 10262 u8 reserved_at_38[0x3]; 10263 u8 prio_tc[0x5]; 10264 10265 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10266 }; 10267 10268 struct mlx5_ifc_mpein_reg_bits { 10269 u8 reserved_at_0[0x2]; 10270 u8 depth[0x6]; 10271 u8 pcie_index[0x8]; 10272 u8 node[0x8]; 10273 u8 reserved_at_18[0x8]; 10274 10275 u8 capability_mask[0x20]; 10276 10277 u8 reserved_at_40[0x8]; 10278 u8 link_width_enabled[0x8]; 10279 u8 link_speed_enabled[0x10]; 10280 10281 u8 lane0_physical_position[0x8]; 10282 u8 link_width_active[0x8]; 10283 u8 link_speed_active[0x10]; 10284 10285 u8 num_of_pfs[0x10]; 10286 u8 num_of_vfs[0x10]; 10287 10288 u8 bdf0[0x10]; 10289 u8 reserved_at_b0[0x10]; 10290 10291 u8 max_read_request_size[0x4]; 10292 u8 max_payload_size[0x4]; 10293 u8 reserved_at_c8[0x5]; 10294 u8 pwr_status[0x3]; 10295 u8 port_type[0x4]; 10296 u8 reserved_at_d4[0xb]; 10297 u8 lane_reversal[0x1]; 10298 10299 u8 reserved_at_e0[0x14]; 10300 u8 pci_power[0xc]; 10301 10302 u8 reserved_at_100[0x20]; 10303 10304 u8 device_status[0x10]; 10305 u8 port_state[0x8]; 10306 u8 reserved_at_138[0x8]; 10307 10308 u8 reserved_at_140[0x10]; 10309 u8 receiver_detect_result[0x10]; 10310 10311 u8 reserved_at_160[0x20]; 10312 }; 10313 10314 struct mlx5_ifc_mpcnt_reg_bits { 10315 u8 reserved_at_0[0x8]; 10316 u8 pcie_index[0x8]; 10317 u8 reserved_at_10[0xa]; 10318 u8 grp[0x6]; 10319 10320 u8 clr[0x1]; 10321 u8 reserved_at_21[0x1f]; 10322 10323 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 10324 }; 10325 10326 struct mlx5_ifc_ppad_reg_bits { 10327 u8 reserved_at_0[0x3]; 10328 u8 single_mac[0x1]; 10329 u8 reserved_at_4[0x4]; 10330 u8 local_port[0x8]; 10331 u8 mac_47_32[0x10]; 10332 10333 u8 mac_31_0[0x20]; 10334 10335 u8 reserved_at_40[0x40]; 10336 }; 10337 10338 struct mlx5_ifc_pmtu_reg_bits { 10339 u8 reserved_at_0[0x8]; 10340 u8 local_port[0x8]; 10341 u8 reserved_at_10[0x10]; 10342 10343 u8 max_mtu[0x10]; 10344 u8 reserved_at_30[0x10]; 10345 10346 u8 admin_mtu[0x10]; 10347 u8 reserved_at_50[0x10]; 10348 10349 u8 oper_mtu[0x10]; 10350 u8 reserved_at_70[0x10]; 10351 }; 10352 10353 struct mlx5_ifc_pmpr_reg_bits { 10354 u8 reserved_at_0[0x8]; 10355 u8 module[0x8]; 10356 u8 reserved_at_10[0x10]; 10357 10358 u8 reserved_at_20[0x18]; 10359 u8 attenuation_5g[0x8]; 10360 10361 u8 reserved_at_40[0x18]; 10362 u8 attenuation_7g[0x8]; 10363 10364 u8 reserved_at_60[0x18]; 10365 u8 attenuation_12g[0x8]; 10366 }; 10367 10368 struct mlx5_ifc_pmpe_reg_bits { 10369 u8 reserved_at_0[0x8]; 10370 u8 module[0x8]; 10371 u8 reserved_at_10[0xc]; 10372 u8 module_status[0x4]; 10373 10374 u8 reserved_at_20[0x60]; 10375 }; 10376 10377 struct mlx5_ifc_pmpc_reg_bits { 10378 u8 module_state_updated[32][0x8]; 10379 }; 10380 10381 struct mlx5_ifc_pmlpn_reg_bits { 10382 u8 reserved_at_0[0x4]; 10383 u8 mlpn_status[0x4]; 10384 u8 local_port[0x8]; 10385 u8 reserved_at_10[0x10]; 10386 10387 u8 e[0x1]; 10388 u8 reserved_at_21[0x1f]; 10389 }; 10390 10391 struct mlx5_ifc_pmlp_reg_bits { 10392 u8 rxtx[0x1]; 10393 u8 reserved_at_1[0x7]; 10394 u8 local_port[0x8]; 10395 u8 reserved_at_10[0x8]; 10396 u8 width[0x8]; 10397 10398 u8 lane0_module_mapping[0x20]; 10399 10400 u8 lane1_module_mapping[0x20]; 10401 10402 u8 lane2_module_mapping[0x20]; 10403 10404 u8 lane3_module_mapping[0x20]; 10405 10406 u8 reserved_at_a0[0x160]; 10407 }; 10408 10409 struct mlx5_ifc_pmaos_reg_bits { 10410 u8 reserved_at_0[0x8]; 10411 u8 module[0x8]; 10412 u8 reserved_at_10[0x4]; 10413 u8 admin_status[0x4]; 10414 u8 reserved_at_18[0x4]; 10415 u8 oper_status[0x4]; 10416 10417 u8 ase[0x1]; 10418 u8 ee[0x1]; 10419 u8 reserved_at_22[0x1c]; 10420 u8 e[0x2]; 10421 10422 u8 reserved_at_40[0x40]; 10423 }; 10424 10425 struct mlx5_ifc_plpc_reg_bits { 10426 u8 reserved_at_0[0x4]; 10427 u8 profile_id[0xc]; 10428 u8 reserved_at_10[0x4]; 10429 u8 proto_mask[0x4]; 10430 u8 reserved_at_18[0x8]; 10431 10432 u8 reserved_at_20[0x10]; 10433 u8 lane_speed[0x10]; 10434 10435 u8 reserved_at_40[0x17]; 10436 u8 lpbf[0x1]; 10437 u8 fec_mode_policy[0x8]; 10438 10439 u8 retransmission_capability[0x8]; 10440 u8 fec_mode_capability[0x18]; 10441 10442 u8 retransmission_support_admin[0x8]; 10443 u8 fec_mode_support_admin[0x18]; 10444 10445 u8 retransmission_request_admin[0x8]; 10446 u8 fec_mode_request_admin[0x18]; 10447 10448 u8 reserved_at_c0[0x80]; 10449 }; 10450 10451 struct mlx5_ifc_plib_reg_bits { 10452 u8 reserved_at_0[0x8]; 10453 u8 local_port[0x8]; 10454 u8 reserved_at_10[0x8]; 10455 u8 ib_port[0x8]; 10456 10457 u8 reserved_at_20[0x60]; 10458 }; 10459 10460 struct mlx5_ifc_plbf_reg_bits { 10461 u8 reserved_at_0[0x8]; 10462 u8 local_port[0x8]; 10463 u8 reserved_at_10[0xd]; 10464 u8 lbf_mode[0x3]; 10465 10466 u8 reserved_at_20[0x20]; 10467 }; 10468 10469 struct mlx5_ifc_pipg_reg_bits { 10470 u8 reserved_at_0[0x8]; 10471 u8 local_port[0x8]; 10472 u8 reserved_at_10[0x10]; 10473 10474 u8 dic[0x1]; 10475 u8 reserved_at_21[0x19]; 10476 u8 ipg[0x4]; 10477 u8 reserved_at_3e[0x2]; 10478 }; 10479 10480 struct mlx5_ifc_pifr_reg_bits { 10481 u8 reserved_at_0[0x8]; 10482 u8 local_port[0x8]; 10483 u8 reserved_at_10[0x10]; 10484 10485 u8 reserved_at_20[0xe0]; 10486 10487 u8 port_filter[8][0x20]; 10488 10489 u8 port_filter_update_en[8][0x20]; 10490 }; 10491 10492 enum { 10493 MLX5_BUF_OWNERSHIP_UNKNOWN = 0x0, 10494 MLX5_BUF_OWNERSHIP_FW_OWNED = 0x1, 10495 MLX5_BUF_OWNERSHIP_SW_OWNED = 0x2, 10496 }; 10497 10498 struct mlx5_ifc_pfcc_reg_bits { 10499 u8 reserved_at_0[0x4]; 10500 u8 buf_ownership[0x2]; 10501 u8 reserved_at_6[0x2]; 10502 u8 local_port[0x8]; 10503 u8 reserved_at_10[0xa]; 10504 u8 cable_length_mask[0x1]; 10505 u8 ppan_mask_n[0x1]; 10506 u8 minor_stall_mask[0x1]; 10507 u8 critical_stall_mask[0x1]; 10508 u8 reserved_at_1e[0x2]; 10509 10510 u8 ppan[0x4]; 10511 u8 reserved_at_24[0x4]; 10512 u8 prio_mask_tx[0x8]; 10513 u8 reserved_at_30[0x8]; 10514 u8 prio_mask_rx[0x8]; 10515 10516 u8 pptx[0x1]; 10517 u8 aptx[0x1]; 10518 u8 pptx_mask_n[0x1]; 10519 u8 reserved_at_43[0x5]; 10520 u8 pfctx[0x8]; 10521 u8 reserved_at_50[0x10]; 10522 10523 u8 pprx[0x1]; 10524 u8 aprx[0x1]; 10525 u8 pprx_mask_n[0x1]; 10526 u8 reserved_at_63[0x5]; 10527 u8 pfcrx[0x8]; 10528 u8 reserved_at_70[0x10]; 10529 10530 u8 device_stall_minor_watermark[0x10]; 10531 u8 device_stall_critical_watermark[0x10]; 10532 10533 u8 reserved_at_a0[0x18]; 10534 u8 cable_length[0x8]; 10535 10536 u8 reserved_at_c0[0x40]; 10537 }; 10538 10539 struct mlx5_ifc_pelc_reg_bits { 10540 u8 op[0x4]; 10541 u8 reserved_at_4[0x4]; 10542 u8 local_port[0x8]; 10543 u8 reserved_at_10[0x10]; 10544 10545 u8 op_admin[0x8]; 10546 u8 op_capability[0x8]; 10547 u8 op_request[0x8]; 10548 u8 op_active[0x8]; 10549 10550 u8 admin[0x40]; 10551 10552 u8 capability[0x40]; 10553 10554 u8 request[0x40]; 10555 10556 u8 active[0x40]; 10557 10558 u8 reserved_at_140[0x80]; 10559 }; 10560 10561 struct mlx5_ifc_peir_reg_bits { 10562 u8 reserved_at_0[0x8]; 10563 u8 local_port[0x8]; 10564 u8 reserved_at_10[0x10]; 10565 10566 u8 reserved_at_20[0xc]; 10567 u8 error_count[0x4]; 10568 u8 reserved_at_30[0x10]; 10569 10570 u8 reserved_at_40[0xc]; 10571 u8 lane[0x4]; 10572 u8 reserved_at_50[0x8]; 10573 u8 error_type[0x8]; 10574 }; 10575 10576 struct mlx5_ifc_mpegc_reg_bits { 10577 u8 reserved_at_0[0x30]; 10578 u8 field_select[0x10]; 10579 10580 u8 tx_overflow_sense[0x1]; 10581 u8 mark_cqe[0x1]; 10582 u8 mark_cnp[0x1]; 10583 u8 reserved_at_43[0x1b]; 10584 u8 tx_lossy_overflow_oper[0x2]; 10585 10586 u8 reserved_at_60[0x100]; 10587 }; 10588 10589 struct mlx5_ifc_mpir_reg_bits { 10590 u8 sdm[0x1]; 10591 u8 reserved_at_1[0x1b]; 10592 u8 host_buses[0x4]; 10593 10594 u8 reserved_at_20[0x20]; 10595 10596 u8 local_port[0x8]; 10597 u8 reserved_at_28[0x18]; 10598 10599 u8 reserved_at_60[0x20]; 10600 }; 10601 10602 enum { 10603 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10604 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10605 }; 10606 10607 enum { 10608 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10609 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10610 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10611 }; 10612 10613 struct mlx5_ifc_mtutc_reg_bits { 10614 u8 reserved_at_0[0x5]; 10615 u8 freq_adj_units[0x3]; 10616 u8 reserved_at_8[0x3]; 10617 u8 log_max_freq_adjustment[0x5]; 10618 10619 u8 reserved_at_10[0xc]; 10620 u8 operation[0x4]; 10621 10622 u8 freq_adjustment[0x20]; 10623 10624 u8 reserved_at_40[0x40]; 10625 10626 u8 utc_sec[0x20]; 10627 10628 u8 reserved_at_a0[0x2]; 10629 u8 utc_nsec[0x1e]; 10630 10631 u8 time_adjustment[0x20]; 10632 }; 10633 10634 struct mlx5_ifc_pcam_enhanced_features_bits { 10635 u8 reserved_at_0[0x10]; 10636 u8 ppcnt_recovery_counters[0x1]; 10637 u8 reserved_at_11[0x7]; 10638 u8 cable_length[0x1]; 10639 u8 reserved_at_19[0x4]; 10640 u8 fec_200G_per_lane_in_pplm[0x1]; 10641 u8 reserved_at_1e[0x2a]; 10642 u8 fec_100G_per_lane_in_pplm[0x1]; 10643 u8 reserved_at_49[0xa]; 10644 u8 buffer_ownership[0x1]; 10645 u8 resereved_at_54[0x14]; 10646 u8 fec_50G_per_lane_in_pplm[0x1]; 10647 u8 reserved_at_69[0x4]; 10648 u8 rx_icrc_encapsulated_counter[0x1]; 10649 u8 reserved_at_6e[0x4]; 10650 u8 ptys_extended_ethernet[0x1]; 10651 u8 reserved_at_73[0x3]; 10652 u8 pfcc_mask[0x1]; 10653 u8 reserved_at_77[0x3]; 10654 u8 per_lane_error_counters[0x1]; 10655 u8 rx_buffer_fullness_counters[0x1]; 10656 u8 ptys_connector_type[0x1]; 10657 u8 reserved_at_7d[0x1]; 10658 u8 ppcnt_discard_group[0x1]; 10659 u8 ppcnt_statistical_group[0x1]; 10660 }; 10661 10662 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10663 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10664 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10665 10666 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10667 u8 pplm[0x1]; 10668 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10669 10670 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10671 u8 pbmc[0x1]; 10672 u8 pptb[0x1]; 10673 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10674 u8 ppcnt[0x1]; 10675 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10676 }; 10677 10678 struct mlx5_ifc_pcam_reg_bits { 10679 u8 reserved_at_0[0x8]; 10680 u8 feature_group[0x8]; 10681 u8 reserved_at_10[0x8]; 10682 u8 access_reg_group[0x8]; 10683 10684 u8 reserved_at_20[0x20]; 10685 10686 union { 10687 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10688 u8 reserved_at_0[0x80]; 10689 } port_access_reg_cap_mask; 10690 10691 u8 reserved_at_c0[0x80]; 10692 10693 union { 10694 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10695 u8 reserved_at_0[0x80]; 10696 } feature_cap_mask; 10697 10698 u8 reserved_at_1c0[0xc0]; 10699 }; 10700 10701 struct mlx5_ifc_mcam_enhanced_features_bits { 10702 u8 reserved_at_0[0x50]; 10703 u8 mtutc_freq_adj_units[0x1]; 10704 u8 mtutc_time_adjustment_extended_range[0x1]; 10705 u8 reserved_at_52[0xb]; 10706 u8 mcia_32dwords[0x1]; 10707 u8 out_pulse_duration_ns[0x1]; 10708 u8 npps_period[0x1]; 10709 u8 reserved_at_60[0xa]; 10710 u8 reset_state[0x1]; 10711 u8 ptpcyc2realtime_modify[0x1]; 10712 u8 reserved_at_6c[0x2]; 10713 u8 pci_status_and_power[0x1]; 10714 u8 reserved_at_6f[0x5]; 10715 u8 mark_tx_action_cnp[0x1]; 10716 u8 mark_tx_action_cqe[0x1]; 10717 u8 dynamic_tx_overflow[0x1]; 10718 u8 reserved_at_77[0x4]; 10719 u8 pcie_outbound_stalled[0x1]; 10720 u8 tx_overflow_buffer_pkt[0x1]; 10721 u8 mtpps_enh_out_per_adj[0x1]; 10722 u8 mtpps_fs[0x1]; 10723 u8 pcie_performance_group[0x1]; 10724 }; 10725 10726 struct mlx5_ifc_mcam_access_reg_bits { 10727 u8 reserved_at_0[0x1c]; 10728 u8 mcda[0x1]; 10729 u8 mcc[0x1]; 10730 u8 mcqi[0x1]; 10731 u8 mcqs[0x1]; 10732 10733 u8 regs_95_to_90[0x6]; 10734 u8 mpir[0x1]; 10735 u8 regs_88_to_87[0x2]; 10736 u8 mpegc[0x1]; 10737 u8 mtutc[0x1]; 10738 u8 regs_84_to_68[0x11]; 10739 u8 tracer_registers[0x4]; 10740 10741 u8 regs_63_to_46[0x12]; 10742 u8 mrtc[0x1]; 10743 u8 regs_44_to_41[0x4]; 10744 u8 mfrl[0x1]; 10745 u8 regs_39_to_32[0x8]; 10746 10747 u8 regs_31_to_11[0x15]; 10748 u8 mtmp[0x1]; 10749 u8 regs_9_to_0[0xa]; 10750 }; 10751 10752 struct mlx5_ifc_mcam_access_reg_bits1 { 10753 u8 regs_127_to_96[0x20]; 10754 10755 u8 regs_95_to_64[0x20]; 10756 10757 u8 regs_63_to_32[0x20]; 10758 10759 u8 regs_31_to_0[0x20]; 10760 }; 10761 10762 struct mlx5_ifc_mcam_access_reg_bits2 { 10763 u8 regs_127_to_99[0x1d]; 10764 u8 mirc[0x1]; 10765 u8 regs_97_to_96[0x2]; 10766 10767 u8 regs_95_to_87[0x09]; 10768 u8 synce_registers[0x2]; 10769 u8 regs_84_to_64[0x15]; 10770 10771 u8 regs_63_to_32[0x20]; 10772 10773 u8 regs_31_to_0[0x20]; 10774 }; 10775 10776 struct mlx5_ifc_mcam_access_reg_bits3 { 10777 u8 regs_127_to_96[0x20]; 10778 10779 u8 regs_95_to_64[0x20]; 10780 10781 u8 regs_63_to_32[0x20]; 10782 10783 u8 regs_31_to_3[0x1d]; 10784 u8 mrtcq[0x1]; 10785 u8 mtctr[0x1]; 10786 u8 mtptm[0x1]; 10787 }; 10788 10789 struct mlx5_ifc_mcam_reg_bits { 10790 u8 reserved_at_0[0x8]; 10791 u8 feature_group[0x8]; 10792 u8 reserved_at_10[0x8]; 10793 u8 access_reg_group[0x8]; 10794 10795 u8 reserved_at_20[0x20]; 10796 10797 union { 10798 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10799 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10800 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10801 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; 10802 u8 reserved_at_0[0x80]; 10803 } mng_access_reg_cap_mask; 10804 10805 u8 reserved_at_c0[0x80]; 10806 10807 union { 10808 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10809 u8 reserved_at_0[0x80]; 10810 } mng_feature_cap_mask; 10811 10812 u8 reserved_at_1c0[0x80]; 10813 }; 10814 10815 struct mlx5_ifc_qcam_access_reg_cap_mask { 10816 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10817 u8 qpdpm[0x1]; 10818 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10819 u8 qdpm[0x1]; 10820 u8 qpts[0x1]; 10821 u8 qcap[0x1]; 10822 u8 qcam_access_reg_cap_mask_0[0x1]; 10823 }; 10824 10825 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10826 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10827 u8 qpts_trust_both[0x1]; 10828 }; 10829 10830 struct mlx5_ifc_qcam_reg_bits { 10831 u8 reserved_at_0[0x8]; 10832 u8 feature_group[0x8]; 10833 u8 reserved_at_10[0x8]; 10834 u8 access_reg_group[0x8]; 10835 u8 reserved_at_20[0x20]; 10836 10837 union { 10838 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10839 u8 reserved_at_0[0x80]; 10840 } qos_access_reg_cap_mask; 10841 10842 u8 reserved_at_c0[0x80]; 10843 10844 union { 10845 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10846 u8 reserved_at_0[0x80]; 10847 } qos_feature_cap_mask; 10848 10849 u8 reserved_at_1c0[0x80]; 10850 }; 10851 10852 struct mlx5_ifc_core_dump_reg_bits { 10853 u8 reserved_at_0[0x18]; 10854 u8 core_dump_type[0x8]; 10855 10856 u8 reserved_at_20[0x30]; 10857 u8 vhca_id[0x10]; 10858 10859 u8 reserved_at_60[0x8]; 10860 u8 qpn[0x18]; 10861 u8 reserved_at_80[0x180]; 10862 }; 10863 10864 struct mlx5_ifc_pcap_reg_bits { 10865 u8 reserved_at_0[0x8]; 10866 u8 local_port[0x8]; 10867 u8 reserved_at_10[0x10]; 10868 10869 u8 port_capability_mask[4][0x20]; 10870 }; 10871 10872 struct mlx5_ifc_paos_reg_bits { 10873 u8 swid[0x8]; 10874 u8 local_port[0x8]; 10875 u8 reserved_at_10[0x4]; 10876 u8 admin_status[0x4]; 10877 u8 reserved_at_18[0x4]; 10878 u8 oper_status[0x4]; 10879 10880 u8 ase[0x1]; 10881 u8 ee[0x1]; 10882 u8 reserved_at_22[0x1c]; 10883 u8 e[0x2]; 10884 10885 u8 reserved_at_40[0x40]; 10886 }; 10887 10888 struct mlx5_ifc_pamp_reg_bits { 10889 u8 reserved_at_0[0x8]; 10890 u8 opamp_group[0x8]; 10891 u8 reserved_at_10[0xc]; 10892 u8 opamp_group_type[0x4]; 10893 10894 u8 start_index[0x10]; 10895 u8 reserved_at_30[0x4]; 10896 u8 num_of_indices[0xc]; 10897 10898 u8 index_data[18][0x10]; 10899 }; 10900 10901 struct mlx5_ifc_pcmr_reg_bits { 10902 u8 reserved_at_0[0x8]; 10903 u8 local_port[0x8]; 10904 u8 reserved_at_10[0x10]; 10905 10906 u8 entropy_force_cap[0x1]; 10907 u8 entropy_calc_cap[0x1]; 10908 u8 entropy_gre_calc_cap[0x1]; 10909 u8 reserved_at_23[0xf]; 10910 u8 rx_ts_over_crc_cap[0x1]; 10911 u8 reserved_at_33[0xb]; 10912 u8 fcs_cap[0x1]; 10913 u8 reserved_at_3f[0x1]; 10914 10915 u8 entropy_force[0x1]; 10916 u8 entropy_calc[0x1]; 10917 u8 entropy_gre_calc[0x1]; 10918 u8 reserved_at_43[0xf]; 10919 u8 rx_ts_over_crc[0x1]; 10920 u8 reserved_at_53[0xb]; 10921 u8 fcs_chk[0x1]; 10922 u8 reserved_at_5f[0x1]; 10923 }; 10924 10925 struct mlx5_ifc_lane_2_module_mapping_bits { 10926 u8 reserved_at_0[0x4]; 10927 u8 rx_lane[0x4]; 10928 u8 reserved_at_8[0x4]; 10929 u8 tx_lane[0x4]; 10930 u8 reserved_at_10[0x8]; 10931 u8 module[0x8]; 10932 }; 10933 10934 struct mlx5_ifc_bufferx_reg_bits { 10935 u8 reserved_at_0[0x6]; 10936 u8 lossy[0x1]; 10937 u8 epsb[0x1]; 10938 u8 reserved_at_8[0x8]; 10939 u8 size[0x10]; 10940 10941 u8 xoff_threshold[0x10]; 10942 u8 xon_threshold[0x10]; 10943 }; 10944 10945 struct mlx5_ifc_set_node_in_bits { 10946 u8 node_description[64][0x8]; 10947 }; 10948 10949 struct mlx5_ifc_register_power_settings_bits { 10950 u8 reserved_at_0[0x18]; 10951 u8 power_settings_level[0x8]; 10952 10953 u8 reserved_at_20[0x60]; 10954 }; 10955 10956 struct mlx5_ifc_register_host_endianness_bits { 10957 u8 he[0x1]; 10958 u8 reserved_at_1[0x1f]; 10959 10960 u8 reserved_at_20[0x60]; 10961 }; 10962 10963 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10964 u8 reserved_at_0[0x20]; 10965 10966 u8 mkey[0x20]; 10967 10968 u8 addressh_63_32[0x20]; 10969 10970 u8 addressl_31_0[0x20]; 10971 }; 10972 10973 struct mlx5_ifc_ud_adrs_vector_bits { 10974 u8 dc_key[0x40]; 10975 10976 u8 ext[0x1]; 10977 u8 reserved_at_41[0x7]; 10978 u8 destination_qp_dct[0x18]; 10979 10980 u8 static_rate[0x4]; 10981 u8 sl_eth_prio[0x4]; 10982 u8 fl[0x1]; 10983 u8 mlid[0x7]; 10984 u8 rlid_udp_sport[0x10]; 10985 10986 u8 reserved_at_80[0x20]; 10987 10988 u8 rmac_47_16[0x20]; 10989 10990 u8 rmac_15_0[0x10]; 10991 u8 tclass[0x8]; 10992 u8 hop_limit[0x8]; 10993 10994 u8 reserved_at_e0[0x1]; 10995 u8 grh[0x1]; 10996 u8 reserved_at_e2[0x2]; 10997 u8 src_addr_index[0x8]; 10998 u8 flow_label[0x14]; 10999 11000 u8 rgid_rip[16][0x8]; 11001 }; 11002 11003 struct mlx5_ifc_pages_req_event_bits { 11004 u8 reserved_at_0[0x10]; 11005 u8 function_id[0x10]; 11006 11007 u8 num_pages[0x20]; 11008 11009 u8 reserved_at_40[0xa0]; 11010 }; 11011 11012 struct mlx5_ifc_eqe_bits { 11013 u8 reserved_at_0[0x8]; 11014 u8 event_type[0x8]; 11015 u8 reserved_at_10[0x8]; 11016 u8 event_sub_type[0x8]; 11017 11018 u8 reserved_at_20[0xe0]; 11019 11020 union mlx5_ifc_event_auto_bits event_data; 11021 11022 u8 reserved_at_1e0[0x10]; 11023 u8 signature[0x8]; 11024 u8 reserved_at_1f8[0x7]; 11025 u8 owner[0x1]; 11026 }; 11027 11028 enum { 11029 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 11030 }; 11031 11032 struct mlx5_ifc_cmd_queue_entry_bits { 11033 u8 type[0x8]; 11034 u8 reserved_at_8[0x18]; 11035 11036 u8 input_length[0x20]; 11037 11038 u8 input_mailbox_pointer_63_32[0x20]; 11039 11040 u8 input_mailbox_pointer_31_9[0x17]; 11041 u8 reserved_at_77[0x9]; 11042 11043 u8 command_input_inline_data[16][0x8]; 11044 11045 u8 command_output_inline_data[16][0x8]; 11046 11047 u8 output_mailbox_pointer_63_32[0x20]; 11048 11049 u8 output_mailbox_pointer_31_9[0x17]; 11050 u8 reserved_at_1b7[0x9]; 11051 11052 u8 output_length[0x20]; 11053 11054 u8 token[0x8]; 11055 u8 signature[0x8]; 11056 u8 reserved_at_1f0[0x8]; 11057 u8 status[0x7]; 11058 u8 ownership[0x1]; 11059 }; 11060 11061 struct mlx5_ifc_cmd_out_bits { 11062 u8 status[0x8]; 11063 u8 reserved_at_8[0x18]; 11064 11065 u8 syndrome[0x20]; 11066 11067 u8 command_output[0x20]; 11068 }; 11069 11070 struct mlx5_ifc_cmd_in_bits { 11071 u8 opcode[0x10]; 11072 u8 reserved_at_10[0x10]; 11073 11074 u8 reserved_at_20[0x10]; 11075 u8 op_mod[0x10]; 11076 11077 u8 command[][0x20]; 11078 }; 11079 11080 struct mlx5_ifc_cmd_if_box_bits { 11081 u8 mailbox_data[512][0x8]; 11082 11083 u8 reserved_at_1000[0x180]; 11084 11085 u8 next_pointer_63_32[0x20]; 11086 11087 u8 next_pointer_31_10[0x16]; 11088 u8 reserved_at_11b6[0xa]; 11089 11090 u8 block_number[0x20]; 11091 11092 u8 reserved_at_11e0[0x8]; 11093 u8 token[0x8]; 11094 u8 ctrl_signature[0x8]; 11095 u8 signature[0x8]; 11096 }; 11097 11098 struct mlx5_ifc_mtt_bits { 11099 u8 ptag_63_32[0x20]; 11100 11101 u8 ptag_31_8[0x18]; 11102 u8 reserved_at_38[0x6]; 11103 u8 wr_en[0x1]; 11104 u8 rd_en[0x1]; 11105 }; 11106 11107 struct mlx5_ifc_query_wol_rol_out_bits { 11108 u8 status[0x8]; 11109 u8 reserved_at_8[0x18]; 11110 11111 u8 syndrome[0x20]; 11112 11113 u8 reserved_at_40[0x10]; 11114 u8 rol_mode[0x8]; 11115 u8 wol_mode[0x8]; 11116 11117 u8 reserved_at_60[0x20]; 11118 }; 11119 11120 struct mlx5_ifc_query_wol_rol_in_bits { 11121 u8 opcode[0x10]; 11122 u8 reserved_at_10[0x10]; 11123 11124 u8 reserved_at_20[0x10]; 11125 u8 op_mod[0x10]; 11126 11127 u8 reserved_at_40[0x40]; 11128 }; 11129 11130 struct mlx5_ifc_set_wol_rol_out_bits { 11131 u8 status[0x8]; 11132 u8 reserved_at_8[0x18]; 11133 11134 u8 syndrome[0x20]; 11135 11136 u8 reserved_at_40[0x40]; 11137 }; 11138 11139 struct mlx5_ifc_set_wol_rol_in_bits { 11140 u8 opcode[0x10]; 11141 u8 reserved_at_10[0x10]; 11142 11143 u8 reserved_at_20[0x10]; 11144 u8 op_mod[0x10]; 11145 11146 u8 rol_mode_valid[0x1]; 11147 u8 wol_mode_valid[0x1]; 11148 u8 reserved_at_42[0xe]; 11149 u8 rol_mode[0x8]; 11150 u8 wol_mode[0x8]; 11151 11152 u8 reserved_at_60[0x20]; 11153 }; 11154 11155 enum { 11156 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 11157 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 11158 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 11159 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 11160 }; 11161 11162 enum { 11163 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 11164 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 11165 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 11166 }; 11167 11168 enum { 11169 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 11170 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 11171 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 11172 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 11173 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 11174 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 11175 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 11176 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 11177 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 11178 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 11179 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 11180 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 11181 MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR = 0x13, 11182 }; 11183 11184 struct mlx5_ifc_initial_seg_bits { 11185 u8 fw_rev_minor[0x10]; 11186 u8 fw_rev_major[0x10]; 11187 11188 u8 cmd_interface_rev[0x10]; 11189 u8 fw_rev_subminor[0x10]; 11190 11191 u8 reserved_at_40[0x40]; 11192 11193 u8 cmdq_phy_addr_63_32[0x20]; 11194 11195 u8 cmdq_phy_addr_31_12[0x14]; 11196 u8 reserved_at_b4[0x2]; 11197 u8 nic_interface[0x2]; 11198 u8 log_cmdq_size[0x4]; 11199 u8 log_cmdq_stride[0x4]; 11200 11201 u8 command_doorbell_vector[0x20]; 11202 11203 u8 reserved_at_e0[0xf00]; 11204 11205 u8 initializing[0x1]; 11206 u8 reserved_at_fe1[0x4]; 11207 u8 nic_interface_supported[0x3]; 11208 u8 embedded_cpu[0x1]; 11209 u8 reserved_at_fe9[0x17]; 11210 11211 struct mlx5_ifc_health_buffer_bits health_buffer; 11212 11213 u8 no_dram_nic_offset[0x20]; 11214 11215 u8 reserved_at_1220[0x6e40]; 11216 11217 u8 reserved_at_8060[0x1f]; 11218 u8 clear_int[0x1]; 11219 11220 u8 health_syndrome[0x8]; 11221 u8 health_counter[0x18]; 11222 11223 u8 reserved_at_80a0[0x17fc0]; 11224 }; 11225 11226 struct mlx5_ifc_mtpps_reg_bits { 11227 u8 reserved_at_0[0xc]; 11228 u8 cap_number_of_pps_pins[0x4]; 11229 u8 reserved_at_10[0x4]; 11230 u8 cap_max_num_of_pps_in_pins[0x4]; 11231 u8 reserved_at_18[0x4]; 11232 u8 cap_max_num_of_pps_out_pins[0x4]; 11233 11234 u8 reserved_at_20[0x13]; 11235 u8 cap_log_min_npps_period[0x5]; 11236 u8 reserved_at_38[0x3]; 11237 u8 cap_log_min_out_pulse_duration_ns[0x5]; 11238 11239 u8 reserved_at_40[0x4]; 11240 u8 cap_pin_3_mode[0x4]; 11241 u8 reserved_at_48[0x4]; 11242 u8 cap_pin_2_mode[0x4]; 11243 u8 reserved_at_50[0x4]; 11244 u8 cap_pin_1_mode[0x4]; 11245 u8 reserved_at_58[0x4]; 11246 u8 cap_pin_0_mode[0x4]; 11247 11248 u8 reserved_at_60[0x4]; 11249 u8 cap_pin_7_mode[0x4]; 11250 u8 reserved_at_68[0x4]; 11251 u8 cap_pin_6_mode[0x4]; 11252 u8 reserved_at_70[0x4]; 11253 u8 cap_pin_5_mode[0x4]; 11254 u8 reserved_at_78[0x4]; 11255 u8 cap_pin_4_mode[0x4]; 11256 11257 u8 field_select[0x20]; 11258 u8 reserved_at_a0[0x20]; 11259 11260 u8 npps_period[0x40]; 11261 11262 u8 enable[0x1]; 11263 u8 reserved_at_101[0xb]; 11264 u8 pattern[0x4]; 11265 u8 reserved_at_110[0x4]; 11266 u8 pin_mode[0x4]; 11267 u8 pin[0x8]; 11268 11269 u8 reserved_at_120[0x2]; 11270 u8 out_pulse_duration_ns[0x1e]; 11271 11272 u8 time_stamp[0x40]; 11273 11274 u8 out_pulse_duration[0x10]; 11275 u8 out_periodic_adjustment[0x10]; 11276 u8 enhanced_out_periodic_adjustment[0x20]; 11277 11278 u8 reserved_at_1c0[0x20]; 11279 }; 11280 11281 struct mlx5_ifc_mtppse_reg_bits { 11282 u8 reserved_at_0[0x18]; 11283 u8 pin[0x8]; 11284 u8 event_arm[0x1]; 11285 u8 reserved_at_21[0x1b]; 11286 u8 event_generation_mode[0x4]; 11287 u8 reserved_at_40[0x40]; 11288 }; 11289 11290 struct mlx5_ifc_mcqs_reg_bits { 11291 u8 last_index_flag[0x1]; 11292 u8 reserved_at_1[0x7]; 11293 u8 fw_device[0x8]; 11294 u8 component_index[0x10]; 11295 11296 u8 reserved_at_20[0x10]; 11297 u8 identifier[0x10]; 11298 11299 u8 reserved_at_40[0x17]; 11300 u8 component_status[0x5]; 11301 u8 component_update_state[0x4]; 11302 11303 u8 last_update_state_changer_type[0x4]; 11304 u8 last_update_state_changer_host_id[0x4]; 11305 u8 reserved_at_68[0x18]; 11306 }; 11307 11308 struct mlx5_ifc_mcqi_cap_bits { 11309 u8 supported_info_bitmask[0x20]; 11310 11311 u8 component_size[0x20]; 11312 11313 u8 max_component_size[0x20]; 11314 11315 u8 log_mcda_word_size[0x4]; 11316 u8 reserved_at_64[0xc]; 11317 u8 mcda_max_write_size[0x10]; 11318 11319 u8 rd_en[0x1]; 11320 u8 reserved_at_81[0x1]; 11321 u8 match_chip_id[0x1]; 11322 u8 match_psid[0x1]; 11323 u8 check_user_timestamp[0x1]; 11324 u8 match_base_guid_mac[0x1]; 11325 u8 reserved_at_86[0x1a]; 11326 }; 11327 11328 struct mlx5_ifc_mcqi_version_bits { 11329 u8 reserved_at_0[0x2]; 11330 u8 build_time_valid[0x1]; 11331 u8 user_defined_time_valid[0x1]; 11332 u8 reserved_at_4[0x14]; 11333 u8 version_string_length[0x8]; 11334 11335 u8 version[0x20]; 11336 11337 u8 build_time[0x40]; 11338 11339 u8 user_defined_time[0x40]; 11340 11341 u8 build_tool_version[0x20]; 11342 11343 u8 reserved_at_e0[0x20]; 11344 11345 u8 version_string[92][0x8]; 11346 }; 11347 11348 struct mlx5_ifc_mcqi_activation_method_bits { 11349 u8 pending_server_ac_power_cycle[0x1]; 11350 u8 pending_server_dc_power_cycle[0x1]; 11351 u8 pending_server_reboot[0x1]; 11352 u8 pending_fw_reset[0x1]; 11353 u8 auto_activate[0x1]; 11354 u8 all_hosts_sync[0x1]; 11355 u8 device_hw_reset[0x1]; 11356 u8 reserved_at_7[0x19]; 11357 }; 11358 11359 union mlx5_ifc_mcqi_reg_data_bits { 11360 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 11361 struct mlx5_ifc_mcqi_version_bits mcqi_version; 11362 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 11363 }; 11364 11365 struct mlx5_ifc_mcqi_reg_bits { 11366 u8 read_pending_component[0x1]; 11367 u8 reserved_at_1[0xf]; 11368 u8 component_index[0x10]; 11369 11370 u8 reserved_at_20[0x20]; 11371 11372 u8 reserved_at_40[0x1b]; 11373 u8 info_type[0x5]; 11374 11375 u8 info_size[0x20]; 11376 11377 u8 offset[0x20]; 11378 11379 u8 reserved_at_a0[0x10]; 11380 u8 data_size[0x10]; 11381 11382 union mlx5_ifc_mcqi_reg_data_bits data[]; 11383 }; 11384 11385 struct mlx5_ifc_mcc_reg_bits { 11386 u8 reserved_at_0[0x4]; 11387 u8 time_elapsed_since_last_cmd[0xc]; 11388 u8 reserved_at_10[0x8]; 11389 u8 instruction[0x8]; 11390 11391 u8 reserved_at_20[0x10]; 11392 u8 component_index[0x10]; 11393 11394 u8 reserved_at_40[0x8]; 11395 u8 update_handle[0x18]; 11396 11397 u8 handle_owner_type[0x4]; 11398 u8 handle_owner_host_id[0x4]; 11399 u8 reserved_at_68[0x1]; 11400 u8 control_progress[0x7]; 11401 u8 error_code[0x8]; 11402 u8 reserved_at_78[0x4]; 11403 u8 control_state[0x4]; 11404 11405 u8 component_size[0x20]; 11406 11407 u8 reserved_at_a0[0x60]; 11408 }; 11409 11410 struct mlx5_ifc_mcda_reg_bits { 11411 u8 reserved_at_0[0x8]; 11412 u8 update_handle[0x18]; 11413 11414 u8 offset[0x20]; 11415 11416 u8 reserved_at_40[0x10]; 11417 u8 size[0x10]; 11418 11419 u8 reserved_at_60[0x20]; 11420 11421 u8 data[][0x20]; 11422 }; 11423 11424 enum { 11425 MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0, 11426 MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1, 11427 }; 11428 11429 enum { 11430 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11431 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11432 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11433 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11434 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11435 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11436 }; 11437 11438 enum { 11439 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11440 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11441 }; 11442 11443 enum { 11444 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11445 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11446 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11447 }; 11448 11449 struct mlx5_ifc_mfrl_reg_bits { 11450 u8 reserved_at_0[0x20]; 11451 11452 u8 reserved_at_20[0x2]; 11453 u8 pci_sync_for_fw_update_start[0x1]; 11454 u8 pci_sync_for_fw_update_resp[0x2]; 11455 u8 rst_type_sel[0x3]; 11456 u8 pci_reset_req_method[0x3]; 11457 u8 reserved_at_2b[0x1]; 11458 u8 reset_state[0x4]; 11459 u8 reset_type[0x8]; 11460 u8 reset_level[0x8]; 11461 }; 11462 11463 struct mlx5_ifc_mirc_reg_bits { 11464 u8 reserved_at_0[0x18]; 11465 u8 status_code[0x8]; 11466 11467 u8 reserved_at_20[0x20]; 11468 }; 11469 11470 struct mlx5_ifc_pddr_monitor_opcode_bits { 11471 u8 reserved_at_0[0x10]; 11472 u8 monitor_opcode[0x10]; 11473 }; 11474 11475 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11476 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11477 u8 reserved_at_0[0x20]; 11478 }; 11479 11480 enum { 11481 /* Monitor opcodes */ 11482 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11483 }; 11484 11485 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11486 u8 reserved_at_0[0x10]; 11487 u8 group_opcode[0x10]; 11488 11489 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11490 11491 u8 reserved_at_40[0x20]; 11492 11493 u8 status_message[59][0x20]; 11494 }; 11495 11496 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11497 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11498 u8 reserved_at_0[0x7c0]; 11499 }; 11500 11501 enum { 11502 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11503 }; 11504 11505 struct mlx5_ifc_pddr_reg_bits { 11506 u8 reserved_at_0[0x8]; 11507 u8 local_port[0x8]; 11508 u8 pnat[0x2]; 11509 u8 reserved_at_12[0xe]; 11510 11511 u8 reserved_at_20[0x18]; 11512 u8 page_select[0x8]; 11513 11514 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11515 }; 11516 11517 struct mlx5_ifc_mrtc_reg_bits { 11518 u8 time_synced[0x1]; 11519 u8 reserved_at_1[0x1f]; 11520 11521 u8 reserved_at_20[0x20]; 11522 11523 u8 time_h[0x20]; 11524 11525 u8 time_l[0x20]; 11526 }; 11527 11528 struct mlx5_ifc_mtcap_reg_bits { 11529 u8 reserved_at_0[0x19]; 11530 u8 sensor_count[0x7]; 11531 11532 u8 reserved_at_20[0x20]; 11533 11534 u8 sensor_map[0x40]; 11535 }; 11536 11537 struct mlx5_ifc_mtmp_reg_bits { 11538 u8 reserved_at_0[0x14]; 11539 u8 sensor_index[0xc]; 11540 11541 u8 reserved_at_20[0x10]; 11542 u8 temperature[0x10]; 11543 11544 u8 mte[0x1]; 11545 u8 mtr[0x1]; 11546 u8 reserved_at_42[0xe]; 11547 u8 max_temperature[0x10]; 11548 11549 u8 tee[0x2]; 11550 u8 reserved_at_62[0xe]; 11551 u8 temp_threshold_hi[0x10]; 11552 11553 u8 reserved_at_80[0x10]; 11554 u8 temp_threshold_lo[0x10]; 11555 11556 u8 reserved_at_a0[0x20]; 11557 11558 u8 sensor_name_hi[0x20]; 11559 u8 sensor_name_lo[0x20]; 11560 }; 11561 11562 struct mlx5_ifc_mtptm_reg_bits { 11563 u8 reserved_at_0[0x10]; 11564 u8 psta[0x1]; 11565 u8 reserved_at_11[0xf]; 11566 11567 u8 reserved_at_20[0x60]; 11568 }; 11569 11570 enum { 11571 MLX5_MTCTR_REQUEST_NOP = 0x0, 11572 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, 11573 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, 11574 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, 11575 }; 11576 11577 struct mlx5_ifc_mtctr_reg_bits { 11578 u8 first_clock_timestamp_request[0x8]; 11579 u8 second_clock_timestamp_request[0x8]; 11580 u8 reserved_at_10[0x10]; 11581 11582 u8 first_clock_valid[0x1]; 11583 u8 second_clock_valid[0x1]; 11584 u8 reserved_at_22[0x1e]; 11585 11586 u8 first_clock_timestamp[0x40]; 11587 u8 second_clock_timestamp[0x40]; 11588 }; 11589 11590 union mlx5_ifc_ports_control_registers_document_bits { 11591 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11592 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11593 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11594 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11595 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11596 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11597 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11598 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11599 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11600 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11601 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11602 struct mlx5_ifc_paos_reg_bits paos_reg; 11603 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11604 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11605 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11606 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11607 struct mlx5_ifc_peir_reg_bits peir_reg; 11608 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11609 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11610 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11611 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11612 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11613 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11614 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11615 struct mlx5_ifc_plib_reg_bits plib_reg; 11616 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11617 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11618 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11619 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11620 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11621 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11622 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11623 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11624 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11625 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11626 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11627 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11628 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11629 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11630 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11631 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11632 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11633 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11634 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11635 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11636 struct mlx5_ifc_pude_reg_bits pude_reg; 11637 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11638 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11639 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11640 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11641 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11642 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11643 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11644 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11645 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11646 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11647 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11648 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11649 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11650 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11651 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11652 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11653 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11654 struct mlx5_ifc_mtptm_reg_bits mtptm_reg; 11655 struct mlx5_ifc_mtctr_reg_bits mtctr_reg; 11656 u8 reserved_at_0[0x60e0]; 11657 }; 11658 11659 union mlx5_ifc_debug_enhancements_document_bits { 11660 struct mlx5_ifc_health_buffer_bits health_buffer; 11661 u8 reserved_at_0[0x200]; 11662 }; 11663 11664 union mlx5_ifc_uplink_pci_interface_document_bits { 11665 struct mlx5_ifc_initial_seg_bits initial_seg; 11666 u8 reserved_at_0[0x20060]; 11667 }; 11668 11669 struct mlx5_ifc_set_flow_table_root_out_bits { 11670 u8 status[0x8]; 11671 u8 reserved_at_8[0x18]; 11672 11673 u8 syndrome[0x20]; 11674 11675 u8 reserved_at_40[0x40]; 11676 }; 11677 11678 struct mlx5_ifc_set_flow_table_root_in_bits { 11679 u8 opcode[0x10]; 11680 u8 reserved_at_10[0x10]; 11681 11682 u8 reserved_at_20[0x10]; 11683 u8 op_mod[0x10]; 11684 11685 u8 other_vport[0x1]; 11686 u8 reserved_at_41[0xf]; 11687 u8 vport_number[0x10]; 11688 11689 u8 reserved_at_60[0x20]; 11690 11691 u8 table_type[0x8]; 11692 u8 reserved_at_88[0x7]; 11693 u8 table_of_other_vport[0x1]; 11694 u8 table_vport_number[0x10]; 11695 11696 u8 reserved_at_a0[0x8]; 11697 u8 table_id[0x18]; 11698 11699 u8 reserved_at_c0[0x8]; 11700 u8 underlay_qpn[0x18]; 11701 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11702 u8 reserved_at_e1[0xf]; 11703 u8 table_eswitch_owner_vhca_id[0x10]; 11704 u8 reserved_at_100[0x100]; 11705 }; 11706 11707 enum { 11708 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11709 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11710 }; 11711 11712 struct mlx5_ifc_modify_flow_table_out_bits { 11713 u8 status[0x8]; 11714 u8 reserved_at_8[0x18]; 11715 11716 u8 syndrome[0x20]; 11717 11718 u8 reserved_at_40[0x40]; 11719 }; 11720 11721 struct mlx5_ifc_modify_flow_table_in_bits { 11722 u8 opcode[0x10]; 11723 u8 reserved_at_10[0x10]; 11724 11725 u8 reserved_at_20[0x10]; 11726 u8 op_mod[0x10]; 11727 11728 u8 other_vport[0x1]; 11729 u8 reserved_at_41[0xf]; 11730 u8 vport_number[0x10]; 11731 11732 u8 reserved_at_60[0x10]; 11733 u8 modify_field_select[0x10]; 11734 11735 u8 table_type[0x8]; 11736 u8 reserved_at_88[0x18]; 11737 11738 u8 reserved_at_a0[0x8]; 11739 u8 table_id[0x18]; 11740 11741 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11742 }; 11743 11744 struct mlx5_ifc_ets_tcn_config_reg_bits { 11745 u8 g[0x1]; 11746 u8 b[0x1]; 11747 u8 r[0x1]; 11748 u8 reserved_at_3[0x9]; 11749 u8 group[0x4]; 11750 u8 reserved_at_10[0x9]; 11751 u8 bw_allocation[0x7]; 11752 11753 u8 reserved_at_20[0xc]; 11754 u8 max_bw_units[0x4]; 11755 u8 reserved_at_30[0x8]; 11756 u8 max_bw_value[0x8]; 11757 }; 11758 11759 struct mlx5_ifc_ets_global_config_reg_bits { 11760 u8 reserved_at_0[0x2]; 11761 u8 r[0x1]; 11762 u8 reserved_at_3[0x1d]; 11763 11764 u8 reserved_at_20[0xc]; 11765 u8 max_bw_units[0x4]; 11766 u8 reserved_at_30[0x8]; 11767 u8 max_bw_value[0x8]; 11768 }; 11769 11770 struct mlx5_ifc_qetc_reg_bits { 11771 u8 reserved_at_0[0x8]; 11772 u8 port_number[0x8]; 11773 u8 reserved_at_10[0x30]; 11774 11775 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11776 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11777 }; 11778 11779 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11780 u8 e[0x1]; 11781 u8 reserved_at_01[0x0b]; 11782 u8 prio[0x04]; 11783 }; 11784 11785 struct mlx5_ifc_qpdpm_reg_bits { 11786 u8 reserved_at_0[0x8]; 11787 u8 local_port[0x8]; 11788 u8 reserved_at_10[0x10]; 11789 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11790 }; 11791 11792 struct mlx5_ifc_qpts_reg_bits { 11793 u8 reserved_at_0[0x8]; 11794 u8 local_port[0x8]; 11795 u8 reserved_at_10[0x2d]; 11796 u8 trust_state[0x3]; 11797 }; 11798 11799 struct mlx5_ifc_pptb_reg_bits { 11800 u8 reserved_at_0[0x2]; 11801 u8 mm[0x2]; 11802 u8 reserved_at_4[0x4]; 11803 u8 local_port[0x8]; 11804 u8 reserved_at_10[0x6]; 11805 u8 cm[0x1]; 11806 u8 um[0x1]; 11807 u8 pm[0x8]; 11808 11809 u8 prio_x_buff[0x20]; 11810 11811 u8 pm_msb[0x8]; 11812 u8 reserved_at_48[0x10]; 11813 u8 ctrl_buff[0x4]; 11814 u8 untagged_buff[0x4]; 11815 }; 11816 11817 struct mlx5_ifc_sbcam_reg_bits { 11818 u8 reserved_at_0[0x8]; 11819 u8 feature_group[0x8]; 11820 u8 reserved_at_10[0x8]; 11821 u8 access_reg_group[0x8]; 11822 11823 u8 reserved_at_20[0x20]; 11824 11825 u8 sb_access_reg_cap_mask[4][0x20]; 11826 11827 u8 reserved_at_c0[0x80]; 11828 11829 u8 sb_feature_cap_mask[4][0x20]; 11830 11831 u8 reserved_at_1c0[0x40]; 11832 11833 u8 cap_total_buffer_size[0x20]; 11834 11835 u8 cap_cell_size[0x10]; 11836 u8 cap_max_pg_buffers[0x8]; 11837 u8 cap_num_pool_supported[0x8]; 11838 11839 u8 reserved_at_240[0x8]; 11840 u8 cap_sbsr_stat_size[0x8]; 11841 u8 cap_max_tclass_data[0x8]; 11842 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11843 }; 11844 11845 struct mlx5_ifc_pbmc_reg_bits { 11846 u8 reserved_at_0[0x8]; 11847 u8 local_port[0x8]; 11848 u8 reserved_at_10[0x10]; 11849 11850 u8 xoff_timer_value[0x10]; 11851 u8 xoff_refresh[0x10]; 11852 11853 u8 reserved_at_40[0x9]; 11854 u8 fullness_threshold[0x7]; 11855 u8 port_buffer_size[0x10]; 11856 11857 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11858 11859 u8 reserved_at_2e0[0x80]; 11860 }; 11861 11862 struct mlx5_ifc_sbpr_reg_bits { 11863 u8 desc[0x1]; 11864 u8 snap[0x1]; 11865 u8 reserved_at_2[0x4]; 11866 u8 dir[0x2]; 11867 u8 reserved_at_8[0x14]; 11868 u8 pool[0x4]; 11869 11870 u8 infi_size[0x1]; 11871 u8 reserved_at_21[0x7]; 11872 u8 size[0x18]; 11873 11874 u8 reserved_at_40[0x1c]; 11875 u8 mode[0x4]; 11876 11877 u8 reserved_at_60[0x8]; 11878 u8 buff_occupancy[0x18]; 11879 11880 u8 clr[0x1]; 11881 u8 reserved_at_81[0x7]; 11882 u8 max_buff_occupancy[0x18]; 11883 11884 u8 reserved_at_a0[0x8]; 11885 u8 ext_buff_occupancy[0x18]; 11886 }; 11887 11888 struct mlx5_ifc_sbcm_reg_bits { 11889 u8 desc[0x1]; 11890 u8 snap[0x1]; 11891 u8 reserved_at_2[0x6]; 11892 u8 local_port[0x8]; 11893 u8 pnat[0x2]; 11894 u8 pg_buff[0x6]; 11895 u8 reserved_at_18[0x6]; 11896 u8 dir[0x2]; 11897 11898 u8 reserved_at_20[0x1f]; 11899 u8 exc[0x1]; 11900 11901 u8 reserved_at_40[0x40]; 11902 11903 u8 reserved_at_80[0x8]; 11904 u8 buff_occupancy[0x18]; 11905 11906 u8 clr[0x1]; 11907 u8 reserved_at_a1[0x7]; 11908 u8 max_buff_occupancy[0x18]; 11909 11910 u8 reserved_at_c0[0x8]; 11911 u8 min_buff[0x18]; 11912 11913 u8 infi_max[0x1]; 11914 u8 reserved_at_e1[0x7]; 11915 u8 max_buff[0x18]; 11916 11917 u8 reserved_at_100[0x20]; 11918 11919 u8 reserved_at_120[0x1c]; 11920 u8 pool[0x4]; 11921 }; 11922 11923 struct mlx5_ifc_qtct_reg_bits { 11924 u8 reserved_at_0[0x8]; 11925 u8 port_number[0x8]; 11926 u8 reserved_at_10[0xd]; 11927 u8 prio[0x3]; 11928 11929 u8 reserved_at_20[0x1d]; 11930 u8 tclass[0x3]; 11931 }; 11932 11933 struct mlx5_ifc_mcia_reg_bits { 11934 u8 l[0x1]; 11935 u8 reserved_at_1[0x7]; 11936 u8 module[0x8]; 11937 u8 reserved_at_10[0x8]; 11938 u8 status[0x8]; 11939 11940 u8 i2c_device_address[0x8]; 11941 u8 page_number[0x8]; 11942 u8 device_address[0x10]; 11943 11944 u8 reserved_at_40[0x10]; 11945 u8 size[0x10]; 11946 11947 u8 reserved_at_60[0x20]; 11948 11949 u8 dword_0[0x20]; 11950 u8 dword_1[0x20]; 11951 u8 dword_2[0x20]; 11952 u8 dword_3[0x20]; 11953 u8 dword_4[0x20]; 11954 u8 dword_5[0x20]; 11955 u8 dword_6[0x20]; 11956 u8 dword_7[0x20]; 11957 u8 dword_8[0x20]; 11958 u8 dword_9[0x20]; 11959 u8 dword_10[0x20]; 11960 u8 dword_11[0x20]; 11961 }; 11962 11963 struct mlx5_ifc_dcbx_param_bits { 11964 u8 dcbx_cee_cap[0x1]; 11965 u8 dcbx_ieee_cap[0x1]; 11966 u8 dcbx_standby_cap[0x1]; 11967 u8 reserved_at_3[0x5]; 11968 u8 port_number[0x8]; 11969 u8 reserved_at_10[0xa]; 11970 u8 max_application_table_size[6]; 11971 u8 reserved_at_20[0x15]; 11972 u8 version_oper[0x3]; 11973 u8 reserved_at_38[5]; 11974 u8 version_admin[0x3]; 11975 u8 willing_admin[0x1]; 11976 u8 reserved_at_41[0x3]; 11977 u8 pfc_cap_oper[0x4]; 11978 u8 reserved_at_48[0x4]; 11979 u8 pfc_cap_admin[0x4]; 11980 u8 reserved_at_50[0x4]; 11981 u8 num_of_tc_oper[0x4]; 11982 u8 reserved_at_58[0x4]; 11983 u8 num_of_tc_admin[0x4]; 11984 u8 remote_willing[0x1]; 11985 u8 reserved_at_61[3]; 11986 u8 remote_pfc_cap[4]; 11987 u8 reserved_at_68[0x14]; 11988 u8 remote_num_of_tc[0x4]; 11989 u8 reserved_at_80[0x18]; 11990 u8 error[0x8]; 11991 u8 reserved_at_a0[0x160]; 11992 }; 11993 11994 enum { 11995 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11996 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11997 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11998 }; 11999 12000 struct mlx5_ifc_lagc_bits { 12001 u8 fdb_selection_mode[0x1]; 12002 u8 reserved_at_1[0x14]; 12003 u8 port_select_mode[0x3]; 12004 u8 reserved_at_18[0x5]; 12005 u8 lag_state[0x3]; 12006 12007 u8 reserved_at_20[0xc]; 12008 u8 active_port[0x4]; 12009 u8 reserved_at_30[0x4]; 12010 u8 tx_remap_affinity_2[0x4]; 12011 u8 reserved_at_38[0x4]; 12012 u8 tx_remap_affinity_1[0x4]; 12013 }; 12014 12015 struct mlx5_ifc_create_lag_out_bits { 12016 u8 status[0x8]; 12017 u8 reserved_at_8[0x18]; 12018 12019 u8 syndrome[0x20]; 12020 12021 u8 reserved_at_40[0x40]; 12022 }; 12023 12024 struct mlx5_ifc_create_lag_in_bits { 12025 u8 opcode[0x10]; 12026 u8 reserved_at_10[0x10]; 12027 12028 u8 reserved_at_20[0x10]; 12029 u8 op_mod[0x10]; 12030 12031 struct mlx5_ifc_lagc_bits ctx; 12032 }; 12033 12034 struct mlx5_ifc_modify_lag_out_bits { 12035 u8 status[0x8]; 12036 u8 reserved_at_8[0x18]; 12037 12038 u8 syndrome[0x20]; 12039 12040 u8 reserved_at_40[0x40]; 12041 }; 12042 12043 struct mlx5_ifc_modify_lag_in_bits { 12044 u8 opcode[0x10]; 12045 u8 reserved_at_10[0x10]; 12046 12047 u8 reserved_at_20[0x10]; 12048 u8 op_mod[0x10]; 12049 12050 u8 reserved_at_40[0x20]; 12051 u8 field_select[0x20]; 12052 12053 struct mlx5_ifc_lagc_bits ctx; 12054 }; 12055 12056 struct mlx5_ifc_query_lag_out_bits { 12057 u8 status[0x8]; 12058 u8 reserved_at_8[0x18]; 12059 12060 u8 syndrome[0x20]; 12061 12062 struct mlx5_ifc_lagc_bits ctx; 12063 }; 12064 12065 struct mlx5_ifc_query_lag_in_bits { 12066 u8 opcode[0x10]; 12067 u8 reserved_at_10[0x10]; 12068 12069 u8 reserved_at_20[0x10]; 12070 u8 op_mod[0x10]; 12071 12072 u8 reserved_at_40[0x40]; 12073 }; 12074 12075 struct mlx5_ifc_destroy_lag_out_bits { 12076 u8 status[0x8]; 12077 u8 reserved_at_8[0x18]; 12078 12079 u8 syndrome[0x20]; 12080 12081 u8 reserved_at_40[0x40]; 12082 }; 12083 12084 struct mlx5_ifc_destroy_lag_in_bits { 12085 u8 opcode[0x10]; 12086 u8 reserved_at_10[0x10]; 12087 12088 u8 reserved_at_20[0x10]; 12089 u8 op_mod[0x10]; 12090 12091 u8 reserved_at_40[0x40]; 12092 }; 12093 12094 struct mlx5_ifc_create_vport_lag_out_bits { 12095 u8 status[0x8]; 12096 u8 reserved_at_8[0x18]; 12097 12098 u8 syndrome[0x20]; 12099 12100 u8 reserved_at_40[0x40]; 12101 }; 12102 12103 struct mlx5_ifc_create_vport_lag_in_bits { 12104 u8 opcode[0x10]; 12105 u8 reserved_at_10[0x10]; 12106 12107 u8 reserved_at_20[0x10]; 12108 u8 op_mod[0x10]; 12109 12110 u8 reserved_at_40[0x40]; 12111 }; 12112 12113 struct mlx5_ifc_destroy_vport_lag_out_bits { 12114 u8 status[0x8]; 12115 u8 reserved_at_8[0x18]; 12116 12117 u8 syndrome[0x20]; 12118 12119 u8 reserved_at_40[0x40]; 12120 }; 12121 12122 struct mlx5_ifc_destroy_vport_lag_in_bits { 12123 u8 opcode[0x10]; 12124 u8 reserved_at_10[0x10]; 12125 12126 u8 reserved_at_20[0x10]; 12127 u8 op_mod[0x10]; 12128 12129 u8 reserved_at_40[0x40]; 12130 }; 12131 12132 enum { 12133 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 12134 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 12135 }; 12136 12137 struct mlx5_ifc_modify_memic_in_bits { 12138 u8 opcode[0x10]; 12139 u8 uid[0x10]; 12140 12141 u8 reserved_at_20[0x10]; 12142 u8 op_mod[0x10]; 12143 12144 u8 reserved_at_40[0x20]; 12145 12146 u8 reserved_at_60[0x18]; 12147 u8 memic_operation_type[0x8]; 12148 12149 u8 memic_start_addr[0x40]; 12150 12151 u8 reserved_at_c0[0x140]; 12152 }; 12153 12154 struct mlx5_ifc_modify_memic_out_bits { 12155 u8 status[0x8]; 12156 u8 reserved_at_8[0x18]; 12157 12158 u8 syndrome[0x20]; 12159 12160 u8 reserved_at_40[0x40]; 12161 12162 u8 memic_operation_addr[0x40]; 12163 12164 u8 reserved_at_c0[0x140]; 12165 }; 12166 12167 struct mlx5_ifc_alloc_memic_in_bits { 12168 u8 opcode[0x10]; 12169 u8 reserved_at_10[0x10]; 12170 12171 u8 reserved_at_20[0x10]; 12172 u8 op_mod[0x10]; 12173 12174 u8 reserved_at_30[0x20]; 12175 12176 u8 reserved_at_40[0x18]; 12177 u8 log_memic_addr_alignment[0x8]; 12178 12179 u8 range_start_addr[0x40]; 12180 12181 u8 range_size[0x20]; 12182 12183 u8 memic_size[0x20]; 12184 }; 12185 12186 struct mlx5_ifc_alloc_memic_out_bits { 12187 u8 status[0x8]; 12188 u8 reserved_at_8[0x18]; 12189 12190 u8 syndrome[0x20]; 12191 12192 u8 memic_start_addr[0x40]; 12193 }; 12194 12195 struct mlx5_ifc_dealloc_memic_in_bits { 12196 u8 opcode[0x10]; 12197 u8 reserved_at_10[0x10]; 12198 12199 u8 reserved_at_20[0x10]; 12200 u8 op_mod[0x10]; 12201 12202 u8 reserved_at_40[0x40]; 12203 12204 u8 memic_start_addr[0x40]; 12205 12206 u8 memic_size[0x20]; 12207 12208 u8 reserved_at_e0[0x20]; 12209 }; 12210 12211 struct mlx5_ifc_dealloc_memic_out_bits { 12212 u8 status[0x8]; 12213 u8 reserved_at_8[0x18]; 12214 12215 u8 syndrome[0x20]; 12216 12217 u8 reserved_at_40[0x40]; 12218 }; 12219 12220 struct mlx5_ifc_umem_bits { 12221 u8 reserved_at_0[0x80]; 12222 12223 u8 ats[0x1]; 12224 u8 reserved_at_81[0x1a]; 12225 u8 log_page_size[0x5]; 12226 12227 u8 page_offset[0x20]; 12228 12229 u8 num_of_mtt[0x40]; 12230 12231 struct mlx5_ifc_mtt_bits mtt[]; 12232 }; 12233 12234 struct mlx5_ifc_uctx_bits { 12235 u8 cap[0x20]; 12236 12237 u8 reserved_at_20[0x160]; 12238 }; 12239 12240 struct mlx5_ifc_sw_icm_bits { 12241 u8 modify_field_select[0x40]; 12242 12243 u8 reserved_at_40[0x18]; 12244 u8 log_sw_icm_size[0x8]; 12245 12246 u8 reserved_at_60[0x20]; 12247 12248 u8 sw_icm_start_addr[0x40]; 12249 12250 u8 reserved_at_c0[0x140]; 12251 }; 12252 12253 struct mlx5_ifc_geneve_tlv_option_bits { 12254 u8 modify_field_select[0x40]; 12255 12256 u8 reserved_at_40[0x18]; 12257 u8 geneve_option_fte_index[0x8]; 12258 12259 u8 option_class[0x10]; 12260 u8 option_type[0x8]; 12261 u8 reserved_at_78[0x3]; 12262 u8 option_data_length[0x5]; 12263 12264 u8 reserved_at_80[0x180]; 12265 }; 12266 12267 struct mlx5_ifc_create_umem_in_bits { 12268 u8 opcode[0x10]; 12269 u8 uid[0x10]; 12270 12271 u8 reserved_at_20[0x10]; 12272 u8 op_mod[0x10]; 12273 12274 u8 reserved_at_40[0x40]; 12275 12276 struct mlx5_ifc_umem_bits umem; 12277 }; 12278 12279 struct mlx5_ifc_create_umem_out_bits { 12280 u8 status[0x8]; 12281 u8 reserved_at_8[0x18]; 12282 12283 u8 syndrome[0x20]; 12284 12285 u8 reserved_at_40[0x8]; 12286 u8 umem_id[0x18]; 12287 12288 u8 reserved_at_60[0x20]; 12289 }; 12290 12291 struct mlx5_ifc_destroy_umem_in_bits { 12292 u8 opcode[0x10]; 12293 u8 uid[0x10]; 12294 12295 u8 reserved_at_20[0x10]; 12296 u8 op_mod[0x10]; 12297 12298 u8 reserved_at_40[0x8]; 12299 u8 umem_id[0x18]; 12300 12301 u8 reserved_at_60[0x20]; 12302 }; 12303 12304 struct mlx5_ifc_destroy_umem_out_bits { 12305 u8 status[0x8]; 12306 u8 reserved_at_8[0x18]; 12307 12308 u8 syndrome[0x20]; 12309 12310 u8 reserved_at_40[0x40]; 12311 }; 12312 12313 struct mlx5_ifc_create_uctx_in_bits { 12314 u8 opcode[0x10]; 12315 u8 reserved_at_10[0x10]; 12316 12317 u8 reserved_at_20[0x10]; 12318 u8 op_mod[0x10]; 12319 12320 u8 reserved_at_40[0x40]; 12321 12322 struct mlx5_ifc_uctx_bits uctx; 12323 }; 12324 12325 struct mlx5_ifc_create_uctx_out_bits { 12326 u8 status[0x8]; 12327 u8 reserved_at_8[0x18]; 12328 12329 u8 syndrome[0x20]; 12330 12331 u8 reserved_at_40[0x10]; 12332 u8 uid[0x10]; 12333 12334 u8 reserved_at_60[0x20]; 12335 }; 12336 12337 struct mlx5_ifc_destroy_uctx_in_bits { 12338 u8 opcode[0x10]; 12339 u8 reserved_at_10[0x10]; 12340 12341 u8 reserved_at_20[0x10]; 12342 u8 op_mod[0x10]; 12343 12344 u8 reserved_at_40[0x10]; 12345 u8 uid[0x10]; 12346 12347 u8 reserved_at_60[0x20]; 12348 }; 12349 12350 struct mlx5_ifc_destroy_uctx_out_bits { 12351 u8 status[0x8]; 12352 u8 reserved_at_8[0x18]; 12353 12354 u8 syndrome[0x20]; 12355 12356 u8 reserved_at_40[0x40]; 12357 }; 12358 12359 struct mlx5_ifc_create_sw_icm_in_bits { 12360 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12361 struct mlx5_ifc_sw_icm_bits sw_icm; 12362 }; 12363 12364 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 12365 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12366 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 12367 }; 12368 12369 struct mlx5_ifc_mtrc_string_db_param_bits { 12370 u8 string_db_base_address[0x20]; 12371 12372 u8 reserved_at_20[0x8]; 12373 u8 string_db_size[0x18]; 12374 }; 12375 12376 struct mlx5_ifc_mtrc_cap_bits { 12377 u8 trace_owner[0x1]; 12378 u8 trace_to_memory[0x1]; 12379 u8 reserved_at_2[0x4]; 12380 u8 trc_ver[0x2]; 12381 u8 reserved_at_8[0x14]; 12382 u8 num_string_db[0x4]; 12383 12384 u8 first_string_trace[0x8]; 12385 u8 num_string_trace[0x8]; 12386 u8 reserved_at_30[0x28]; 12387 12388 u8 log_max_trace_buffer_size[0x8]; 12389 12390 u8 reserved_at_60[0x20]; 12391 12392 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 12393 12394 u8 reserved_at_280[0x180]; 12395 }; 12396 12397 struct mlx5_ifc_mtrc_conf_bits { 12398 u8 reserved_at_0[0x1c]; 12399 u8 trace_mode[0x4]; 12400 u8 reserved_at_20[0x18]; 12401 u8 log_trace_buffer_size[0x8]; 12402 u8 trace_mkey[0x20]; 12403 u8 reserved_at_60[0x3a0]; 12404 }; 12405 12406 struct mlx5_ifc_mtrc_stdb_bits { 12407 u8 string_db_index[0x4]; 12408 u8 reserved_at_4[0x4]; 12409 u8 read_size[0x18]; 12410 u8 start_offset[0x20]; 12411 u8 string_db_data[]; 12412 }; 12413 12414 struct mlx5_ifc_mtrc_ctrl_bits { 12415 u8 trace_status[0x2]; 12416 u8 reserved_at_2[0x2]; 12417 u8 arm_event[0x1]; 12418 u8 reserved_at_5[0xb]; 12419 u8 modify_field_select[0x10]; 12420 u8 reserved_at_20[0x2b]; 12421 u8 current_timestamp52_32[0x15]; 12422 u8 current_timestamp31_0[0x20]; 12423 u8 reserved_at_80[0x180]; 12424 }; 12425 12426 struct mlx5_ifc_host_params_context_bits { 12427 u8 host_number[0x8]; 12428 u8 reserved_at_8[0x5]; 12429 u8 host_pf_not_exist[0x1]; 12430 u8 reserved_at_14[0x1]; 12431 u8 host_pf_disabled[0x1]; 12432 u8 host_num_of_vfs[0x10]; 12433 12434 u8 host_total_vfs[0x10]; 12435 u8 host_pci_bus[0x10]; 12436 12437 u8 reserved_at_40[0x10]; 12438 u8 host_pci_device[0x10]; 12439 12440 u8 reserved_at_60[0x10]; 12441 u8 host_pci_function[0x10]; 12442 12443 u8 reserved_at_80[0x180]; 12444 }; 12445 12446 struct mlx5_ifc_query_esw_functions_in_bits { 12447 u8 opcode[0x10]; 12448 u8 reserved_at_10[0x10]; 12449 12450 u8 reserved_at_20[0x10]; 12451 u8 op_mod[0x10]; 12452 12453 u8 reserved_at_40[0x40]; 12454 }; 12455 12456 struct mlx5_ifc_query_esw_functions_out_bits { 12457 u8 status[0x8]; 12458 u8 reserved_at_8[0x18]; 12459 12460 u8 syndrome[0x20]; 12461 12462 u8 reserved_at_40[0x40]; 12463 12464 struct mlx5_ifc_host_params_context_bits host_params_context; 12465 12466 u8 reserved_at_280[0x180]; 12467 u8 host_sf_enable[][0x40]; 12468 }; 12469 12470 struct mlx5_ifc_sf_partition_bits { 12471 u8 reserved_at_0[0x10]; 12472 u8 log_num_sf[0x8]; 12473 u8 log_sf_bar_size[0x8]; 12474 }; 12475 12476 struct mlx5_ifc_query_sf_partitions_out_bits { 12477 u8 status[0x8]; 12478 u8 reserved_at_8[0x18]; 12479 12480 u8 syndrome[0x20]; 12481 12482 u8 reserved_at_40[0x18]; 12483 u8 num_sf_partitions[0x8]; 12484 12485 u8 reserved_at_60[0x20]; 12486 12487 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12488 }; 12489 12490 struct mlx5_ifc_query_sf_partitions_in_bits { 12491 u8 opcode[0x10]; 12492 u8 reserved_at_10[0x10]; 12493 12494 u8 reserved_at_20[0x10]; 12495 u8 op_mod[0x10]; 12496 12497 u8 reserved_at_40[0x40]; 12498 }; 12499 12500 struct mlx5_ifc_dealloc_sf_out_bits { 12501 u8 status[0x8]; 12502 u8 reserved_at_8[0x18]; 12503 12504 u8 syndrome[0x20]; 12505 12506 u8 reserved_at_40[0x40]; 12507 }; 12508 12509 struct mlx5_ifc_dealloc_sf_in_bits { 12510 u8 opcode[0x10]; 12511 u8 reserved_at_10[0x10]; 12512 12513 u8 reserved_at_20[0x10]; 12514 u8 op_mod[0x10]; 12515 12516 u8 reserved_at_40[0x10]; 12517 u8 function_id[0x10]; 12518 12519 u8 reserved_at_60[0x20]; 12520 }; 12521 12522 struct mlx5_ifc_alloc_sf_out_bits { 12523 u8 status[0x8]; 12524 u8 reserved_at_8[0x18]; 12525 12526 u8 syndrome[0x20]; 12527 12528 u8 reserved_at_40[0x40]; 12529 }; 12530 12531 struct mlx5_ifc_alloc_sf_in_bits { 12532 u8 opcode[0x10]; 12533 u8 reserved_at_10[0x10]; 12534 12535 u8 reserved_at_20[0x10]; 12536 u8 op_mod[0x10]; 12537 12538 u8 reserved_at_40[0x10]; 12539 u8 function_id[0x10]; 12540 12541 u8 reserved_at_60[0x20]; 12542 }; 12543 12544 struct mlx5_ifc_affiliated_event_header_bits { 12545 u8 reserved_at_0[0x10]; 12546 u8 obj_type[0x10]; 12547 12548 u8 obj_id[0x20]; 12549 }; 12550 12551 enum { 12552 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12553 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12554 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12555 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12556 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12557 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12558 MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53, 12559 MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58, 12560 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12561 }; 12562 12563 enum { 12564 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 12565 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY), 12566 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 12567 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC), 12568 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = 12569 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER), 12570 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 12571 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO), 12572 }; 12573 12574 enum { 12575 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL = 12576 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40), 12577 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 12578 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40), 12579 }; 12580 12581 enum { 12582 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12583 }; 12584 12585 enum { 12586 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12587 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12588 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12589 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12590 }; 12591 12592 enum { 12593 MLX5_IPSEC_ASO_MODE = 0x0, 12594 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12595 MLX5_IPSEC_ASO_INC_SN = 0x2, 12596 }; 12597 12598 enum { 12599 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12600 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12601 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12602 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12603 }; 12604 12605 struct mlx5_ifc_ipsec_aso_bits { 12606 u8 valid[0x1]; 12607 u8 reserved_at_201[0x1]; 12608 u8 mode[0x2]; 12609 u8 window_sz[0x2]; 12610 u8 soft_lft_arm[0x1]; 12611 u8 hard_lft_arm[0x1]; 12612 u8 remove_flow_enable[0x1]; 12613 u8 esn_event_arm[0x1]; 12614 u8 reserved_at_20a[0x16]; 12615 12616 u8 remove_flow_pkt_cnt[0x20]; 12617 12618 u8 remove_flow_soft_lft[0x20]; 12619 12620 u8 reserved_at_260[0x80]; 12621 12622 u8 mode_parameter[0x20]; 12623 12624 u8 replay_protection_window[0x100]; 12625 }; 12626 12627 struct mlx5_ifc_ipsec_obj_bits { 12628 u8 modify_field_select[0x40]; 12629 u8 full_offload[0x1]; 12630 u8 reserved_at_41[0x1]; 12631 u8 esn_en[0x1]; 12632 u8 esn_overlap[0x1]; 12633 u8 reserved_at_44[0x2]; 12634 u8 icv_length[0x2]; 12635 u8 reserved_at_48[0x4]; 12636 u8 aso_return_reg[0x4]; 12637 u8 reserved_at_50[0x10]; 12638 12639 u8 esn_msb[0x20]; 12640 12641 u8 reserved_at_80[0x8]; 12642 u8 dekn[0x18]; 12643 12644 u8 salt[0x20]; 12645 12646 u8 implicit_iv[0x40]; 12647 12648 u8 reserved_at_100[0x8]; 12649 u8 ipsec_aso_access_pd[0x18]; 12650 u8 reserved_at_120[0xe0]; 12651 12652 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12653 }; 12654 12655 struct mlx5_ifc_create_ipsec_obj_in_bits { 12656 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12657 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12658 }; 12659 12660 enum { 12661 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12662 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12663 }; 12664 12665 struct mlx5_ifc_query_ipsec_obj_out_bits { 12666 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12667 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12668 }; 12669 12670 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12671 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12672 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12673 }; 12674 12675 enum { 12676 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12677 }; 12678 12679 enum { 12680 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12681 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12682 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12683 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12684 }; 12685 12686 #define MLX5_MACSEC_ASO_INC_SN 0x2 12687 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12688 12689 struct mlx5_ifc_macsec_aso_bits { 12690 u8 valid[0x1]; 12691 u8 reserved_at_1[0x1]; 12692 u8 mode[0x2]; 12693 u8 window_size[0x2]; 12694 u8 soft_lifetime_arm[0x1]; 12695 u8 hard_lifetime_arm[0x1]; 12696 u8 remove_flow_enable[0x1]; 12697 u8 epn_event_arm[0x1]; 12698 u8 reserved_at_a[0x16]; 12699 12700 u8 remove_flow_packet_count[0x20]; 12701 12702 u8 remove_flow_soft_lifetime[0x20]; 12703 12704 u8 reserved_at_60[0x80]; 12705 12706 u8 mode_parameter[0x20]; 12707 12708 u8 replay_protection_window[8][0x20]; 12709 }; 12710 12711 struct mlx5_ifc_macsec_offload_obj_bits { 12712 u8 modify_field_select[0x40]; 12713 12714 u8 confidentiality_en[0x1]; 12715 u8 reserved_at_41[0x1]; 12716 u8 epn_en[0x1]; 12717 u8 epn_overlap[0x1]; 12718 u8 reserved_at_44[0x2]; 12719 u8 confidentiality_offset[0x2]; 12720 u8 reserved_at_48[0x4]; 12721 u8 aso_return_reg[0x4]; 12722 u8 reserved_at_50[0x10]; 12723 12724 u8 epn_msb[0x20]; 12725 12726 u8 reserved_at_80[0x8]; 12727 u8 dekn[0x18]; 12728 12729 u8 reserved_at_a0[0x20]; 12730 12731 u8 sci[0x40]; 12732 12733 u8 reserved_at_100[0x8]; 12734 u8 macsec_aso_access_pd[0x18]; 12735 12736 u8 reserved_at_120[0x60]; 12737 12738 u8 salt[3][0x20]; 12739 12740 u8 reserved_at_1e0[0x20]; 12741 12742 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12743 }; 12744 12745 struct mlx5_ifc_create_macsec_obj_in_bits { 12746 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12747 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12748 }; 12749 12750 struct mlx5_ifc_modify_macsec_obj_in_bits { 12751 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12752 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12753 }; 12754 12755 enum { 12756 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12757 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12758 }; 12759 12760 struct mlx5_ifc_query_macsec_obj_out_bits { 12761 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12762 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12763 }; 12764 12765 struct mlx5_ifc_wrapped_dek_bits { 12766 u8 gcm_iv[0x60]; 12767 12768 u8 reserved_at_60[0x20]; 12769 12770 u8 const0[0x1]; 12771 u8 key_size[0x1]; 12772 u8 reserved_at_82[0x2]; 12773 u8 key2_invalid[0x1]; 12774 u8 reserved_at_85[0x3]; 12775 u8 pd[0x18]; 12776 12777 u8 key_purpose[0x5]; 12778 u8 reserved_at_a5[0x13]; 12779 u8 kek_id[0x8]; 12780 12781 u8 reserved_at_c0[0x40]; 12782 12783 u8 key1[0x8][0x20]; 12784 12785 u8 key2[0x8][0x20]; 12786 12787 u8 reserved_at_300[0x40]; 12788 12789 u8 const1[0x1]; 12790 u8 reserved_at_341[0x1f]; 12791 12792 u8 reserved_at_360[0x20]; 12793 12794 u8 auth_tag[0x80]; 12795 }; 12796 12797 struct mlx5_ifc_encryption_key_obj_bits { 12798 u8 modify_field_select[0x40]; 12799 12800 u8 state[0x8]; 12801 u8 sw_wrapped[0x1]; 12802 u8 reserved_at_49[0xb]; 12803 u8 key_size[0x4]; 12804 u8 reserved_at_58[0x4]; 12805 u8 key_purpose[0x4]; 12806 12807 u8 reserved_at_60[0x8]; 12808 u8 pd[0x18]; 12809 12810 u8 reserved_at_80[0x100]; 12811 12812 u8 opaque[0x40]; 12813 12814 u8 reserved_at_1c0[0x40]; 12815 12816 u8 key[8][0x80]; 12817 12818 u8 sw_wrapped_dek[8][0x80]; 12819 12820 u8 reserved_at_a00[0x600]; 12821 }; 12822 12823 struct mlx5_ifc_create_encryption_key_in_bits { 12824 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12825 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12826 }; 12827 12828 struct mlx5_ifc_modify_encryption_key_in_bits { 12829 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12830 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12831 }; 12832 12833 enum { 12834 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12835 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12836 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12837 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12838 }; 12839 12840 struct mlx5_ifc_flow_meter_parameters_bits { 12841 u8 valid[0x1]; 12842 u8 bucket_overflow[0x1]; 12843 u8 start_color[0x2]; 12844 u8 both_buckets_on_green[0x1]; 12845 u8 reserved_at_5[0x1]; 12846 u8 meter_mode[0x2]; 12847 u8 reserved_at_8[0x18]; 12848 12849 u8 reserved_at_20[0x20]; 12850 12851 u8 reserved_at_40[0x3]; 12852 u8 cbs_exponent[0x5]; 12853 u8 cbs_mantissa[0x8]; 12854 u8 reserved_at_50[0x3]; 12855 u8 cir_exponent[0x5]; 12856 u8 cir_mantissa[0x8]; 12857 12858 u8 reserved_at_60[0x20]; 12859 12860 u8 reserved_at_80[0x3]; 12861 u8 ebs_exponent[0x5]; 12862 u8 ebs_mantissa[0x8]; 12863 u8 reserved_at_90[0x3]; 12864 u8 eir_exponent[0x5]; 12865 u8 eir_mantissa[0x8]; 12866 12867 u8 reserved_at_a0[0x60]; 12868 }; 12869 12870 struct mlx5_ifc_flow_meter_aso_obj_bits { 12871 u8 modify_field_select[0x40]; 12872 12873 u8 reserved_at_40[0x40]; 12874 12875 u8 reserved_at_80[0x8]; 12876 u8 meter_aso_access_pd[0x18]; 12877 12878 u8 reserved_at_a0[0x160]; 12879 12880 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12881 }; 12882 12883 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12884 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12885 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12886 }; 12887 12888 struct mlx5_ifc_int_kek_obj_bits { 12889 u8 modify_field_select[0x40]; 12890 12891 u8 state[0x8]; 12892 u8 auto_gen[0x1]; 12893 u8 reserved_at_49[0xb]; 12894 u8 key_size[0x4]; 12895 u8 reserved_at_58[0x8]; 12896 12897 u8 reserved_at_60[0x8]; 12898 u8 pd[0x18]; 12899 12900 u8 reserved_at_80[0x180]; 12901 u8 key[8][0x80]; 12902 12903 u8 reserved_at_600[0x200]; 12904 }; 12905 12906 struct mlx5_ifc_create_int_kek_obj_in_bits { 12907 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12908 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12909 }; 12910 12911 struct mlx5_ifc_create_int_kek_obj_out_bits { 12912 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12913 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12914 }; 12915 12916 struct mlx5_ifc_sampler_obj_bits { 12917 u8 modify_field_select[0x40]; 12918 12919 u8 table_type[0x8]; 12920 u8 level[0x8]; 12921 u8 reserved_at_50[0xf]; 12922 u8 ignore_flow_level[0x1]; 12923 12924 u8 sample_ratio[0x20]; 12925 12926 u8 reserved_at_80[0x8]; 12927 u8 sample_table_id[0x18]; 12928 12929 u8 reserved_at_a0[0x8]; 12930 u8 default_table_id[0x18]; 12931 12932 u8 sw_steering_icm_address_rx[0x40]; 12933 u8 sw_steering_icm_address_tx[0x40]; 12934 12935 u8 reserved_at_140[0xa0]; 12936 }; 12937 12938 struct mlx5_ifc_create_sampler_obj_in_bits { 12939 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12940 struct mlx5_ifc_sampler_obj_bits sampler_object; 12941 }; 12942 12943 struct mlx5_ifc_query_sampler_obj_out_bits { 12944 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12945 struct mlx5_ifc_sampler_obj_bits sampler_object; 12946 }; 12947 12948 enum { 12949 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12950 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12951 }; 12952 12953 enum { 12954 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12955 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12956 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12957 }; 12958 12959 struct mlx5_ifc_tls_static_params_bits { 12960 u8 const_2[0x2]; 12961 u8 tls_version[0x4]; 12962 u8 const_1[0x2]; 12963 u8 reserved_at_8[0x14]; 12964 u8 encryption_standard[0x4]; 12965 12966 u8 reserved_at_20[0x20]; 12967 12968 u8 initial_record_number[0x40]; 12969 12970 u8 resync_tcp_sn[0x20]; 12971 12972 u8 gcm_iv[0x20]; 12973 12974 u8 implicit_iv[0x40]; 12975 12976 u8 reserved_at_100[0x8]; 12977 u8 dek_index[0x18]; 12978 12979 u8 reserved_at_120[0xe0]; 12980 }; 12981 12982 struct mlx5_ifc_tls_progress_params_bits { 12983 u8 next_record_tcp_sn[0x20]; 12984 12985 u8 hw_resync_tcp_sn[0x20]; 12986 12987 u8 record_tracker_state[0x2]; 12988 u8 auth_state[0x2]; 12989 u8 reserved_at_44[0x4]; 12990 u8 hw_offset_record_number[0x18]; 12991 }; 12992 12993 enum { 12994 MLX5_MTT_PERM_READ = 1 << 0, 12995 MLX5_MTT_PERM_WRITE = 1 << 1, 12996 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12997 }; 12998 12999 enum { 13000 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 13001 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 13002 }; 13003 13004 struct mlx5_ifc_suspend_vhca_in_bits { 13005 u8 opcode[0x10]; 13006 u8 uid[0x10]; 13007 13008 u8 reserved_at_20[0x10]; 13009 u8 op_mod[0x10]; 13010 13011 u8 reserved_at_40[0x10]; 13012 u8 vhca_id[0x10]; 13013 13014 u8 reserved_at_60[0x20]; 13015 }; 13016 13017 struct mlx5_ifc_suspend_vhca_out_bits { 13018 u8 status[0x8]; 13019 u8 reserved_at_8[0x18]; 13020 13021 u8 syndrome[0x20]; 13022 13023 u8 reserved_at_40[0x40]; 13024 }; 13025 13026 enum { 13027 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 13028 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 13029 }; 13030 13031 struct mlx5_ifc_resume_vhca_in_bits { 13032 u8 opcode[0x10]; 13033 u8 uid[0x10]; 13034 13035 u8 reserved_at_20[0x10]; 13036 u8 op_mod[0x10]; 13037 13038 u8 reserved_at_40[0x10]; 13039 u8 vhca_id[0x10]; 13040 13041 u8 reserved_at_60[0x20]; 13042 }; 13043 13044 struct mlx5_ifc_resume_vhca_out_bits { 13045 u8 status[0x8]; 13046 u8 reserved_at_8[0x18]; 13047 13048 u8 syndrome[0x20]; 13049 13050 u8 reserved_at_40[0x40]; 13051 }; 13052 13053 struct mlx5_ifc_query_vhca_migration_state_in_bits { 13054 u8 opcode[0x10]; 13055 u8 uid[0x10]; 13056 13057 u8 reserved_at_20[0x10]; 13058 u8 op_mod[0x10]; 13059 13060 u8 incremental[0x1]; 13061 u8 chunk[0x1]; 13062 u8 reserved_at_42[0xe]; 13063 u8 vhca_id[0x10]; 13064 13065 u8 reserved_at_60[0x20]; 13066 }; 13067 13068 struct mlx5_ifc_query_vhca_migration_state_out_bits { 13069 u8 status[0x8]; 13070 u8 reserved_at_8[0x18]; 13071 13072 u8 syndrome[0x20]; 13073 13074 u8 reserved_at_40[0x40]; 13075 13076 u8 required_umem_size[0x20]; 13077 13078 u8 reserved_at_a0[0x20]; 13079 13080 u8 remaining_total_size[0x40]; 13081 13082 u8 reserved_at_100[0x100]; 13083 }; 13084 13085 struct mlx5_ifc_save_vhca_state_in_bits { 13086 u8 opcode[0x10]; 13087 u8 uid[0x10]; 13088 13089 u8 reserved_at_20[0x10]; 13090 u8 op_mod[0x10]; 13091 13092 u8 incremental[0x1]; 13093 u8 set_track[0x1]; 13094 u8 reserved_at_42[0xe]; 13095 u8 vhca_id[0x10]; 13096 13097 u8 reserved_at_60[0x20]; 13098 13099 u8 va[0x40]; 13100 13101 u8 mkey[0x20]; 13102 13103 u8 size[0x20]; 13104 }; 13105 13106 struct mlx5_ifc_save_vhca_state_out_bits { 13107 u8 status[0x8]; 13108 u8 reserved_at_8[0x18]; 13109 13110 u8 syndrome[0x20]; 13111 13112 u8 actual_image_size[0x20]; 13113 13114 u8 next_required_umem_size[0x20]; 13115 }; 13116 13117 struct mlx5_ifc_load_vhca_state_in_bits { 13118 u8 opcode[0x10]; 13119 u8 uid[0x10]; 13120 13121 u8 reserved_at_20[0x10]; 13122 u8 op_mod[0x10]; 13123 13124 u8 reserved_at_40[0x10]; 13125 u8 vhca_id[0x10]; 13126 13127 u8 reserved_at_60[0x20]; 13128 13129 u8 va[0x40]; 13130 13131 u8 mkey[0x20]; 13132 13133 u8 size[0x20]; 13134 }; 13135 13136 struct mlx5_ifc_load_vhca_state_out_bits { 13137 u8 status[0x8]; 13138 u8 reserved_at_8[0x18]; 13139 13140 u8 syndrome[0x20]; 13141 13142 u8 reserved_at_40[0x40]; 13143 }; 13144 13145 struct mlx5_ifc_adv_rdma_cap_bits { 13146 u8 rdma_transport_manager[0x1]; 13147 u8 rdma_transport_manager_other_eswitch[0x1]; 13148 u8 reserved_at_2[0x1e]; 13149 13150 u8 rcx_type[0x8]; 13151 u8 reserved_at_28[0x2]; 13152 u8 ps_entry_log_max_value[0x6]; 13153 u8 reserved_at_30[0x6]; 13154 u8 qp_max_ps_num_entry[0xa]; 13155 13156 u8 mp_max_num_queues[0x8]; 13157 u8 ps_user_context_max_log_size[0x8]; 13158 u8 message_based_qp_and_striding_wq[0x8]; 13159 u8 reserved_at_58[0x8]; 13160 13161 u8 max_receive_send_message_size_stride[0x10]; 13162 u8 reserved_at_70[0x10]; 13163 13164 u8 max_receive_send_message_size_byte[0x20]; 13165 13166 u8 reserved_at_a0[0x160]; 13167 13168 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties; 13169 13170 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties; 13171 13172 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2; 13173 13174 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2; 13175 13176 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2; 13177 13178 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2; 13179 13180 u8 reserved_at_800[0x3800]; 13181 }; 13182 13183 struct mlx5_ifc_adv_virtualization_cap_bits { 13184 u8 reserved_at_0[0x3]; 13185 u8 pg_track_log_max_num[0x5]; 13186 u8 pg_track_max_num_range[0x8]; 13187 u8 pg_track_log_min_addr_space[0x8]; 13188 u8 pg_track_log_max_addr_space[0x8]; 13189 13190 u8 reserved_at_20[0x3]; 13191 u8 pg_track_log_min_msg_size[0x5]; 13192 u8 reserved_at_28[0x3]; 13193 u8 pg_track_log_max_msg_size[0x5]; 13194 u8 reserved_at_30[0x3]; 13195 u8 pg_track_log_min_page_size[0x5]; 13196 u8 reserved_at_38[0x3]; 13197 u8 pg_track_log_max_page_size[0x5]; 13198 13199 u8 reserved_at_40[0x7c0]; 13200 }; 13201 13202 struct mlx5_ifc_page_track_report_entry_bits { 13203 u8 dirty_address_high[0x20]; 13204 13205 u8 dirty_address_low[0x20]; 13206 }; 13207 13208 enum { 13209 MLX5_PAGE_TRACK_STATE_TRACKING, 13210 MLX5_PAGE_TRACK_STATE_REPORTING, 13211 MLX5_PAGE_TRACK_STATE_ERROR, 13212 }; 13213 13214 struct mlx5_ifc_page_track_range_bits { 13215 u8 start_address[0x40]; 13216 13217 u8 length[0x40]; 13218 }; 13219 13220 struct mlx5_ifc_page_track_bits { 13221 u8 modify_field_select[0x40]; 13222 13223 u8 reserved_at_40[0x10]; 13224 u8 vhca_id[0x10]; 13225 13226 u8 reserved_at_60[0x20]; 13227 13228 u8 state[0x4]; 13229 u8 track_type[0x4]; 13230 u8 log_addr_space_size[0x8]; 13231 u8 reserved_at_90[0x3]; 13232 u8 log_page_size[0x5]; 13233 u8 reserved_at_98[0x3]; 13234 u8 log_msg_size[0x5]; 13235 13236 u8 reserved_at_a0[0x8]; 13237 u8 reporting_qpn[0x18]; 13238 13239 u8 reserved_at_c0[0x18]; 13240 u8 num_ranges[0x8]; 13241 13242 u8 reserved_at_e0[0x20]; 13243 13244 u8 range_start_address[0x40]; 13245 13246 u8 length[0x40]; 13247 13248 struct mlx5_ifc_page_track_range_bits track_range[0]; 13249 }; 13250 13251 struct mlx5_ifc_create_page_track_obj_in_bits { 13252 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13253 struct mlx5_ifc_page_track_bits obj_context; 13254 }; 13255 13256 struct mlx5_ifc_modify_page_track_obj_in_bits { 13257 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13258 struct mlx5_ifc_page_track_bits obj_context; 13259 }; 13260 13261 struct mlx5_ifc_query_page_track_obj_out_bits { 13262 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13263 struct mlx5_ifc_page_track_bits obj_context; 13264 }; 13265 13266 struct mlx5_ifc_msecq_reg_bits { 13267 u8 reserved_at_0[0x20]; 13268 13269 u8 reserved_at_20[0x12]; 13270 u8 network_option[0x2]; 13271 u8 local_ssm_code[0x4]; 13272 u8 local_enhanced_ssm_code[0x8]; 13273 13274 u8 local_clock_identity[0x40]; 13275 13276 u8 reserved_at_80[0x180]; 13277 }; 13278 13279 enum { 13280 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 13281 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 13282 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 13283 }; 13284 13285 enum mlx5_msees_admin_status { 13286 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 13287 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 13288 }; 13289 13290 enum mlx5_msees_oper_status { 13291 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 13292 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 13293 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 13294 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 13295 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 13296 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 13297 }; 13298 13299 enum mlx5_msees_failure_reason { 13300 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 13301 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 13302 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 13303 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 13304 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 13305 }; 13306 13307 struct mlx5_ifc_msees_reg_bits { 13308 u8 reserved_at_0[0x8]; 13309 u8 local_port[0x8]; 13310 u8 pnat[0x2]; 13311 u8 lp_msb[0x2]; 13312 u8 reserved_at_14[0xc]; 13313 13314 u8 field_select[0x20]; 13315 13316 u8 admin_status[0x4]; 13317 u8 oper_status[0x4]; 13318 u8 ho_acq[0x1]; 13319 u8 reserved_at_49[0xc]; 13320 u8 admin_freq_measure[0x1]; 13321 u8 oper_freq_measure[0x1]; 13322 u8 failure_reason[0x9]; 13323 13324 u8 frequency_diff[0x20]; 13325 13326 u8 reserved_at_80[0x180]; 13327 }; 13328 13329 struct mlx5_ifc_mrtcq_reg_bits { 13330 u8 reserved_at_0[0x40]; 13331 13332 u8 rt_clock_identity[0x40]; 13333 13334 u8 reserved_at_80[0x180]; 13335 }; 13336 13337 struct mlx5_ifc_pcie_cong_event_obj_bits { 13338 u8 modify_select_field[0x40]; 13339 13340 u8 inbound_event_en[0x1]; 13341 u8 outbound_event_en[0x1]; 13342 u8 reserved_at_42[0x1e]; 13343 13344 u8 reserved_at_60[0x1]; 13345 u8 inbound_cong_state[0x3]; 13346 u8 reserved_at_64[0x1]; 13347 u8 outbound_cong_state[0x3]; 13348 u8 reserved_at_68[0x18]; 13349 13350 u8 inbound_cong_low_threshold[0x10]; 13351 u8 inbound_cong_high_threshold[0x10]; 13352 13353 u8 outbound_cong_low_threshold[0x10]; 13354 u8 outbound_cong_high_threshold[0x10]; 13355 13356 u8 reserved_at_e0[0x340]; 13357 }; 13358 13359 struct mlx5_ifc_pcie_cong_event_cmd_in_bits { 13360 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13361 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13362 }; 13363 13364 struct mlx5_ifc_pcie_cong_event_cmd_out_bits { 13365 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 13366 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13367 }; 13368 13369 enum mlx5e_pcie_cong_event_mod_field { 13370 MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0), 13371 MLX5_PCIE_CONG_EVENT_MOD_THRESH = BIT(2), 13372 }; 13373 13374 #endif /* MLX5_IFC_H */ 13375