xref: /linux/drivers/atm/midway.h (revision 498495dba268b20e8eadd7fe93c140c68b6cc9d2)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* drivers/atm/midway.h - Efficient Networks Midway (SAR) description */
3 
4 /* Written 1995-1999 by Werner Almesberger, EPFL LRC/ICA */
5 
6 
7 #ifndef DRIVERS_ATM_MIDWAY_H
8 #define DRIVERS_ATM_MIDWAY_H
9 
10 
11 #define NR_VCI		1024		/* number of VCIs */
12 #define NR_VCI_LD	10		/* log2(NR_VCI) */
13 #define NR_DMA_RX	512		/* RX DMA queue entries */
14 #define NR_DMA_TX	512		/* TX DMA queue entries */
15 #define NR_SERVICE	NR_VCI		/* service list size */
16 #define NR_CHAN		8		/* number of TX channels */
17 #define TS_CLOCK	25000000	/* traffic shaper clock (cell/sec) */
18 
19 #define MAP_MAX_SIZE	0x00400000	/* memory window for max config */
20 #define EPROM_SIZE	0x00010000
21 #define	MEM_VALID	0xffc00000	/* mask base address with this */
22 #define PHY_BASE	0x00020000	/* offset of PHY register are */
23 #define REG_BASE	0x00040000	/* offset of Midway register area */
24 #define RAM_BASE	0x00200000	/* offset of RAM area */
25 #define RAM_INCREMENT	0x00020000	/* probe for RAM every 128kB */
26 
27 #define MID_VCI_BASE	RAM_BASE
28 #define MID_DMA_RX_BASE	(MID_VCI_BASE+NR_VCI*16)
29 #define MID_DMA_TX_BASE	(MID_DMA_RX_BASE+NR_DMA_RX*8)
30 #define MID_SERVICE_BASE (MID_DMA_TX_BASE+NR_DMA_TX*8)
31 #define MID_FREE_BASE	(MID_SERVICE_BASE+NR_SERVICE*4)
32 
33 #define MAC_LEN 6 /* atm.h */
34 
35 #define MID_MIN_BUF_SIZE (1024)		/*   1 kB is minimum */
36 #define MID_MAX_BUF_SIZE (128*1024)	/* 128 kB is maximum */
37 
38 #define RX_DESCR_SIZE	1		/* RX PDU descr is 1 longword */
39 #define TX_DESCR_SIZE	2		/* TX PDU descr is 2 longwords */
40 #define AAL5_TRAILER	(ATM_AAL5_TRAILER/4) /* AAL5 trailer is 2 longwords */
41 
42 #define TX_GAP		8		/* TX buffer gap (words) */
43 
44 /*
45  * Midway Reset/ID
46  *
47  * All values read-only. Writing to this register resets Midway chip.
48  */
49 
50 #define MID_RES_ID_MCON	0x00		/* Midway Reset/ID */
51 
52 #define MID_ID		0xf0000000	/* Midway version */
53 #define MID_SHIFT	24
54 #define MID_MOTHER_ID	0x00000700	/* mother board id */
55 #define MID_MOTHER_SHIFT 8
56 #define MID_CON_TI	0x00000080	/* 0: normal ctrl; 1: SABRE */
57 #define MID_CON_SUNI	0x00000040	/* 0: UTOPIA; 1: SUNI */
58 #define MID_CON_V6	0x00000020	/* 0: non-pipel UTOPIA (required iff
59 					   !CON_SUNI; 1: UTOPIA */
60 #define DAUGHTER_ID	0x0000001f	/* daughter board id */
61 
62 /*
63  * Interrupt Status Acknowledge, Interrupt Status & Interrupt Enable
64  */
65 
66 #define MID_ISA		0x01		/* Interrupt Status Acknowledge */
67 #define MID_IS		0x02		/* Interrupt Status */
68 #define MID_IE		0x03		/* Interrupt Enable */
69 
70 #define MID_TX_COMPLETE_7 0x00010000	/* channel N completed a PDU */
71 #define MID_TX_COMPLETE_6 0x00008000	/* transmission */
72 #define MID_TX_COMPLETE_5 0x00004000
73 #define MID_TX_COMPLETE_4 0x00002000
74 #define MID_TX_COMPLETE_3 0x00001000
75 #define MID_TX_COMPLETE_2 0x00000800
76 #define MID_TX_COMPLETE_1 0x00000400
77 #define MID_TX_COMPLETE_0 0x00000200
78 #define MID_TX_COMPLETE	0x0001fe00	/* any TX */
79 #define MID_TX_DMA_OVFL	0x00000100	/* DMA to adapter overflow */
80 #define MID_TX_IDENT_MISM 0x00000080	/* TX: ident mismatch => halted */
81 #define MID_DMA_LERR_ACK 0x00000040	/* LERR - SBus ? */
82 #define MID_DMA_ERR_ACK	0x00000020	/* DMA error */
83 #define	MID_RX_DMA_COMPLETE 0x00000010	/* DMA to host done */
84 #define MID_TX_DMA_COMPLETE 0x00000008	/* DMA from host done */
85 #define MID_SERVICE	0x00000004	/* something in service list */
86 #define MID_SUNI_INT	0x00000002	/* interrupt from SUNI */
87 #define MID_STAT_OVFL	0x00000001	/* statistics overflow */
88 
89 /*
90  * Master Control/Status
91  */
92 
93 #define MID_MC_S	0x04
94 
95 #define MID_INT_SELECT	0x000001C0	/* Interrupt level (000: off) */
96 #define MID_INT_SEL_SHIFT 6
97 #define	MID_TX_LOCK_MODE 0x00000020	/* 0: streaming; 1: TX ovfl->lock */
98 #define MID_DMA_ENABLE	0x00000010	/* R: 0: disable; 1: enable
99 					   W: 0: no change; 1: enable */
100 #define MID_TX_ENABLE	0x00000008	/* R: 0: TX disabled; 1: enabled
101 					   W: 0: no change; 1: enable */
102 #define MID_RX_ENABLE	0x00000004	/* like TX */
103 #define MID_WAIT_1MS	0x00000002	/* R: 0: timer not running; 1: running
104 					   W: 0: no change; 1: no interrupts
105 							       for 1 ms */
106 #define MID_WAIT_500US	0x00000001	/* like WAIT_1MS, but 0.5 ms */
107 
108 /*
109  * Statistics
110  *
111  * Cleared when reading.
112  */
113 
114 #define MID_STAT		0x05
115 
116 #define MID_VCI_TRASH	0xFFFF0000	/* trashed cells because of VCI mode */
117 #define MID_VCI_TRASH_SHIFT 16
118 #define MID_OVFL_TRASH	0x0000FFFF	/* trashed cells because of overflow */
119 
120 /*
121  * Address registers
122  */
123 
124 #define MID_SERV_WRITE	0x06	/* free pos in service area (R, 10 bits) */
125 #define MID_DMA_ADDR	0x07	/* virtual DMA address (R, 32 bits) */
126 #define MID_DMA_WR_RX	0x08	/* (RW, 9 bits) */
127 #define MID_DMA_RD_RX	0x09
128 #define MID_DMA_WR_TX	0x0A
129 #define MID_DMA_RD_TX	0x0B
130 
131 /*
132  * Transmit Place Registers (0x10+4*channel)
133  */
134 
135 #define MID_TX_PLACE(c)	(0x10+4*(c))
136 
137 #define MID_SIZE	0x00003800	/* size, N*256 x 32 bit */
138 #define MID_SIZE_SHIFT	11
139 #define MID_LOCATION	0x000007FF	/* location in adapter memory (word) */
140 
141 #define MID_LOC_SKIP	8		/* 8 bits of location are always zero
142 					   (applies to all uses of location) */
143 
144 /*
145  * Transmit ReadPtr Registers (0x11+4*channel)
146  */
147 
148 #define MID_TX_RDPTR(c)	(0x11+4*(c))
149 
150 #define MID_READ_PTR	0x00007FFF	/* next word for PHY */
151 
152 /*
153  * Transmit DescrStart Registers (0x12+4*channel)
154  */
155 
156 #define MID_TX_DESCRSTART(c) (0x12+4*(c))
157 
158 #define MID_DESCR_START	0x00007FFF	/* seg buffer being DMAed */
159 
160 #define ENI155_MAGIC	0xa54b872d
161 
162 struct midway_eprom {
163 	unsigned char mac[MAC_LEN],inv_mac[MAC_LEN];
164 	unsigned char pad[36];
165 	u32 serial,inv_serial;
166 	u32 magic,inv_magic;
167 };
168 
169 
170 /*
171  * VCI table entry
172  */
173 
174 #define MID_VCI_IN_SERVICE	0x00000001	/* set if VCI is currently in
175 						   service list */
176 #define MID_VCI_SIZE		0x00038000	/* reassembly buffer size,
177 						   2*<size> kB */
178 #define MID_VCI_SIZE_SHIFT	15
179 #define MID_VCI_LOCATION	0x1ffc0000	/* buffer location */
180 #define MID_VCI_LOCATION_SHIFT	18
181 #define MID_VCI_PTI_MODE	0x20000000	/* 0: trash, 1: preserve */
182 #define MID_VCI_MODE		0xc0000000
183 #define MID_VCI_MODE_SHIFT	30
184 #define MID_VCI_READ		0x00007fff
185 #define MID_VCI_READ_SHIFT	0
186 #define MID_VCI_DESCR		0x7fff0000
187 #define MID_VCI_DESCR_SHIFT	16
188 #define MID_VCI_COUNT		0x000007ff
189 #define MID_VCI_COUNT_SHIFT	0
190 #define MID_VCI_STATE		0x0000c000
191 #define MID_VCI_STATE_SHIFT	14
192 #define MID_VCI_WRITE		0x7fff0000
193 #define MID_VCI_WRITE_SHIFT	16
194 
195 #define MID_MODE_TRASH	0
196 #define MID_MODE_RAW	1
197 #define MID_MODE_AAL5	2
198 
199 /*
200  * Reassembly buffer descriptor
201  */
202 
203 #define MID_RED_COUNT		0x000007ff
204 #define MID_RED_CRC_ERR		0x00000800
205 #define MID_RED_T		0x00001000
206 #define MID_RED_CE		0x00010000
207 #define MID_RED_CLP		0x01000000
208 #define MID_RED_IDEN		0xfe000000
209 #define MID_RED_SHIFT		25
210 
211 #define MID_RED_RX_ID		0x1b		/* constant identifier */
212 
213 /*
214  * Segmentation buffer descriptor
215  */
216 
217 #define MID_SEG_COUNT		MID_RED_COUNT
218 #define MID_SEG_RATE		0x01f80000
219 #define MID_SEG_RATE_SHIFT	19
220 #define MID_SEG_PR		0x06000000
221 #define MID_SEG_PR_SHIFT	25
222 #define MID_SEG_AAL5		0x08000000
223 #define MID_SEG_ID		0xf0000000
224 #define MID_SEG_ID_SHIFT	28
225 #define MID_SEG_MAX_RATE	63
226 
227 #define MID_SEG_CLP		0x00000001
228 #define MID_SEG_PTI		0x0000000e
229 #define MID_SEG_PTI_SHIFT	1
230 #define MID_SEG_VCI		0x00003ff0
231 #define MID_SEG_VCI_SHIFT	4
232 
233 #define MID_SEG_TX_ID		0xb		/* constant identifier */
234 
235 /*
236  * DMA entry
237  */
238 
239 #define MID_DMA_COUNT		0xffff0000
240 #define MID_DMA_COUNT_SHIFT	16
241 #define MID_DMA_END		0x00000020
242 #define MID_DMA_TYPE		0x0000000f
243 
244 #define MID_DT_JK	0x3
245 #define MID_DT_WORD	0x0
246 #define MID_DT_2W	0x7
247 #define MID_DT_4W	0x4
248 #define MID_DT_8W	0x5
249 #define MID_DT_16W	0x6
250 #define MID_DT_2WM	0xf
251 #define MID_DT_4WM	0xc
252 #define MID_DT_8WM	0xd
253 #define MID_DT_16WM	0xe
254 
255 /* only for RX*/
256 #define MID_DMA_VCI		0x0000ffc0
257 #define	MID_DMA_VCI_SHIFT	6
258 
259 /* only for TX */
260 #define MID_DMA_CHAN		0x000001c0
261 #define MID_DMA_CHAN_SHIFT	6
262 
263 #define MID_DT_BYTE	0x1
264 #define MID_DT_HWORD	0x2
265 
266 #endif
267