| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64MachineScheduler.cpp | 36 static bool mayOverlapWrite(const MachineInstr &MI0, const MachineInstr &MI1, in mayOverlapWrite()
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| H A D | AArch64CollectLOH.cpp | 285 const MachineInstr *MI1; ///< Second instruction involved in the LOH global() member
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsSizeReduction.cpp | 398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr()
464 MachineInstr *MI1 = Arguments->MI; in ReduceXWtoXWP() local
621 MachineInstr *MI1 = Arguments->MI; in ReduceMoveToMovep() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 272 bool VLIWPacketizerList::alias(const MachineInstr &MI1, in alias()
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| H A D | TargetInstrInfo.cpp | 429 const MachineInstr &MI1, in produceSameValue()
841 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
861 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86OptimizeLEAs.cpp | 397 int64_t X86OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, in getAddrDispShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 1822 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableVectorSibling() local
1851 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
2650 memOpsHaveSameBasePtr(const MachineInstr & MI1,ArrayRef<const MachineOperand * > BaseOps1,const MachineInstr & MI2,ArrayRef<const MachineOperand * > BaseOps2) memOpsHaveSameBasePtr() argument
3866 hasEqualFRM(const MachineInstr & MI1,const MachineInstr & MI2) hasEqualFRM() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.cpp | 104 bool GISelAddressing::aliasIsKnownForLoadStore(const MachineInstr &MI1, in aliasIsKnownForLoadStore()
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| H A D | CombinerHelper.cpp | 5683 static bool hasMoreUses(const MachineInstr &MI0, const MachineInstr &MI1, in hasMoreUses()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 264 MachineInstr &MI1 = *SU.getInstr(); in apply() local
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| H A D | HexagonVLIWPacketizer.cpp | 967 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements()
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| H A D | HexagonInstrInfo.cpp | 2687 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1, in isToBeScheduledASAP()
3063 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1, in addLatencyToSchedule()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRExpandPseudoInsts.cpp | 1646 auto MI1 = in expandLSLW4Rd() local
1732 auto MI1 = in expandLSLW12Rd() local
1844 auto MI1 = in expandLSRW4Rd() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 473 MachineInstr *MI1 = *I1; in hoistAndMergeSGPRInits() local
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| H A D | GCNHazardRecognizer.cpp | 2225 const MachineInstr *MI1; in checkMAIHazards90A() local
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| H A D | SIInstrInfo.cpp | 518 static bool memOpsHaveSameBasePtr(const MachineInstr &MI1, in memOpsHaveSameBasePtr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 1862 const MachineInstr &MI1, in produceSameValue()
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