| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GenericMachineInstrs.h | 40 static bool classof(const MachineInstr *MI) { in classof()
74 static bool classof(const MachineInstr *MI) { in classof()
86 static bool classof(const MachineInstr *MI) { in classof()
116 static bool classof(const MachineInstr *MI) { in classof()
124 static bool classof(const MachineInstr *MI) { in classof()
133 static bool classof(const MachineInstr *MI) { in classof()
148 static bool classof(const MachineInstr *MI) { in classof()
156 static bool classof(const MachineInstr *MI) { in classof()
176 static bool classof(const MachineInstr *MI) { in classof()
192 static bool classof(const MachineInstr *MI) { in classof()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/ |
| H A D | M68kInstPrinter.h | 61 void printPCRelImm(const MCInst *MI, uint64_t Address, unsigned opNum, in printPCRelImm()
66 void printARI8Mem(const MCInst *MI, unsigned opNum, raw_ostream &O) { in printARI8Mem()
69 void printARI16Mem(const MCInst *MI, unsigned opNum, raw_ostream &O) { in printARI16Mem()
72 void printARI32Mem(const MCInst *MI, unsigned opNum, raw_ostream &O) { in printARI32Mem()
76 void printARIPI8Mem(const MCInst *MI, unsigned opNum, raw_ostream &O) { in printARIPI8Mem()
79 void printARIPI16Mem(const MCInst *MI, unsigned opNum, raw_ostream &O) { in printARIPI16Mem()
82 void printARIPI32Mem(const MCInst *MI, unsigned opNum, raw_ostream &O) { in printARIPI32Mem()
86 void printARIPD8Mem(const MCInst *MI, unsigned opNum, raw_ostream &O) { in printARIPD8Mem()
89 void printARIPD16Mem(const MCInst *MI, unsigned opNum, raw_ostream &O) { in printARIPD16Mem()
92 void printARIPD32Mem(const MCInst *MI, unsigned opNum, raw_ostream &O) { in printARIPD32Mem()
[all …]
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| H A D | M68kMemOperandPrinter.h | 27 void printARIMem(const InstTy *MI, unsigned OpNum, raw_ostream &O) { in printARIMem()
33 void printARIPIMem(const InstTy *MI, unsigned OpNum, raw_ostream &O) { in printARIPIMem()
39 void printARIPDMem(const InstTy *MI, unsigned OpNum, raw_ostream &O) { in printARIPDMem()
45 void printARIDMem(const InstTy *MI, unsigned OpNum, raw_ostream &O) { in printARIDMem()
53 void printARIIMem(const InstTy *MI, unsigned OpNum, raw_ostream &O) { in printARIIMem()
63 void printPCDMem(const InstTy *MI, uint64_t Address, unsigned OpNum, in printPCDMem()
70 void printPCIMem(const InstTy *MI, uint64_t Address, unsigned OpNum, in printPCIMem()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 318 inline int commuteOpcode(const MachineInstr &MI) const { in commuteOpcode()
408 static bool isSALU(const MachineInstr &MI) { in isSALU()
416 static bool isVALU(const MachineInstr &MI) { in isVALU()
424 static bool isImage(const MachineInstr &MI) { in isImage()
432 static bool isVMEM(const MachineInstr &MI) { in isVMEM()
440 static bool isSOP1(const MachineInstr &MI) { in isSOP1()
448 static bool isSOP2(const MachineInstr &MI) { in isSOP2()
456 static bool isSOPC(const MachineInstr &MI) { in isSOPC()
464 static bool isSOPK(const MachineInstr &MI) { in isSOPK()
472 static bool isSOPP(const MachineInstr &MI) { in isSOPP()
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| H A D | GCNHazardRecognizer.cpp | 76 void GCNHazardRecognizer::EmitInstruction(MachineInstr *MI) { in EmitInstruction()
123 static bool isXDL(const GCNSubtarget &ST, const MachineInstr &MI) { in isXDL()
139 const MachineInstr &MI) { in isSendMsgTraceDataOrGDS()
164 static bool isPermlane(const MachineInstr &MI) { in isPermlane()
173 static bool isLdsDma(const MachineInstr &MI) { in isLdsDma()
186 MachineInstr *MI = SU->getInstr(); in getHazardType() local
263 static void insertNoopsInBundle(MachineInstr *MI, const SIInstrInfo &TII, in insertNoopsInBundle()
282 MachineBasicBlock::instr_iterator MI = std::next(CurrCycleInstr->getIterator()); in processBundle() local
307 void GCNHazardRecognizer::runOnInstruction(MachineInstr *MI) { in runOnInstruction()
321 unsigned GCNHazardRecognizer::PreEmitNoops(MachineInstr *MI) { in PreEmitNoops()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86ATTInstPrinter.h | 51 void printbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printbytemem()
54 void printwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printwordmem()
57 void printdwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printdwordmem()
60 void printqwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printqwordmem()
63 void printxmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printxmmwordmem()
66 void printymmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printymmwordmem()
69 void printzmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printzmmwordmem()
72 void printtbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printtbytemem()
76 void printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printSrcIdx8()
79 void printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printSrcIdx16()
[all …]
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| H A D | X86IntelInstPrinter.h | 52 void printbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printbytemem()
56 void printwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printwordmem()
60 void printdwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printdwordmem()
64 void printqwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printqwordmem()
68 void printxmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printxmmwordmem()
72 void printymmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printymmwordmem()
76 void printzmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printzmmwordmem()
80 void printtbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printtbytemem()
86 void printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printSrcIdx8()
90 void printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printSrcIdx16()
[all …]
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| H A D | X86InstPrinterCommon.cpp | 29 void X86InstPrinterCommon::printCondCode(const MCInst *MI, unsigned Op, in printCondCode()
59 void X86InstPrinterCommon::printCondFlags(const MCInst *MI, unsigned Op, in printCondFlags()
80 void X86InstPrinterCommon::printSSEAVXCC(const MCInst *MI, unsigned Op, in printSSEAVXCC()
120 void X86InstPrinterCommon::printVPCOMMnemonic(const MCInst *MI, in printVPCOMMnemonic()
150 void X86InstPrinterCommon::printVPCMPMnemonic(const MCInst *MI, in printVPCMPMnemonic()
237 void X86InstPrinterCommon::printCMPMnemonic(const MCInst *MI, bool IsVCmp, in printCMPMnemonic()
316 void X86InstPrinterCommon::printRoundingControl(const MCInst *MI, unsigned Op, in printRoundingControl()
342 void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, uint64_t Address, in printPCRelImm()
372 void X86InstPrinterCommon::printOptionalSegReg(const MCInst *MI, unsigned OpNo, in printOptionalSegReg()
380 void X86InstPrinterCommon::printInstFlags(const MCInst *MI, raw_ostream &O, in printInstFlags()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | R600InstPrinter.cpp | 21 void R600InstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst()
28 void R600InstPrinter::printAbs(const MCInst *MI, unsigned OpNo, in printAbs()
33 void R600InstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo, in printBankSwizzle()
57 void R600InstPrinter::printClamp(const MCInst *MI, unsigned OpNo, in printClamp()
62 void R600InstPrinter::printCT(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printCT()
76 void R600InstPrinter::printKCache(const MCInst *MI, unsigned OpNo, in printKCache()
88 void R600InstPrinter::printLast(const MCInst *MI, unsigned OpNo, in printLast()
93 void R600InstPrinter::printLiteral(const MCInst *MI, unsigned OpNo, in printLiteral()
106 void R600InstPrinter::printNeg(const MCInst *MI, unsigned OpNo, in printNeg()
111 void R600InstPrinter::printOMOD(const MCInst *MI, unsigned OpNo, in printOMOD()
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| H A D | AMDGPUInstPrinter.cpp | 43 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst()
50 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo, in printU4ImmOperand()
56 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, in printU16ImmOperand()
74 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, in printU4ImmDecOperand()
79 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, in printU8ImmDecOperand()
84 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, in printU16ImmDecOperand()
89 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo, in printU32ImmOperand()
95 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo, in printNamedBit()
102 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo, in printOffset()
119 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo, in printFlatOffset()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| H A D | SystemZInstPrinter.cpp | 76 printInst(const MCInst * MI,uint64_t Address,StringRef Annot,const MCSubtargetInfo & STI,raw_ostream & O) printInst() argument
84 printUImmOperand(const MCInst * MI,int OpNum,raw_ostream & O) printUImmOperand() argument
97 printSImmOperand(const MCInst * MI,int OpNum,raw_ostream & O) printSImmOperand() argument
109 printU1ImmOperand(const MCInst * MI,int OpNum,raw_ostream & O) printU1ImmOperand() argument
114 printU2ImmOperand(const MCInst * MI,int OpNum,raw_ostream & O) printU2ImmOperand() argument
119 printU3ImmOperand(const MCInst * MI,int OpNum,raw_ostream & O) printU3ImmOperand() argument
124 printU4ImmOperand(const MCInst * MI,int OpNum,raw_ostream & O) printU4ImmOperand() argument
129 printS8ImmOperand(const MCInst * MI,int OpNum,raw_ostream & O) printS8ImmOperand() argument
134 printU8ImmOperand(const MCInst * MI,int OpNum,raw_ostream & O) printU8ImmOperand() argument
139 printU12ImmOperand(const MCInst * MI,int OpNum,raw_ostream & O) printU12ImmOperand() argument
144 printS16ImmOperand(const MCInst * MI,int OpNum,raw_ostream & O) printS16ImmOperand() argument
149 printU16ImmOperand(const MCInst * MI,int OpNum,raw_ostream & O) printU16ImmOperand() argument
154 printS32ImmOperand(const MCInst * MI,int OpNum,raw_ostream & O) printS32ImmOperand() argument
159 printU32ImmOperand(const MCInst * MI,int OpNum,raw_ostream & O) printU32ImmOperand() argument
164 printU48ImmOperand(const MCInst * MI,int OpNum,raw_ostream & O) printU48ImmOperand() argument
169 printPCRelOperand(const MCInst * MI,int OpNum,raw_ostream & O) printPCRelOperand() argument
180 printPCRelTLSOperand(const MCInst * MI,uint64_t Address,int OpNum,raw_ostream & O) printPCRelTLSOperand() argument
204 printOperand(const MCInst * MI,int OpNum,raw_ostream & O) printOperand() argument
209 printBDAddrOperand(const MCInst * MI,int OpNum,raw_ostream & O) printBDAddrOperand() argument
215 printBDXAddrOperand(const MCInst * MI,int OpNum,raw_ostream & O) printBDXAddrOperand() argument
221 printBDLAddrOperand(const MCInst * MI,int OpNum,raw_ostream & O) printBDLAddrOperand() argument
235 printBDRAddrOperand(const MCInst * MI,int OpNum,raw_ostream & O) printBDRAddrOperand() argument
250 printBDVAddrOperand(const MCInst * MI,int OpNum,raw_ostream & O) printBDVAddrOperand() argument
256 printCond4Operand(const MCInst * MI,int OpNum,raw_ostream & O) printCond4Operand() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/ |
| H A D | XtensaInstPrinter.cpp | 70 void XtensaInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst()
81 void XtensaInstPrinter::printOperand(const MCInst *MI, int OpNum, in printOperand()
86 void XtensaInstPrinter::printMemOperand(const MCInst *MI, int OpNum, in printMemOperand()
93 void XtensaInstPrinter::printBranchTarget(const MCInst *MI, int OpNum, in printBranchTarget()
108 void XtensaInstPrinter::printJumpTarget(const MCInst *MI, int OpNum, in printJumpTarget()
124 void XtensaInstPrinter::printCallOperand(const MCInst *MI, int OpNum, in printCallOperand()
139 void XtensaInstPrinter::printL32RTarget(const MCInst *MI, int OpNum, in printL32RTarget()
157 void XtensaInstPrinter::printImm8_AsmOperand(const MCInst *MI, int OpNum, in printImm8_AsmOperand()
169 void XtensaInstPrinter::printImm8_sh8_AsmOperand(const MCInst *MI, int OpNum, in printImm8_sh8_AsmOperand()
181 void XtensaInstPrinter::printImm12_AsmOperand(const MCInst *MI, int OpNum, in printImm12_AsmOperand()
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| H A D | XtensaMCCodeEmitter.cpp | 125 void XtensaMCCodeEmitter::encodeInstruction(const MCInst &MI, in encodeInstruction()
146 XtensaMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue()
161 XtensaMCCodeEmitter::getJumpTargetEncoding(const MCInst &MI, unsigned int OpNum, in getJumpTargetEncoding()
176 const MCInst &MI, unsigned int OpNum, SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetEncoding()
199 XtensaMCCodeEmitter::getCallEncoding(const MCInst &MI, unsigned int OpNum, in getCallEncoding()
220 XtensaMCCodeEmitter::getL32RTargetEncoding(const MCInst &MI, unsigned OpNum, in getL32RTargetEncoding()
240 XtensaMCCodeEmitter::getMemRegEncoding(const MCInst &MI, unsigned OpNo, in getMemRegEncoding()
273 uint32_t XtensaMCCodeEmitter::getImm8OpValue(const MCInst &MI, unsigned OpNo, in getImm8OpValue()
285 XtensaMCCodeEmitter::getImm8_sh8OpValue(const MCInst &MI, unsigned OpNo, in getImm8_sh8OpValue()
298 XtensaMCCodeEmitter::getImm12OpValue(const MCInst &MI, unsigned OpNo, in getImm12OpValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 88 void ARMInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst()
341 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, in printOperand()
381 void ARMInstPrinter::printOperand(const MCInst *MI, uint64_t Address, in printOperand()
395 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, in printThumbLdrLabelOperand()
426 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum, in printSORegRegOperand()
446 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum, in printSORegImmOperand()
463 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, in printAM2PreOrOffsetIndexOp()
494 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op, in printAddrModeTBB()
508 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op, in printAddrModeTBH()
523 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op, in printAddrMode2Operand()
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| H A D | ARMMCCodeEmitter.cpp | 232 getLdStmModeOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLdStmModeOpValue() argument
307 getCCOutOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getCCOutOpValue() argument
315 getModImmOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & ST) const getModImmOpValue() argument
334 getT2SOImmOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2SOImmOpValue() argument
375 getNEONVcvtImm32OpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getNEONVcvtImm32OpValue() argument
481 NEONThumb2DataIPostEncoder(const MCInst & MI,unsigned EncodedValue,const MCSubtargetInfo & STI) const NEONThumb2DataIPostEncoder() argument
501 NEONThumb2LoadStorePostEncoder(const MCInst & MI,unsigned EncodedValue,const MCSubtargetInfo & STI) const NEONThumb2LoadStorePostEncoder() argument
515 NEONThumb2DupPostEncoder(const MCInst & MI,unsigned EncodedValue,const MCSubtargetInfo & STI) const NEONThumb2DupPostEncoder() argument
528 NEONThumb2V8PostEncoder(const MCInst & MI,unsigned EncodedValue,const MCSubtargetInfo & STI) const NEONThumb2V8PostEncoder() argument
541 VFPThumb2PostEncoder(const MCInst & MI,unsigned EncodedValue,const MCSubtargetInfo & STI) const VFPThumb2PostEncoder() argument
553 getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMachineOpValue() argument
592 EncodeAddrModeOpValues(const MCInst & MI,unsigned OpIdx,unsigned & Reg,unsigned & Imm,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeAddrModeOpValues() argument
621 getBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,unsigned FixupKind,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) getBranchTargetOpValue() argument
659 getThumbBLTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBLTargetOpValue() argument
672 getThumbBLXTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBLXTargetOpValue() argument
684 getThumbBRTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBRTargetOpValue() argument
696 getThumbBCCTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBCCTargetOpValue() argument
708 getThumbCBTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbCBTargetOpValue() argument
718 HasConditionalBranch(const MCInst & MI) HasConditionalBranch() argument
737 getBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue() argument
751 getARMBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getARMBranchTargetOpValue() argument
767 getARMBLTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getARMBLTargetOpValue() argument
782 getARMBLXTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getARMBLXTargetOpValue() argument
795 getThumbBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbBranchTargetOpValue() argument
824 getAdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAdrLabelOpValue() argument
865 getT2AdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AdrLabelOpValue() argument
885 getITMaskOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getITMaskOpValue() argument
912 getThumbAdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getThumbAdrLabelOpValue() argument
925 getThumbAddrModeRegRegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> &,const MCSubtargetInfo & STI) const getThumbAddrModeRegRegOpValue() argument
941 getMVEShiftImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMVEShiftImmOpValue() argument
975 getAddrModeImm12OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModeImm12OpValue() argument
1030 getT2ScaledImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2ScaledImmOpValue() argument
1061 getMveAddrModeRQOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMveAddrModeRQOpValue() argument
1081 getMveAddrModeQOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMveAddrModeQOpValue() argument
1112 getT2AddrModeImm8s4OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImm8s4OpValue() argument
1154 getT2AddrModeImm7s4OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImm7s4OpValue() argument
1181 getT2AddrModeImm0_1020s4OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImm0_1020s4OpValue() argument
1193 getHiLoImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getHiLoImmOpValue() argument
1281 getLdStSORegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLdStSORegOpValue() argument
1315 getAddrMode2OffsetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode2OffsetOpValue() argument
1338 getPostIdxRegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getPostIdxRegOpValue() argument
1350 getAddrMode3OffsetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode3OffsetOpValue() argument
1370 getAddrMode3OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode3OpValue() argument
1407 getAddrModeThumbSPOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModeThumbSPOpValue() argument
1423 getAddrModeISOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModeISOpValue() argument
1438 getAddrModePCOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrModePCOpValue() argument
1449 getAddrMode5OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode5OpValue() argument
1489 getAddrMode5FP16OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode5FP16OpValue() argument
1528 getSORegRegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSORegRegOpValue() argument
1576 getSORegImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSORegImmOpValue() argument
1623 getT2AddrModeSORegOpValue(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeSORegOpValue() argument
1643 getT2AddrModeImmOpValue(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImmOpValue() argument
1668 getT2AddrModeImm8OffsetOpValue(const MCInst & MI,unsigned OpNum,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2AddrModeImm8OffsetOpValue() argument
1685 getT2SORegOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getT2SORegOpValue() argument
1728 getBitfieldInvertedMaskOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBitfieldInvertedMaskOpValue() argument
1742 getRegisterListOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRegisterListOpValue() argument
1789 getAddrMode6AddressOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode6AddressOpValue() argument
1813 getAddrMode6OneLane32AddressOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode6OneLane32AddressOpValue() argument
1840 getAddrMode6DupAddressOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode6DupAddressOpValue() argument
1861 getAddrMode6OffsetOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddrMode6OffsetOpValue() argument
1870 getShiftRight8Imm(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getShiftRight8Imm() argument
1877 getShiftRight16Imm(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getShiftRight16Imm() argument
1884 getShiftRight32Imm(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getShiftRight32Imm() argument
1891 getShiftRight64Imm(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getShiftRight64Imm() argument
1898 encodeInstruction(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeInstruction() argument
1926 getBFTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBFTargetOpValue() argument
1936 getBFAfterTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBFAfterTargetOpValue() argument
1958 getVPTMaskOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVPTMaskOpValue() argument
1990 getRestrictedCondCodeOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRestrictedCondCodeOpValue() argument
2018 getPowerTwoOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getPowerTwoOpValue() argument
2028 getMVEPairVectorIndexOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMVEPairVectorIndexOpValue() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiInstPrinter.cpp | 38 bool LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, in printInst()
48 static bool usesGivenOffset(const MCInst *MI, int AddOffset) { in usesGivenOffset()
55 static bool isPreIncrementForm(const MCInst *MI, int AddOffset) { in isPreIncrementForm()
60 static bool isPostIncrementForm(const MCInst *MI, int AddOffset) { in isPostIncrementForm()
65 static StringRef decIncOperator(const MCInst *MI) { in decIncOperator()
71 bool LanaiInstPrinter::printMemoryLoadIncrement(const MCInst *MI, in printMemoryLoadIncrement()
90 bool LanaiInstPrinter::printMemoryStoreIncrement(const MCInst *MI, in printMemoryStoreIncrement()
109 bool LanaiInstPrinter::printAlias(const MCInst *MI, raw_ostream &OS) { in printAlias()
140 void LanaiInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst()
149 void LanaiInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, in printOperand()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 217 getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMachineOpValue() argument
228 getLdStUImm12OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLdStUImm12OpValue() argument
249 getAdrLabelOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAdrLabelOpValue() argument
275 getAddSubImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAddSubImmOpValue() argument
312 getCondBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getCondBranchTargetOpValue() argument
333 getLoadLiteralOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getLoadLiteralOpValue() argument
353 getMemExtendOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemExtendOpValue() argument
362 getMoveWideImmOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMoveWideImmOpValue() argument
382 getTestBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getTestBranchTargetOpValue() argument
403 getBranchTargetOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue() argument
431 getVecShifterOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShifterOpValue() argument
456 getFixedPointScaleOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getFixedPointScaleOpValue() argument
464 getVecShiftR64OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR64OpValue() argument
473 getVecShiftR32OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR32OpValue() argument
482 getVecShiftR16OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR16OpValue() argument
491 getVecShiftR8OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftR8OpValue() argument
500 getVecShiftL64OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL64OpValue() argument
509 getVecShiftL32OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL32OpValue() argument
518 getVecShiftL16OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL16OpValue() argument
527 getVecShiftL8OpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVecShiftL8OpValue() argument
537 EncodeRegAsMultipleOf(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeRegAsMultipleOf() argument
547 EncodePPR_p8to15(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodePPR_p8to15() argument
555 EncodeZPR2StridedRegisterClass(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeZPR2StridedRegisterClass() argument
565 EncodeZPR4StridedRegisterClass(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeZPR4StridedRegisterClass() argument
575 EncodeMatrixTileListRegisterClass(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const EncodeMatrixTileListRegisterClass() argument
584 encodeMatrixIndexGPR32(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeMatrixIndexGPR32() argument
592 getImm8OptLsl(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImm8OptLsl() argument
610 getSVEIncDecImm(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSVEIncDecImm() argument
622 getMoveVecShifterOpValue(const MCInst & MI,unsigned OpIdx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMoveVecShifterOpValue() argument
632 fixMOVZ(const MCInst & MI,unsigned EncodedValue,const MCSubtargetInfo & STI) const fixMOVZ() argument
664 encodeInstruction(const MCInst & MI,SmallVectorImpl<char> & CB,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeInstruction() argument
693 fixMulHigh(const MCInst & MI,unsigned EncodedValue,const MCSubtargetInfo & STI) const fixMulHigh() argument
703 fixLoadStoreExclusive(const MCInst & MI,unsigned EncodedValue,const MCSubtargetInfo & STI) const fixLoadStoreExclusive() argument
713 fixOneOperandFPComparison(const MCInst & MI,unsigned EncodedValue,const MCSubtargetInfo & STI) const fixOneOperandFPComparison() argument
[all...] |
| H A D | AArch64InstPrinter.cpp | 75 void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
769 printInst(const MCInst * MI,uint64_t Address,StringRef Annot,const MCSubtargetInfo & STI,raw_ostream & O) printInst() argument
832 printRangePrefetchAlias(const MCInst * MI,const MCSubtargetInfo & STI,raw_ostream & O,StringRef Annot) printRangePrefetchAlias() argument
882 printSysAlias(const MCInst * MI,const MCSubtargetInfo & STI,raw_ostream & O) printSysAlias() argument
1002 printSyspAlias(const MCInst * MI,const MCSubtargetInfo & STI,raw_ostream & O) printSyspAlias() argument
1063 printMatrix(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printMatrix() argument
1094 printMatrixTileVector(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printMatrixTileVector() argument
1107 printMatrixTile(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printMatrixTile() argument
1115 printSVCROp(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printSVCROp() argument
1126 printOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printOperand() argument
1141 printImm(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printImm() argument
1148 printImmHex(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printImmHex() argument
1156 printSImm(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printSImm() argument
1170 printPostIncOperand(const MCInst * MI,unsigned OpNo,unsigned Imm,raw_ostream & O) printPostIncOperand() argument
1183 printVRegOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printVRegOperand() argument
1192 printSysCROperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printSysCROperand() argument
1200 printAddSubImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printAddSubImm() argument
1223 printLogicalImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printLogicalImm() argument
1232 printShifter(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printShifter() argument
1245 printShiftedRegister(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printShiftedRegister() argument
1252 printExtendedRegister(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printExtendedRegister() argument
1259 printArithExtend(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printArithExtend() argument
1306 printMemExtend(const MCInst * MI,unsigned OpNum,raw_ostream & O,char SrcRegKind,unsigned Width) printMemExtend() argument
1315 printRegWithShiftExtend(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printRegWithShiftExtend() argument
1333 printPredicateAsCounter(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printPredicateAsCounter() argument
1361 printCondCode(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printCondCode() argument
1368 printInverseCondCode(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printInverseCondCode() argument
1375 printAMNoIndex(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printAMNoIndex() argument
1384 printImmScale(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printImmScale() argument
1392 printImmRangeScale(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printImmRangeScale() argument
1400 printUImm12Offset(const MCInst * MI,unsigned OpNum,unsigned Scale,raw_ostream & O) printUImm12Offset() argument
1412 printAMIndexedWB(const MCInst * MI,unsigned OpNum,unsigned Scale,raw_ostream & O) printAMIndexedWB() argument
1428 printRPRFMOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printRPRFMOperand() argument
1441 printPrefetchOp(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printPrefetchOp() argument
1461 printPSBHintOp(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printPSBHintOp() argument
1472 printBTIHintOp(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printBTIHintOp() argument
1483 printFPImmOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printFPImmOperand() argument
1592 printGPRSeqPairsClassOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printGPRSeqPairsClassOperand() argument
1610 printMatrixTileList(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printMatrixTileList() argument
1635 printVectorList(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O,StringRef LayoutSuffix) printVectorList() argument
1719 printImplicitlyTypedVectorList(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printImplicitlyTypedVectorList() argument
1727 printTypedVectorList(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printTypedVectorList() argument
1740 printVectorIndex(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorIndex() argument
1746 printMatrixIndex(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printMatrixIndex() argument
1752 printAlignedLabel(const MCInst * MI,uint64_t Address,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printAlignedLabel() argument
1783 printAdrAdrpLabel(const MCInst * MI,uint64_t Address,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printAdrAdrpLabel() argument
1810 printBarrierOption(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printBarrierOption() argument
1833 printBarriernXSOption(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printBarriernXSOption() argument
1871 printMRSSystemRegister(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMRSSystemRegister() argument
1898 printMSRSystemRegister(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMSRSystemRegister() argument
1925 printSystemPStateField(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printSystemPStateField() argument
1940 printSIMDType10Operand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printSIMDType10Operand() argument
1949 printComplexRotationOp(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printComplexRotationOp() argument
1956 printSVEPattern(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printSVEPattern() argument
1966 printSVEVecLenSpecifier(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printSVEVecLenSpecifier() argument
1982 printSVERegOp(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printSVERegOp() argument
2021 printImm8OptLsl(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printImm8OptLsl() argument
2046 printSVELogicalImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printSVELogicalImm() argument
2065 printZPRasFPR(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printZPRasFPR() argument
2083 printExactFPImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printExactFPImm() argument
2093 printGPR64as32(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printGPR64as32() argument
2100 printGPR64x8(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printGPR64x8() argument
2107 printSyspXzrPair(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printSyspXzrPair() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsMCCodeEmitter.cpp | 151 encodeInstruction(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeInstruction() argument
234 getBranchTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue() argument
256 getBranchTargetOpValue1SImm16(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue1SImm16() argument
278 getBranchTargetOpValueMMR6(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValueMMR6() argument
301 getBranchTargetOpValueLsl2MMR6(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValueLsl2MMR6() argument
324 getBranchTarget7OpValueMM(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTarget7OpValueMM() argument
345 getBranchTargetOpValueMMPC10(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValueMMPC10() argument
366 getBranchTargetOpValueMM(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValueMM() argument
388 getBranchTarget21OpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTarget21OpValue() argument
410 getBranchTarget21OpValueMM(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTarget21OpValueMM() argument
432 getBranchTarget26OpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTarget26OpValue() argument
454 getBranchTarget26OpValueMM(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTarget26OpValueMM() argument
476 getJumpOffset16OpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getJumpOffset16OpValue() argument
497 getJumpTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getJumpTargetOpValue() argument
514 getJumpTargetOpValueMM(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getJumpTargetOpValueMM() argument
531 getUImm5Lsl2Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getUImm5Lsl2Encoding() argument
549 getSImm3Lsa2Value(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSImm3Lsa2Value() argument
562 getUImm6Lsl2Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getUImm6Lsl2Encoding() argument
575 getSImm9AddiuspValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSImm9AddiuspValue() argument
732 getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMachineOpValue() argument
752 getMemEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncoding() argument
768 getMemEncodingMMImm4(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm4() argument
782 getMemEncodingMMImm4Lsl1(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm4Lsl1() argument
796 getMemEncodingMMImm4Lsl2(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm4Lsl2() argument
810 getMemEncodingMMSPImm5Lsl2(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMSPImm5Lsl2() argument
825 getMemEncodingMMGPImm7Lsl2(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMGPImm7Lsl2() argument
840 getMemEncodingMMImm9(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm9() argument
854 getMemEncodingMMImm11(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm11() argument
867 getMemEncodingMMImm12(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm12() argument
891 getMemEncodingMMImm16(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm16() argument
904 getMemEncodingMMImm4sp(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm4sp() argument
932 getSizeInsEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSizeInsEncoding() argument
945 getUImmWithOffsetEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getUImmWithOffsetEncoding() argument
955 getSimm19Lsl2Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSimm19Lsl2Encoding() argument
977 getSimm18Lsl3Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSimm18Lsl3Encoding() argument
999 getUImm3Mod8Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getUImm3Mod8Encoding() argument
1008 getUImm4AndValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getUImm4AndValue() argument
1036 getRegisterListOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRegisterListOpValue() argument
1056 getRegisterListOpValue16(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRegisterListOpValue16() argument
1063 getMovePRegPairOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMovePRegPairOpValue() argument
1097 getMovePRegSingleOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMovePRegSingleOpValue() argument
1120 getSimm23Lsl2Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSimm23Lsl2Encoding() argument
[all...] |
| H A D | MipsInstPrinter.cpp | 31 isReg(const MCInst & MI,unsigned OpNo) isReg() argument
79 printInst(const MCInst * MI,uint64_t Address,StringRef Annot,const MCSubtargetInfo & STI,raw_ostream & O) printInst() argument
127 printOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printOperand() argument
144 printJumpOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printJumpOperand() argument
157 printBranchOperand(const MCInst * MI,uint64_t Address,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printBranchOperand() argument
178 printUImm(const MCInst * MI,int opNum,const MCSubtargetInfo & STI,raw_ostream & O) printUImm() argument
193 printMemOperand(const MCInst * MI,int opNum,const MCSubtargetInfo & STI,raw_ostream & O) printMemOperand() argument
223 printMemOperandEA(const MCInst * MI,int opNum,const MCSubtargetInfo & STI,raw_ostream & O) printMemOperandEA() argument
233 printFCCOperand(const MCInst * MI,int opNum,const MCSubtargetInfo &,raw_ostream & O) printFCCOperand() argument
241 printSHFMask(const MCInst * MI,int opNum,raw_ostream & O) printSHFMask() argument
245 printAlias(const char * Str,const MCInst & MI,uint64_t Address,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & OS,bool IsBranch) printAlias() argument
257 printAlias(const char * Str,const MCInst & MI,uint64_t Address,unsigned OpNo0,unsigned OpNo1,const MCSubtargetInfo & STI,raw_ostream & OS,bool IsBranch) printAlias() argument
270 printAlias(const MCInst & MI,uint64_t Address,const MCSubtargetInfo & STI,raw_ostream & OS) printAlias() argument
341 printSaveRestore(const MCInst * MI,const MCSubtargetInfo & STI,raw_ostream & O) printSaveRestore() argument
353 printRegisterList(const MCInst * MI,int opNum,const MCSubtargetInfo &,raw_ostream & O) printRegisterList() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCInstPrinter.cpp | 55 void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
218 printPredicateOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O,const char * Modifier) printPredicateOperand() argument
316 printATBitsAsHint(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printATBitsAsHint() argument
326 printU1ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU1ImmOperand() argument
334 printU2ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU2ImmOperand() argument
342 printU3ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU3ImmOperand() argument
350 printU4ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU4ImmOperand() argument
358 printS5ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printS5ImmOperand() argument
366 printImmZeroOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printImmZeroOperand() argument
374 printU5ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU5ImmOperand() argument
382 printU6ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU6ImmOperand() argument
390 printU7ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU7ImmOperand() argument
401 printU8ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU8ImmOperand() argument
408 printU10ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU10ImmOperand() argument
416 printU12ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU12ImmOperand() argument
424 printS16ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printS16ImmOperand() argument
433 printS34ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printS34ImmOperand() argument
445 printU16ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU16ImmOperand() argument
454 printBranchOperand(const MCInst * MI,uint64_t Address,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printBranchOperand() argument
481 printAbsBranchOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printAbsBranchOperand() argument
490 printcrbitm(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printcrbitm() argument
508 printMemRegImm(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMemRegImm() argument
520 printMemRegImmHash(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMemRegImmHash() argument
529 printMemRegImm34PCRel(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMemRegImm34PCRel() argument
538 printMemRegImm34(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMemRegImm34() argument
547 printMemRegReg(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMemRegReg() argument
561 printTLSCall(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printTLSCall() argument
643 printOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printOperand() argument
[all...] |
| H A D | PPCMCCodeEmitter.cpp | 42 getDirectBrEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDirectBrEncoding() argument
60 getCondBrEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getCondBrEncoding() argument
73 getAbsDirectBrEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAbsDirectBrEncoding() argument
86 getAbsCondBrEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAbsCondBrEncoding() argument
99 getVSRpEvenEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVSRpEvenEncoding() argument
108 getImm16Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImm16Encoding() argument
120 getImm34Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI,MCFixupKind Fixup) const getImm34Encoding() argument
135 getImm34EncodingNoPCRel(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImm34EncodingNoPCRel() argument
143 getImm34EncodingPCRel(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImm34EncodingPCRel() argument
150 getDispRIEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRIEncoding() argument
164 getDispRIXEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRIXEncoding() argument
178 getDispRIX16Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRIX16Encoding() argument
195 getDispRIHashEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRIHashEncoding() argument
210 getDispRI34PCRelEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRI34PCRelEncoding() argument
293 getDispRI34Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRI34Encoding() argument
302 getDispSPE8Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispSPE8Encoding() argument
312 getDispSPE4Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispSPE4Encoding() argument
322 getDispSPE2Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispSPE2Encoding() argument
331 getTLSRegEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getTLSRegEncoding() argument
351 getTLSCallEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getTLSCallEncoding() argument
364 get_crbitm_encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const get_crbitm_encoding() argument
378 getOpIdxForMO(const MCInst & MI,const MCOperand & MO) getOpIdxForMO() argument
389 getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMachineOpValue() argument
410 encodeInstruction(const MCInst & MI,SmallVectorImpl<char> & CB,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeInstruction() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 514 short changeAddrMode_abs_io(const MachineInstr &MI) const { in changeAddrMode_abs_io()
517 short changeAddrMode_io_abs(const MachineInstr &MI) const { in changeAddrMode_io_abs()
520 short changeAddrMode_io_rr(const MachineInstr &MI) const { in changeAddrMode_io_rr()
523 short changeAddrMode_rr_io(const MachineInstr &MI) const { in changeAddrMode_rr_io()
526 short changeAddrMode_rr_ur(const MachineInstr &MI) const { in changeAddrMode_rr_ur()
529 short changeAddrMode_ur_rr(const MachineInstr &MI) const { in changeAddrMode_ur_rr()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 143 bool isTriviallyReMaterializable(const MachineInstr &MI) const { in isTriviallyReMaterializable()
156 virtual bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo, in isSafeToSink()
264 virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, in isCoalescableExtInstr()
274 virtual Register isLoadFromStackSlot(const MachineInstr &MI, in isLoadFromStackSlot()
283 virtual Register isLoadFromStackSlot(const MachineInstr &MI, in isLoadFromStackSlot()
292 virtual Register isLoadFromStackSlotPostFE(const MachineInstr &MI, in isLoadFromStackSlotPostFE()
312 virtual Register isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot()
321 virtual Register isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot()
330 virtual Register isStoreToStackSlotPostFE(const MachineInstr &MI, in isStoreToStackSlotPostFE()
348 virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, in isStackSlotCopy()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchAsmPrinter.cpp | 32 void LoongArchAsmPrinter::emitInstruction(const MachineInstr *MI) { in emitInstruction()
57 bool LoongArchAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, in PrintAsmOperand()
113 bool LoongArchAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, in PrintAsmMemoryOperand()
142 const MachineInstr &MI) { in LowerPATCHABLE_FUNCTION_ENTER()
157 void LoongArchAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI) { in LowerPATCHABLE_FUNCTION_EXIT()
161 void LoongArchAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI) { in LowerPATCHABLE_TAIL_CALL()
165 void LoongArchAsmPrinter::emitSled(const MachineInstr &MI, SledKind Kind) { in emitSled()
|