1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __MES_API_DEF_H__ 25 #define __MES_API_DEF_H__ 26 27 #pragma pack(push, 8) 28 29 #define MES_API_VERSION 0x14 30 31 /* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG_12 */ 32 #define AMDGPU_MES_LOG_BUFFER_SIZE 0xC000 33 34 /* Driver submits one API(cmd) as a single Frame and this command size is same for all API 35 * to ease the debugging and parsing of ring buffer. 36 */ 37 enum {API_FRAME_SIZE_IN_DWORDS = 64}; 38 39 /* To avoid command in scheduler context to be overwritten whenenver mutilple interrupts come in, 40 * this creates another queue 41 */ 42 enum {API_NUMBER_OF_COMMAND_MAX = 32}; 43 44 enum MES_API_TYPE { 45 MES_API_TYPE_SCHEDULER = 1, 46 MES_API_TYPE_MAX 47 }; 48 49 enum MES_SCH_API_OPCODE { 50 MES_SCH_API_SET_HW_RSRC = 0, 51 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */ 52 MES_SCH_API_ADD_QUEUE = 2, 53 MES_SCH_API_REMOVE_QUEUE = 3, 54 MES_SCH_API_PERFORM_YIELD = 4, 55 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5, /* For windows GANG = Context */ 56 MES_SCH_API_SUSPEND = 6, 57 MES_SCH_API_RESUME = 7, 58 MES_SCH_API_RESET = 8, 59 MES_SCH_API_SET_LOG_BUFFER = 9, 60 MES_SCH_API_CHANGE_GANG_PRORITY = 10, 61 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11, 62 MES_SCH_API_SET_DEBUG_VMID = 13, 63 MES_SCH_API_MISC = 14, 64 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15, 65 MES_SCH_API_AMD_LOG = 16, 66 MES_SCH_API_SET_SE_MODE = 17, 67 MES_SCH_API_SET_GANG_SUBMIT = 18, 68 MES_SCH_API_SET_HW_RSRC_1 = 19, 69 70 MES_SCH_API_MAX = 0xFF 71 }; 72 73 union MES_API_HEADER { 74 struct { 75 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */ 76 uint32_t opcode : 8; 77 uint32_t dwsize : 8; /* including header */ 78 uint32_t reserved : 12; 79 }; 80 81 uint32_t u32All; 82 }; 83 84 enum MES_AMD_PRIORITY_LEVEL { 85 AMD_PRIORITY_LEVEL_LOW = 0, 86 AMD_PRIORITY_LEVEL_NORMAL = 1, 87 AMD_PRIORITY_LEVEL_MEDIUM = 2, 88 AMD_PRIORITY_LEVEL_HIGH = 3, 89 AMD_PRIORITY_LEVEL_REALTIME = 4, 90 91 AMD_PRIORITY_NUM_LEVELS 92 }; 93 94 enum MES_QUEUE_TYPE { 95 MES_QUEUE_TYPE_GFX, 96 MES_QUEUE_TYPE_COMPUTE, 97 MES_QUEUE_TYPE_SDMA, 98 99 MES_QUEUE_TYPE_MAX, 100 MES_QUEUE_TYPE_SCHQ = MES_QUEUE_TYPE_MAX, 101 }; 102 103 struct MES_API_STATUS { 104 uint64_t api_completion_fence_addr; 105 uint64_t api_completion_fence_value; 106 }; 107 108 109 enum { MAX_COMPUTE_PIPES = 8 }; 110 enum { MAX_GFX_PIPES = 2 }; 111 enum { MAX_SDMA_PIPES = 2 }; 112 113 enum { MAX_COMPUTE_HQD_PER_PIPE = 8 }; 114 enum { MAX_GFX_HQD_PER_PIPE = 8 }; 115 enum { MAX_SDMA_HQD_PER_PIPE = 10 }; 116 enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 }; 117 118 119 enum { MAX_QUEUES_IN_A_GANG = 8 }; 120 121 enum VM_HUB_TYPE { 122 VM_HUB_TYPE_GC = 0, 123 VM_HUB_TYPE_MM = 1, 124 125 VM_HUB_TYPE_MAX, 126 }; 127 128 enum { VMID_INVALID = 0xffff }; 129 130 enum { MAX_VMID_GCHUB = 16 }; 131 enum { MAX_VMID_MMHUB = 16 }; 132 133 enum SET_DEBUG_VMID_OPERATIONS { 134 DEBUG_VMID_OP_PROGRAM = 0, 135 DEBUG_VMID_OP_ALLOCATE = 1, 136 DEBUG_VMID_OP_RELEASE = 2, 137 DEBUG_VMID_OP_VM_SETUP = 3 // used to set up the debug vmid page table in the kernel queue case (mode 1) 138 }; 139 140 enum MES_MS_LOG_CONTEXT_STATE { 141 MES_LOG_CONTEXT_STATE_IDLE = 0, 142 MES_LOG_CONTEXT_STATE_RUNNING = 1, 143 MES_LOG_CONTEXT_STATE_READY = 2, 144 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3, 145 MES_LOG_CONTEXT_STATE_INVALID = 0xF, 146 }; 147 148 enum MES_MS_LOG_OPERATION { 149 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0, 150 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1, 151 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2, 152 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3, 153 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4, 154 MES_LOG_OPERATION_QUEUE_INVALID = 0xF, 155 }; 156 157 struct MES_LOG_CONTEXT_STATE_CHANGE { 158 uint64_t h_context; 159 enum MES_MS_LOG_CONTEXT_STATE new_context_state; 160 }; 161 162 struct MES_LOG_QUEUE_NEW_WORK { 163 uint64_t h_queue; 164 uint64_t reserved; 165 }; 166 167 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT { 168 uint64_t h_queue; 169 uint64_t h_sync_object; 170 }; 171 172 struct MES_LOG_QUEUE_NO_MORE_WORK { 173 uint64_t h_queue; 174 uint64_t reserved; 175 }; 176 177 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT { 178 uint64_t h_queue; 179 uint64_t h_sync_object; 180 }; 181 182 struct MES_LOG_ENTRY_HEADER { 183 uint32_t first_free_entry_index; 184 uint32_t wraparound_count; 185 uint64_t number_of_entries; 186 uint64_t reserved[2]; 187 }; 188 189 struct MES_LOG_ENTRY_DATA { 190 uint64_t gpu_time_stamp; 191 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */ 192 uint32_t reserved_operation_type_bits; 193 union { 194 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change; 195 struct MES_LOG_QUEUE_NEW_WORK queue_new_work; 196 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object; 197 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work; 198 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object; 199 uint64_t all[2]; 200 }; 201 }; 202 203 struct MES_LOG_BUFFER { 204 struct MES_LOG_ENTRY_HEADER header; 205 struct MES_LOG_ENTRY_DATA entries[]; 206 }; 207 208 enum MES_SWIP_TO_HWIP_DEF { 209 MES_MAX_HWIP_SEGMENT = 8, 210 }; 211 212 union MESAPI_SET_HW_RESOURCES { 213 struct { 214 union MES_API_HEADER header; 215 uint32_t vmid_mask_mmhub; 216 uint32_t vmid_mask_gfxhub; 217 uint32_t gds_size; 218 uint32_t paging_vmid; 219 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES]; 220 uint32_t gfx_hqd_mask[MAX_GFX_PIPES]; 221 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES]; 222 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS]; 223 uint64_t g_sch_ctx_gpu_mc_ptr; 224 uint64_t query_status_fence_gpu_mc_ptr; 225 uint32_t gc_base[MES_MAX_HWIP_SEGMENT]; 226 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT]; 227 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT]; 228 struct MES_API_STATUS api_status; 229 union { 230 struct { 231 uint32_t disable_reset : 1; 232 uint32_t use_different_vmid_compute : 1; 233 uint32_t disable_mes_log : 1; 234 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1; 235 uint32_t apply_grbm_remote_register_dummy_read_wa : 1; 236 uint32_t second_gfx_pipe_enabled : 1; 237 uint32_t enable_level_process_quantum_check : 1; 238 uint32_t legacy_sch_mode : 1; 239 uint32_t disable_add_queue_wptr_mc_addr : 1; 240 uint32_t enable_mes_event_int_logging : 1; 241 uint32_t enable_reg_active_poll : 1; 242 uint32_t use_disable_queue_in_legacy_uq_preemption : 1; 243 uint32_t send_write_data : 1; 244 uint32_t os_tdr_timeout_override : 1; 245 uint32_t use_rs64mem_for_proc_gang_ctx : 1; 246 uint32_t halt_on_misaligned_access : 1; 247 uint32_t use_add_queue_unmap_flag_addr : 1; 248 uint32_t enable_mes_sch_stb_log : 1; 249 uint32_t limit_single_process : 1; 250 uint32_t unmapped_doorbell_handling: 2; 251 uint32_t reserved : 11; 252 }; 253 uint32_t uint32_all; 254 }; 255 uint32_t oversubscription_timer; 256 uint64_t doorbell_info; 257 uint64_t event_intr_history_gpu_mc_ptr; 258 uint64_t timestamp; 259 uint32_t os_tdr_timeout_in_sec; 260 }; 261 262 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 263 }; 264 265 union MESAPI_SET_HW_RESOURCES_1 { 266 struct { 267 union MES_API_HEADER header; 268 struct MES_API_STATUS api_status; 269 uint64_t timestamp; 270 union { 271 struct { 272 uint32_t enable_mes_debug_ctx : 1; 273 uint32_t reserved : 31; 274 }; 275 uint32_t uint32_all; 276 }; 277 uint64_t mes_debug_ctx_mc_addr; 278 uint32_t mes_debug_ctx_size; 279 /* unit is 100ms */ 280 uint32_t mes_kiq_unmap_timeout; 281 }; 282 283 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 284 }; 285 286 union MESAPI__ADD_QUEUE { 287 struct { 288 union MES_API_HEADER header; 289 uint32_t process_id; 290 uint64_t page_table_base_addr; 291 uint64_t process_va_start; 292 uint64_t process_va_end; 293 uint64_t process_quantum; 294 uint64_t process_context_addr; 295 uint64_t gang_quantum; 296 uint64_t gang_context_addr; 297 uint32_t inprocess_gang_priority; 298 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 299 uint32_t doorbell_offset; 300 uint64_t mqd_addr; 301 /* From MES_API_VERSION 2, mc addr is expected for wptr_addr */ 302 uint64_t wptr_addr; 303 uint64_t h_context; 304 uint64_t h_queue; 305 enum MES_QUEUE_TYPE queue_type; 306 uint32_t gds_base; 307 union { 308 /* backwards compatibility with Linux, remove union once they use kfd_queue_size */ 309 uint32_t gds_size; 310 uint32_t kfd_queue_size; 311 }; 312 uint32_t gws_base; 313 uint32_t gws_size; 314 uint32_t oa_mask; 315 uint64_t trap_handler_addr; 316 uint32_t vm_context_cntl; 317 318 struct { 319 uint32_t paging : 1; 320 uint32_t debug_vmid : 4; 321 uint32_t program_gds : 1; 322 uint32_t is_gang_suspended : 1; 323 uint32_t is_tmz_queue : 1; 324 uint32_t map_kiq_utility_queue : 1; 325 uint32_t is_kfd_process : 1; 326 uint32_t trap_en : 1; 327 uint32_t is_aql_queue : 1; 328 uint32_t skip_process_ctx_clear : 1; 329 uint32_t map_legacy_kq : 1; 330 uint32_t exclusively_scheduled : 1; 331 uint32_t is_long_running : 1; 332 uint32_t is_dwm_queue : 1; 333 uint32_t reserved : 15; 334 }; 335 struct MES_API_STATUS api_status; 336 uint64_t tma_addr; 337 uint32_t sch_id; 338 uint64_t timestamp; 339 uint32_t process_context_array_index; 340 uint32_t gang_context_array_index; 341 uint32_t pipe_id; //used for mapping legacy kernel queue 342 uint32_t queue_id; 343 uint32_t alignment_mode_setting; 344 }; 345 346 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 347 }; 348 349 union MESAPI__REMOVE_QUEUE { 350 struct { 351 union MES_API_HEADER header; 352 uint32_t doorbell_offset; 353 uint64_t gang_context_addr; 354 355 struct { 356 uint32_t reserved01 : 1; 357 uint32_t unmap_kiq_utility_queue : 1; 358 uint32_t preempt_legacy_gfx_queue : 1; 359 uint32_t unmap_legacy_queue : 1; 360 uint32_t reserved : 28; 361 }; 362 struct MES_API_STATUS api_status; 363 364 uint32_t pipe_id; 365 uint32_t queue_id; 366 367 uint64_t tf_addr; 368 uint32_t tf_data; 369 370 enum MES_QUEUE_TYPE queue_type; 371 uint64_t timestamp; 372 uint32_t gang_context_array_index; 373 }; 374 375 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 376 }; 377 378 union MESAPI__SET_SCHEDULING_CONFIG { 379 struct { 380 union MES_API_HEADER header; 381 /* Grace period when preempting another priority band for this priority band. 382 * The value for idle priority band is ignored, as it never preempts other bands. 383 */ 384 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS]; 385 386 /* Default quantum for scheduling across processes within a priority band. */ 387 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS]; 388 389 /* Default grace period for processes that preempt each other within a priority band.*/ 390 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS]; 391 392 /* For normal level this field specifies the target GPU percentage in situations when it's starved by the high level. 393 * Valid values are between 0 and 50, with the default being 10. 394 */ 395 uint32_t normal_yield_percent; 396 397 struct MES_API_STATUS api_status; 398 uint64_t timestamp; 399 }; 400 401 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 402 }; 403 404 union MESAPI__PERFORM_YIELD { 405 struct { 406 union MES_API_HEADER header; 407 uint32_t dummy; 408 struct MES_API_STATUS api_status; 409 uint64_t timestamp; 410 }; 411 412 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 413 }; 414 415 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL { 416 struct { 417 union MES_API_HEADER header; 418 uint32_t inprocess_gang_priority; 419 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 420 uint64_t gang_quantum; 421 uint64_t gang_context_addr; 422 struct MES_API_STATUS api_status; 423 uint32_t doorbell_offset; 424 uint64_t timestamp; 425 uint32_t gang_context_array_index; 426 struct { 427 uint32_t queue_quantum_scale : 2; 428 uint32_t queue_quantum_duration : 8; 429 uint32_t apply_quantum_all_processes : 1; 430 uint32_t reserved : 21; 431 }; 432 }; 433 434 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 435 }; 436 437 union MESAPI__SUSPEND { 438 struct { 439 union MES_API_HEADER header; 440 /* false - suspend all gangs; true - specific gang */ 441 struct { 442 uint32_t suspend_all_gangs : 1; 443 uint32_t reserved : 31; 444 }; 445 /* gang_context_addr is valid only if suspend_all = false */ 446 447 uint64_t gang_context_addr; 448 449 uint64_t suspend_fence_addr; 450 uint32_t suspend_fence_value; 451 452 struct MES_API_STATUS api_status; 453 454 union { 455 uint32_t return_value; // to be removed 456 uint32_t sch_id; //keep the old return_value temporarily for compatibility 457 }; 458 uint32_t doorbell_offset; 459 uint64_t timestamp; 460 enum MES_QUEUE_TYPE legacy_uq_type; 461 enum MES_AMD_PRIORITY_LEVEL legacy_uq_priority_level; 462 uint32_t gang_context_array_index; 463 }; 464 465 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 466 }; 467 468 union MESAPI__RESUME { 469 struct { 470 union MES_API_HEADER header; 471 /* false - resume all gangs; true - specified gang */ 472 struct { 473 uint32_t resume_all_gangs : 1; 474 uint32_t reserved : 31; 475 }; 476 /* valid only if resume_all_gangs = false */ 477 uint64_t gang_context_addr; 478 479 struct MES_API_STATUS api_status; 480 uint32_t doorbell_offset; 481 uint64_t timestamp; 482 uint32_t gang_context_array_index; 483 }; 484 485 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 486 }; 487 488 union MESAPI__RESET { 489 struct { 490 union MES_API_HEADER header; 491 492 struct { 493 /* Only reset the queue given by doorbell_offset (not entire gang) */ 494 uint32_t reset_queue_only : 1; 495 /* Hang detection first then reset any queues that are hung */ 496 uint32_t hang_detect_then_reset : 1; 497 /* Only do hang detection (no reset) */ 498 uint32_t hang_detect_only : 1; 499 /* Reset HP and LP kernel queues not managed by MES */ 500 uint32_t reset_legacy_gfx : 1; 501 /* Fallback to use conneceted queue index when CP_CNTX_STAT method fails (gfx pipe 0) */ 502 uint32_t use_connected_queue_index : 1; 503 /* For gfx pipe 1 */ 504 uint32_t use_connected_queue_index_p1 : 1; 505 uint32_t reserved : 26; 506 }; 507 508 uint64_t gang_context_addr; 509 510 /* valid only if reset_queue_only = true */ 511 uint32_t doorbell_offset; 512 513 /* valid only if hang_detect_then_reset = true */ 514 uint64_t doorbell_offset_addr; 515 enum MES_QUEUE_TYPE queue_type; 516 517 /* valid only if reset_legacy_gfx = true */ 518 uint32_t pipe_id_lp; 519 uint32_t queue_id_lp; 520 uint32_t vmid_id_lp; 521 uint64_t mqd_mc_addr_lp; 522 uint32_t doorbell_offset_lp; 523 uint64_t wptr_addr_lp; 524 525 uint32_t pipe_id_hp; 526 uint32_t queue_id_hp; 527 uint32_t vmid_id_hp; 528 uint64_t mqd_mc_addr_hp; 529 uint32_t doorbell_offset_hp; 530 uint64_t wptr_addr_hp; 531 532 struct MES_API_STATUS api_status; 533 uint32_t active_vmids; 534 uint64_t timestamp; 535 536 uint32_t gang_context_array_index; 537 538 uint32_t connected_queue_index; 539 uint32_t connected_queue_index_p1; 540 }; 541 542 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 543 }; 544 545 union MESAPI__SET_LOGGING_BUFFER { 546 struct { 547 union MES_API_HEADER header; 548 /* There are separate log buffers for each queue type */ 549 enum MES_QUEUE_TYPE log_type; 550 /* Log buffer GPU Address */ 551 uint64_t logging_buffer_addr; 552 /* number of entries in the log buffer */ 553 uint32_t number_of_entries; 554 /* Entry index at which CPU interrupt needs to be signalled */ 555 uint32_t interrupt_entry; 556 557 struct MES_API_STATUS api_status; 558 uint64_t timestamp; 559 uint32_t vmid; 560 }; 561 562 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 563 }; 564 565 enum MES_API_QUERY_MES_OPCODE { 566 MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE, 567 MES_API_QUERY_MES__CHECK_HEALTHY, 568 MES_API_QUERY_MES__MAX, 569 }; 570 571 enum { QUERY_MES_MAX_SIZE_IN_DWORDS = 20 }; 572 573 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE { 574 uint64_t proc_ctx_array_size_addr; 575 uint64_t gang_ctx_array_size_addr; 576 }; 577 578 struct MES_API_QUERY_MES__HEALTHY_CHECK { 579 uint64_t healthy_addr; 580 }; 581 582 union MESAPI__QUERY_MES_STATUS { 583 struct { 584 union MES_API_HEADER header; 585 enum MES_API_QUERY_MES_OPCODE subopcode; 586 struct MES_API_STATUS api_status; 587 uint64_t timestamp; 588 union { 589 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE ctx_array_size; 590 struct MES_API_QUERY_MES__HEALTHY_CHECK healthy_check; 591 uint32_t data[QUERY_MES_MAX_SIZE_IN_DWORDS]; 592 }; 593 }; 594 595 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 596 }; 597 598 union MESAPI__SET_DEBUG_VMID { 599 struct { 600 union MES_API_HEADER header; 601 struct MES_API_STATUS api_status; 602 union { 603 struct { 604 uint32_t use_gds : 1; 605 uint32_t operation : 2; 606 uint32_t reserved : 29; 607 } flags; 608 uint32_t u32All; 609 }; 610 uint32_t reserved; 611 uint32_t debug_vmid; 612 uint64_t process_context_addr; 613 uint64_t page_table_base_addr; 614 uint64_t process_va_start; 615 uint64_t process_va_end; 616 uint32_t gds_base; 617 uint32_t gds_size; 618 uint32_t gws_base; 619 uint32_t gws_size; 620 uint32_t oa_mask; 621 622 uint64_t output_addr; // output addr of the acquired vmid value 623 624 uint64_t timestamp; 625 626 uint32_t process_vm_cntl; 627 enum MES_QUEUE_TYPE queue_type; 628 629 uint32_t process_context_array_index; 630 631 uint32_t alignment_mode_setting; 632 }; 633 634 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 635 }; 636 637 enum MESAPI_MISC_OPCODE { 638 MESAPI_MISC__WRITE_REG, 639 MESAPI_MISC__INV_GART, 640 MESAPI_MISC__QUERY_STATUS, 641 MESAPI_MISC__READ_REG, 642 MESAPI_MISC__WAIT_REG_MEM, 643 MESAPI_MISC__SET_SHADER_DEBUGGER, 644 MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE, 645 MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES, 646 MESAPI_MISC__QUERY_HUNG_ENGINE_ID, 647 MESAPI_MISC__CHANGE_CONFIG, 648 MESAPI_MISC__LAUNCH_CLEANER_SHADER, 649 MESAPI_MISC__SETUP_MES_DBGEXT, 650 651 MESAPI_MISC__MAX, 652 }; 653 654 enum {MISC_DATA_MAX_SIZE_IN_DWORDS = 20}; 655 656 struct WRITE_REG { 657 uint32_t reg_offset; 658 uint32_t reg_value; 659 }; 660 661 struct READ_REG { 662 uint32_t reg_offset; 663 uint64_t buffer_addr; 664 union { 665 struct { 666 uint32_t read64Bits : 1; 667 uint32_t reserved : 31; 668 } bits; 669 uint32_t all; 670 } option; 671 }; 672 673 struct INV_GART { 674 uint64_t inv_range_va_start; 675 uint64_t inv_range_size; 676 }; 677 678 struct QUERY_STATUS { 679 uint32_t context_id; 680 }; 681 682 enum WRM_OPERATION { 683 WRM_OPERATION__WAIT_REG_MEM, 684 WRM_OPERATION__WR_WAIT_WR_REG, 685 686 WRM_OPERATION__MAX, 687 }; 688 689 struct WAIT_REG_MEM { 690 enum WRM_OPERATION op; 691 /* only function = equal_to_the_reference_value and mem_space = register_space supported for now */ 692 uint32_t reference; 693 uint32_t mask; 694 uint32_t reg_offset1; 695 uint32_t reg_offset2; 696 }; 697 698 struct SET_SHADER_DEBUGGER { 699 uint64_t process_context_addr; 700 union { 701 struct { 702 uint32_t single_memop : 1; // SQ_DEBUG.single_memop 703 uint32_t single_alu_op : 1; // SQ_DEBUG.single_alu_op 704 uint32_t reserved : 30; 705 }; 706 uint32_t u32all; 707 } flags; 708 uint32_t spi_gdbg_per_vmid_cntl; 709 uint32_t tcp_watch_cntl[4]; // TCP_WATCHx_CNTL 710 uint32_t trap_en; 711 }; 712 713 struct SET_GANG_SUBMIT { 714 uint64_t gang_context_addr; 715 uint64_t slave_gang_context_addr; 716 uint32_t gang_context_array_index; 717 uint32_t slave_gang_context_array_index; 718 }; 719 720 enum MESAPI_MISC__CHANGE_CONFIG_OPTION { 721 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0, 722 MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1, 723 MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG = 2, 724 725 MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F 726 }; 727 728 struct CHANGE_CONFIG { 729 enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode; 730 union { 731 struct { 732 uint32_t limit_single_process : 1; 733 uint32_t enable_hws_logging_buffer : 1; 734 uint32_t reserved : 30; 735 } bits; 736 uint32_t all; 737 } option; 738 739 struct { 740 uint32_t tdr_level; 741 uint32_t tdr_delay; 742 } tdr_config; 743 }; 744 745 union MESAPI__MISC { 746 struct { 747 union MES_API_HEADER header; 748 enum MESAPI_MISC_OPCODE opcode; 749 struct MES_API_STATUS api_status; 750 union { 751 struct WRITE_REG write_reg; 752 struct INV_GART inv_gart; 753 struct QUERY_STATUS query_status; 754 struct READ_REG read_reg; 755 struct WAIT_REG_MEM wait_reg_mem; 756 struct SET_SHADER_DEBUGGER set_shader_debugger; 757 enum MES_AMD_PRIORITY_LEVEL queue_sch_level; 758 struct CHANGE_CONFIG change_config; 759 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS]; 760 }; 761 uint64_t timestamp; 762 uint32_t doorbell_offset; 763 uint32_t os_fence; 764 }; 765 766 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 767 }; 768 769 union MESAPI__UPDATE_ROOT_PAGE_TABLE { 770 struct { 771 union MES_API_HEADER header; 772 uint64_t page_table_base_addr; 773 uint64_t process_context_addr; 774 struct MES_API_STATUS api_status; 775 uint64_t timestamp; 776 uint32_t process_context_array_index; 777 }; 778 779 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 780 }; 781 782 union MESAPI_AMD_LOG { 783 struct { 784 union MES_API_HEADER header; 785 uint64_t p_buffer_memory; 786 uint64_t p_buffer_size_used; 787 struct MES_API_STATUS api_status; 788 uint64_t timestamp; 789 }; 790 791 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 792 }; 793 794 enum MES_SE_MODE { 795 MES_SE_MODE_INVALID = 0, 796 MES_SE_MODE_SINGLE_SE = 1, 797 MES_SE_MODE_DUAL_SE = 2, 798 MES_SE_MODE_LOWER_POWER = 3, 799 }; 800 801 union MESAPI__SET_SE_MODE { 802 struct { 803 union MES_API_HEADER header; 804 /* the new SE mode to apply*/ 805 enum MES_SE_MODE new_se_mode; 806 /* the fence to make sure the ItCpgCtxtSync packet is completed */ 807 uint64_t cpg_ctxt_sync_fence_addr; 808 uint32_t cpg_ctxt_sync_fence_value; 809 /* log_seq_time - Scheduler logs the switch seq start/end ts in the IH cookies */ 810 union { 811 struct { 812 uint32_t log_seq_time : 1; 813 uint32_t reserved : 31; 814 }; 815 uint32_t uint32_all; 816 }; 817 struct MES_API_STATUS api_status; 818 }; 819 820 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 821 }; 822 823 union MESAPI__SET_GANG_SUBMIT { 824 struct { 825 union MES_API_HEADER header; 826 struct MES_API_STATUS api_status; 827 struct SET_GANG_SUBMIT set_gang_submit; 828 }; 829 830 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 831 }; 832 833 #pragma pack(pop) 834 835 #endif 836